SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/pm3fb.c

   1 /*
   2  *  linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
   3  *
   4  *  Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
   5  *
   6  *  Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
   7  *      based on pm2fb.c
   8  *
   9  *  Based on code written by:
  10  *         Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11  *         Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12  *         Russell King, <rmk@arm.linux.org.uk>
  13  *  Based on linux/drivers/video/skeletonfb.c:
  14  *      Copyright (C) 1997 Geert Uytterhoeven
  15  *  Based on linux/driver/video/pm2fb.c:
  16  *      Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17  *      Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License. See the file COPYING in the main directory of this archive for
  21  *  more details.
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/fb.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #ifdef CONFIG_MTRR
  36 #include <asm/mtrr.h>
  37 #endif
  38
  39 #include <video/pm3fb.h>
  40
  41 #if !defined(CONFIG_PCI)
  42 #error "Only generic PCI cards supported."
  43 #endif
  44
  45 #undef PM3FB_MASTER_DEBUG
  46 #ifdef PM3FB_MASTER_DEBUG
  47 #define DPRINTK(a, b...)        \
  48         printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
  49 #else
  50 #define DPRINTK(a, b...)
  51 #endif
  52
  53 #define PM3_PIXMAP_SIZE (2048 * 4)
  54
  55 /*
  56  * Driver data
  57  */
  58 static int hwcursor = 1;
  59 static char *mode_option __devinitdata;
  60 static int noaccel __devinitdata;
  61
  62 /* mtrr option */
  63 #ifdef CONFIG_MTRR
  64 static int nomtrr __devinitdata;
  65 #endif
  66
  67 /*
  68  * This structure defines the hardware state of the graphics card. Normally
  69  * you place this in a header file in linux/include/video. This file usually
  70  * also includes register information. That allows other driver subsystems
  71  * and userland applications the ability to use the same header file to
  72  * avoid duplicate work and easy porting of software.
  73  */
  74 struct pm3_par {
  75         unsigned char   __iomem *v_regs;/* virtual address of p_regs */
  76         u32             video;          /* video flags before blanking */
  77         u32             base;           /* screen base in 128 bits unit */
  78         u32             palette[16];
  79         int             mtrr_handle;
  80 };
  81
  82 /*
  83  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  84  * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  85  * to get a fb_var_screeninfo. Otherwise define a default var as well.
  86  */
  87 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
  88         .id =           "Permedia3",
  89         .type =         FB_TYPE_PACKED_PIXELS,
  90         .visual =       FB_VISUAL_PSEUDOCOLOR,
  91         .xpanstep =     1,
  92         .ypanstep =     1,
  93         .ywrapstep =    0,
  94         .accel =        FB_ACCEL_3DLABS_PERMEDIA3,
  95 };
  96
  97 /*
  98  * Utility functions
  99  */
 100
 101 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
 102 {
 103         return fb_readl(par->v_regs + off);
 104 }
 105
 106 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
 107 {
 108         fb_writel(v, par->v_regs + off);
 109 }
 110
 111 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
 112 {
 113         while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
 114 }
 115
 116 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
 117 {
 118         PM3_WAIT(par, 3);
 119         PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
 120         PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
 121         wmb();
 122         PM3_WRITE_REG(par, PM3RD_IndexedData, v);
 123         wmb();
 124 }
 125
 126 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
 127                         unsigned char r, unsigned char g, unsigned char b)
 128 {
 129         PM3_WAIT(par, 4);
 130         PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
 131         wmb();
 132         PM3_WRITE_REG(par, PM3RD_PaletteData, r);
 133         wmb();
 134         PM3_WRITE_REG(par, PM3RD_PaletteData, g);
 135         wmb();
 136         PM3_WRITE_REG(par, PM3RD_PaletteData, b);
 137         wmb();
 138 }
 139
 140 static void pm3fb_clear_colormap(struct pm3_par *par,
 141                         unsigned char r, unsigned char g, unsigned char b)
 142 {
 143         int i;
 144
 145         for (i = 0; i < 256 ; i++)
 146                 pm3fb_set_color(par, i, r, g, b);
 147
 148 }
 149
 150 /* Calculating various clock parameters */
 151 static void pm3fb_calculate_clock(unsigned long reqclock,
 152                                 unsigned char *prescale,
 153                                 unsigned char *feedback,
 154                                 unsigned char *postscale)
 155 {
 156         int f, pre, post;
 157         unsigned long freq;
 158         long freqerr = 1000;
 159         long currerr;
 160
 161         for (f = 1; f < 256; f++) {
 162                 for (pre = 1; pre < 256; pre++) {
 163                         for (post = 0; post < 5; post++) {
 164                                 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
 165                                 currerr = (reqclock > freq)
 166                                         ? reqclock - freq
 167                                         : freq - reqclock;
 168                                 if (currerr < freqerr) {
 169                                         freqerr = currerr;
 170                                         *feedback = f;
 171                                         *prescale = pre;
 172                                         *postscale = post;
 173                                 }
 174                         }
 175                 }
 176         }
 177 }
 178
 179 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
 180 {
 181         if (var->bits_per_pixel == 16)
 182                 return var->red.length + var->green.length
 183                         + var->blue.length;
 184
 185         return var->bits_per_pixel;
 186 }
 187
 188 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
 189 {
 190         switch (bpp) {
 191         case 8:
 192                 return (v >> 4);
 193         case 16:
 194                 return (v >> 3);
 195         case 32:
 196                 return (v >> 2);
 197         }
 198         DPRINTK("Unsupported depth %u\n", bpp);
 199         return 0;
 200 }
 201
 202 /* acceleration */
 203 static int pm3fb_sync(struct fb_info *info)
 204 {
 205         struct pm3_par *par = info->par;
 206
 207         PM3_WAIT(par, 2);
 208         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 209         PM3_WRITE_REG(par, PM3Sync, 0);
 210         mb();
 211         do {
 212                 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
 213                 rmb();
 214         } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
 215
 216         return 0;
 217 }
 218
 219 static void pm3fb_init_engine(struct fb_info *info)
 220 {
 221         struct pm3_par *par = info->par;
 222         const u32 width = (info->var.xres_virtual + 7) & ~7;
 223
 224         PM3_WAIT(par, 50);
 225         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 226         PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
 227         PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
 228         PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
 229         PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
 230         PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
 231         PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
 232         PM3_WRITE_REG(par, PM3GIDMode, 0x0);
 233         PM3_WRITE_REG(par, PM3DepthMode, 0x0);
 234         PM3_WRITE_REG(par, PM3StencilMode, 0x0);
 235         PM3_WRITE_REG(par, PM3StencilData, 0x0);
 236         PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
 237         PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
 238         PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
 239         PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
 240         PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
 241         PM3_WRITE_REG(par, PM3LUTMode, 0x0);
 242         PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
 243         PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
 244         PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
 245         PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
 246         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
 247         PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
 248         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
 249         PM3_WRITE_REG(par, PM3FogMode, 0x0);
 250         PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
 251         PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
 252         PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
 253         PM3_WRITE_REG(par, PM3YUVMode, 0x0);
 254         PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
 255         PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
 256         PM3_WRITE_REG(par, PM3DitherMode, 0x0);
 257         PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
 258         PM3_WRITE_REG(par, PM3RouterMode, 0x0);
 259         PM3_WRITE_REG(par, PM3Window, 0x0);
 260
 261         PM3_WRITE_REG(par, PM3Config2D, 0x0);
 262
 263         PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
 264
 265         PM3_WRITE_REG(par, PM3XBias, 0x0);
 266         PM3_WRITE_REG(par, PM3YBias, 0x0);
 267         PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
 268
 269         PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
 270
 271         PM3_WRITE_REG(par, PM3FBDestReadEnables,
 272                            PM3FBDestReadEnables_E(0xff) |
 273                            PM3FBDestReadEnables_R(0xff) |
 274                            PM3FBDestReadEnables_ReferenceAlpha(0xff));
 275         PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
 276         PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
 277         PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
 278                            PM3FBDestReadBufferWidth_Width(width));
 279
 280         PM3_WRITE_REG(par, PM3FBDestReadMode,
 281                            PM3FBDestReadMode_ReadEnable |
 282                            PM3FBDestReadMode_Enable0);
 283         PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
 284         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
 285         PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
 286                            PM3FBSourceReadBufferWidth_Width(width));
 287         PM3_WRITE_REG(par, PM3FBSourceReadMode,
 288                            PM3FBSourceReadMode_Blocking |
 289                            PM3FBSourceReadMode_ReadEnable);
 290
 291         PM3_WAIT(par, 2);
 292         {
 293                 /* invert bits in bitmask */
 294                 unsigned long rm = 1 | (3 << 7);
 295                 switch (info->var.bits_per_pixel) {
 296                 case 8:
 297                         PM3_WRITE_REG(par, PM3PixelSize,
 298                                            PM3PixelSize_GLOBAL_8BIT);
 299 #ifdef __BIG_ENDIAN
 300                         rm |= 3 << 15;
 301 #endif
 302                         break;
 303                 case 16:
 304                         PM3_WRITE_REG(par, PM3PixelSize,
 305                                            PM3PixelSize_GLOBAL_16BIT);
 306 #ifdef __BIG_ENDIAN
 307                         rm |= 2 << 15;
 308 #endif
 309                         break;
 310                 case 32:
 311                         PM3_WRITE_REG(par, PM3PixelSize,
 312                                            PM3PixelSize_GLOBAL_32BIT);
 313                         break;
 314                 default:
 315                         DPRINTK(1, "Unsupported depth %d\n",
 316                                 info->var.bits_per_pixel);
 317                         break;
 318                 }
 319                 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
 320         }
 321
 322         PM3_WAIT(par, 20);
 323         PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
 324         PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
 325         PM3_WRITE_REG(par, PM3FBWriteMode,
 326                            PM3FBWriteMode_WriteEnable |
 327                            PM3FBWriteMode_OpaqueSpan |
 328                            PM3FBWriteMode_Enable0);
 329         PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
 330         PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
 331         PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
 332                            PM3FBWriteBufferWidth_Width(width));
 333
 334         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
 335         {
 336                 /* size in lines of FB */
 337                 unsigned long sofb = info->screen_size /
 338                         info->fix.line_length;
 339                 if (sofb > 4095)
 340                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
 341                 else
 342                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
 343
 344                 switch (info->var.bits_per_pixel) {
 345                 case 8:
 346                         PM3_WRITE_REG(par, PM3DitherMode,
 347                                            (1 << 10) | (2 << 3));
 348                         break;
 349                 case 16:
 350                         PM3_WRITE_REG(par, PM3DitherMode,
 351                                            (1 << 10) | (1 << 3));
 352                         break;
 353                 case 32:
 354                         PM3_WRITE_REG(par, PM3DitherMode,
 355                                            (1 << 10) | (0 << 3));
 356                         break;
 357                 default:
 358                         DPRINTK(1, "Unsupported depth %d\n",
 359                                 info->current_par->depth);
 360                         break;
 361                 }
 362         }
 363
 364         PM3_WRITE_REG(par, PM3dXDom, 0x0);
 365         PM3_WRITE_REG(par, PM3dXSub, 0x0);
 366         PM3_WRITE_REG(par, PM3dY, 1 << 16);
 367         PM3_WRITE_REG(par, PM3StartXDom, 0x0);
 368         PM3_WRITE_REG(par, PM3StartXSub, 0x0);
 369         PM3_WRITE_REG(par, PM3StartY, 0x0);
 370         PM3_WRITE_REG(par, PM3Count, 0x0);
 371
 372 /* Disable LocalBuffer. better safe than sorry */
 373         PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
 374         PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
 375         PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
 376         PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
 377
 378         pm3fb_sync(info);
 379 }
 380
 381 static void pm3fb_fillrect(struct fb_info *info,
 382                                 const struct fb_fillrect *region)
 383 {
 384         struct pm3_par *par = info->par;
 385         struct fb_fillrect modded;
 386         int vxres, vyres;
 387         int rop;
 388         u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
 389                 ((u32 *)info->pseudo_palette)[region->color] : region->color;
 390
 391         if (info->state != FBINFO_STATE_RUNNING)
 392                 return;
 393         if (info->flags & FBINFO_HWACCEL_DISABLED) {
 394                 cfb_fillrect(info, region);
 395                 return;
 396         }
 397         if (region->rop == ROP_COPY )
 398                 rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
 399         else
 400                 rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
 401                         PM3Config2D_FBDestReadEnable;
 402
 403         vxres = info->var.xres_virtual;
 404         vyres = info->var.yres_virtual;
 405
 406         memcpy(&modded, region, sizeof(struct fb_fillrect));
 407
 408         if (!modded.width || !modded.height ||
 409             modded.dx >= vxres || modded.dy >= vyres)
 410                 return;
 411
 412         if (modded.dx + modded.width  > vxres)
 413                 modded.width  = vxres - modded.dx;
 414         if (modded.dy + modded.height > vyres)
 415                 modded.height = vyres - modded.dy;
 416
 417         if (info->var.bits_per_pixel == 8)
 418                 color |= color << 8;
 419         if (info->var.bits_per_pixel <= 16)
 420                 color |= color << 16;
 421
 422         PM3_WAIT(par, 4);
 423         /* ROP Ox3 is GXcopy */
 424         PM3_WRITE_REG(par, PM3Config2D,
 425                         PM3Config2D_UseConstantSource |
 426                         PM3Config2D_ForegroundROPEnable |
 427                         rop |
 428                         PM3Config2D_FBWriteEnable);
 429
 430         PM3_WRITE_REG(par, PM3ForegroundColor, color);
 431
 432         PM3_WRITE_REG(par, PM3RectanglePosition,
 433                         PM3RectanglePosition_XOffset(modded.dx) |
 434                         PM3RectanglePosition_YOffset(modded.dy));
 435
 436         PM3_WRITE_REG(par, PM3Render2D,
 437                       PM3Render2D_XPositive |
 438                       PM3Render2D_YPositive |
 439                       PM3Render2D_Operation_Normal |
 440                       PM3Render2D_SpanOperation |
 441                       PM3Render2D_Width(modded.width) |
 442                       PM3Render2D_Height(modded.height));
 443 }
 444
 445 static void pm3fb_copyarea(struct fb_info *info,
 446                                 const struct fb_copyarea *area)
 447 {
 448         struct pm3_par *par = info->par;
 449         struct fb_copyarea modded;
 450         u32 vxres, vyres;
 451         int x_align, o_x, o_y;
 452
 453         if (info->state != FBINFO_STATE_RUNNING)
 454                 return;
 455         if (info->flags & FBINFO_HWACCEL_DISABLED) {
 456                 cfb_copyarea(info, area);
 457                 return;
 458         }
 459
 460         memcpy(&modded, area, sizeof(struct fb_copyarea));
 461
 462         vxres = info->var.xres_virtual;
 463         vyres = info->var.yres_virtual;
 464
 465         if (!modded.width || !modded.height ||
 466             modded.sx >= vxres || modded.sy >= vyres ||
 467             modded.dx >= vxres || modded.dy >= vyres)
 468                 return;
 469
 470         if (modded.sx + modded.width > vxres)
 471                 modded.width = vxres - modded.sx;
 472         if (modded.dx + modded.width > vxres)
 473                 modded.width = vxres - modded.dx;
 474         if (modded.sy + modded.height > vyres)
 475                 modded.height = vyres - modded.sy;
 476         if (modded.dy + modded.height > vyres)
 477                 modded.height = vyres - modded.dy;
 478
 479         o_x = modded.sx - modded.dx;    /*(sx > dx ) ? (sx - dx) : (dx - sx); */
 480         o_y = modded.sy - modded.dy;    /*(sy > dy ) ? (sy - dy) : (dy - sy); */
 481
 482         x_align = (modded.sx & 0x1f);
 483
 484         PM3_WAIT(par, 6);
 485
 486         PM3_WRITE_REG(par, PM3Config2D,
 487                         PM3Config2D_UserScissorEnable |
 488                         PM3Config2D_ForegroundROPEnable |
 489                         PM3Config2D_Blocking |
 490                         PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
 491                         PM3Config2D_FBWriteEnable);
 492
 493         PM3_WRITE_REG(par, PM3ScissorMinXY,
 494                         ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
 495         PM3_WRITE_REG(par, PM3ScissorMaxXY,
 496                         (((modded.dy + modded.height) & 0x0fff) << 16) |
 497                         ((modded.dx + modded.width) & 0x0fff));
 498
 499         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
 500                         PM3FBSourceReadBufferOffset_XOffset(o_x) |
 501                         PM3FBSourceReadBufferOffset_YOffset(o_y));
 502
 503         PM3_WRITE_REG(par, PM3RectanglePosition,
 504                         PM3RectanglePosition_XOffset(modded.dx - x_align) |
 505                         PM3RectanglePosition_YOffset(modded.dy));
 506
 507         PM3_WRITE_REG(par, PM3Render2D,
 508                         ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
 509                         ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
 510                         PM3Render2D_Operation_Normal |
 511                         PM3Render2D_SpanOperation |
 512                         PM3Render2D_FBSourceReadEnable |
 513                         PM3Render2D_Width(modded.width + x_align) |
 514                         PM3Render2D_Height(modded.height));
 515 }
 516
 517 static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
 518 {
 519         struct pm3_par *par = info->par;
 520         u32 height = image->height;
 521         u32 fgx, bgx;
 522         const u32 *src = (const u32 *)image->data;
 523
 524         if (info->state != FBINFO_STATE_RUNNING)
 525                 return;
 526         if (info->flags & FBINFO_HWACCEL_DISABLED) {
 527                 cfb_imageblit(info, image);
 528                 return;
 529         }
 530         switch (info->fix.visual) {
 531         case FB_VISUAL_PSEUDOCOLOR:
 532                 fgx = image->fg_color;
 533                 bgx = image->bg_color;
 534                 break;
 535         case FB_VISUAL_TRUECOLOR:
 536         default:
 537                 fgx = par->palette[image->fg_color];
 538                 bgx = par->palette[image->bg_color];
 539                 break;
 540         }
 541         if (image->depth != 1)
 542                 return cfb_imageblit(info, image);
 543
 544         if (info->var.bits_per_pixel == 8) {
 545                 fgx |= fgx << 8;
 546                 bgx |= bgx << 8;
 547         }
 548         if (info->var.bits_per_pixel <= 16) {
 549                 fgx |= fgx << 16;
 550                 bgx |= bgx << 16;
 551         }
 552
 553         PM3_WAIT(par, 7);
 554
 555         PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
 556         PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
 557
 558         /* ROP Ox3 is GXcopy */
 559         PM3_WRITE_REG(par, PM3Config2D,
 560                         PM3Config2D_UserScissorEnable |
 561                         PM3Config2D_UseConstantSource |
 562                         PM3Config2D_ForegroundROPEnable |
 563                         PM3Config2D_ForegroundROP(0x3) |
 564                         PM3Config2D_OpaqueSpan |
 565                         PM3Config2D_FBWriteEnable);
 566         PM3_WRITE_REG(par, PM3ScissorMinXY,
 567                         ((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
 568         PM3_WRITE_REG(par, PM3ScissorMaxXY,
 569                         (((image->dy + image->height) & 0x0fff) << 16) |
 570                         ((image->dx + image->width) & 0x0fff));
 571         PM3_WRITE_REG(par, PM3RectanglePosition,
 572                         PM3RectanglePosition_XOffset(image->dx) |
 573                         PM3RectanglePosition_YOffset(image->dy));
 574         PM3_WRITE_REG(par, PM3Render2D,
 575                         PM3Render2D_XPositive |
 576                         PM3Render2D_YPositive |
 577                         PM3Render2D_Operation_SyncOnBitMask |
 578                         PM3Render2D_SpanOperation |
 579                         PM3Render2D_Width(image->width) |
 580                         PM3Render2D_Height(image->height));
 581
 582
 583         while (height--) {
 584                 int width = ((image->width + 7) >> 3)
 585                                 + info->pixmap.scan_align - 1;
 586                 width >>= 2;
 587
 588                 while (width >= PM3_FIFO_SIZE) {
 589                         int i = PM3_FIFO_SIZE - 1;
 590
 591                         PM3_WAIT(par, PM3_FIFO_SIZE);
 592                         while (i--) {
 593                                 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 594                                 src++;
 595                         }
 596                         width -= PM3_FIFO_SIZE - 1;
 597                 }
 598
 599                 PM3_WAIT(par, width + 1);
 600                 while (width--) {
 601                         PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 602                         src++;
 603                 }
 604         }
 605 }
 606 /* end of acceleration functions */
 607
 608 /*
 609  *      Hardware Cursor support.
 610  */
 611 static const u8 cursor_bits_lookup[16] = {
 612         0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
 613         0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
 614 };
 615
 616 static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
 617 {
 618         struct pm3_par *par = info->par;
 619         u8 mode;
 620
 621         if (!hwcursor)
 622                 return -EINVAL; /* just to force soft_cursor() call */
 623
 624         /* Too large of a cursor or wrong bpp :-( */
 625         if (cursor->image.width > 64 ||
 626             cursor->image.height > 64 ||
 627             cursor->image.depth > 1)
 628                 return -EINVAL;
 629
 630         mode = PM3RD_CursorMode_TYPE_X;
 631         if (cursor->enable)
 632                  mode |= PM3RD_CursorMode_CURSOR_ENABLE;
 633
 634         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
 635
 636         /*
 637          * If the cursor is not be changed this means either we want the
 638          * current cursor state (if enable is set) or we want to query what
 639          * we can do with the cursor (if enable is not set)
 640          */
 641         if (!cursor->set)
 642                 return 0;
 643
 644         if (cursor->set & FB_CUR_SETPOS) {
 645                 int x = cursor->image.dx - info->var.xoffset;
 646                 int y = cursor->image.dy - info->var.yoffset;
 647
 648                 PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
 649                 PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
 650                 PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
 651                 PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
 652         }
 653
 654         if (cursor->set & FB_CUR_SETHOT) {
 655                 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
 656                                   cursor->hot.x & 0x3f);
 657                 PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
 658                                   cursor->hot.y & 0x3f);
 659         }
 660
 661         if (cursor->set & FB_CUR_SETCMAP) {
 662                 u32 fg_idx = cursor->image.fg_color;
 663                 u32 bg_idx = cursor->image.bg_color;
 664                 struct fb_cmap cmap = info->cmap;
 665
 666                 /* the X11 driver says one should use these color registers */
 667                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
 668                                   cmap.red[fg_idx] >> 8 );
 669                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
 670                                   cmap.green[fg_idx] >> 8 );
 671                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
 672                                   cmap.blue[fg_idx] >> 8 );
 673
 674                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
 675                                   cmap.red[bg_idx] >> 8 );
 676                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
 677                                   cmap.green[bg_idx] >> 8 );
 678                 PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
 679                                   cmap.blue[bg_idx] >> 8 );
 680         }
 681
 682         if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
 683                 u8 *bitmap = (u8 *)cursor->image.data;
 684                 u8 *mask = (u8 *)cursor->mask;
 685                 int i;
 686                 int pos = PM3RD_CursorPattern(0);
 687
 688                 for (i = 0; i < cursor->image.height; i++) {
 689                         int j = (cursor->image.width + 7) >> 3;
 690                         int k = 8 - j;
 691
 692                         for (; j > 0; j--) {
 693                                 u8 data = *bitmap ^ *mask;
 694
 695                                 if (cursor->rop == ROP_COPY)
 696                                         data = *mask & *bitmap;
 697                                 /* Upper 4 bits of bitmap data */
 698                                 PM3_WRITE_DAC_REG(par, pos++,
 699                                         cursor_bits_lookup[data >> 4] |
 700                                         (cursor_bits_lookup[*mask >> 4] << 1));
 701                                 /* Lower 4 bits of bitmap */
 702                                 PM3_WRITE_DAC_REG(par, pos++,
 703                                         cursor_bits_lookup[data & 0xf] |
 704                                         (cursor_bits_lookup[*mask & 0xf] << 1));
 705                                 bitmap++;
 706                                 mask++;
 707                         }
 708                         for (; k > 0; k--) {
 709                                 PM3_WRITE_DAC_REG(par, pos++, 0);
 710                                 PM3_WRITE_DAC_REG(par, pos++, 0);
 711                         }
 712                 }
 713                 while (pos < PM3RD_CursorPattern(1024))
 714                         PM3_WRITE_DAC_REG(par, pos++, 0);
 715         }
 716         return 0;
 717 }
 718
 719 /* write the mode to registers */
 720 static void pm3fb_write_mode(struct fb_info *info)
 721 {
 722         struct pm3_par *par = info->par;
 723         char tempsync = 0x00;
 724         char tempmisc = 0x00;
 725         const u32 hsstart = info->var.right_margin;
 726         const u32 hsend = hsstart + info->var.hsync_len;
 727         const u32 hbend = hsend + info->var.left_margin;
 728         const u32 xres = (info->var.xres + 31) & ~31;
 729         const u32 htotal = xres + hbend;
 730         const u32 vsstart = info->var.lower_margin;
 731         const u32 vsend = vsstart + info->var.vsync_len;
 732         const u32 vbend = vsend + info->var.upper_margin;
 733         const u32 vtotal = info->var.yres + vbend;
 734         const u32 width = (info->var.xres_virtual + 7) & ~7;
 735         const unsigned bpp = info->var.bits_per_pixel;
 736
 737         PM3_WAIT(par, 20);
 738         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
 739         PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
 740         PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
 741         PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
 742
 743         PM3_WRITE_REG(par, PM3HTotal,
 744                            pm3fb_shift_bpp(bpp, htotal - 1));
 745         PM3_WRITE_REG(par, PM3HsEnd,
 746                            pm3fb_shift_bpp(bpp, hsend));
 747         PM3_WRITE_REG(par, PM3HsStart,
 748                            pm3fb_shift_bpp(bpp, hsstart));
 749         PM3_WRITE_REG(par, PM3HbEnd,
 750                            pm3fb_shift_bpp(bpp, hbend));
 751         PM3_WRITE_REG(par, PM3HgEnd,
 752                            pm3fb_shift_bpp(bpp, hbend));
 753         PM3_WRITE_REG(par, PM3ScreenStride,
 754                            pm3fb_shift_bpp(bpp, width));
 755         PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
 756         PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
 757         PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
 758         PM3_WRITE_REG(par, PM3VbEnd, vbend);
 759
 760         switch (bpp) {
 761         case 8:
 762                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 763                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 764                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 765                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 766                 break;
 767
 768         case 16:
 769 #ifndef __BIG_ENDIAN
 770                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 771                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 772                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 773                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 774 #else
 775                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 776                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 777                                    PM3ByApertureMode_BYTESWAP_BADC);
 778                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 779                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 780                                    PM3ByApertureMode_BYTESWAP_BADC);
 781 #endif /* ! __BIG_ENDIAN */
 782                 break;
 783
 784         case 32:
 785 #ifndef __BIG_ENDIAN
 786                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 787                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 788                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 789                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 790 #else
 791                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 792                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 793                                    PM3ByApertureMode_BYTESWAP_DCBA);
 794                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 795                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 796                                    PM3ByApertureMode_BYTESWAP_DCBA);
 797 #endif /* ! __BIG_ENDIAN */
 798                 break;
 799
 800         default:
 801                 DPRINTK("Unsupported depth %d\n", bpp);
 802                 break;
 803         }
 804
 805         /*
 806          * Oxygen VX1 - it appears that setting PM3VideoControl and
 807          * then PM3RD_SyncControl to the same SYNC settings undoes
 808          * any net change - they seem to xor together.  Only set the
 809          * sync options in PM3RD_SyncControl.  --rmk
 810          */
 811         {
 812                 unsigned int video = par->video;
 813
 814                 video &= ~(PM3VideoControl_HSYNC_MASK |
 815                            PM3VideoControl_VSYNC_MASK);
 816                 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 817                          PM3VideoControl_VSYNC_ACTIVE_HIGH;
 818                 PM3_WRITE_REG(par, PM3VideoControl, video);
 819         }
 820         PM3_WRITE_REG(par, PM3VClkCtl,
 821                            (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
 822         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
 823         PM3_WRITE_REG(par, PM3ChipConfig,
 824                            (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
 825
 826         wmb();
 827         {
 828                 unsigned char uninitialized_var(m);     /* ClkPreScale */
 829                 unsigned char uninitialized_var(n);     /* ClkFeedBackScale */
 830                 unsigned char uninitialized_var(p);     /* ClkPostScale */
 831                 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
 832
 833                 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
 834
 835                 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
 836                         pixclock, (int) m, (int) n, (int) p);
 837
 838                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
 839                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
 840                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
 841         }
 842         /*
 843            PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
 844          */
 845         /*
 846            PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
 847          */
 848         if ((par->video & PM3VideoControl_HSYNC_MASK) ==
 849             PM3VideoControl_HSYNC_ACTIVE_HIGH)
 850                 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
 851         if ((par->video & PM3VideoControl_VSYNC_MASK) ==
 852             PM3VideoControl_VSYNC_ACTIVE_HIGH)
 853                 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
 854
 855         PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
 856         DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
 857
 858         PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
 859
 860         switch (pm3fb_depth(&info->var)) {
 861         case 8:
 862                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 863                                   PM3RD_PixelSize_8_BIT_PIXELS);
 864                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 865                                   PM3RD_ColorFormat_CI8_COLOR |
 866                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 867                 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 868                 break;
 869         case 12:
 870                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 871                                   PM3RD_PixelSize_16_BIT_PIXELS);
 872                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 873                                   PM3RD_ColorFormat_4444_COLOR |
 874                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 875                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 876                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 877                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 878                 break;
 879         case 15:
 880                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 881                                   PM3RD_PixelSize_16_BIT_PIXELS);
 882                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 883                                   PM3RD_ColorFormat_5551_FRONT_COLOR |
 884                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 885                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 886                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 887                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 888                 break;
 889         case 16:
 890                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 891                                   PM3RD_PixelSize_16_BIT_PIXELS);
 892                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 893                                   PM3RD_ColorFormat_565_FRONT_COLOR |
 894                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 895                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 896                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 897                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 898                 break;
 899         case 32:
 900                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 901                                   PM3RD_PixelSize_32_BIT_PIXELS);
 902                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 903                                   PM3RD_ColorFormat_8888_COLOR |
 904                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 905                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 906                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 907                 break;
 908         }
 909         PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
 910 }
 911
 912 /*
 913  * hardware independent functions
 914  */
 915 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 916 {
 917         u32 lpitch;
 918         unsigned bpp = var->red.length + var->green.length
 919                         + var->blue.length + var->transp.length;
 920
 921         if (bpp != var->bits_per_pixel) {
 922                 /* set predefined mode for bits_per_pixel settings */
 923
 924                 switch (var->bits_per_pixel) {
 925                 case 8:
 926                         var->red.length = 8;
 927                         var->green.length = 8;
 928                         var->blue.length = 8;
 929                         var->red.offset = 0;
 930                         var->green.offset = 0;
 931                         var->blue.offset = 0;
 932                         var->transp.offset = 0;
 933                         var->transp.length = 0;
 934                         break;
 935                 case 16:
 936                         var->red.length = 5;
 937                         var->blue.length = 5;
 938                         var->green.length = 6;
 939                         var->transp.length = 0;
 940                         break;
 941                 case 32:
 942                         var->red.length = 8;
 943                         var->green.length = 8;
 944                         var->blue.length = 8;
 945                         var->transp.length = 8;
 946                         break;
 947                 default:
 948                         DPRINTK("depth not supported: %u\n",
 949                                 var->bits_per_pixel);
 950                         return -EINVAL;
 951                 }
 952         }
 953         /* it is assumed BGRA order */
 954         if (var->bits_per_pixel > 8 ) {
 955                 var->blue.offset = 0;
 956                 var->green.offset = var->blue.length;
 957                 var->red.offset = var->green.offset + var->green.length;
 958                 var->transp.offset = var->red.offset + var->red.length;
 959         }
 960         var->height = -1;
 961         var->width = -1;
 962
 963         if (var->xres != var->xres_virtual) {
 964                 DPRINTK("virtual x resolution != "
 965                         "physical x resolution not supported\n");
 966                 return -EINVAL;
 967         }
 968
 969         if (var->yres > var->yres_virtual) {
 970                 DPRINTK("virtual y resolution < "
 971                         "physical y resolution not possible\n");
 972                 return -EINVAL;
 973         }
 974
 975         if (var->xoffset) {
 976                 DPRINTK("xoffset not supported\n");
 977                 return -EINVAL;
 978         }
 979
 980         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 981                 DPRINTK("interlace not supported\n");
 982                 return -EINVAL;
 983         }
 984
 985         var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
 986         lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
 987
 988         if (var->xres < 200 || var->xres > 2048) {
 989                 DPRINTK("width not supported: %u\n", var->xres);
 990                 return -EINVAL;
 991         }
 992
 993         if (var->yres < 200 || var->yres > 4095) {
 994                 DPRINTK("height not supported: %u\n", var->yres);
 995                 return -EINVAL;
 996         }
 997
 998         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 999                 DPRINTK("no memory for screen (%ux%ux%u)\n",
1000                         var->xres, var->yres_virtual, var->bits_per_pixel);
1001                 return -EINVAL;
1002         }
1003
1004         if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
1005                 DPRINTK("pixclock too high (%ldKHz)\n",
1006                         PICOS2KHZ(var->pixclock));
1007                 return -EINVAL;
1008         }
1009
1010         var->accel_flags = 0;   /* Can't mmap if this is on */
1011
1012         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
1013                 var->xres, var->yres, var->bits_per_pixel);
1014         return 0;
1015 }
1016
1017 static int pm3fb_set_par(struct fb_info *info)
1018 {
1019         struct pm3_par *par = info->par;
1020         const u32 xres = (info->var.xres + 31) & ~31;
1021         const unsigned bpp = info->var.bits_per_pixel;
1022
1023         par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
1024                                         + info->var.xoffset);
1025         par->video = 0;
1026
1027         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
1028                 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
1029         else
1030                 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
1031
1032         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
1033                 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
1034         else
1035                 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
1036
1037         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
1038                 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
1039
1040         if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1041                 par->video |= PM3VideoControl_ENABLE;
1042         else
1043                 DPRINTK("PM3Video disabled\n");
1044
1045         switch (bpp) {
1046         case 8:
1047                 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
1048                 break;
1049         case 16:
1050                 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
1051                 break;
1052         case 32:
1053                 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
1054                 break;
1055         default:
1056                 DPRINTK("Unsupported depth\n");
1057                 break;
1058         }
1059
1060         info->fix.visual =
1061                 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1062         info->fix.line_length = ((info->var.xres_virtual + 7)  >> 3) * bpp;
1063
1064 /*      pm3fb_clear_memory(info, 0);*/
1065         pm3fb_clear_colormap(par, 0, 0, 0);
1066         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
1067         pm3fb_init_engine(info);
1068         pm3fb_write_mode(info);
1069         return 0;
1070 }
1071
1072 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1073                            unsigned blue, unsigned transp,
1074                            struct fb_info *info)
1075 {
1076         struct pm3_par *par = info->par;
1077
1078         if (regno >= 256)  /* no. of hw registers */
1079            return -EINVAL;
1080
1081         /* grayscale works only partially under directcolor */
1082         /* grayscale = 0.30*R + 0.59*G + 0.11*B */
1083         if (info->var.grayscale)
1084            red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1085
1086         /* Directcolor:
1087          *   var->{color}.offset contains start of bitfield
1088          *   var->{color}.length contains length of bitfield
1089          *   {hardwarespecific} contains width of DAC
1090          *   pseudo_palette[X] is programmed to (X << red.offset) |
1091          *                                      (X << green.offset) |
1092          *                                      (X << blue.offset)
1093          *   RAMDAC[X] is programmed to (red, green, blue)
1094          *   color depth = SUM(var->{color}.length)
1095          *
1096          * Pseudocolor:
1097          *      var->{color}.offset is 0
1098          *      var->{color}.length contains width of DAC or the number
1099          *                      of unique colors available (color depth)
1100          *      pseudo_palette is not used
1101          *      RAMDAC[X] is programmed to (red, green, blue)
1102          *      color depth = var->{color}.length
1103          */
1104
1105         /*
1106          * This is the point where the color is converted to something that
1107          * is acceptable by the hardware.
1108          */
1109 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
1110         red = CNVT_TOHW(red, info->var.red.length);
1111         green = CNVT_TOHW(green, info->var.green.length);
1112         blue = CNVT_TOHW(blue, info->var.blue.length);
1113         transp = CNVT_TOHW(transp, info->var.transp.length);
1114 #undef CNVT_TOHW
1115
1116         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
1117         info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1118                 u32 v;
1119
1120                 if (regno >= 16)
1121                         return -EINVAL;
1122
1123                 v = (red << info->var.red.offset) |
1124                         (green << info->var.green.offset) |
1125                         (blue << info->var.blue.offset) |
1126                         (transp << info->var.transp.offset);
1127
1128                 switch (info->var.bits_per_pixel) {
1129                 case 8:
1130                         break;
1131                 case 16:
1132                 case 32:
1133                         ((u32 *)(info->pseudo_palette))[regno] = v;
1134                         break;
1135                 }
1136                 return 0;
1137         } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
1138                 pm3fb_set_color(par, regno, red, green, blue);
1139
1140         return 0;
1141 }
1142
1143 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
1144                                  struct fb_info *info)
1145 {
1146         struct pm3_par *par = info->par;
1147         const u32 xres = (var->xres + 31) & ~31;
1148
1149         par->base = pm3fb_shift_bpp(var->bits_per_pixel,
1150                                         (var->yoffset * xres)
1151                                         + var->xoffset);
1152         PM3_WAIT(par, 1);
1153         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1154         return 0;
1155 }
1156
1157 static int pm3fb_blank(int blank_mode, struct fb_info *info)
1158 {
1159         struct pm3_par *par = info->par;
1160         u32 video = par->video;
1161
1162         /*
1163          * Oxygen VX1 - it appears that setting PM3VideoControl and
1164          * then PM3RD_SyncControl to the same SYNC settings undoes
1165          * any net change - they seem to xor together.  Only set the
1166          * sync options in PM3RD_SyncControl.  --rmk
1167          */
1168         video &= ~(PM3VideoControl_HSYNC_MASK |
1169                    PM3VideoControl_VSYNC_MASK);
1170         video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1171                  PM3VideoControl_VSYNC_ACTIVE_HIGH;
1172
1173         switch (blank_mode) {
1174         case FB_BLANK_UNBLANK:
1175                 video |= PM3VideoControl_ENABLE;
1176                 break;
1177         case FB_BLANK_NORMAL:
1178                 video &= ~PM3VideoControl_ENABLE;
1179                 break;
1180         case FB_BLANK_HSYNC_SUSPEND:
1181                 video &= ~(PM3VideoControl_HSYNC_MASK |
1182                           PM3VideoControl_BLANK_ACTIVE_LOW);
1183                 break;
1184         case FB_BLANK_VSYNC_SUSPEND:
1185                 video &= ~(PM3VideoControl_VSYNC_MASK |
1186                           PM3VideoControl_BLANK_ACTIVE_LOW);
1187                 break;
1188         case FB_BLANK_POWERDOWN:
1189                 video &= ~(PM3VideoControl_HSYNC_MASK |
1190                           PM3VideoControl_VSYNC_MASK |
1191                           PM3VideoControl_BLANK_ACTIVE_LOW);
1192                 break;
1193         default:
1194                 DPRINTK("Unsupported blanking %d\n", blank_mode);
1195                 return 1;
1196         }
1197
1198         PM3_WAIT(par, 1);
1199         PM3_WRITE_REG(par, PM3VideoControl, video);
1200         return 0;
1201 }
1202
1203         /*
1204          *  Frame buffer operations
1205          */
1206
1207 static struct fb_ops pm3fb_ops = {
1208         .owner          = THIS_MODULE,
1209         .fb_check_var   = pm3fb_check_var,
1210         .fb_set_par     = pm3fb_set_par,
1211         .fb_setcolreg   = pm3fb_setcolreg,
1212         .fb_pan_display = pm3fb_pan_display,
1213         .fb_fillrect    = pm3fb_fillrect,
1214         .fb_copyarea    = pm3fb_copyarea,
1215         .fb_imageblit   = pm3fb_imageblit,
1216         .fb_blank       = pm3fb_blank,
1217         .fb_sync        = pm3fb_sync,
1218         .fb_cursor      = pm3fb_cursor,
1219 };
1220
1221 /* ------------------------------------------------------------------------- */
1222
1223         /*
1224          *  Initialization
1225          */
1226
1227 /* mmio register are already mapped when this function is called */
1228 /* the pm3fb_fix.smem_start is also set */
1229 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1230 {
1231         unsigned long   memsize = 0;
1232         unsigned long   tempBypass, i, temp1, temp2;
1233         unsigned char   __iomem *screen_mem;
1234
1235         pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1236         /* Linear frame buffer - request region and map it. */
1237         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1238                                  "pm3fb smem")) {
1239                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1240                 return 0;
1241         }
1242         screen_mem =
1243                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1244         if (!screen_mem) {
1245                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1246                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1247                 return 0;
1248         }
1249
1250         /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1251         /* For Appian Jeronimo 2000 board second head */
1252
1253         tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1254
1255         DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1256
1257         PM3_WAIT(par, 1);
1258         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1259
1260         /* pm3 split up memory, replicates, and do a lot of
1261          * nasty stuff IMHO ;-)
1262          */
1263         for (i = 0; i < 32; i++) {
1264                 fb_writel(i * 0x00345678,
1265                           (screen_mem + (i * 1048576)));
1266                 mb();
1267                 temp1 = fb_readl((screen_mem + (i * 1048576)));
1268
1269                 /* Let's check for wrapover, write will fail at 16MB boundary */
1270                 if (temp1 == (i * 0x00345678))
1271                         memsize = i;
1272                 else
1273                         break;
1274         }
1275
1276         DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1277
1278         if (memsize + 1 == i) {
1279                 for (i = 0; i < 32; i++) {
1280                         /* Clear first 32MB ; 0 is 0, no need to byteswap */
1281                         writel(0x0000000, (screen_mem + (i * 1048576)));
1282                 }
1283                 wmb();
1284
1285                 for (i = 32; i < 64; i++) {
1286                         fb_writel(i * 0x00345678,
1287                                   (screen_mem + (i * 1048576)));
1288                         mb();
1289                         temp1 =
1290                             fb_readl((screen_mem + (i * 1048576)));
1291                         temp2 =
1292                             fb_readl((screen_mem + ((i - 32) * 1048576)));
1293                         /* different value, different RAM... */
1294                         if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1295                                 memsize = i;
1296                         else
1297                                 break;
1298                 }
1299         }
1300         DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1301
1302         PM3_WAIT(par, 1);
1303         PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1304
1305         iounmap(screen_mem);
1306         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1307         memsize = 1048576 * (memsize + 1);
1308
1309         DPRINTK("Returning 0x%08lx bytes\n", memsize);
1310
1311         return memsize;
1312 }
1313
1314 static int __devinit pm3fb_probe(struct pci_dev *dev,
1315                                   const struct pci_device_id *ent)
1316 {
1317         struct fb_info *info;
1318         struct pm3_par *par;
1319         struct device *device = &dev->dev; /* for pci drivers */
1320         int err;
1321         int retval = -ENXIO;
1322
1323         err = pci_enable_device(dev);
1324         if (err) {
1325                 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1326                 return err;
1327         }
1328         /*
1329          * Dynamically allocate info and par
1330          */
1331         info = framebuffer_alloc(sizeof(struct pm3_par), device);
1332
1333         if (!info)
1334                 return -ENOMEM;
1335         par = info->par;
1336
1337         /*
1338          * Here we set the screen_base to the virtual memory address
1339          * for the framebuffer.
1340          */
1341         pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1342         pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1343 #if defined(__BIG_ENDIAN)
1344         pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1345         DPRINTK("Adjusting register base for big-endian.\n");
1346 #endif
1347
1348         /* Registers - request region and map it. */
1349         if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1350                                  "pm3fb regbase")) {
1351                 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1352                 goto err_exit_neither;
1353         }
1354         par->v_regs =
1355                 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1356         if (!par->v_regs) {
1357                 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1358                         pm3fb_fix.id);
1359                 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1360                 goto err_exit_neither;
1361         }
1362
1363         /* Linear frame buffer - request region and map it. */
1364         pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1365         pm3fb_fix.smem_len = pm3fb_size_memory(par);
1366         if (!pm3fb_fix.smem_len) {
1367                 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1368                 goto err_exit_mmio;
1369         }
1370         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1371                                  "pm3fb smem")) {
1372                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1373                 goto err_exit_mmio;
1374         }
1375         info->screen_base =
1376                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1377         if (!info->screen_base) {
1378                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1379                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1380                 goto err_exit_mmio;
1381         }
1382         info->screen_size = pm3fb_fix.smem_len;
1383
1384 #ifdef CONFIG_MTRR
1385         if (!nomtrr)
1386                 par->mtrr_handle = mtrr_add(pm3fb_fix.smem_start,
1387                                                 pm3fb_fix.smem_len,
1388                                                 MTRR_TYPE_WRCOMB, 1);
1389 #endif
1390         info->fbops = &pm3fb_ops;
1391
1392         par->video = PM3_READ_REG(par, PM3VideoControl);
1393
1394         info->fix = pm3fb_fix;
1395         info->pseudo_palette = par->palette;
1396         info->flags = FBINFO_DEFAULT |
1397                         FBINFO_HWACCEL_XPAN |
1398                         FBINFO_HWACCEL_YPAN |
1399                         FBINFO_HWACCEL_COPYAREA |
1400                         FBINFO_HWACCEL_IMAGEBLIT |
1401                         FBINFO_HWACCEL_FILLRECT;
1402
1403         if (noaccel) {
1404                 printk(KERN_DEBUG "disabling acceleration\n");
1405                 info->flags |= FBINFO_HWACCEL_DISABLED;
1406         }
1407         info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
1408         if (!info->pixmap.addr) {
1409                 retval = -ENOMEM;
1410                 goto err_exit_pixmap;
1411         }
1412         info->pixmap.size = PM3_PIXMAP_SIZE;
1413         info->pixmap.buf_align = 4;
1414         info->pixmap.scan_align = 4;
1415         info->pixmap.access_align = 32;
1416         info->pixmap.flags = FB_PIXMAP_SYSTEM;
1417
1418         /*
1419          * This should give a reasonable default video mode. The following is
1420          * done when we can set a video mode.
1421          */
1422         if (!mode_option)
1423                 mode_option = "640x480@60";
1424
1425         retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1426
1427         if (!retval || retval == 4) {
1428                 retval = -EINVAL;
1429                 goto err_exit_both;
1430         }
1431
1432         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1433                 retval = -ENOMEM;
1434                 goto err_exit_both;
1435         }
1436
1437         /*
1438          * For drivers that can...
1439          */
1440         pm3fb_check_var(&info->var, info);
1441
1442         if (register_framebuffer(info) < 0) {
1443                 retval = -EINVAL;
1444                 goto err_exit_all;
1445         }
1446         printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1447            info->fix.id);
1448         pci_set_drvdata(dev, info);
1449         return 0;
1450
1451  err_exit_all:
1452         fb_dealloc_cmap(&info->cmap);
1453  err_exit_both:
1454         kfree(info->pixmap.addr);
1455  err_exit_pixmap:
1456         iounmap(info->screen_base);
1457         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1458  err_exit_mmio:
1459         iounmap(par->v_regs);
1460         release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1461  err_exit_neither:
1462         framebuffer_release(info);
1463         return retval;
1464 }
1465
1466         /*
1467          *  Cleanup
1468          */
1469 static void __devexit pm3fb_remove(struct pci_dev *dev)
1470 {
1471         struct fb_info *info = pci_get_drvdata(dev);
1472
1473         if (info) {
1474                 struct fb_fix_screeninfo *fix = &info->fix;
1475                 struct pm3_par *par = info->par;
1476
1477                 unregister_framebuffer(info);
1478                 fb_dealloc_cmap(&info->cmap);
1479
1480 #ifdef CONFIG_MTRR
1481         if (par->mtrr_handle >= 0)
1482                 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1483                          info->fix.smem_len);
1484 #endif /* CONFIG_MTRR */
1485                 iounmap(info->screen_base);
1486                 release_mem_region(fix->smem_start, fix->smem_len);
1487                 iounmap(par->v_regs);
1488                 release_mem_region(fix->mmio_start, fix->mmio_len);
1489
1490                 pci_set_drvdata(dev, NULL);
1491                 kfree(info->pixmap.addr);
1492                 framebuffer_release(info);
1493         }
1494 }
1495
1496 static struct pci_device_id pm3fb_id_table[] = {
1497         { PCI_VENDOR_ID_3DLABS, 0x0a,
1498           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1499         { 0, }
1500 };
1501
1502 /* For PCI drivers */
1503 static struct pci_driver pm3fb_driver = {
1504         .name =         "pm3fb",
1505         .id_table =     pm3fb_id_table,
1506         .probe =        pm3fb_probe,
1507         .remove =       __devexit_p(pm3fb_remove),
1508 };
1509
1510 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1511
1512 #ifndef MODULE
1513         /*
1514          *  Setup
1515          */
1516
1517 /*
1518  * Only necessary if your driver takes special options,
1519  * otherwise we fall back on the generic fb_setup().
1520  */
1521 static int __init pm3fb_setup(char *options)
1522 {
1523         char *this_opt;
1524
1525         /* Parse user speficied options (`video=pm3fb:') */
1526         if (!options || !*options)
1527                 return 0;
1528
1529         while ((this_opt = strsep(&options, ",")) != NULL) {
1530                 if (!*this_opt)
1531                         continue;
1532                 else if (!strncmp(this_opt, "noaccel", 7))
1533                         noaccel = 1;
1534                 else if (!strncmp(this_opt, "hwcursor=", 9))
1535                         hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1536 #ifdef CONFIG_MTRR
1537                 else if (!strncmp(this_opt, "nomtrr", 6))
1538                         nomtrr = 1;
1539 #endif
1540                 else
1541                         mode_option = this_opt;
1542         }
1543         return 0;
1544 }
1545 #endif /* MODULE */
1546
1547 static int __init pm3fb_init(void)
1548 {
1549         /*
1550          *  For kernel boot options (in 'video=pm3fb:<options>' format)
1551          */
1552 #ifndef MODULE
1553         char *option = NULL;
1554
1555         if (fb_get_options("pm3fb", &option))
1556                 return -ENODEV;
1557         pm3fb_setup(option);
1558 #endif
1559
1560         return pci_register_driver(&pm3fb_driver);
1561 }
1562
1563 #ifdef MODULE
1564 static void __exit pm3fb_exit(void)
1565 {
1566         pci_unregister_driver(&pm3fb_driver);
1567 }
1568
1569 module_exit(pm3fb_exit);
1570 #endif
1571 module_init(pm3fb_init);
1572
1573 module_param(noaccel, bool, 0);
1574 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1575 module_param(hwcursor, int, 0644);
1576 MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1577                         "(1=enable, 0=disable, default=1)");
1578 #ifdef CONFIG_MTRR
1579 module_param(nomtrr, bool, 0);
1580 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1581 #endif
1582
1583 MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
1584 MODULE_LICENSE("GPL");