SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/nvidia/nv_setup.c

   1  /***************************************************************************\
   2 |*                                                                           *|
   3 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
   4 |*                                                                           *|
   5 |*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
   6 |*     international laws.  Users and possessors of this source code are     *|
   7 |*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
   8 |*     use this code in individual and commercial software.                  *|
   9 |*                                                                           *|
  10 |*     Any use of this source code must include,  in the user documenta-     *|
  11 |*     tion and  internal comments to the code,  notices to the end user     *|
  12 |*     as follows:                                                           *|
  13 |*                                                                           *|
  14 |*       Copyright 2003 NVIDIA, Corporation.  All rights reserved.           *|
  15 |*                                                                           *|
  16 |*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
  17 |*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
  18 |*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
  19 |*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
  20 |*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
  21 |*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
  22 |*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
  23 |*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
  24 |*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
  25 |*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
  26 |*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
  27 |*                                                                           *|
  28 |*     U.S. Government  End  Users.   This source code  is a "commercial     *|
  29 |*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
  30 |*     consisting  of "commercial  computer  software"  and  "commercial     *|
  31 |*     computer  software  documentation,"  as such  terms  are  used in     *|
  32 |*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
  33 |*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
  34 |*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
  35 |*     all U.S. Government End Users  acquire the source code  with only     *|
  36 |*     those rights set forth herein.                                        *|
  37 |*                                                                           *|
  38  \***************************************************************************/
  39
  40 /*
  41  * GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
  42  * XFree86 'nv' driver, this source code is provided under MIT-style licensing
  43  * where the source code is provided "as is" without warranty of any kind.
  44  * The only usage restriction is for the copyright notices to be retained
  45  * whenever code is used.
  46  *
  47  * Antonino Daplas <adaplas@pol.net> 2005-03-11
  48  */
  49
  50 #include <video/vga.h>
  51 #include <linux/delay.h>
  52 #include <linux/pci.h>
  53 #include "nv_type.h"
  54 #include "nv_local.h"
  55 #include "nv_proto.h"
  56 /*
  57  * Override VGA I/O routines.
  58  */
  59 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
  60 {
  61         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
  62         VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
  63 }
  64 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
  65 {
  66         VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
  67         return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
  68 }
  69 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
  70 {
  71         VGA_WR08(par->PVIO, VGA_GFX_I, index);
  72         VGA_WR08(par->PVIO, VGA_GFX_D, value);
  73 }
  74 u8 NVReadGr(struct nvidia_par *par, u8 index)
  75 {
  76         VGA_WR08(par->PVIO, VGA_GFX_I, index);
  77         return (VGA_RD08(par->PVIO, VGA_GFX_D));
  78 }
  79 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
  80 {
  81         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
  82         VGA_WR08(par->PVIO, VGA_SEQ_D, value);
  83 }
  84 u8 NVReadSeq(struct nvidia_par *par, u8 index)
  85 {
  86         VGA_WR08(par->PVIO, VGA_SEQ_I, index);
  87         return (VGA_RD08(par->PVIO, VGA_SEQ_D));
  88 }
  89 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
  90 {
  91         volatile u8 tmp;
  92
  93         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
  94         if (par->paletteEnabled)
  95                 index &= ~0x20;
  96         else
  97                 index |= 0x20;
  98         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
  99         VGA_WR08(par->PCIO, VGA_ATT_W, value);
 100 }
 101 u8 NVReadAttr(struct nvidia_par *par, u8 index)
 102 {
 103         volatile u8 tmp;
 104
 105         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
 106         if (par->paletteEnabled)
 107                 index &= ~0x20;
 108         else
 109                 index |= 0x20;
 110         VGA_WR08(par->PCIO, VGA_ATT_IW, index);
 111         return (VGA_RD08(par->PCIO, VGA_ATT_R));
 112 }
 113 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
 114 {
 115         VGA_WR08(par->PVIO, VGA_MIS_W, value);
 116 }
 117 u8 NVReadMiscOut(struct nvidia_par *par)
 118 {
 119         return (VGA_RD08(par->PVIO, VGA_MIS_R));
 120 }
 121 #if 0
 122 void NVEnablePalette(struct nvidia_par *par)
 123 {
 124         volatile u8 tmp;
 125
 126         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
 127         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
 128         par->paletteEnabled = 1;
 129 }
 130 void NVDisablePalette(struct nvidia_par *par)
 131 {
 132         volatile u8 tmp;
 133
 134         tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
 135         VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
 136         par->paletteEnabled = 0;
 137 }
 138 #endif  /*  0  */
 139 void NVWriteDacMask(struct nvidia_par *par, u8 value)
 140 {
 141         VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
 142 }
 143 #if 0
 144 u8 NVReadDacMask(struct nvidia_par *par)
 145 {
 146         return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
 147 }
 148 #endif  /*  0  */
 149 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
 150 {
 151         VGA_WR08(par->PDIO, VGA_PEL_IR, value);
 152 }
 153 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
 154 {
 155         VGA_WR08(par->PDIO, VGA_PEL_IW, value);
 156 }
 157 void NVWriteDacData(struct nvidia_par *par, u8 value)
 158 {
 159         VGA_WR08(par->PDIO, VGA_PEL_D, value);
 160 }
 161 u8 NVReadDacData(struct nvidia_par *par)
 162 {
 163         return (VGA_RD08(par->PDIO, VGA_PEL_D));
 164 }
 165
 166 static int NVIsConnected(struct nvidia_par *par, int output)
 167 {
 168         volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
 169         u32 reg52C, reg608;
 170         int present;
 171
 172         if (output)
 173                 PRAMDAC += 0x800;
 174
 175         reg52C = NV_RD32(PRAMDAC, 0x052C);
 176         reg608 = NV_RD32(PRAMDAC, 0x0608);
 177
 178         NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
 179
 180         NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
 181         msleep(1);
 182         NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
 183
 184         NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
 185         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
 186                 0x00001000);
 187
 188         msleep(1);
 189
 190         present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
 191
 192         if (present)
 193                 printk("nvidiafb: CRTC%i analog found\n", output);
 194         else
 195                 printk("nvidiafb: CRTC%i analog not found\n", output);
 196
 197         NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) &
 198                 0x0000EFFF);
 199
 200         NV_WR32(PRAMDAC, 0x052C, reg52C);
 201         NV_WR32(PRAMDAC, 0x0608, reg608);
 202
 203         return present;
 204 }
 205
 206 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
 207 {
 208         if (head) {
 209                 par->PCIO = par->PCIO0 + 0x2000;
 210                 par->PCRTC = par->PCRTC0 + 0x800;
 211                 par->PRAMDAC = par->PRAMDAC0 + 0x800;
 212                 par->PDIO = par->PDIO0 + 0x2000;
 213         } else {
 214                 par->PCIO = par->PCIO0;
 215                 par->PCRTC = par->PCRTC0;
 216                 par->PRAMDAC = par->PRAMDAC0;
 217                 par->PDIO = par->PDIO0;
 218         }
 219 }
 220
 221 static void nv4GetConfig(struct nvidia_par *par)
 222 {
 223         if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
 224                 par->RamAmountKBytes =
 225                     ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
 226                     1024 * 2;
 227         } else {
 228                 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
 229                 case 0:
 230                         par->RamAmountKBytes = 1024 * 32;
 231                         break;
 232                 case 1:
 233                         par->RamAmountKBytes = 1024 * 4;
 234                         break;
 235                 case 2:
 236                         par->RamAmountKBytes = 1024 * 8;
 237                         break;
 238                 case 3:
 239                 default:
 240                         par->RamAmountKBytes = 1024 * 16;
 241                         break;
 242                 }
 243         }
 244         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
 245             14318 : 13500;
 246         par->CURSOR = &par->PRAMIN[0x1E00];
 247         par->MinVClockFreqKHz = 12000;
 248         par->MaxVClockFreqKHz = 350000;
 249 }
 250
 251 static void nv10GetConfig(struct nvidia_par *par)
 252 {
 253         struct pci_dev *dev;
 254         u32 implementation = par->Chipset & 0x0ff0;
 255
 256 #ifdef __BIG_ENDIAN
 257         /* turn on big endian register access */
 258         if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
 259                 NV_WR32(par->PMC, 0x0004, 0x01000001);
 260                 mb();
 261         }
 262 #endif
 263
 264         dev = pci_find_slot(0, 1);
 265         if ((par->Chipset && 0xffff) == 0x01a0) {
 266                 int amt = 0;
 267
 268                 pci_read_config_dword(dev, 0x7c, &amt);
 269                 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
 270         } else if ((par->Chipset & 0xffff) == 0x01f0) {
 271                 int amt = 0;
 272
 273                 pci_read_config_dword(dev, 0x84, &amt);
 274                 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
 275         } else {
 276                 par->RamAmountKBytes =
 277                     (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
 278         }
 279
 280         par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
 281             14318 : 13500;
 282
 283         if (par->twoHeads && (implementation != 0x0110)) {
 284                 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
 285                         par->CrystalFreqKHz = 27000;
 286         }
 287
 288         par->CursorStart = (par->RamAmountKBytes - 96) * 1024;
 289         par->CURSOR = NULL;     /* can't set this here */
 290         par->MinVClockFreqKHz = 12000;
 291         par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
 292 }
 293
 294 void NVCommonSetup(struct fb_info *info)
 295 {
 296         struct nvidia_par *par = info->par;
 297         struct fb_var_screeninfo var;
 298         u16 implementation = par->Chipset & 0x0ff0;
 299         u8 *edidA = NULL, *edidB = NULL;
 300         struct fb_monspecs monitorA, monitorB;
 301         struct fb_monspecs *monA = NULL, *monB = NULL;
 302         int mobile = 0;
 303         int tvA = 0;
 304         int tvB = 0;
 305         int FlatPanel = -1;     /* really means the CRTC is slaved */
 306         int Television = 0;
 307
 308         memset(&monitorA, 0, sizeof(struct fb_monspecs));
 309         memset(&monitorB, 0, sizeof(struct fb_monspecs));
 310
 311         par->PRAMIN = par->REGS + (0x00710000 / 4);
 312         par->PCRTC0 = par->REGS + (0x00600000 / 4);
 313         par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
 314         par->PFB = par->REGS + (0x00100000 / 4);
 315         par->PFIFO = par->REGS + (0x00002000 / 4);
 316         par->PGRAPH = par->REGS + (0x00400000 / 4);
 317         par->PEXTDEV = par->REGS + (0x00101000 / 4);
 318         par->PTIMER = par->REGS + (0x00009000 / 4);
 319         par->PMC = par->REGS + (0x00000000 / 4);
 320         par->FIFO = par->REGS + (0x00800000 / 4);
 321
 322         /* 8 bit registers */
 323         par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
 324         par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
 325         par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
 326
 327         par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
 328             (implementation != 0x0100) &&
 329             (implementation != 0x0150) &&
 330             (implementation != 0x01A0) && (implementation != 0x0200);
 331
 332         par->fpScaler = (par->FpScale && par->twoHeads &&
 333                          (implementation != 0x0110));
 334
 335         par->twoStagePLL = (implementation == 0x0310) ||
 336             (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
 337
 338         par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
 339             (implementation != 0x0100);
 340
 341         par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
 342
 343         /* look for known laptop chips */
 344         switch (par->Chipset & 0xffff) {
 345         case 0x0112:
 346         case 0x0174:
 347         case 0x0175:
 348         case 0x0176:
 349         case 0x0177:
 350         case 0x0179:
 351         case 0x017C:
 352         case 0x017D:
 353         case 0x0186:
 354         case 0x0187:
 355         case 0x018D:
 356         case 0x0286:
 357         case 0x028C:
 358         case 0x0316:
 359         case 0x0317:
 360         case 0x031A:
 361         case 0x031B:
 362         case 0x031C:
 363         case 0x031D:
 364         case 0x031E:
 365         case 0x031F:
 366         case 0x0324:
 367         case 0x0325:
 368         case 0x0328:
 369         case 0x0329:
 370         case 0x032C:
 371         case 0x032D:
 372         case 0x0347:
 373         case 0x0348:
 374         case 0x0349:
 375         case 0x034B:
 376         case 0x034C:
 377         case 0x0160:
 378         case 0x0166:
 379         case 0x00C8:
 380         case 0x00CC:
 381         case 0x0144:
 382         case 0x0146:
 383         case 0x0147:
 384         case 0x0148:
 385                 mobile = 1;
 386                 break;
 387         default:
 388                 break;
 389         }
 390
 391         if (par->Architecture == NV_ARCH_04)
 392                 nv4GetConfig(par);
 393         else
 394                 nv10GetConfig(par);
 395
 396         NVSelectHeadRegisters(par, 0);
 397
 398         NVLockUnlock(par, 0);
 399
 400         par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
 401
 402         par->Television = 0;
 403
 404         nvidia_create_i2c_busses(par);
 405         if (!par->twoHeads) {
 406                 par->CRTCnumber = 0;
 407                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
 408                         nvidia_probe_of_connector(info, 1, &edidA);
 409                 if (edidA && !fb_parse_edid(edidA, &var)) {
 410                         printk("nvidiafb: EDID found from BUS1\n");
 411                         monA = &monitorA;
 412                         fb_edid_to_monspecs(edidA, monA);
 413                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
 414
 415                         /* NV4 doesn't support FlatPanels */
 416                         if ((par->Chipset & 0x0fff) <= 0x0020)
 417                                 FlatPanel = 0;
 418                 } else {
 419                         VGA_WR08(par->PCIO, 0x03D4, 0x28);
 420                         if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
 421                                 VGA_WR08(par->PCIO, 0x03D4, 0x33);
 422                                 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
 423                                         Television = 1;
 424                                 FlatPanel = 1;
 425                         } else {
 426                                 FlatPanel = 0;
 427                         }
 428                         printk("nvidiafb: HW is currently programmed for %s\n",
 429                                FlatPanel ? (Television ? "TV" : "DFP") :
 430                                "CRT");
 431                 }
 432
 433                 if (par->FlatPanel == -1) {
 434                         par->FlatPanel = FlatPanel;
 435                         par->Television = Television;
 436                 } else {
 437                         printk("nvidiafb: Forcing display type to %s as "
 438                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
 439                 }
 440         } else {
 441                 u8 outputAfromCRTC, outputBfromCRTC;
 442                 int CRTCnumber = -1;
 443                 u8 slaved_on_A, slaved_on_B;
 444                 int analog_on_A, analog_on_B;
 445                 u32 oldhead;
 446                 u8 cr44;
 447
 448                 if (implementation != 0x0110) {
 449                         if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
 450                                 outputAfromCRTC = 1;
 451                         else
 452                                 outputAfromCRTC = 0;
 453                         if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
 454                                 outputBfromCRTC = 1;
 455                         else
 456                                 outputBfromCRTC = 0;
 457                         analog_on_A = NVIsConnected(par, 0);
 458                         analog_on_B = NVIsConnected(par, 1);
 459                 } else {
 460                         outputAfromCRTC = 0;
 461                         outputBfromCRTC = 1;
 462                         analog_on_A = 0;
 463                         analog_on_B = 0;
 464                 }
 465
 466                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
 467                 cr44 = VGA_RD08(par->PCIO, 0x03D5);
 468
 469                 VGA_WR08(par->PCIO, 0x03D5, 3);
 470                 NVSelectHeadRegisters(par, 1);
 471                 NVLockUnlock(par, 0);
 472
 473                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
 474                 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
 475                 if (slaved_on_B) {
 476                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
 477                         tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
 478                 }
 479
 480                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
 481                 VGA_WR08(par->PCIO, 0x03D5, 0);
 482                 NVSelectHeadRegisters(par, 0);
 483                 NVLockUnlock(par, 0);
 484
 485                 VGA_WR08(par->PCIO, 0x03D4, 0x28);
 486                 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
 487                 if (slaved_on_A) {
 488                         VGA_WR08(par->PCIO, 0x03D4, 0x33);
 489                         tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
 490                 }
 491
 492                 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
 493                 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
 494
 495                 if (nvidia_probe_i2c_connector(info, 1, &edidA))
 496                         nvidia_probe_of_connector(info, 1, &edidA);
 497                 if (edidA && !fb_parse_edid(edidA, &var)) {
 498                         printk("nvidiafb: EDID found from BUS1\n");
 499                         monA = &monitorA;
 500                         fb_edid_to_monspecs(edidA, monA);
 501                 }
 502
 503                 if (nvidia_probe_i2c_connector(info, 2, &edidB))
 504                         nvidia_probe_of_connector(info, 2, &edidB);
 505                 if (edidB && !fb_parse_edid(edidB, &var)) {
 506                         printk("nvidiafb: EDID found from BUS2\n");
 507                         monB = &monitorB;
 508                         fb_edid_to_monspecs(edidB, monB);
 509                 }
 510
 511                 if (slaved_on_A && !tvA) {
 512                         CRTCnumber = 0;
 513                         FlatPanel = 1;
 514                         printk("nvidiafb: CRTC 0 is currently programmed for "
 515                                "DFP\n");
 516                 } else if (slaved_on_B && !tvB) {
 517                         CRTCnumber = 1;
 518                         FlatPanel = 1;
 519                         printk("nvidiafb: CRTC 1 is currently programmed "
 520                                "for DFP\n");
 521                 } else if (analog_on_A) {
 522                         CRTCnumber = outputAfromCRTC;
 523                         FlatPanel = 0;
 524                         printk("nvidiafb: CRTC %i appears to have a "
 525                                "CRT attached\n", CRTCnumber);
 526                 } else if (analog_on_B) {
 527                         CRTCnumber = outputBfromCRTC;
 528                         FlatPanel = 0;
 529                         printk("nvidiafb: CRTC %i"
 530                                "appears to have a "
 531                                "CRT attached\n", CRTCnumber);
 532                 } else if (slaved_on_A) {
 533                         CRTCnumber = 0;
 534                         FlatPanel = 1;
 535                         Television = 1;
 536                         printk("nvidiafb: CRTC 0 is currently programmed "
 537                                "for TV\n");
 538                 } else if (slaved_on_B) {
 539                         CRTCnumber = 1;
 540                         FlatPanel = 1;
 541                         Television = 1;
 542                         printk("nvidiafb: CRTC 1 is currently programmed for "
 543                                "TV\n");
 544                 } else if (monA) {
 545                         FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
 546                 } else if (monB) {
 547                         FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
 548                 }
 549
 550                 if (par->FlatPanel == -1) {
 551                         if (FlatPanel != -1) {
 552                                 par->FlatPanel = FlatPanel;
 553                                 par->Television = Television;
 554                         } else {
 555                                 printk("nvidiafb: Unable to detect display "
 556                                        "type...\n");
 557                                 if (mobile) {
 558                                         printk("...On a laptop, assuming "
 559                                                "DFP\n");
 560                                         par->FlatPanel = 1;
 561                                 } else {
 562                                         printk("...Using default of CRT\n");
 563                                         par->FlatPanel = 0;
 564                                 }
 565                         }
 566                 } else {
 567                         printk("nvidiafb: Forcing display type to %s as "
 568                                "specified\n", par->FlatPanel ? "DFP" : "CRT");
 569                 }
 570
 571                 if (par->CRTCnumber == -1) {
 572                         if (CRTCnumber != -1)
 573                                 par->CRTCnumber = CRTCnumber;
 574                         else {
 575                                 printk("nvidiafb: Unable to detect which "
 576                                        "CRTCNumber...\n");
 577                                 if (par->FlatPanel)
 578                                         par->CRTCnumber = 1;
 579                                 else
 580                                         par->CRTCnumber = 0;
 581                                 printk("...Defaulting to CRTCNumber %i\n",
 582                                        par->CRTCnumber);
 583                         }
 584                 } else {
 585                         printk("nvidiafb: Forcing CRTCNumber %i as "
 586                                "specified\n", par->CRTCnumber);
 587                 }
 588
 589                 if (monA) {
 590                         if (((monA->input & FB_DISP_DDI) &&
 591                              par->FlatPanel) ||
 592                             ((!(monA->input & FB_DISP_DDI)) &&
 593                              !par->FlatPanel)) {
 594                                 if (monB) {
 595                                         fb_destroy_modedb(monB->modedb);
 596                                         monB = NULL;
 597                                 }
 598                         } else {
 599                                 fb_destroy_modedb(monA->modedb);
 600                                 monA = NULL;
 601                         }
 602                 }
 603
 604                 if (monB) {
 605                         if (((monB->input & FB_DISP_DDI) &&
 606                              !par->FlatPanel) ||
 607                             ((!(monB->input & FB_DISP_DDI)) &&
 608                              par->FlatPanel)) {
 609                                 fb_destroy_modedb(monB->modedb);
 610                                 monB = NULL;
 611                         } else
 612                                 monA = monB;
 613                 }
 614
 615                 if (implementation == 0x0110)
 616                         cr44 = par->CRTCnumber * 0x3;
 617
 618                 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
 619
 620                 VGA_WR08(par->PCIO, 0x03D4, 0x44);
 621                 VGA_WR08(par->PCIO, 0x03D5, cr44);
 622                 NVSelectHeadRegisters(par, par->CRTCnumber);
 623         }
 624
 625         printk("nvidiafb: Using %s on CRTC %i\n",
 626                par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
 627                par->CRTCnumber);
 628
 629         if (par->FlatPanel && !par->Television) {
 630                 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
 631                 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
 632                 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
 633
 634                 printk("Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
 635         }
 636
 637         if (monA)
 638                 info->monspecs = *monA;
 639
 640         kfree(edidA);
 641         kfree(edidB);
 642 }