2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
79 #include "../macmodes.h"
87 #include <linux/adb.h>
88 #include <linux/pmu.h>
90 #ifdef CONFIG_BOOTX_TEXT
91 #include <asm/btext.h>
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 #include <asm/backlight.h>
106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107 /* - must be large enough to catch all GUI-Regs */
108 /* - must be aligned to a PAGE boundary */
109 #define GUI_RESERVE (1 * PAGE_SIZE)
111 /* FIXME: remove the FAIL definition */
112 #define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
113 #define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
116 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
118 #define DPRINTK(fmt, args...)
121 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
122 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
124 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
125 static const u32 lt_lcd_regs[] = {
132 0, /* EXT_VERT_STRETCH */
137 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
139 if (M64_HAS(LT_LCD_REGS)) {
140 aty_st_le32(lt_lcd_regs[index], val, par);
144 /* write addr byte */
145 temp = aty_ld_le32(LCD_INDEX, par);
146 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
147 /* write the register value */
148 aty_st_le32(LCD_DATA, val, par);
152 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
154 if (M64_HAS(LT_LCD_REGS)) {
155 return aty_ld_le32(lt_lcd_regs[index], par);
159 /* write addr byte */
160 temp = aty_ld_le32(LCD_INDEX, par);
161 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
162 /* read the register value */
163 return aty_ld_le32(LCD_DATA, par);
166 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
168 #ifdef CONFIG_FB_ATY_GENERIC_LCD
172 * Reduce a fraction by factoring out the largest common divider of the
173 * fraction's numerator and denominator.
175 static void ATIReduceRatio(int *Numerator, int *Denominator)
177 int Multiplier, Divider, Remainder;
179 Multiplier = *Numerator;
180 Divider = *Denominator;
182 while ((Remainder = Multiplier % Divider))
184 Multiplier = Divider;
188 *Numerator /= Divider;
189 *Denominator /= Divider;
193 * The Hardware parameters for each card
196 struct aty_cmap_regs {
204 struct pci_mmap_map {
208 unsigned long prot_flag;
209 unsigned long prot_mask;
212 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
214 .type = FB_TYPE_PACKED_PIXELS,
215 .visual = FB_VISUAL_PSEUDOCOLOR,
221 * Frame buffer device API
224 static int atyfb_open(struct fb_info *info, int user);
225 static int atyfb_release(struct fb_info *info, int user);
226 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
227 static int atyfb_set_par(struct fb_info *info);
228 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
229 u_int transp, struct fb_info *info);
230 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
231 static int atyfb_blank(int blank, struct fb_info *info);
232 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
233 u_long arg, struct fb_info *info);
234 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
235 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
236 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
238 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
240 static int atyfb_sync(struct fb_info *info);
246 static int aty_init(struct fb_info *info, const char *name);
248 static int store_video_par(char *videopar, unsigned char m64_num);
251 static struct crtc saved_crtc;
252 static union aty_pll saved_pll;
253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
260 static int read_aty_sense(const struct atyfb_par *par);
265 * Interface used by the world
268 static struct fb_var_screeninfo default_var = {
269 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270 640, 480, 640, 480, 0, 0, 8, 0,
271 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273 0, FB_VMODE_NONINTERLACED
276 static struct fb_videomode defmode = {
277 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279 0, FB_VMODE_NONINTERLACED
282 static struct fb_ops atyfb_ops = {
283 .owner = THIS_MODULE,
284 .fb_open = atyfb_open,
285 .fb_release = atyfb_release,
286 .fb_check_var = atyfb_check_var,
287 .fb_set_par = atyfb_set_par,
288 .fb_setcolreg = atyfb_setcolreg,
289 .fb_pan_display = atyfb_pan_display,
290 .fb_blank = atyfb_blank,
291 .fb_ioctl = atyfb_ioctl,
292 .fb_fillrect = atyfb_fillrect,
293 .fb_copyarea = atyfb_copyarea,
294 .fb_imageblit = atyfb_imageblit,
296 .fb_mmap = atyfb_mmap,
298 .fb_sync = atyfb_sync,
309 static int comp_sync __initdata = -1;
313 static int default_vmode __initdata = VMODE_CHOOSE;
314 static int default_cmode __initdata = CMODE_CHOOSE;
316 module_param_named(vmode, default_vmode, int, 0);
317 MODULE_PARM_DESC(vmode, "int: video mode for mac");
318 module_param_named(cmode, default_cmode, int, 0);
319 MODULE_PARM_DESC(cmode, "int: color mode for mac");
323 static unsigned int mach64_count __initdata = 0;
324 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
325 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
326 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
329 /* top -> down is an evolution of mach64 chipset, any corrections? */
330 #define ATI_CHIP_88800GX (M64F_GX)
331 #define ATI_CHIP_88800CX (M64F_GX)
333 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
334 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
336 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
337 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
339 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
340 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
341 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
343 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
345 /* make sets shorter */
346 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
349 /*#define ATI_CHIP_264GTDVD ?*/
350 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
352 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
353 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
354 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
356 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
357 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
364 } aty_chips[] __devinitdata = {
365 #ifdef CONFIG_FB_ATY_GX
367 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
368 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
369 #endif /* CONFIG_FB_ATY_GX */
371 #ifdef CONFIG_FB_ATY_CT
372 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
373 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
374 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
375 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
376 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
377 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB },
378 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
380 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
381 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
382 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
384 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
386 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
387 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
388 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
389 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
391 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
392 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
393 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
394 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
395 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
397 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
398 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
399 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
400 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
401 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
403 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
404 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
405 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
406 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, ATI_CHIP_264XL },
407 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
408 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
410 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
411 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
412 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
413 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
414 #endif /* CONFIG_FB_ATY_CT */
418 static int __devinit correct_chipset(struct atyfb_par *par)
426 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
427 if (par->pci_id == aty_chips[i].pci_id)
430 name = aty_chips[i].name;
431 par->pll_limits.pll_max = aty_chips[i].pll;
432 par->pll_limits.mclk = aty_chips[i].mclk;
433 par->pll_limits.xclk = aty_chips[i].xclk;
434 par->features = aty_chips[i].features;
436 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
437 type = chip_id & CFG_CHIP_TYPE;
438 rev = (chip_id & CFG_CHIP_REV) >> 24;
440 switch(par->pci_id) {
441 #ifdef CONFIG_FB_ATY_GX
442 case PCI_CHIP_MACH64GX:
446 case PCI_CHIP_MACH64CX:
451 #ifdef CONFIG_FB_ATY_CT
452 case PCI_CHIP_MACH64VT:
455 name = "ATI264VTA3 (Mach64 VT)";
456 par->pll_limits.pll_max = 170;
457 par->pll_limits.mclk = 67;
458 par->pll_limits.xclk = 67;
459 par->features = ATI_CHIP_264VT;
460 } else if(rev == 0x40) {
461 name = "ATI264VTA4 (Mach64 VT)";
462 par->pll_limits.pll_max = 200;
463 par->pll_limits.mclk = 67;
464 par->pll_limits.xclk = 67;
465 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
467 name = "ATI264VTB (Mach64 VT)";
468 par->pll_limits.pll_max = 200;
469 par->pll_limits.mclk = 67;
470 par->pll_limits.xclk = 67;
471 par->features = ATI_CHIP_264VTB;
474 case PCI_CHIP_MACH64GT:
477 par->pll_limits.pll_max = 170;
478 par->pll_limits.mclk = 67;
479 par->pll_limits.xclk = 67;
480 par->features = ATI_CHIP_264GTB;
481 } else if(rev == 0x02) {
482 par->pll_limits.pll_max = 200;
483 par->pll_limits.mclk = 67;
484 par->pll_limits.xclk = 67;
485 par->features = ATI_CHIP_264GTB;
491 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
495 static char ram_dram[] __devinitdata = "DRAM";
496 static char ram_resv[] __devinitdata = "RESV";
497 #ifdef CONFIG_FB_ATY_GX
498 static char ram_vram[] __devinitdata = "VRAM";
499 #endif /* CONFIG_FB_ATY_GX */
500 #ifdef CONFIG_FB_ATY_CT
501 static char ram_edo[] __devinitdata = "EDO";
502 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
503 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
504 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
505 static char ram_off[] __devinitdata = "OFF";
506 #endif /* CONFIG_FB_ATY_CT */
509 static u32 pseudo_palette[17];
511 #ifdef CONFIG_FB_ATY_GX
512 static char *aty_gx_ram[8] __devinitdata = {
513 ram_dram, ram_vram, ram_vram, ram_dram,
514 ram_dram, ram_vram, ram_vram, ram_resv
516 #endif /* CONFIG_FB_ATY_GX */
518 #ifdef CONFIG_FB_ATY_CT
519 static char *aty_ct_ram[8] __devinitdata = {
520 ram_off, ram_dram, ram_edo, ram_edo,
521 ram_sdram, ram_sgram, ram_sdram32, ram_resv
523 #endif /* CONFIG_FB_ATY_CT */
525 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
527 u32 pixclock = var->pixclock;
528 #ifdef CONFIG_FB_ATY_GENERIC_LCD
530 par->pll.ct.xres = 0;
531 if (par->lcd_table != 0) {
532 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
533 if(lcd_on_off & LCD_ON) {
534 par->pll.ct.xres = var->xres;
535 pixclock = par->lcd_pixclock;
542 #if defined(CONFIG_PPC)
545 * Apple monitor sense
548 static int __init read_aty_sense(const struct atyfb_par *par)
552 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
554 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
556 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
557 sense = ((i & 0x3000) >> 3) | (i & 0x100);
559 /* drive each sense line low in turn and collect the other 2 */
560 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
562 i = aty_ld_le32(GP_IO, par);
563 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
564 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
567 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
569 i = aty_ld_le32(GP_IO, par);
570 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
571 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
574 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
576 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
577 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
581 #endif /* defined(CONFIG_PPC) */
583 /* ------------------------------------------------------------------------- */
589 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
591 #ifdef CONFIG_FB_ATY_GENERIC_LCD
592 if (par->lcd_table != 0) {
593 if(!M64_HAS(LT_LCD_REGS)) {
594 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
595 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
597 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
598 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
601 /* switch to non shadow registers */
602 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
603 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
605 /* save stretching */
606 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
607 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
608 if (!M64_HAS(LT_LCD_REGS))
609 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
612 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
613 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
614 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
615 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
616 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
617 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
618 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
620 #ifdef CONFIG_FB_ATY_GENERIC_LCD
621 if (par->lcd_table != 0) {
622 /* switch to shadow registers */
623 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
624 SHADOW_EN | SHADOW_RW_EN, par);
626 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
627 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
628 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
629 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
631 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
633 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
636 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
638 #ifdef CONFIG_FB_ATY_GENERIC_LCD
639 if (par->lcd_table != 0) {
641 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
643 /* update non-shadow registers first */
644 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
645 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
646 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
648 /* temporarily disable stretching */
649 aty_st_lcd(HORZ_STRETCHING,
650 crtc->horz_stretching &
651 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
652 aty_st_lcd(VERT_STRETCHING,
653 crtc->vert_stretching &
654 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
655 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
659 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
661 DPRINTK("setting up CRTC\n");
662 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
663 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
664 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
665 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
667 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
668 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
669 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
670 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
671 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
672 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
673 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
675 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
676 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
677 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
678 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
679 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
680 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
682 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
685 if (par->accel_flags & FB_ACCELF_TEXT)
686 aty_init_engine(par, info);
688 #ifdef CONFIG_FB_ATY_GENERIC_LCD
689 /* after setting the CRTC registers we should set the LCD registers. */
690 if (par->lcd_table != 0) {
691 /* switch to shadow registers */
692 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
693 (SHADOW_EN | SHADOW_RW_EN), par);
695 DPRINTK("set secondary CRT to %ix%i %c%c\n",
696 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
697 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
699 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
700 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
701 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
702 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
704 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
705 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
706 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
707 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
709 /* restore CRTC selection & shadow state and enable stretching */
710 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
711 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
712 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
713 if(!M64_HAS(LT_LCD_REGS))
714 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
716 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
717 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
718 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
719 if(!M64_HAS(LT_LCD_REGS)) {
720 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
721 aty_ld_le32(LCD_INDEX, par);
722 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
725 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
728 static int aty_var_to_crtc(const struct fb_info *info,
729 const struct fb_var_screeninfo *var, struct crtc *crtc)
731 struct atyfb_par *par = (struct atyfb_par *) info->par;
732 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
733 u32 sync, vmode, vdisplay;
734 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
735 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
736 u32 pix_width, dp_pix_width, dp_chain_mask;
741 vxres = var->xres_virtual;
742 vyres = var->yres_virtual;
743 xoffset = var->xoffset;
744 yoffset = var->yoffset;
745 bpp = var->bits_per_pixel;
747 bpp = (var->green.length == 5) ? 15 : 16;
751 /* convert (and round up) and validate */
752 if (vxres < xres + xoffset)
753 vxres = xres + xoffset;
756 if (vyres < yres + yoffset)
757 vyres = yres + yoffset;
762 pix_width = CRTC_PIX_WIDTH_8BPP;
764 HOST_8BPP | SRC_8BPP | DST_8BPP |
765 BYTE_ORDER_LSB_TO_MSB;
766 dp_chain_mask = DP_CHAIN_8BPP;
767 } else if (bpp <= 15) {
769 pix_width = CRTC_PIX_WIDTH_15BPP;
770 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
771 BYTE_ORDER_LSB_TO_MSB;
772 dp_chain_mask = DP_CHAIN_15BPP;
773 } else if (bpp <= 16) {
775 pix_width = CRTC_PIX_WIDTH_16BPP;
776 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
777 BYTE_ORDER_LSB_TO_MSB;
778 dp_chain_mask = DP_CHAIN_16BPP;
779 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
781 pix_width = CRTC_PIX_WIDTH_24BPP;
783 HOST_8BPP | SRC_8BPP | DST_8BPP |
784 BYTE_ORDER_LSB_TO_MSB;
785 dp_chain_mask = DP_CHAIN_24BPP;
786 } else if (bpp <= 32) {
788 pix_width = CRTC_PIX_WIDTH_32BPP;
789 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
790 BYTE_ORDER_LSB_TO_MSB;
791 dp_chain_mask = DP_CHAIN_32BPP;
795 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
796 FAIL("not enough video RAM");
798 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
799 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
801 if((xres > 1600) || (yres > 1200)) {
802 FAIL("MACH64 chips are designed for max 1600x1200\n"
803 "select anoter resolution.");
805 h_sync_strt = h_disp + var->right_margin;
806 h_sync_end = h_sync_strt + var->hsync_len;
807 h_sync_dly = var->right_margin & 7;
808 h_total = h_sync_end + h_sync_dly + var->left_margin;
810 v_sync_strt = v_disp + var->lower_margin;
811 v_sync_end = v_sync_strt + var->vsync_len;
812 v_total = v_sync_end + var->upper_margin;
814 #ifdef CONFIG_FB_ATY_GENERIC_LCD
815 if (par->lcd_table != 0) {
816 if(!M64_HAS(LT_LCD_REGS)) {
817 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
818 crtc->lcd_index = lcd_index &
819 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
820 aty_st_le32(LCD_INDEX, lcd_index, par);
823 if (!M64_HAS(MOBIL_BUS))
824 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
826 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
827 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
829 crtc->lcd_gen_cntl &=
830 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
831 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
832 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
833 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
835 if((crtc->lcd_gen_cntl & LCD_ON) &&
836 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
837 /* We cannot display the mode on the LCD. If the CRT is enabled
838 we can turn off the LCD.
839 If the CRT is off, it isn't a good idea to switch it on; we don't
840 know if one is connected. So it's better to fail then.
842 if (crtc->lcd_gen_cntl & CRT_ON) {
843 PRINTKI("Disable lcd panel, because video mode does not fit.\n");
844 crtc->lcd_gen_cntl &= ~LCD_ON;
845 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
847 FAIL("Video mode exceeds size of lcd panel.\nConnect this computer to a conventional monitor if you really need this mode.");
852 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
854 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
855 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
856 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
858 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
860 /* This is horror! When we simulate, say 640x480 on an 800x600
861 lcd monitor, the CRTC should be programmed 800x600 values for
862 the non visible part, but 640x480 for the visible part.
863 This code has been tested on a laptop with it's 1400x1050 lcd
864 monitor and a conventional monitor both switched on.
865 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
866 works with little glitches also with DOUBLESCAN modes
868 if (yres < par->lcd_height) {
869 VScan = par->lcd_height / yres;
872 vmode |= FB_VMODE_DOUBLE;
876 h_sync_strt = h_disp + par->lcd_right_margin;
877 h_sync_end = h_sync_strt + par->lcd_hsync_len;
878 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
879 h_total = h_disp + par->lcd_hblank_len;
881 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
882 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
883 v_total = v_disp + par->lcd_vblank_len / VScan;
885 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
887 h_disp = (h_disp >> 3) - 1;
888 h_sync_strt = (h_sync_strt >> 3) - 1;
889 h_sync_end = (h_sync_end >> 3) - 1;
890 h_total = (h_total >> 3) - 1;
891 h_sync_wid = h_sync_end - h_sync_strt;
893 FAIL_MAX("h_disp too large", h_disp, 0xff);
894 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
895 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
896 if(h_sync_wid > 0x1f)
898 FAIL_MAX("h_total too large", h_total, 0x1ff);
900 if (vmode & FB_VMODE_DOUBLE) {
908 #ifdef CONFIG_FB_ATY_GENERIC_LCD
909 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
910 vdisplay = par->lcd_height;
917 v_sync_wid = v_sync_end - v_sync_strt;
919 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
920 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
921 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
922 if(v_sync_wid > 0x1f)
924 FAIL_MAX("v_total too large", v_total, 0x7ff);
926 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
931 crtc->xoffset = xoffset;
932 crtc->yoffset = yoffset;
934 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
935 crtc->vline_crnt_vline = 0;
937 crtc->h_tot_disp = h_total | (h_disp<<16);
938 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
939 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
940 crtc->v_tot_disp = v_total | (v_disp<<16);
941 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
943 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
944 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
945 crtc->gen_cntl |= CRTC_VGA_LINEAR;
947 /* Enable doublescan mode if requested */
948 if (vmode & FB_VMODE_DOUBLE)
949 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
950 /* Enable interlaced mode if requested */
951 if (vmode & FB_VMODE_INTERLACED)
952 crtc->gen_cntl |= CRTC_INTERLACE_EN;
953 #ifdef CONFIG_FB_ATY_GENERIC_LCD
954 if (par->lcd_table != 0) {
956 if(vmode & FB_VMODE_DOUBLE)
958 if(vmode & FB_VMODE_INTERLACED) {
961 /* The prefered mode for the lcd is not interlaced, so disable it if
962 it was enabled. For doublescan there is no problem, because we can
963 compensate for it in the hardware stretching (we stretch half as much)
965 vmode &= ~FB_VMODE_INTERLACED;
966 /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
968 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
969 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
970 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
971 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
972 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
974 /* MOBILITY M1 tested, FIXME: LT */
975 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
976 if (!M64_HAS(LT_LCD_REGS))
977 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
978 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
980 crtc->horz_stretching &=
981 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
982 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
983 if (xres < par->lcd_width) {
986 * The horizontal blender misbehaves when HDisplay is less than a
987 * a certain threshold (440 for a 1024-wide panel). It doesn't
988 * stretch such modes enough. Use pixel replication instead of
989 * blending to stretch modes that can be made to exactly fit the
990 * panel width. The undocumented "NoLCDBlend" option allows the
991 * pixel-replicated mode to be slightly wider or narrower than the
992 * panel width. It also causes a mode that is exactly half as wide
993 * as the panel to be pixel-replicated, rather than blended.
995 int HDisplay = xres & ~7;
996 int nStretch = par->lcd_width / HDisplay;
997 int Remainder = par->lcd_width % HDisplay;
999 if ((!Remainder && ((nStretch > 2))) ||
1000 (((HDisplay * 16) / par->lcd_width) < 7)) {
1001 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1002 int horz_stretch_loop = -1, BestRemainder;
1003 int Numerator = HDisplay, Denominator = par->lcd_width;
1005 ATIReduceRatio(&Numerator, &Denominator);
1007 BestRemainder = (Numerator * 16) / Denominator;
1008 while (--Index >= 0) {
1009 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1011 if (Remainder < BestRemainder) {
1012 horz_stretch_loop = Index;
1013 if (!(BestRemainder = Remainder))
1018 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1019 int horz_stretch_ratio = 0, Accumulator = 0;
1020 int reuse_previous = 1;
1022 Index = StretchLoops[horz_stretch_loop];
1024 while (--Index >= 0) {
1025 if (Accumulator > 0)
1026 horz_stretch_ratio |= reuse_previous;
1028 Accumulator += Denominator;
1029 Accumulator -= Numerator;
1030 reuse_previous <<= 1;
1033 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1034 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1035 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1036 break; /* Out of the do { ... } while (0) */
1040 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1041 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1045 if (vdisplay < par->lcd_height) {
1046 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1047 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1049 if (!M64_HAS(LT_LCD_REGS) &&
1050 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1051 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1054 * Don't use vertical blending if the mode is too wide or not
1055 * vertically stretched.
1057 crtc->vert_stretching = 0;
1059 /* copy to shadow crtc */
1060 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1061 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1062 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1063 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1065 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1067 if (M64_HAS(MAGIC_FIFO)) {
1069 /* FIXME: magic FIFO values */
1070 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1072 crtc->dp_pix_width = dp_pix_width;
1073 crtc->dp_chain_mask = dp_chain_mask;
1078 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1080 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1081 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1083 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1085 u32 double_scan, interlace;
1088 h_total = crtc->h_tot_disp & 0x1ff;
1089 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1090 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1091 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1092 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1093 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1094 v_total = crtc->v_tot_disp & 0x7ff;
1095 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1096 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1097 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1098 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1099 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1100 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1101 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1102 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1105 xres = (h_disp + 1) * 8;
1107 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1108 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1109 hslen = h_sync_wid * 8;
1110 upper = v_total - v_sync_strt - v_sync_wid;
1111 lower = v_sync_strt - v_disp;
1113 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1114 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1115 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1117 switch (pix_width) {
1119 case CRTC_PIX_WIDTH_4BPP:
1121 var->red.offset = 0;
1122 var->red.length = 8;
1123 var->green.offset = 0;
1124 var->green.length = 8;
1125 var->blue.offset = 0;
1126 var->blue.length = 8;
1127 var->transp.offset = 0;
1128 var->transp.length = 0;
1131 case CRTC_PIX_WIDTH_8BPP:
1133 var->red.offset = 0;
1134 var->red.length = 8;
1135 var->green.offset = 0;
1136 var->green.length = 8;
1137 var->blue.offset = 0;
1138 var->blue.length = 8;
1139 var->transp.offset = 0;
1140 var->transp.length = 0;
1142 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1144 var->red.offset = 10;
1145 var->red.length = 5;
1146 var->green.offset = 5;
1147 var->green.length = 5;
1148 var->blue.offset = 0;
1149 var->blue.length = 5;
1150 var->transp.offset = 0;
1151 var->transp.length = 0;
1153 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1155 var->red.offset = 11;
1156 var->red.length = 5;
1157 var->green.offset = 5;
1158 var->green.length = 6;
1159 var->blue.offset = 0;
1160 var->blue.length = 5;
1161 var->transp.offset = 0;
1162 var->transp.length = 0;
1164 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1166 var->red.offset = 16;
1167 var->red.length = 8;
1168 var->green.offset = 8;
1169 var->green.length = 8;
1170 var->blue.offset = 0;
1171 var->blue.length = 8;
1172 var->transp.offset = 0;
1173 var->transp.length = 0;
1175 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1177 var->red.offset = 16;
1178 var->red.length = 8;
1179 var->green.offset = 8;
1180 var->green.length = 8;
1181 var->blue.offset = 0;
1182 var->blue.length = 8;
1183 var->transp.offset = 24;
1184 var->transp.length = 8;
1187 FAIL("Invalid pixel width");
1193 var->xres_virtual = crtc->vxres;
1194 var->yres_virtual = crtc->vyres;
1195 var->bits_per_pixel = bpp;
1196 var->left_margin = left;
1197 var->right_margin = right;
1198 var->upper_margin = upper;
1199 var->lower_margin = lower;
1200 var->hsync_len = hslen;
1201 var->vsync_len = vslen;
1203 var->vmode = FB_VMODE_NONINTERLACED;
1204 /* In double scan mode, the vertical parameters are doubled, so we need to
1205 half them to get the right values.
1206 In interlaced mode the values are already correct, so no correction is
1210 var->vmode = FB_VMODE_INTERLACED;
1213 var->vmode = FB_VMODE_DOUBLE;
1215 var->upper_margin>>=1;
1216 var->lower_margin>>=1;
1223 /* ------------------------------------------------------------------------- */
1225 static int atyfb_set_par(struct fb_info *info)
1227 struct atyfb_par *par = (struct atyfb_par *) info->par;
1228 struct fb_var_screeninfo *var = &info->var;
1232 struct fb_var_screeninfo debug;
1238 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1241 pixclock = atyfb_get_pixclock(var, par);
1243 if (pixclock == 0) {
1244 FAIL("Invalid pixclock");
1246 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1250 par->accel_flags = var->accel_flags; /* hack */
1252 if (par->blitter_may_be_busy)
1255 aty_set_crtc(par, &par->crtc);
1256 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1257 par->pll_ops->set_pll(info, &par->pll);
1260 if(par->pll_ops && par->pll_ops->pll_to_var)
1261 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1265 if(0 == pixclock_in_ps) {
1266 PRINTKE("ALERT ops->pll_to_var get 0\n");
1267 pixclock_in_ps = pixclock;
1270 memset(&debug, 0, sizeof(debug));
1271 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1272 u32 hSync, vRefresh;
1273 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1274 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1276 h_disp = debug.xres;
1277 h_sync_strt = h_disp + debug.right_margin;
1278 h_sync_end = h_sync_strt + debug.hsync_len;
1279 h_total = h_sync_end + debug.left_margin;
1280 v_disp = debug.yres;
1281 v_sync_strt = v_disp + debug.lower_margin;
1282 v_sync_end = v_sync_strt + debug.vsync_len;
1283 v_total = v_sync_end + debug.upper_margin;
1285 hSync = 1000000000 / (pixclock_in_ps * h_total);
1286 vRefresh = (hSync * 1000) / v_total;
1287 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1289 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1292 DPRINTK("atyfb_set_par\n");
1293 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1294 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1295 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1296 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1297 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1298 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1299 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1300 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1301 h_disp, h_sync_strt, h_sync_end, h_total,
1302 v_disp, v_sync_strt, v_sync_end, v_total);
1303 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1305 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1306 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1310 if (!M64_HAS(INTEGRATED)) {
1311 /* Don't forget MEM_CNTL */
1312 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1313 switch (var->bits_per_pixel) {
1324 aty_st_le32(MEM_CNTL, tmp, par);
1326 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1327 if (!M64_HAS(MAGIC_POSTDIV))
1328 tmp |= par->mem_refresh_rate << 20;
1329 switch (var->bits_per_pixel) {
1341 if (M64_HAS(CT_BUS)) {
1342 aty_st_le32(DAC_CNTL, 0x87010184, par);
1343 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1344 } else if (M64_HAS(VT_BUS)) {
1345 aty_st_le32(DAC_CNTL, 0x87010184, par);
1346 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1347 } else if (M64_HAS(MOBIL_BUS)) {
1348 aty_st_le32(DAC_CNTL, 0x80010102, par);
1349 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1352 aty_st_le32(DAC_CNTL, 0x86010102, par);
1353 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1354 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1356 aty_st_le32(MEM_CNTL, tmp, par);
1358 aty_st_8(DAC_MASK, 0xff, par);
1360 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1361 info->fix.visual = var->bits_per_pixel <= 8 ?
1362 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1364 /* Initialize the graphics engine */
1365 if (par->accel_flags & FB_ACCELF_TEXT)
1366 aty_init_engine(par, info);
1368 #ifdef CONFIG_BOOTX_TEXT
1369 btext_update_display(info->fix.smem_start,
1370 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1371 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1372 var->bits_per_pixel,
1373 par->crtc.vxres * var->bits_per_pixel / 8);
1374 #endif /* CONFIG_BOOTX_TEXT */
1376 /* switch to accelerator mode */
1377 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1378 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1382 /* dump non shadow CRTC, pll, LCD registers */
1385 /* CRTC registers */
1387 printk("debug atyfb: Mach64 non-shadow register values:");
1388 for (i = 0; i < 256; i = i+4) {
1389 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1390 printk(" %08X", aty_ld_le32(i, par));
1394 #ifdef CONFIG_FB_ATY_CT
1397 printk("debug atyfb: Mach64 PLL register values:");
1398 for (i = 0; i < 64; i++) {
1399 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1400 if(i%4 == 0) printk(" ");
1401 printk("%02X", aty_ld_pll_ct(i, par));
1404 #endif /* CONFIG_FB_ATY_CT */
1406 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1407 if (par->lcd_table != 0) {
1410 printk("debug atyfb: LCD register values:");
1411 if(M64_HAS(LT_LCD_REGS)) {
1412 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1413 if(i == EXT_VERT_STRETCH)
1415 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1416 printk(" %08X", aty_ld_lcd(i, par));
1420 for (i = 0; i < 64; i++) {
1421 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1422 printk(" %08X", aty_ld_lcd(i, par));
1427 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1433 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1435 struct atyfb_par *par = (struct atyfb_par *) info->par;
1441 memcpy(&pll, &(par->pll), sizeof(pll));
1443 if((err = aty_var_to_crtc(info, var, &crtc)))
1446 pixclock = atyfb_get_pixclock(var, par);
1448 if (pixclock == 0) {
1449 FAIL("Invalid pixclock");
1451 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1455 if (var->accel_flags & FB_ACCELF_TEXT)
1456 info->var.accel_flags = FB_ACCELF_TEXT;
1458 info->var.accel_flags = 0;
1460 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1461 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1464 aty_crtc_to_var(&crtc, var);
1465 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1469 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1471 u32 xoffset = info->var.xoffset;
1472 u32 yoffset = info->var.yoffset;
1473 u32 vxres = par->crtc.vxres;
1474 u32 bpp = info->var.bits_per_pixel;
1476 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1481 * Open/Release the frame buffer device
1484 static int atyfb_open(struct fb_info *info, int user)
1486 struct atyfb_par *par = (struct atyfb_par *) info->par;
1497 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1499 struct atyfb_par *par = dev_id;
1503 spin_lock(&par->int_lock);
1505 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1507 if (int_cntl & CRTC_VBLANK_INT) {
1508 /* clear interrupt */
1509 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1510 par->vblank.count++;
1511 if (par->vblank.pan_display) {
1512 par->vblank.pan_display = 0;
1513 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1515 wake_up_interruptible(&par->vblank.wait);
1519 spin_unlock(&par->int_lock);
1521 return IRQ_RETVAL(handled);
1524 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1528 if (!test_and_set_bit(0, &par->irq_flags)) {
1529 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1530 clear_bit(0, &par->irq_flags);
1533 spin_lock_irq(&par->int_lock);
1534 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1535 /* clear interrupt */
1536 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1537 /* enable interrupt */
1538 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1539 spin_unlock_irq(&par->int_lock);
1540 } else if (reenable) {
1541 spin_lock_irq(&par->int_lock);
1542 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1543 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1544 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1545 /* re-enable interrupt */
1546 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1548 spin_unlock_irq(&par->int_lock);
1554 static int aty_disable_irq(struct atyfb_par *par)
1558 if (test_and_clear_bit(0, &par->irq_flags)) {
1559 if (par->vblank.pan_display) {
1560 par->vblank.pan_display = 0;
1561 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1563 spin_lock_irq(&par->int_lock);
1564 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1565 /* disable interrupt */
1566 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1567 spin_unlock_irq(&par->int_lock);
1568 free_irq(par->irq, par);
1574 static int atyfb_release(struct fb_info *info, int user)
1576 struct atyfb_par *par = (struct atyfb_par *) info->par;
1583 int was_mmaped = par->mmaped;
1588 struct fb_var_screeninfo var;
1590 /* Now reset the default display config, we have no
1591 * idea what the program(s) which mmap'd the chip did
1592 * to the configuration, nor whether it restored it
1597 var.accel_flags &= ~FB_ACCELF_TEXT;
1599 var.accel_flags |= FB_ACCELF_TEXT;
1600 if (var.yres == var.yres_virtual) {
1601 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1602 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1603 if (var.yres_virtual < var.yres)
1604 var.yres_virtual = var.yres;
1608 aty_disable_irq(par);
1615 * Pan or Wrap the Display
1617 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1620 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1622 struct atyfb_par *par = (struct atyfb_par *) info->par;
1623 u32 xres, yres, xoffset, yoffset;
1625 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1626 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1627 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1629 xoffset = (var->xoffset + 7) & ~7;
1630 yoffset = var->yoffset;
1631 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1633 info->var.xoffset = xoffset;
1634 info->var.yoffset = yoffset;
1638 set_off_pitch(par, info);
1639 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1640 par->vblank.pan_display = 1;
1642 par->vblank.pan_display = 0;
1643 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1649 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1651 struct aty_interrupt *vbl;
1663 ret = aty_enable_irq(par, 0);
1668 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1673 aty_enable_irq(par, 1);
1682 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1683 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1689 u8 mclk_post_div; /* 1,2,3,4,8 */
1690 u8 mclk_fb_mult; /* 2 or 4 */
1691 u8 xclk_post_div; /* 1,2,3,4,8 */
1693 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1694 u32 dsp_xclks_per_row; /* 0-16383 */
1695 u32 dsp_loop_latency; /* 0-15 */
1696 u32 dsp_precision; /* 0-7 */
1697 u32 dsp_on; /* 0-2047 */
1698 u32 dsp_off; /* 0-2047 */
1701 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1702 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1705 #ifndef FBIO_WAITFORVSYNC
1706 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1709 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1710 u_long arg, struct fb_info *info)
1712 struct atyfb_par *par = (struct atyfb_par *) info->par;
1714 struct fbtype fbtyp;
1720 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1721 fbtyp.fb_width = par->crtc.vxres;
1722 fbtyp.fb_height = par->crtc.vyres;
1723 fbtyp.fb_depth = info->var.bits_per_pixel;
1724 fbtyp.fb_cmsize = info->cmap.len;
1725 fbtyp.fb_size = info->fix.smem_len;
1726 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1729 #endif /* __sparc__ */
1731 case FBIO_WAITFORVSYNC:
1735 if (get_user(crtc, (__u32 __user *) arg))
1738 return aty_waitforvblank(par, crtc);
1742 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1744 if (M64_HAS(INTEGRATED)) {
1746 union aty_pll *pll = &(par->pll);
1747 u32 dsp_config = pll->ct.dsp_config;
1748 u32 dsp_on_off = pll->ct.dsp_on_off;
1749 clk.ref_clk_per = par->ref_clk_per;
1750 clk.pll_ref_div = pll->ct.pll_ref_div;
1751 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1752 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1753 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1754 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1755 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1756 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1757 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1758 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1759 clk.dsp_precision = (dsp_config >> 20) & 7;
1760 clk.dsp_off = dsp_on_off & 0x7ff;
1761 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1762 if (copy_to_user((struct atyclk __user *) arg, &clk,
1769 if (M64_HAS(INTEGRATED)) {
1771 union aty_pll *pll = &(par->pll);
1772 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1774 par->ref_clk_per = clk.ref_clk_per;
1775 pll->ct.pll_ref_div = clk.pll_ref_div;
1776 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1777 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1778 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1779 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1780 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1781 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1782 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1783 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1784 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1785 /*aty_calc_pll_ct(info, &pll->ct);*/
1786 aty_set_pll_ct(info, pll);
1791 if (get_user(par->features, (u32 __user *) arg))
1795 if (put_user(par->features, (u32 __user *) arg))
1798 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1805 static int atyfb_sync(struct fb_info *info)
1807 struct atyfb_par *par = (struct atyfb_par *) info->par;
1809 if (par->blitter_may_be_busy)
1815 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1817 struct atyfb_par *par = (struct atyfb_par *) info->par;
1818 unsigned int size, page, map_size = 0;
1819 unsigned long map_offset = 0;
1826 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1829 off = vma->vm_pgoff << PAGE_SHIFT;
1830 size = vma->vm_end - vma->vm_start;
1832 /* To stop the swapper from even considering these pages. */
1833 vma->vm_flags |= (VM_IO | VM_RESERVED);
1835 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1836 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1837 off += 0x8000000000000000UL;
1839 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1841 /* Each page, see which map applies */
1842 for (page = 0; page < size;) {
1844 for (i = 0; par->mmap_map[i].size; i++) {
1845 unsigned long start = par->mmap_map[i].voff;
1846 unsigned long end = start + par->mmap_map[i].size;
1847 unsigned long offset = off + page;
1854 map_size = par->mmap_map[i].size - (offset - start);
1856 par->mmap_map[i].poff + (offset - start);
1863 if (page + map_size > size)
1864 map_size = size - page;
1866 pgprot_val(vma->vm_page_prot) &=
1867 ~(par->mmap_map[i].prot_mask);
1868 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1870 if (remap_pfn_range(vma, vma->vm_start + page,
1871 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1892 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1896 for (i = 0; i < 256; i++) {
1897 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1898 if (M64_HAS(EXTRA_BRIGHT))
1900 aty_st_8(DAC_CNTL, tmp, par);
1901 aty_st_8(DAC_MASK, 0xff, par);
1903 writeb(i, &par->aty_cmap_regs->rindex);
1904 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1905 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1906 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1907 writeb(i, &par->aty_cmap_regs->windex);
1908 writeb(atyfb_save.r[1 - enter][i],
1909 &par->aty_cmap_regs->lut);
1910 writeb(atyfb_save.g[1 - enter][i],
1911 &par->aty_cmap_regs->lut);
1912 writeb(atyfb_save.b[1 - enter][i],
1913 &par->aty_cmap_regs->lut);
1917 static void atyfb_palette(int enter)
1919 struct atyfb_par *par;
1920 struct fb_info *info;
1923 for (i = 0; i < FB_MAX; i++) {
1924 info = registered_fb[i];
1925 if (info && info->fbops == &atyfb_ops) {
1926 par = (struct atyfb_par *) info->par;
1928 atyfb_save_palette(par, enter);
1930 atyfb_save.yoffset = info->var.yoffset;
1931 info->var.yoffset = 0;
1932 set_off_pitch(par, info);
1934 info->var.yoffset = atyfb_save.yoffset;
1935 set_off_pitch(par, info);
1937 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1942 #endif /* __sparc__ */
1946 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1948 /* Power management routines. Those are used for PowerBook sleep.
1950 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1955 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1956 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1957 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1958 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1964 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1965 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1967 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1969 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1970 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1973 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1975 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1977 if ((--timeout) == 0)
1979 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1983 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1984 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1987 pm |= (PWR_BLON | AUTO_PWR_UP);
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1992 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1994 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996 if ((--timeout) == 0)
1998 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2002 return timeout ? 0 : -EIO;
2005 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2007 struct fb_info *info = pci_get_drvdata(pdev);
2008 struct atyfb_par *par = (struct atyfb_par *) info->par;
2010 #ifndef CONFIG_PPC_PMAC
2011 /* HACK ALERT ! Once I find a proper way to say to each driver
2012 * individually what will happen with it's PCI slot, I'll change
2013 * that. On laptops, the AGP slot is just unclocked, so D2 is
2014 * expected, while on desktops, the card is powered off
2017 #endif /* CONFIG_PPC_PMAC */
2019 if (state.event == pdev->dev.power.power_state.event)
2022 acquire_console_sem();
2024 fb_set_suspend(info, 1);
2026 /* Idle & reset engine */
2028 aty_reset_engine(par);
2030 /* Blank display and LCD */
2031 atyfb_blank(FB_BLANK_POWERDOWN, info);
2034 par->lock_blank = 1;
2036 /* Set chip to "suspend" mode */
2037 if (aty_power_mgmt(1, par)) {
2039 par->lock_blank = 0;
2040 atyfb_blank(FB_BLANK_UNBLANK, info);
2041 fb_set_suspend(info, 0);
2042 release_console_sem();
2046 release_console_sem();
2048 pdev->dev.power.power_state = state;
2053 static int atyfb_pci_resume(struct pci_dev *pdev)
2055 struct fb_info *info = pci_get_drvdata(pdev);
2056 struct atyfb_par *par = (struct atyfb_par *) info->par;
2058 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2061 acquire_console_sem();
2063 if (pdev->dev.power.power_state.event == 2)
2064 aty_power_mgmt(0, par);
2067 /* Restore display */
2068 atyfb_set_par(info);
2071 fb_set_suspend(info, 0);
2074 par->lock_blank = 0;
2075 atyfb_blank(FB_BLANK_UNBLANK, info);
2077 release_console_sem();
2079 pdev->dev.power.power_state = PMSG_ON;
2084 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2086 #ifdef CONFIG_PMAC_BACKLIGHT
2089 * LCD backlight control
2092 static int backlight_conv[] = {
2093 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2094 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2097 static int aty_set_backlight_enable(int on, int level, void *data)
2099 struct fb_info *info = (struct fb_info *) data;
2100 struct atyfb_par *par = (struct atyfb_par *) info->par;
2101 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2103 reg |= (BLMOD_EN | BIASMOD_EN);
2104 if (on && level > BACKLIGHT_OFF) {
2105 reg &= ~BIAS_MOD_LEVEL_MASK;
2106 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2108 reg &= ~BIAS_MOD_LEVEL_MASK;
2109 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2111 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2115 static int aty_set_backlight_level(int level, void *data)
2117 return aty_set_backlight_enable(1, level, data);
2120 static struct backlight_controller aty_backlight_controller = {
2121 aty_set_backlight_enable,
2122 aty_set_backlight_level
2124 #endif /* CONFIG_PMAC_BACKLIGHT */
2126 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2128 const int ragepro_tbl[] = {
2129 44, 50, 55, 66, 75, 80, 100
2131 const int ragexl_tbl[] = {
2132 50, 66, 75, 83, 90, 95, 100, 105,
2133 110, 115, 120, 125, 133, 143, 166
2135 const int *refresh_tbl;
2138 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2139 refresh_tbl = ragexl_tbl;
2140 size = sizeof(ragexl_tbl)/sizeof(int);
2142 refresh_tbl = ragepro_tbl;
2143 size = sizeof(ragepro_tbl)/sizeof(int);
2146 for (i=0; i < size; i++) {
2147 if (xclk < refresh_tbl[i])
2150 par->mem_refresh_rate = i;
2157 static struct fb_info *fb_list = NULL;
2159 static int __init aty_init(struct fb_info *info, const char *name)
2161 struct atyfb_par *par = (struct atyfb_par *) info->par;
2162 const char *ramname = NULL, *xtal;
2164 struct fb_var_screeninfo var;
2167 #if defined(CONFIG_PPC)
2171 init_waitqueue_head(&par->vblank.wait);
2172 spin_lock_init(&par->int_lock);
2174 par->aty_cmap_regs =
2175 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2177 #ifdef CONFIG_PPC_PMAC
2178 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2179 * and set the frequency manually. */
2180 if (machine_is_compatible("PowerBook2,1")) {
2181 par->pll_limits.mclk = 70;
2182 par->pll_limits.xclk = 53;
2186 par->pll_limits.pll_max = pll;
2188 par->pll_limits.mclk = mclk;
2190 par->pll_limits.xclk = xclk;
2192 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2193 par->pll_per = 1000000/par->pll_limits.pll_max;
2194 par->mclk_per = 1000000/par->pll_limits.mclk;
2195 par->xclk_per = 1000000/par->pll_limits.xclk;
2197 par->ref_clk_per = 1000000000000ULL / 14318180;
2200 #ifdef CONFIG_FB_ATY_GX
2201 if (!M64_HAS(INTEGRATED)) {
2203 u8 dac_type, dac_subtype, clk_type;
2204 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2205 par->bus_type = (stat0 >> 0) & 0x07;
2206 par->ram_type = (stat0 >> 3) & 0x07;
2207 ramname = aty_gx_ram[par->ram_type];
2208 /* FIXME: clockchip/RAMDAC probing? */
2209 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2211 clk_type = CLK_ATI18818_1;
2212 dac_type = (stat0 >> 9) & 0x07;
2213 if (dac_type == 0x07)
2214 dac_subtype = DAC_ATT20C408;
2216 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2218 dac_type = DAC_IBMRGB514;
2219 dac_subtype = DAC_IBMRGB514;
2220 clk_type = CLK_IBMRGB514;
2222 switch (dac_subtype) {
2224 par->dac_ops = &aty_dac_ibm514;
2226 case DAC_ATI68860_B:
2227 case DAC_ATI68860_C:
2228 par->dac_ops = &aty_dac_ati68860b;
2232 par->dac_ops = &aty_dac_att21c498;
2235 PRINTKI("aty_init: DAC type not implemented yet!\n");
2236 par->dac_ops = &aty_dac_unsupported;
2240 case CLK_ATI18818_1:
2241 par->pll_ops = &aty_pll_ati18818_1;
2244 par->pll_ops = &aty_pll_stg1703;
2247 par->pll_ops = &aty_pll_ch8398;
2250 par->pll_ops = &aty_pll_att20c408;
2253 par->pll_ops = &aty_pll_ibm514;
2256 PRINTKI("aty_init: CLK type not implemented yet!");
2257 par->pll_ops = &aty_pll_unsupported;
2261 #endif /* CONFIG_FB_ATY_GX */
2262 #ifdef CONFIG_FB_ATY_CT
2263 if (M64_HAS(INTEGRATED)) {
2264 par->dac_ops = &aty_dac_ct;
2265 par->pll_ops = &aty_pll_ct;
2266 par->bus_type = PCI;
2267 #ifdef CONFIG_FB_ATY_XL_INIT
2268 if (IS_XL(par->pci_id))
2269 atyfb_xl_init(info);
2271 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2272 ramname = aty_ct_ram[par->ram_type];
2273 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2274 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2275 par->pll_limits.mclk = 63;
2278 if (M64_HAS(GTB_DSP)
2279 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2281 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2282 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2287 if (diff2 < diff1) {
2288 par->ref_clk_per = 1000000000000ULL / 29498928;
2292 #endif /* CONFIG_FB_ATY_CT */
2294 /* save previous video mode */
2295 aty_get_crtc(par, &saved_crtc);
2296 if(par->pll_ops->get_pll)
2297 par->pll_ops->get_pll(info, &saved_pll);
2299 i = aty_ld_le32(MEM_CNTL, par);
2300 gtb_memsize = M64_HAS(GTB_DSP);
2302 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2304 info->fix.smem_len = 0x80000;
2307 info->fix.smem_len = 0x100000;
2309 case MEM_SIZE_2M_GTB:
2310 info->fix.smem_len = 0x200000;
2312 case MEM_SIZE_4M_GTB:
2313 info->fix.smem_len = 0x400000;
2315 case MEM_SIZE_6M_GTB:
2316 info->fix.smem_len = 0x600000;
2318 case MEM_SIZE_8M_GTB:
2319 info->fix.smem_len = 0x800000;
2322 info->fix.smem_len = 0x80000;
2324 switch (i & MEM_SIZE_ALIAS) {
2326 info->fix.smem_len = 0x80000;
2329 info->fix.smem_len = 0x100000;
2332 info->fix.smem_len = 0x200000;
2335 info->fix.smem_len = 0x400000;
2338 info->fix.smem_len = 0x600000;
2341 info->fix.smem_len = 0x800000;
2344 info->fix.smem_len = 0x80000;
2347 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2348 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2349 info->fix.smem_len += 0x400000;
2353 info->fix.smem_len = vram * 1024;
2354 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2355 if (info->fix.smem_len <= 0x80000)
2357 else if (info->fix.smem_len <= 0x100000)
2359 else if (info->fix.smem_len <= 0x200000)
2360 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2361 else if (info->fix.smem_len <= 0x400000)
2362 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2363 else if (info->fix.smem_len <= 0x600000)
2364 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2366 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2367 aty_st_le32(MEM_CNTL, i, par);
2371 * Reg Block 0 (CT-compatible block) is at mmio_start
2372 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2375 info->fix.mmio_len = 0x400;
2376 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2377 } else if (M64_HAS(CT)) {
2378 info->fix.mmio_len = 0x400;
2379 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2380 } else if (M64_HAS(VT)) {
2381 info->fix.mmio_start -= 0x400;
2382 info->fix.mmio_len = 0x800;
2383 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2385 info->fix.mmio_start -= 0x400;
2386 info->fix.mmio_len = 0x800;
2387 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2390 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2391 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2392 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2393 par->pll_limits.mclk, par->pll_limits.xclk);
2395 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2396 if (M64_HAS(INTEGRATED)) {
2398 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2399 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2400 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2402 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2403 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2404 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2405 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2406 for (i = 0; i < 40; i++)
2407 printk(" %02x", aty_ld_pll_ct(i, par));
2411 if(par->pll_ops->init_pll)
2412 par->pll_ops->init_pll(info, &par->pll);
2415 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2416 * FIXME: we should use the auxiliary aperture instead so we can access
2417 * the full 8 MB of video RAM on 8 MB boards
2420 if (!par->aux_start &&
2421 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2422 info->fix.smem_len -= GUI_RESERVE;
2425 * Disable register access through the linear aperture
2426 * if the auxiliary aperture is used so we can access
2427 * the full 8 MB of video RAM on 8 MB boards.
2430 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2433 par->mtrr_aper = -1;
2436 /* Cover the whole resource. */
2437 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2438 if (par->mtrr_aper >= 0 && !par->aux_start) {
2439 /* Make a hole for mmio. */
2440 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2441 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2442 if (par->mtrr_reg < 0) {
2443 mtrr_del(par->mtrr_aper, 0, 0);
2444 par->mtrr_aper = -1;
2450 info->fbops = &atyfb_ops;
2451 info->pseudo_palette = pseudo_palette;
2452 info->flags = FBINFO_FLAG_DEFAULT;
2454 #ifdef CONFIG_PMAC_BACKLIGHT
2455 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2456 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2457 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2458 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2459 } else if (M64_HAS(MOBIL_BUS))
2460 register_backlight_controller(&aty_backlight_controller, info, "ati");
2461 #endif /* CONFIG_PMAC_BACKLIGHT */
2463 memset(&var, 0, sizeof(var));
2465 if (_machine == _MACH_Pmac) {
2467 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2468 * applies to all Mac video cards
2471 if (!mac_find_mode(&var, info, mode, 8))
2474 if (default_vmode == VMODE_CHOOSE) {
2475 if (M64_HAS(G3_PB_1024x768))
2476 /* G3 PowerBook with 1024x768 LCD */
2477 default_vmode = VMODE_1024_768_60;
2478 else if (machine_is_compatible("iMac"))
2479 default_vmode = VMODE_1024_768_75;
2480 else if (machine_is_compatible
2482 /* iBook with 800x600 LCD */
2483 default_vmode = VMODE_800_600_60;
2485 default_vmode = VMODE_640_480_67;
2486 sense = read_aty_sense(par);
2487 PRINTKI("monitor sense=%x, mode %d\n",
2488 sense, mac_map_monitor_sense(sense));
2490 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2491 default_vmode = VMODE_640_480_60;
2492 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2493 default_cmode = CMODE_8;
2494 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2498 #endif /* !CONFIG_PPC */
2500 #if defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
2501 /* On Sparc, unless the user gave a specific mode
2502 * specification, use the PROM probed values in
2507 !fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2511 var.accel_flags &= ~FB_ACCELF_TEXT;
2513 var.accel_flags |= FB_ACCELF_TEXT;
2515 if (comp_sync != -1) {
2517 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2519 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2522 if (var.yres == var.yres_virtual) {
2523 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2524 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2525 if (var.yres_virtual < var.yres)
2526 var.yres_virtual = var.yres;
2529 if (atyfb_check_var(&var, info)) {
2530 PRINTKE("can't set default video mode\n");
2535 atyfb_save_palette(par, 0);
2538 #ifdef CONFIG_FB_ATY_CT
2539 if (!noaccel && M64_HAS(INTEGRATED))
2540 aty_init_cursor(info);
2541 #endif /* CONFIG_FB_ATY_CT */
2544 fb_alloc_cmap(&info->cmap, 256, 0);
2546 if (register_framebuffer(info) < 0)
2551 PRINTKI("fb%d: %s frame buffer device on %s\n",
2552 info->node, info->fix.id, name);
2556 /* restore video mode */
2557 aty_set_crtc(par, &saved_crtc);
2558 par->pll_ops->set_pll(info, &saved_pll);
2561 if (par->mtrr_reg >= 0) {
2562 mtrr_del(par->mtrr_reg, 0, 0);
2565 if (par->mtrr_aper >= 0) {
2566 mtrr_del(par->mtrr_aper, 0, 0);
2567 par->mtrr_aper = -1;
2574 static int __init store_video_par(char *video_str, unsigned char m64_num)
2577 unsigned long vmembase, size, guiregbase;
2579 PRINTKI("store_video_par() '%s' \n", video_str);
2581 if (!(p = strsep(&video_str, ";")) || !*p)
2582 goto mach64_invalid;
2583 vmembase = simple_strtoul(p, NULL, 0);
2584 if (!(p = strsep(&video_str, ";")) || !*p)
2585 goto mach64_invalid;
2586 size = simple_strtoul(p, NULL, 0);
2587 if (!(p = strsep(&video_str, ";")) || !*p)
2588 goto mach64_invalid;
2589 guiregbase = simple_strtoul(p, NULL, 0);
2591 phys_vmembase[m64_num] = vmembase;
2592 phys_size[m64_num] = size;
2593 phys_guiregbase[m64_num] = guiregbase;
2594 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2599 phys_vmembase[m64_num] = 0;
2602 #endif /* CONFIG_ATARI */
2605 * Blank the display.
2608 static int atyfb_blank(int blank, struct fb_info *info)
2610 struct atyfb_par *par = (struct atyfb_par *) info->par;
2613 if (par->lock_blank || par->asleep)
2616 #ifdef CONFIG_PMAC_BACKLIGHT
2617 if ((_machine == _MACH_Pmac) && blank)
2618 set_backlight_enable(0);
2619 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2620 if (par->lcd_table && blank &&
2621 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2622 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2624 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2628 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2630 case FB_BLANK_UNBLANK:
2631 gen_cntl &= ~(0x4c);
2633 case FB_BLANK_NORMAL:
2636 case FB_BLANK_VSYNC_SUSPEND:
2639 case FB_BLANK_HSYNC_SUSPEND:
2642 case FB_BLANK_POWERDOWN:
2646 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2648 #ifdef CONFIG_PMAC_BACKLIGHT
2649 if ((_machine == _MACH_Pmac) && !blank)
2650 set_backlight_enable(1);
2651 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2652 if (par->lcd_table && !blank &&
2653 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2654 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2656 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2663 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2664 const struct atyfb_par *par)
2667 out_8(&par->aty_cmap_regs->windex, regno);
2668 out_8(&par->aty_cmap_regs->lut, red);
2669 out_8(&par->aty_cmap_regs->lut, green);
2670 out_8(&par->aty_cmap_regs->lut, blue);
2672 writeb(regno, &par->aty_cmap_regs->windex);
2673 writeb(red, &par->aty_cmap_regs->lut);
2674 writeb(green, &par->aty_cmap_regs->lut);
2675 writeb(blue, &par->aty_cmap_regs->lut);
2680 * Set a single color register. The values supplied are already
2681 * rounded down to the hardware's capabilities (according to the
2682 * entries in the var structure). Return != 0 for invalid regno.
2683 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2686 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2687 u_int transp, struct fb_info *info)
2689 struct atyfb_par *par = (struct atyfb_par *) info->par;
2691 u32 *pal = info->pseudo_palette;
2693 depth = info->var.bits_per_pixel;
2695 depth = (info->var.green.length == 5) ? 15 : 16;
2701 (depth == 16 && regno > 63) ||
2702 (depth == 15 && regno > 31))
2709 par->palette[regno].red = red;
2710 par->palette[regno].green = green;
2711 par->palette[regno].blue = blue;
2716 pal[regno] = (regno << 10) | (regno << 5) | regno;
2719 pal[regno] = (regno << 11) | (regno << 5) | regno;
2722 pal[regno] = (regno << 16) | (regno << 8) | regno;
2725 i = (regno << 8) | regno;
2726 pal[regno] = (i << 16) | i;
2731 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2732 if (M64_HAS(EXTRA_BRIGHT))
2733 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2734 aty_st_8(DAC_CNTL, i, par);
2735 aty_st_8(DAC_MASK, 0xff, par);
2737 if (M64_HAS(INTEGRATED)) {
2740 aty_st_pal(regno << 3, red,
2741 par->palette[regno<<1].green,
2743 red = par->palette[regno>>1].red;
2744 blue = par->palette[regno>>1].blue;
2746 } else if (depth == 15) {
2748 for(i = 0; i < 8; i++) {
2749 aty_st_pal(regno + i, red, green, blue, par);
2753 aty_st_pal(regno, red, green, blue, par);
2762 extern void (*prom_palette) (int);
2764 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2765 struct fb_info *info, unsigned long addr)
2767 extern int con_is_present(void);
2769 struct atyfb_par *par = info->par;
2770 struct pcidev_cookie *pcp;
2772 int node, len, i, j, ret;
2775 /* Do not attach when we have a serial console. */
2776 if (!con_is_present())
2780 * Map memory-mapped registers.
2782 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2783 info->fix.mmio_start = addr + 0x7ffc00UL;
2786 * Map in big-endian aperture.
2788 info->screen_base = (char *) (addr + 0x800000UL);
2789 info->fix.smem_start = addr + 0x800000UL;
2792 * Figure mmap addresses from PCI config space.
2793 * Split Framebuffer in big- and little-endian halfs.
2795 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2799 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2800 if (!par->mmap_map) {
2801 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2804 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2806 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2807 struct resource *rp = &pdev->resource[i];
2808 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2814 io = (rp->flags & IORESOURCE_IO);
2816 size = rp->end - base + 1;
2818 pci_read_config_dword(pdev, breg, &pbase);
2824 * Map the framebuffer a second time, this time without
2825 * the braindead _PAGE_IE setting. This is used by the
2826 * fixed Xserver, but we need to maintain the old mapping
2827 * to stay compatible with older ones...
2830 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2831 par->mmap_map[j].poff = base & PAGE_MASK;
2832 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2833 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2834 par->mmap_map[j].prot_flag = _PAGE_E;
2839 * Here comes the old framebuffer mapping with _PAGE_IE
2840 * set for the big endian half of the framebuffer...
2843 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2844 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2845 par->mmap_map[j].size = 0x800000;
2846 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2847 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2852 par->mmap_map[j].voff = pbase & PAGE_MASK;
2853 par->mmap_map[j].poff = base & PAGE_MASK;
2854 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2855 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2856 par->mmap_map[j].prot_flag = _PAGE_E;
2860 if((ret = correct_chipset(par)))
2863 if (IS_XL(pdev->device)) {
2865 * Fix PROMs idea of MEM_CNTL settings...
2867 mem = aty_ld_le32(MEM_CNTL, par);
2868 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2869 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2870 switch (mem & 0x0f) {
2872 mem = (mem & ~(0x0f)) | 2;
2875 mem = (mem & ~(0x0f)) | 3;
2878 mem = (mem & ~(0x0f)) | 4;
2881 mem = (mem & ~(0x0f)) | 5;
2886 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2887 mem &= ~(0x00700000);
2889 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2890 aty_st_le32(MEM_CNTL, mem, par);
2894 * If this is the console device, we will set default video
2895 * settings to what the PROM left us with.
2897 node = prom_getchild(prom_root_node);
2898 node = prom_searchsiblings(node, "aliases");
2900 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2903 node = prom_finddevice(prop);
2908 pcp = pdev->sysdata;
2909 if (node == pcp->prom_node) {
2910 struct fb_var_screeninfo *var = &default_var;
2911 unsigned int N, P, Q, M, T, R;
2912 u32 v_total, h_total;
2917 crtc.vxres = prom_getintdefault(node, "width", 1024);
2918 crtc.vyres = prom_getintdefault(node, "height", 768);
2919 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2920 var->xoffset = var->yoffset = 0;
2921 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2922 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2923 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2924 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2925 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2926 aty_crtc_to_var(&crtc, var);
2928 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2929 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2932 * Read the PLL to figure actual Refresh Rate.
2934 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2935 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2936 for (i = 0; i < 16; i++)
2937 pll_regs[i] = aty_ld_pll_ct(i, par);
2940 * PLL Reference Divider M:
2945 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2947 N = pll_regs[7 + (clock_cntl & 3)];
2950 * PLL Post Divider P (Dependant on CLOCK_CNTL):
2952 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2966 * where R is XTALIN (= 14318 or 29498 kHz).
2968 if (IS_XL(pdev->device))
2975 default_var.pixclock = 1000000000 / T;
2981 #else /* __sparc__ */
2984 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2985 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
2987 u32 driv_inf_tab, sig;
2990 /* To support an LCD panel, we should know it's dimensions and
2991 * it's desired pixel clock.
2992 * There are two ways to do it:
2993 * - Check the startup video mode and calculate the panel
2994 * size from it. This is unreliable.
2995 * - Read it from the driver information table in the video BIOS.
2997 /* Address of driver information table is at offset 0x78. */
2998 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3000 /* Check for the driver information table signature. */
3001 sig = (*(u32 *)driv_inf_tab);
3002 if ((sig == 0x54504c24) || /* Rage LT pro */
3003 (sig == 0x544d5224) || /* Rage mobility */
3004 (sig == 0x54435824) || /* Rage XC */
3005 (sig == 0x544c5824)) { /* Rage XL */
3006 PRINTKI("BIOS contains driver information table.\n");
3007 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3010 par->lcd_table = bios_base + lcd_ofs;
3014 if (par->lcd_table != 0) {
3017 char refresh_rates_buf[100];
3018 int id, tech, f, i, m, default_refresh_rate;
3023 u16 width, height, panel_type, refresh_rates;
3026 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3027 /* The most important information is the panel size at
3028 * offset 25 and 27, but there's some other nice information
3029 * which we print to the screen.
3031 id = *(u8 *)par->lcd_table;
3032 strncpy(model,(char *)par->lcd_table+1,24);
3035 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3036 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3037 panel_type = *(u16 *)(par->lcd_table+29);
3039 txtcolour = "colour";
3041 txtcolour = "monochrome";
3043 txtdual = "dual (split) ";
3046 tech = (panel_type>>2) & 63;
3049 txtmonitor = "passive matrix";
3052 txtmonitor = "active matrix";
3055 txtmonitor = "active addressed STN";
3061 txtmonitor = "plasma";
3064 txtmonitor = "unknown";
3066 format = *(u32 *)(par->lcd_table+57);
3067 if (tech == 0 || tech == 2) {
3068 switch (format & 7) {
3070 txtformat = "12 bit interface";
3073 txtformat = "16 bit interface";
3076 txtformat = "24 bit interface";
3079 txtformat = "unkown format";
3082 switch (format & 7) {
3084 txtformat = "8 colours";
3087 txtformat = "512 colours";
3090 txtformat = "4096 colours";
3093 txtformat = "262144 colours (LT mode)";
3096 txtformat = "16777216 colours";
3099 txtformat = "262144 colours (FDPI-2 mode)";
3102 txtformat = "unkown format";
3105 PRINTKI("%s%s %s monitor detected: %s\n",
3106 txtdual ,txtcolour, txtmonitor, model);
3107 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3108 id, width, height, txtformat);
3109 refresh_rates_buf[0] = 0;
3110 refresh_rates = *(u16 *)(par->lcd_table+62);
3113 for (i=0;i<16;i++) {
3114 if (refresh_rates & m) {
3116 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3119 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3121 strcat(refresh_rates_buf,strbuf);
3125 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3126 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3127 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3128 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3129 /* We now need to determine the crtc parameters for the
3130 * lcd monitor. This is tricky, because they are not stored
3131 * individually in the BIOS. Instead, the BIOS contains a
3132 * table of display modes that work for this monitor.
3134 * The idea is that we search for a mode of the same dimensions
3135 * as the dimensions of the lcd monitor. Say our lcd monitor
3136 * is 800x600 pixels, we search for a 800x600 monitor.
3137 * The CRTC parameters we find here are the ones that we need
3138 * to use to simulate other resolutions on the lcd screen.
3140 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3141 while (*lcdmodeptr != 0) {
3143 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3144 modeptr = bios_base + *lcdmodeptr;
3146 mwidth = *((u16 *)(modeptr+0));
3147 mheight = *((u16 *)(modeptr+2));
3149 if (mwidth == width && mheight == height) {
3150 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3151 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3152 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3153 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3154 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3155 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3157 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3158 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3159 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3160 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3162 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3163 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3164 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3165 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3171 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3172 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3173 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3174 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3180 if (*lcdmodeptr == 0) {
3181 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3182 /* To do: Switch to CRT if possible. */
3184 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3185 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3187 par->lcd_hdisp + par->lcd_right_margin,
3188 par->lcd_hdisp + par->lcd_right_margin
3189 + par->lcd_hsync_dly + par->lcd_hsync_len,
3192 par->lcd_vdisp + par->lcd_lower_margin,
3193 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3195 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3197 par->lcd_hblank_len - (par->lcd_right_margin +
3198 par->lcd_hsync_dly + par->lcd_hsync_len),
3200 par->lcd_right_margin,
3202 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3204 par->lcd_lower_margin,
3205 par->lcd_vsync_len);
3209 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3211 static int __devinit init_from_bios(struct atyfb_par *par)
3213 u32 bios_base, rom_addr;
3216 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3217 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3219 /* The BIOS starts with 0xaa55. */
3220 if (*((u16 *)bios_base) == 0xaa55) {
3223 u16 rom_table_offset, freq_table_offset;
3224 PLL_BLOCK_MACH64 pll_block;
3226 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3228 /* check for frequncy table */
3229 bios_ptr = (u8*)bios_base;
3230 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3231 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3232 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3234 PRINTKI("BIOS frequency table:\n");
3235 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3236 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3237 pll_block.ref_freq, pll_block.ref_divider);
3238 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3239 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3240 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3242 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3243 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3244 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3245 par->pll_limits.ref_div = pll_block.ref_divider;
3246 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3247 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3248 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3249 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3250 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3251 aty_init_lcd(par, bios_base);
3255 PRINTKE("no BIOS frequency table found, use parameters\n");
3258 iounmap((void* __iomem )bios_base);
3262 #endif /* __i386__ */
3264 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3266 struct atyfb_par *par = info->par;
3268 unsigned long raddr;
3269 struct resource *rrp;
3272 raddr = addr + 0x7ff000UL;
3273 rrp = &pdev->resource[2];
3274 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3275 par->aux_start = rrp->start;
3276 par->aux_size = rrp->end - rrp->start + 1;
3278 PRINTKI("using auxiliary register aperture\n");
3281 info->fix.mmio_start = raddr;
3282 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3283 if (par->ati_regbase == 0)
3286 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3287 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3290 * Enable memory-space accesses using config-space
3293 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3294 if (!(tmp & PCI_COMMAND_MEMORY)) {
3295 tmp |= PCI_COMMAND_MEMORY;
3296 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3299 /* Use the big-endian aperture */
3303 /* Map in frame buffer */
3304 info->fix.smem_start = addr;
3305 info->screen_base = ioremap(addr, 0x800000);
3306 if (info->screen_base == NULL) {
3308 goto atyfb_setup_generic_fail;
3311 if((ret = correct_chipset(par)))
3312 goto atyfb_setup_generic_fail;
3314 if((ret = init_from_bios(par)))
3315 goto atyfb_setup_generic_fail;
3317 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3318 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3320 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3322 /* according to ATI, we should use clock 3 for acelerated mode */
3323 par->clk_wr_offset = 3;
3327 atyfb_setup_generic_fail:
3328 iounmap(par->ati_regbase);
3329 par->ati_regbase = NULL;
3333 #endif /* !__sparc__ */
3335 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3337 unsigned long addr, res_start, res_size;
3338 struct fb_info *info;
3339 struct resource *rp;
3340 struct atyfb_par *par;
3341 int i, rc = -ENOMEM;
3343 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3344 if (pdev->device == aty_chips[i].pci_id)
3350 /* Enable device in PCI config */
3351 if (pci_enable_device(pdev)) {
3352 PRINTKE("Cannot enable PCI device\n");
3356 /* Find which resource to use */
3357 rp = &pdev->resource[0];
3358 if (rp->flags & IORESOURCE_IO)
3359 rp = &pdev->resource[1];
3365 res_start = rp->start;
3366 res_size = rp->end - rp->start + 1;
3367 if (!request_mem_region (res_start, res_size, "atyfb"))
3370 /* Allocate framebuffer */
3371 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3373 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3377 info->fix = atyfb_fix;
3378 info->device = &pdev->dev;
3379 par->pci_id = aty_chips[i].pci_id;
3380 par->res_start = res_start;
3381 par->res_size = res_size;
3382 par->irq = pdev->irq;
3384 /* Setup "info" structure */
3386 rc = atyfb_setup_sparc(pdev, info, addr);
3388 rc = atyfb_setup_generic(pdev, info, addr);
3391 goto err_release_mem;
3393 pci_set_drvdata(pdev, info);
3395 /* Init chip & register framebuffer */
3396 if (aty_init(info, "PCI"))
3397 goto err_release_io;
3401 prom_palette = atyfb_palette;
3404 * Add /dev/fb mmap values.
3406 par->mmap_map[0].voff = 0x8000000000000000UL;
3407 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3408 par->mmap_map[0].size = info->fix.smem_len;
3409 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3410 par->mmap_map[0].prot_flag = _PAGE_E;
3411 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3412 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3413 par->mmap_map[1].size = PAGE_SIZE;
3414 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3415 par->mmap_map[1].prot_flag = _PAGE_E;
3416 #endif /* __sparc__ */
3422 kfree(par->mmap_map);
3424 if (par->ati_regbase)
3425 iounmap(par->ati_regbase);
3426 if (info->screen_base)
3427 iounmap(info->screen_base);
3431 release_mem_region(par->aux_start, par->aux_size);
3433 release_mem_region(par->res_start, par->res_size);
3434 framebuffer_release(info);
3439 #endif /* CONFIG_PCI */
3443 static int __devinit atyfb_atari_probe(void)
3445 struct aty_par *par;
3446 struct fb_info *info;
3450 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3451 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3452 !phys_guiregbase[m64_num]) {
3453 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3457 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3459 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3464 info->fix = atyfb_fix;
3466 par->irq = (unsigned int) -1; /* something invalid */
3469 * Map the video memory (physical address given) to somewhere in the
3470 * kernel address space.
3472 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3473 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3474 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3476 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3478 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3479 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3481 switch (clock_r & 0x003F) {
3483 par->clk_wr_offset = 3; /* */
3486 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3489 par->clk_wr_offset = 1; /* */
3492 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3496 if (aty_init(info, "ISA bus")) {
3497 framebuffer_release(info);
3498 /* This is insufficient! kernel_map has added two large chunks!! */
3504 #endif /* CONFIG_ATARI */
3506 static void __devexit atyfb_remove(struct fb_info *info)
3508 struct atyfb_par *par = (struct atyfb_par *) info->par;
3510 /* restore video mode */
3511 aty_set_crtc(par, &saved_crtc);
3512 par->pll_ops->set_pll(info, &saved_pll);
3514 unregister_framebuffer(info);
3517 if (par->mtrr_reg >= 0) {
3518 mtrr_del(par->mtrr_reg, 0, 0);
3521 if (par->mtrr_aper >= 0) {
3522 mtrr_del(par->mtrr_aper, 0, 0);
3523 par->mtrr_aper = -1;
3527 if (par->ati_regbase)
3528 iounmap(par->ati_regbase);
3529 if (info->screen_base)
3530 iounmap(info->screen_base);
3532 if (info->sprite.addr)
3533 iounmap(info->sprite.addr);
3537 kfree(par->mmap_map);
3540 release_mem_region(par->aux_start, par->aux_size);
3543 release_mem_region(par->res_start, par->res_size);
3545 framebuffer_release(info);
3550 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3552 struct fb_info *info = pci_get_drvdata(pdev);
3558 * This driver uses its own matching table. That will be more difficult
3559 * to fix, so for now, we just match against any ATI ID and let the
3560 * probe() function find out what's up. That also mean we don't have
3561 * a module ID table though.
3563 static struct pci_device_id atyfb_pci_tbl[] = {
3564 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3565 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3569 static struct pci_driver atyfb_driver = {
3571 .id_table = atyfb_pci_tbl,
3572 .probe = atyfb_pci_probe,
3573 .remove = __devexit_p(atyfb_pci_remove),
3575 .suspend = atyfb_pci_suspend,
3576 .resume = atyfb_pci_resume,
3577 #endif /* CONFIG_PM */
3580 #endif /* CONFIG_PCI */
3583 static int __init atyfb_setup(char *options)
3587 if (!options || !*options)
3590 while ((this_opt = strsep(&options, ",")) != NULL) {
3591 if (!strncmp(this_opt, "noaccel", 7)) {
3594 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3597 } else if (!strncmp(this_opt, "vram:", 5))
3598 vram = simple_strtoul(this_opt + 5, NULL, 0);
3599 else if (!strncmp(this_opt, "pll:", 4))
3600 pll = simple_strtoul(this_opt + 4, NULL, 0);
3601 else if (!strncmp(this_opt, "mclk:", 5))
3602 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3603 else if (!strncmp(this_opt, "xclk:", 5))
3604 xclk = simple_strtoul(this_opt+5, NULL, 0);
3605 else if (!strncmp(this_opt, "comp_sync:", 10))
3606 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3608 else if (!strncmp(this_opt, "vmode:", 6)) {
3609 unsigned int vmode =
3610 simple_strtoul(this_opt + 6, NULL, 0);
3611 if (vmode > 0 && vmode <= VMODE_MAX)
3612 default_vmode = vmode;
3613 } else if (!strncmp(this_opt, "cmode:", 6)) {
3614 unsigned int cmode =
3615 simple_strtoul(this_opt + 6, NULL, 0);
3619 default_cmode = CMODE_8;
3623 default_cmode = CMODE_16;
3627 default_cmode = CMODE_32;
3634 * Why do we need this silly Mach64 argument?
3635 * We are already here because of mach64= so its redundant.
3637 else if (MACH_IS_ATARI
3638 && (!strncmp(this_opt, "Mach64:", 7))) {
3639 static unsigned char m64_num;
3640 static char mach64_str[80];
3641 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3642 if (!store_video_par(mach64_str, m64_num)) {
3644 mach64_count = m64_num;
3655 static int __init atyfb_init(void)
3658 char *option = NULL;
3660 if (fb_get_options("atyfb", &option))
3662 atyfb_setup(option);
3666 pci_register_driver(&atyfb_driver);
3669 atyfb_atari_probe();
3674 static void __exit atyfb_exit(void)
3677 pci_unregister_driver(&atyfb_driver);
3681 module_init(atyfb_init);
3682 module_exit(atyfb_exit);
3684 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3685 MODULE_LICENSE("GPL");
3686 module_param(noaccel, bool, 0);
3687 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3688 module_param(vram, int, 0);
3689 MODULE_PARM_DESC(vram, "int: override size of video ram");
3690 module_param(pll, int, 0);
3691 MODULE_PARM_DESC(pll, "int: override video clock");
3692 module_param(mclk, int, 0);
3693 MODULE_PARM_DESC(mclk, "int: override memory clock");
3694 module_param(xclk, int, 0);
3695 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3696 module_param(comp_sync, int, 0);
3697 MODULE_PARM_DESC(comp_sync,
3698 "Set composite sync signal to low (0) or high (1)");
3699 module_param(mode, charp, 0);
3700 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3702 module_param(nomtrr, bool, 0);
3703 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob