2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
79 #include "../macmodes.h"
87 #include <linux/adb.h>
88 #include <linux/pmu.h>
90 #ifdef CONFIG_BOOTX_TEXT
91 #include <asm/btext.h>
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 #include <asm/backlight.h>
106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107 /* - must be large enough to catch all GUI-Regs */
108 /* - must be aligned to a PAGE boundary */
109 #define GUI_RESERVE (1 * PAGE_SIZE)
111 /* FIXME: remove the FAIL definition */
112 #define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
113 #define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
116 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
118 #define DPRINTK(fmt, args...)
121 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
122 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
124 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
125 static const u32 lt_lcd_regs[] = {
132 0, /* EXT_VERT_STRETCH */
137 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
139 if (M64_HAS(LT_LCD_REGS)) {
140 aty_st_le32(lt_lcd_regs[index], val, par);
144 /* write addr byte */
145 temp = aty_ld_le32(LCD_INDEX, par);
146 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
147 /* write the register value */
148 aty_st_le32(LCD_DATA, val, par);
152 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
154 if (M64_HAS(LT_LCD_REGS)) {
155 return aty_ld_le32(lt_lcd_regs[index], par);
159 /* write addr byte */
160 temp = aty_ld_le32(LCD_INDEX, par);
161 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
162 /* read the register value */
163 return aty_ld_le32(LCD_DATA, par);
166 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
168 #ifdef CONFIG_FB_ATY_GENERIC_LCD
172 * Reduce a fraction by factoring out the largest common divider of the
173 * fraction's numerator and denominator.
175 static void ATIReduceRatio(int *Numerator, int *Denominator)
177 int Multiplier, Divider, Remainder;
179 Multiplier = *Numerator;
180 Divider = *Denominator;
182 while ((Remainder = Multiplier % Divider))
184 Multiplier = Divider;
188 *Numerator /= Divider;
189 *Denominator /= Divider;
193 * The Hardware parameters for each card
196 struct aty_cmap_regs {
204 struct pci_mmap_map {
208 unsigned long prot_flag;
209 unsigned long prot_mask;
212 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
214 .type = FB_TYPE_PACKED_PIXELS,
215 .visual = FB_VISUAL_PSEUDOCOLOR,
221 * Frame buffer device API
224 static int atyfb_open(struct fb_info *info, int user);
225 static int atyfb_release(struct fb_info *info, int user);
226 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
227 static int atyfb_set_par(struct fb_info *info);
228 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
229 u_int transp, struct fb_info *info);
230 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
231 static int atyfb_blank(int blank, struct fb_info *info);
232 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
233 u_long arg, struct fb_info *info);
234 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
235 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
236 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
238 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
240 static int atyfb_sync(struct fb_info *info);
246 static int aty_init(struct fb_info *info, const char *name);
248 static int store_video_par(char *videopar, unsigned char m64_num);
251 static struct crtc saved_crtc;
252 static union aty_pll saved_pll;
253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
260 static int read_aty_sense(const struct atyfb_par *par);
265 * Interface used by the world
268 static struct fb_var_screeninfo default_var = {
269 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
270 640, 480, 640, 480, 0, 0, 8, 0,
271 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
272 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
273 0, FB_VMODE_NONINTERLACED
276 static struct fb_videomode defmode = {
277 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
278 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
279 0, FB_VMODE_NONINTERLACED
282 static struct fb_ops atyfb_ops = {
283 .owner = THIS_MODULE,
284 .fb_open = atyfb_open,
285 .fb_release = atyfb_release,
286 .fb_check_var = atyfb_check_var,
287 .fb_set_par = atyfb_set_par,
288 .fb_setcolreg = atyfb_setcolreg,
289 .fb_pan_display = atyfb_pan_display,
290 .fb_blank = atyfb_blank,
291 .fb_ioctl = atyfb_ioctl,
292 .fb_fillrect = atyfb_fillrect,
293 .fb_copyarea = atyfb_copyarea,
294 .fb_imageblit = atyfb_imageblit,
295 .fb_cursor = soft_cursor,
297 .fb_mmap = atyfb_mmap,
299 .fb_sync = atyfb_sync,
310 static int comp_sync __initdata = -1;
314 static int default_vmode __initdata = VMODE_CHOOSE;
315 static int default_cmode __initdata = CMODE_CHOOSE;
317 module_param_named(vmode, default_vmode, int, 0);
318 MODULE_PARM_DESC(vmode, "int: video mode for mac");
319 module_param_named(cmode, default_cmode, int, 0);
320 MODULE_PARM_DESC(cmode, "int: color mode for mac");
324 static unsigned int mach64_count __initdata = 0;
325 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
326 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
327 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
330 /* top -> down is an evolution of mach64 chipset, any corrections? */
331 #define ATI_CHIP_88800GX (M64F_GX)
332 #define ATI_CHIP_88800CX (M64F_GX)
334 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
335 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
337 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
338 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
340 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
341 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
342 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
344 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
346 /* make sets shorter */
347 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
349 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
350 /*#define ATI_CHIP_264GTDVD ?*/
351 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
353 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
354 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
355 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
357 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
358 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
365 } aty_chips[] __devinitdata = {
366 #ifdef CONFIG_FB_ATY_GX
368 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
369 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
370 #endif /* CONFIG_FB_ATY_GX */
372 #ifdef CONFIG_FB_ATY_CT
373 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
374 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
375 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
376 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
377 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
378 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB },
379 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
381 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
382 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
383 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
385 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
387 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
388 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
389 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
390 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
392 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
393 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
394 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
395 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
396 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
398 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
399 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
400 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
401 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
402 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
404 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
405 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
406 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
407 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 230, 83, 63, ATI_CHIP_264XL },
408 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
409 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
411 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
412 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
413 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
414 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
415 #endif /* CONFIG_FB_ATY_CT */
419 static int __devinit correct_chipset(struct atyfb_par *par)
427 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
428 if (par->pci_id == aty_chips[i].pci_id)
431 name = aty_chips[i].name;
432 par->pll_limits.pll_max = aty_chips[i].pll;
433 par->pll_limits.mclk = aty_chips[i].mclk;
434 par->pll_limits.xclk = aty_chips[i].xclk;
435 par->features = aty_chips[i].features;
437 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
438 type = chip_id & CFG_CHIP_TYPE;
439 rev = (chip_id & CFG_CHIP_REV) >> 24;
441 switch(par->pci_id) {
442 #ifdef CONFIG_FB_ATY_GX
443 case PCI_CHIP_MACH64GX:
447 case PCI_CHIP_MACH64CX:
452 #ifdef CONFIG_FB_ATY_CT
453 case PCI_CHIP_MACH64VT:
456 name = "ATI264VTA3 (Mach64 VT)";
457 par->pll_limits.pll_max = 170;
458 par->pll_limits.mclk = 67;
459 par->pll_limits.xclk = 67;
460 par->features = ATI_CHIP_264VT;
461 } else if(rev == 0x40) {
462 name = "ATI264VTA4 (Mach64 VT)";
463 par->pll_limits.pll_max = 200;
464 par->pll_limits.mclk = 67;
465 par->pll_limits.xclk = 67;
466 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
468 name = "ATI264VTB (Mach64 VT)";
469 par->pll_limits.pll_max = 200;
470 par->pll_limits.mclk = 67;
471 par->pll_limits.xclk = 67;
472 par->features = ATI_CHIP_264VTB;
475 case PCI_CHIP_MACH64GT:
478 par->pll_limits.pll_max = 170;
479 par->pll_limits.mclk = 67;
480 par->pll_limits.xclk = 67;
481 par->features = ATI_CHIP_264GTB;
482 } else if(rev == 0x02) {
483 par->pll_limits.pll_max = 200;
484 par->pll_limits.mclk = 67;
485 par->pll_limits.xclk = 67;
486 par->features = ATI_CHIP_264GTB;
492 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
496 static char ram_dram[] __devinitdata = "DRAM";
497 static char ram_resv[] __devinitdata = "RESV";
498 #ifdef CONFIG_FB_ATY_GX
499 static char ram_vram[] __devinitdata = "VRAM";
500 #endif /* CONFIG_FB_ATY_GX */
501 #ifdef CONFIG_FB_ATY_CT
502 static char ram_edo[] __devinitdata = "EDO";
503 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
504 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
505 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
506 static char ram_off[] __devinitdata = "OFF";
507 #endif /* CONFIG_FB_ATY_CT */
510 static u32 pseudo_palette[17];
512 #ifdef CONFIG_FB_ATY_GX
513 static char *aty_gx_ram[8] __devinitdata = {
514 ram_dram, ram_vram, ram_vram, ram_dram,
515 ram_dram, ram_vram, ram_vram, ram_resv
517 #endif /* CONFIG_FB_ATY_GX */
519 #ifdef CONFIG_FB_ATY_CT
520 static char *aty_ct_ram[8] __devinitdata = {
521 ram_off, ram_dram, ram_edo, ram_edo,
522 ram_sdram, ram_sgram, ram_sdram32, ram_resv
524 #endif /* CONFIG_FB_ATY_CT */
526 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
528 u32 pixclock = var->pixclock;
529 #ifdef CONFIG_FB_ATY_GENERIC_LCD
531 par->pll.ct.xres = 0;
532 if (par->lcd_table != 0) {
533 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
534 if(lcd_on_off & LCD_ON) {
535 par->pll.ct.xres = var->xres;
536 pixclock = par->lcd_pixclock;
543 #if defined(CONFIG_PPC)
546 * Apple monitor sense
549 static int __init read_aty_sense(const struct atyfb_par *par)
553 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
555 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
557 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
558 sense = ((i & 0x3000) >> 3) | (i & 0x100);
560 /* drive each sense line low in turn and collect the other 2 */
561 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
563 i = aty_ld_le32(GP_IO, par);
564 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
565 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
568 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
570 i = aty_ld_le32(GP_IO, par);
571 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
572 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
575 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
577 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
578 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
582 #endif /* defined(CONFIG_PPC) */
584 /* ------------------------------------------------------------------------- */
590 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
592 #ifdef CONFIG_FB_ATY_GENERIC_LCD
593 if (par->lcd_table != 0) {
594 if(!M64_HAS(LT_LCD_REGS)) {
595 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
596 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
598 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
599 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
602 /* switch to non shadow registers */
603 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
604 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
606 /* save stretching */
607 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
608 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
609 if (!M64_HAS(LT_LCD_REGS))
610 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
613 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
614 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
615 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
616 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
617 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
618 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
619 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
621 #ifdef CONFIG_FB_ATY_GENERIC_LCD
622 if (par->lcd_table != 0) {
623 /* switch to shadow registers */
624 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
625 SHADOW_EN | SHADOW_RW_EN, par);
627 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
628 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
629 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
630 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
632 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
634 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
637 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
639 #ifdef CONFIG_FB_ATY_GENERIC_LCD
640 if (par->lcd_table != 0) {
642 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
644 /* update non-shadow registers first */
645 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
646 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
647 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
649 /* temporarily disable stretching */
650 aty_st_lcd(HORZ_STRETCHING,
651 crtc->horz_stretching &
652 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
653 aty_st_lcd(VERT_STRETCHING,
654 crtc->vert_stretching &
655 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
656 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
660 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
662 DPRINTK("setting up CRTC\n");
663 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
664 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
665 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
666 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
668 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
669 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
670 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
671 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
672 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
673 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
674 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
676 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
677 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
678 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
679 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
680 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
681 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
683 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
686 if (par->accel_flags & FB_ACCELF_TEXT)
687 aty_init_engine(par, info);
689 #ifdef CONFIG_FB_ATY_GENERIC_LCD
690 /* after setting the CRTC registers we should set the LCD registers. */
691 if (par->lcd_table != 0) {
692 /* switch to shadow registers */
693 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
694 (SHADOW_EN | SHADOW_RW_EN), par);
696 DPRINTK("set secondary CRT to %ix%i %c%c\n",
697 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
698 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
700 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
701 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
702 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
703 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
705 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
706 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
707 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
708 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
710 /* restore CRTC selection & shadow state and enable stretching */
711 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
712 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
713 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
714 if(!M64_HAS(LT_LCD_REGS))
715 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
717 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
718 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
719 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
720 if(!M64_HAS(LT_LCD_REGS)) {
721 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
722 aty_ld_le32(LCD_INDEX, par);
723 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
726 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
729 static int aty_var_to_crtc(const struct fb_info *info,
730 const struct fb_var_screeninfo *var, struct crtc *crtc)
732 struct atyfb_par *par = (struct atyfb_par *) info->par;
733 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
734 u32 sync, vmode, vdisplay;
735 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
736 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
737 u32 pix_width, dp_pix_width, dp_chain_mask;
742 vxres = var->xres_virtual;
743 vyres = var->yres_virtual;
744 xoffset = var->xoffset;
745 yoffset = var->yoffset;
746 bpp = var->bits_per_pixel;
748 bpp = (var->green.length == 5) ? 15 : 16;
752 /* convert (and round up) and validate */
753 if (vxres < xres + xoffset)
754 vxres = xres + xoffset;
757 if (vyres < yres + yoffset)
758 vyres = yres + yoffset;
763 pix_width = CRTC_PIX_WIDTH_8BPP;
765 HOST_8BPP | SRC_8BPP | DST_8BPP |
766 BYTE_ORDER_LSB_TO_MSB;
767 dp_chain_mask = DP_CHAIN_8BPP;
768 } else if (bpp <= 15) {
770 pix_width = CRTC_PIX_WIDTH_15BPP;
771 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
772 BYTE_ORDER_LSB_TO_MSB;
773 dp_chain_mask = DP_CHAIN_15BPP;
774 } else if (bpp <= 16) {
776 pix_width = CRTC_PIX_WIDTH_16BPP;
777 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
778 BYTE_ORDER_LSB_TO_MSB;
779 dp_chain_mask = DP_CHAIN_16BPP;
780 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
782 pix_width = CRTC_PIX_WIDTH_24BPP;
784 HOST_8BPP | SRC_8BPP | DST_8BPP |
785 BYTE_ORDER_LSB_TO_MSB;
786 dp_chain_mask = DP_CHAIN_24BPP;
787 } else if (bpp <= 32) {
789 pix_width = CRTC_PIX_WIDTH_32BPP;
790 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
791 BYTE_ORDER_LSB_TO_MSB;
792 dp_chain_mask = DP_CHAIN_32BPP;
796 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
797 FAIL("not enough video RAM");
799 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
800 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
802 if((xres > 1600) || (yres > 1200)) {
803 FAIL("MACH64 chips are designed for max 1600x1200\n"
804 "select anoter resolution.");
806 h_sync_strt = h_disp + var->right_margin;
807 h_sync_end = h_sync_strt + var->hsync_len;
808 h_sync_dly = var->right_margin & 7;
809 h_total = h_sync_end + h_sync_dly + var->left_margin;
811 v_sync_strt = v_disp + var->lower_margin;
812 v_sync_end = v_sync_strt + var->vsync_len;
813 v_total = v_sync_end + var->upper_margin;
815 #ifdef CONFIG_FB_ATY_GENERIC_LCD
816 if (par->lcd_table != 0) {
817 if(!M64_HAS(LT_LCD_REGS)) {
818 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
819 crtc->lcd_index = lcd_index &
820 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
821 aty_st_le32(LCD_INDEX, lcd_index, par);
824 if (!M64_HAS(MOBIL_BUS))
825 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
827 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
828 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
830 crtc->lcd_gen_cntl &=
831 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
832 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
833 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
834 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
836 if((crtc->lcd_gen_cntl & LCD_ON) &&
837 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
838 /* We cannot display the mode on the LCD. If the CRT is enabled
839 we can turn off the LCD.
840 If the CRT is off, it isn't a good idea to switch it on; we don't
841 know if one is connected. So it's better to fail then.
843 if (crtc->lcd_gen_cntl & CRT_ON) {
844 PRINTKI("Disable lcd panel, because video mode does not fit.\n");
845 crtc->lcd_gen_cntl &= ~LCD_ON;
846 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
848 FAIL("Video mode exceeds size of lcd panel.\nConnect this computer to a conventional monitor if you really need this mode.");
853 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
855 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
856 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
857 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
859 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
861 /* This is horror! When we simulate, say 640x480 on an 800x600
862 lcd monitor, the CRTC should be programmed 800x600 values for
863 the non visible part, but 640x480 for the visible part.
864 This code has been tested on a laptop with it's 1400x1050 lcd
865 monitor and a conventional monitor both switched on.
866 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
867 works with little glitches also with DOUBLESCAN modes
869 if (yres < par->lcd_height) {
870 VScan = par->lcd_height / yres;
873 vmode |= FB_VMODE_DOUBLE;
877 h_sync_strt = h_disp + par->lcd_right_margin;
878 h_sync_end = h_sync_strt + par->lcd_hsync_len;
879 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
880 h_total = h_disp + par->lcd_hblank_len;
882 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
883 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
884 v_total = v_disp + par->lcd_vblank_len / VScan;
886 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
888 h_disp = (h_disp >> 3) - 1;
889 h_sync_strt = (h_sync_strt >> 3) - 1;
890 h_sync_end = (h_sync_end >> 3) - 1;
891 h_total = (h_total >> 3) - 1;
892 h_sync_wid = h_sync_end - h_sync_strt;
894 FAIL_MAX("h_disp too large", h_disp, 0xff);
895 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
896 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
897 if(h_sync_wid > 0x1f)
899 FAIL_MAX("h_total too large", h_total, 0x1ff);
901 if (vmode & FB_VMODE_DOUBLE) {
909 #ifdef CONFIG_FB_ATY_GENERIC_LCD
910 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
911 vdisplay = par->lcd_height;
917 } else if(vdisplay < 480) {
920 } else if(vdisplay < 768) {
932 v_sync_wid = v_sync_end - v_sync_strt;
934 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
935 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
936 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
937 if(v_sync_wid > 0x1f)
939 FAIL_MAX("v_total too large", v_total, 0x7ff);
941 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
946 crtc->xoffset = xoffset;
947 crtc->yoffset = yoffset;
949 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
950 crtc->vline_crnt_vline = 0;
952 crtc->h_tot_disp = h_total | (h_disp<<16);
953 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
954 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
955 crtc->v_tot_disp = v_total | (v_disp<<16);
956 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
958 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
959 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
960 crtc->gen_cntl |= CRTC_VGA_LINEAR;
962 /* Enable doublescan mode if requested */
963 if (vmode & FB_VMODE_DOUBLE)
964 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
965 /* Enable interlaced mode if requested */
966 if (vmode & FB_VMODE_INTERLACED)
967 crtc->gen_cntl |= CRTC_INTERLACE_EN;
968 #ifdef CONFIG_FB_ATY_GENERIC_LCD
969 if (par->lcd_table != 0) {
971 if(vmode & FB_VMODE_DOUBLE)
973 if(vmode & FB_VMODE_INTERLACED) {
976 /* The prefered mode for the lcd is not interlaced, so disable it if
977 it was enabled. For doublescan there is no problem, because we can
978 compensate for it in the hardware stretching (we stretch half as much)
980 vmode &= ~FB_VMODE_INTERLACED;
981 /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
983 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
984 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
985 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
986 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
987 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
989 /* MOBILITY M1 tested, FIXME: LT */
990 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
991 if (!M64_HAS(LT_LCD_REGS))
992 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
993 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
995 crtc->horz_stretching &=
996 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
997 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
998 if (xres < par->lcd_width) {
1001 * The horizontal blender misbehaves when HDisplay is less than a
1002 * a certain threshold (440 for a 1024-wide panel). It doesn't
1003 * stretch such modes enough. Use pixel replication instead of
1004 * blending to stretch modes that can be made to exactly fit the
1005 * panel width. The undocumented "NoLCDBlend" option allows the
1006 * pixel-replicated mode to be slightly wider or narrower than the
1007 * panel width. It also causes a mode that is exactly half as wide
1008 * as the panel to be pixel-replicated, rather than blended.
1010 int HDisplay = xres & ~7;
1011 int nStretch = par->lcd_width / HDisplay;
1012 int Remainder = par->lcd_width % HDisplay;
1014 if ((!Remainder && ((nStretch > 2))) ||
1015 (((HDisplay * 16) / par->lcd_width) < 7)) {
1016 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1017 int horz_stretch_loop = -1, BestRemainder;
1018 int Numerator = HDisplay, Denominator = par->lcd_width;
1020 ATIReduceRatio(&Numerator, &Denominator);
1022 BestRemainder = (Numerator * 16) / Denominator;
1023 while (--Index >= 0) {
1024 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1026 if (Remainder < BestRemainder) {
1027 horz_stretch_loop = Index;
1028 if (!(BestRemainder = Remainder))
1033 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1034 int horz_stretch_ratio = 0, Accumulator = 0;
1035 int reuse_previous = 1;
1037 Index = StretchLoops[horz_stretch_loop];
1039 while (--Index >= 0) {
1040 if (Accumulator > 0)
1041 horz_stretch_ratio |= reuse_previous;
1043 Accumulator += Denominator;
1044 Accumulator -= Numerator;
1045 reuse_previous <<= 1;
1048 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1049 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1050 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1051 break; /* Out of the do { ... } while (0) */
1055 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1056 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1060 if (vdisplay < par->lcd_height) {
1061 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1062 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1064 if (!M64_HAS(LT_LCD_REGS) &&
1065 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1066 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1069 * Don't use vertical blending if the mode is too wide or not
1070 * vertically stretched.
1072 crtc->vert_stretching = 0;
1074 /* copy to shadow crtc */
1075 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1076 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1077 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1078 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1080 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1082 if (M64_HAS(MAGIC_FIFO)) {
1084 /* FIXME: magic FIFO values */
1085 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1087 crtc->dp_pix_width = dp_pix_width;
1088 crtc->dp_chain_mask = dp_chain_mask;
1093 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1095 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1096 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1098 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1100 u32 double_scan, interlace;
1103 h_total = crtc->h_tot_disp & 0x1ff;
1104 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1105 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1106 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1107 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1108 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1109 v_total = crtc->v_tot_disp & 0x7ff;
1110 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1111 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1112 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1113 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1114 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1115 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1116 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1117 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1120 xres = (h_disp + 1) * 8;
1122 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1123 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1124 hslen = h_sync_wid * 8;
1125 upper = v_total - v_sync_strt - v_sync_wid;
1126 lower = v_sync_strt - v_disp;
1128 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1129 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1130 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1132 switch (pix_width) {
1134 case CRTC_PIX_WIDTH_4BPP:
1136 var->red.offset = 0;
1137 var->red.length = 8;
1138 var->green.offset = 0;
1139 var->green.length = 8;
1140 var->blue.offset = 0;
1141 var->blue.length = 8;
1142 var->transp.offset = 0;
1143 var->transp.length = 0;
1146 case CRTC_PIX_WIDTH_8BPP:
1148 var->red.offset = 0;
1149 var->red.length = 8;
1150 var->green.offset = 0;
1151 var->green.length = 8;
1152 var->blue.offset = 0;
1153 var->blue.length = 8;
1154 var->transp.offset = 0;
1155 var->transp.length = 0;
1157 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1159 var->red.offset = 10;
1160 var->red.length = 5;
1161 var->green.offset = 5;
1162 var->green.length = 5;
1163 var->blue.offset = 0;
1164 var->blue.length = 5;
1165 var->transp.offset = 0;
1166 var->transp.length = 0;
1168 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1170 var->red.offset = 11;
1171 var->red.length = 5;
1172 var->green.offset = 5;
1173 var->green.length = 6;
1174 var->blue.offset = 0;
1175 var->blue.length = 5;
1176 var->transp.offset = 0;
1177 var->transp.length = 0;
1179 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1181 var->red.offset = 16;
1182 var->red.length = 8;
1183 var->green.offset = 8;
1184 var->green.length = 8;
1185 var->blue.offset = 0;
1186 var->blue.length = 8;
1187 var->transp.offset = 0;
1188 var->transp.length = 0;
1190 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1192 var->red.offset = 16;
1193 var->red.length = 8;
1194 var->green.offset = 8;
1195 var->green.length = 8;
1196 var->blue.offset = 0;
1197 var->blue.length = 8;
1198 var->transp.offset = 24;
1199 var->transp.length = 8;
1202 FAIL("Invalid pixel width");
1208 var->xres_virtual = crtc->vxres;
1209 var->yres_virtual = crtc->vyres;
1210 var->bits_per_pixel = bpp;
1211 var->left_margin = left;
1212 var->right_margin = right;
1213 var->upper_margin = upper;
1214 var->lower_margin = lower;
1215 var->hsync_len = hslen;
1216 var->vsync_len = vslen;
1218 var->vmode = FB_VMODE_NONINTERLACED;
1219 /* In double scan mode, the vertical parameters are doubled, so we need to
1220 half them to get the right values.
1221 In interlaced mode the values are already correct, so no correction is
1225 var->vmode = FB_VMODE_INTERLACED;
1228 var->vmode = FB_VMODE_DOUBLE;
1230 var->upper_margin>>=1;
1231 var->lower_margin>>=1;
1238 /* ------------------------------------------------------------------------- */
1240 static int atyfb_set_par(struct fb_info *info)
1242 struct atyfb_par *par = (struct atyfb_par *) info->par;
1243 struct fb_var_screeninfo *var = &info->var;
1247 struct fb_var_screeninfo debug;
1253 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1256 pixclock = atyfb_get_pixclock(var, par);
1258 if (pixclock == 0) {
1259 FAIL("Invalid pixclock");
1261 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1265 par->accel_flags = var->accel_flags; /* hack */
1267 if (par->blitter_may_be_busy)
1270 aty_set_crtc(par, &par->crtc);
1271 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1272 par->pll_ops->set_pll(info, &par->pll);
1275 if(par->pll_ops && par->pll_ops->pll_to_var)
1276 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1280 if(0 == pixclock_in_ps) {
1281 PRINTKE("ALERT ops->pll_to_var get 0\n");
1282 pixclock_in_ps = pixclock;
1285 memset(&debug, 0, sizeof(debug));
1286 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1287 u32 hSync, vRefresh;
1288 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1289 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1291 h_disp = debug.xres;
1292 h_sync_strt = h_disp + debug.right_margin;
1293 h_sync_end = h_sync_strt + debug.hsync_len;
1294 h_total = h_sync_end + debug.left_margin;
1295 v_disp = debug.yres;
1296 v_sync_strt = v_disp + debug.lower_margin;
1297 v_sync_end = v_sync_strt + debug.vsync_len;
1298 v_total = v_sync_end + debug.upper_margin;
1300 hSync = 1000000000 / (pixclock_in_ps * h_total);
1301 vRefresh = (hSync * 1000) / v_total;
1302 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1304 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1307 DPRINTK("atyfb_set_par\n");
1308 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1309 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1310 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1311 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1312 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1313 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1314 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1315 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1316 h_disp, h_sync_strt, h_sync_end, h_total,
1317 v_disp, v_sync_strt, v_sync_end, v_total);
1318 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1320 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1321 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1325 if (!M64_HAS(INTEGRATED)) {
1326 /* Don't forget MEM_CNTL */
1327 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1328 switch (var->bits_per_pixel) {
1339 aty_st_le32(MEM_CNTL, tmp, par);
1341 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1342 if (!M64_HAS(MAGIC_POSTDIV))
1343 tmp |= par->mem_refresh_rate << 20;
1344 switch (var->bits_per_pixel) {
1356 if (M64_HAS(CT_BUS)) {
1357 aty_st_le32(DAC_CNTL, 0x87010184, par);
1358 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1359 } else if (M64_HAS(VT_BUS)) {
1360 aty_st_le32(DAC_CNTL, 0x87010184, par);
1361 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1362 } else if (M64_HAS(MOBIL_BUS)) {
1363 aty_st_le32(DAC_CNTL, 0x80010102, par);
1364 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1367 aty_st_le32(DAC_CNTL, 0x86010102, par);
1368 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1369 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1371 aty_st_le32(MEM_CNTL, tmp, par);
1373 aty_st_8(DAC_MASK, 0xff, par);
1375 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1376 info->fix.visual = var->bits_per_pixel <= 8 ?
1377 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1379 /* Initialize the graphics engine */
1380 if (par->accel_flags & FB_ACCELF_TEXT)
1381 aty_init_engine(par, info);
1383 #ifdef CONFIG_BOOTX_TEXT
1384 btext_update_display(info->fix.smem_start,
1385 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1386 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1387 var->bits_per_pixel,
1388 par->crtc.vxres * var->bits_per_pixel / 8);
1389 #endif /* CONFIG_BOOTX_TEXT */
1391 /* switch to accelerator mode */
1392 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1393 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1397 /* dump non shadow CRTC, pll, LCD registers */
1400 /* CRTC registers */
1402 printk("debug atyfb: Mach64 non-shadow register values:");
1403 for (i = 0; i < 256; i = i+4) {
1404 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1405 printk(" %08X", aty_ld_le32(i, par));
1409 #ifdef CONFIG_FB_ATY_CT
1412 printk("debug atyfb: Mach64 PLL register values:");
1413 for (i = 0; i < 64; i++) {
1414 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1415 if(i%4 == 0) printk(" ");
1416 printk("%02X", aty_ld_pll_ct(i, par));
1419 #endif /* CONFIG_FB_ATY_CT */
1421 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1422 if (par->lcd_table != 0) {
1425 printk("debug atyfb: LCD register values:");
1426 if(M64_HAS(LT_LCD_REGS)) {
1427 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1428 if(i == EXT_VERT_STRETCH)
1430 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1431 printk(" %08X", aty_ld_lcd(i, par));
1435 for (i = 0; i < 64; i++) {
1436 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1437 printk(" %08X", aty_ld_lcd(i, par));
1442 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1448 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1450 struct atyfb_par *par = (struct atyfb_par *) info->par;
1456 memcpy(&pll, &(par->pll), sizeof(pll));
1458 if((err = aty_var_to_crtc(info, var, &crtc)))
1461 pixclock = atyfb_get_pixclock(var, par);
1463 if (pixclock == 0) {
1464 FAIL("Invalid pixclock");
1466 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1470 if (var->accel_flags & FB_ACCELF_TEXT)
1471 info->var.accel_flags = FB_ACCELF_TEXT;
1473 info->var.accel_flags = 0;
1475 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1476 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1479 aty_crtc_to_var(&crtc, var);
1480 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1484 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1486 u32 xoffset = info->var.xoffset;
1487 u32 yoffset = info->var.yoffset;
1488 u32 vxres = par->crtc.vxres;
1489 u32 bpp = info->var.bits_per_pixel;
1491 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1496 * Open/Release the frame buffer device
1499 static int atyfb_open(struct fb_info *info, int user)
1501 struct atyfb_par *par = (struct atyfb_par *) info->par;
1512 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1514 struct atyfb_par *par = dev_id;
1518 spin_lock(&par->int_lock);
1520 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1522 if (int_cntl & CRTC_VBLANK_INT) {
1523 /* clear interrupt */
1524 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1525 par->vblank.count++;
1526 if (par->vblank.pan_display) {
1527 par->vblank.pan_display = 0;
1528 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1530 wake_up_interruptible(&par->vblank.wait);
1534 spin_unlock(&par->int_lock);
1536 return IRQ_RETVAL(handled);
1539 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1543 if (!test_and_set_bit(0, &par->irq_flags)) {
1544 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1545 clear_bit(0, &par->irq_flags);
1548 spin_lock_irq(&par->int_lock);
1549 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1550 /* clear interrupt */
1551 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1552 /* enable interrupt */
1553 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1554 spin_unlock_irq(&par->int_lock);
1555 } else if (reenable) {
1556 spin_lock_irq(&par->int_lock);
1557 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1558 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1559 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1560 /* re-enable interrupt */
1561 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1563 spin_unlock_irq(&par->int_lock);
1569 static int aty_disable_irq(struct atyfb_par *par)
1573 if (test_and_clear_bit(0, &par->irq_flags)) {
1574 if (par->vblank.pan_display) {
1575 par->vblank.pan_display = 0;
1576 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1578 spin_lock_irq(&par->int_lock);
1579 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1580 /* disable interrupt */
1581 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1582 spin_unlock_irq(&par->int_lock);
1583 free_irq(par->irq, par);
1589 static int atyfb_release(struct fb_info *info, int user)
1591 struct atyfb_par *par = (struct atyfb_par *) info->par;
1598 int was_mmaped = par->mmaped;
1603 struct fb_var_screeninfo var;
1605 /* Now reset the default display config, we have no
1606 * idea what the program(s) which mmap'd the chip did
1607 * to the configuration, nor whether it restored it
1612 var.accel_flags &= ~FB_ACCELF_TEXT;
1614 var.accel_flags |= FB_ACCELF_TEXT;
1615 if (var.yres == var.yres_virtual) {
1616 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1617 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1618 if (var.yres_virtual < var.yres)
1619 var.yres_virtual = var.yres;
1623 aty_disable_irq(par);
1630 * Pan or Wrap the Display
1632 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1635 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1637 struct atyfb_par *par = (struct atyfb_par *) info->par;
1638 u32 xres, yres, xoffset, yoffset;
1640 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1641 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1642 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1644 xoffset = (var->xoffset + 7) & ~7;
1645 yoffset = var->yoffset;
1646 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1648 info->var.xoffset = xoffset;
1649 info->var.yoffset = yoffset;
1653 set_off_pitch(par, info);
1654 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1655 par->vblank.pan_display = 1;
1657 par->vblank.pan_display = 0;
1658 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1664 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1666 struct aty_interrupt *vbl;
1678 ret = aty_enable_irq(par, 0);
1683 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1688 aty_enable_irq(par, 1);
1697 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1698 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1704 u8 mclk_post_div; /* 1,2,3,4,8 */
1705 u8 mclk_fb_mult; /* 2 or 4 */
1706 u8 xclk_post_div; /* 1,2,3,4,8 */
1708 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1709 u32 dsp_xclks_per_row; /* 0-16383 */
1710 u32 dsp_loop_latency; /* 0-15 */
1711 u32 dsp_precision; /* 0-7 */
1712 u32 dsp_on; /* 0-2047 */
1713 u32 dsp_off; /* 0-2047 */
1716 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1717 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1720 #ifndef FBIO_WAITFORVSYNC
1721 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1724 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1725 u_long arg, struct fb_info *info)
1727 struct atyfb_par *par = (struct atyfb_par *) info->par;
1729 struct fbtype fbtyp;
1735 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1736 fbtyp.fb_width = par->crtc.vxres;
1737 fbtyp.fb_height = par->crtc.vyres;
1738 fbtyp.fb_depth = info->var.bits_per_pixel;
1739 fbtyp.fb_cmsize = info->cmap.len;
1740 fbtyp.fb_size = info->fix.smem_len;
1741 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1744 #endif /* __sparc__ */
1746 case FBIO_WAITFORVSYNC:
1750 if (get_user(crtc, (__u32 __user *) arg))
1753 return aty_waitforvblank(par, crtc);
1757 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1759 if (M64_HAS(INTEGRATED)) {
1761 union aty_pll *pll = &(par->pll);
1762 u32 dsp_config = pll->ct.dsp_config;
1763 u32 dsp_on_off = pll->ct.dsp_on_off;
1764 clk.ref_clk_per = par->ref_clk_per;
1765 clk.pll_ref_div = pll->ct.pll_ref_div;
1766 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1767 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1768 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1769 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1770 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1771 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1772 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1773 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1774 clk.dsp_precision = (dsp_config >> 20) & 7;
1775 clk.dsp_off = dsp_on_off & 0x7ff;
1776 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1777 if (copy_to_user((struct atyclk __user *) arg, &clk,
1784 if (M64_HAS(INTEGRATED)) {
1786 union aty_pll *pll = &(par->pll);
1787 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1789 par->ref_clk_per = clk.ref_clk_per;
1790 pll->ct.pll_ref_div = clk.pll_ref_div;
1791 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1792 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1793 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1794 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1795 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1796 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1797 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1798 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1799 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1800 /*aty_calc_pll_ct(info, &pll->ct);*/
1801 aty_set_pll_ct(info, pll);
1806 if (get_user(par->features, (u32 __user *) arg))
1810 if (put_user(par->features, (u32 __user *) arg))
1813 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1820 static int atyfb_sync(struct fb_info *info)
1822 struct atyfb_par *par = (struct atyfb_par *) info->par;
1824 if (par->blitter_may_be_busy)
1830 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1832 struct atyfb_par *par = (struct atyfb_par *) info->par;
1833 unsigned int size, page, map_size = 0;
1834 unsigned long map_offset = 0;
1841 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1844 off = vma->vm_pgoff << PAGE_SHIFT;
1845 size = vma->vm_end - vma->vm_start;
1847 /* To stop the swapper from even considering these pages. */
1848 vma->vm_flags |= (VM_IO | VM_RESERVED);
1850 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1851 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1852 off += 0x8000000000000000UL;
1854 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1856 /* Each page, see which map applies */
1857 for (page = 0; page < size;) {
1859 for (i = 0; par->mmap_map[i].size; i++) {
1860 unsigned long start = par->mmap_map[i].voff;
1861 unsigned long end = start + par->mmap_map[i].size;
1862 unsigned long offset = off + page;
1869 map_size = par->mmap_map[i].size - (offset - start);
1871 par->mmap_map[i].poff + (offset - start);
1878 if (page + map_size > size)
1879 map_size = size - page;
1881 pgprot_val(vma->vm_page_prot) &=
1882 ~(par->mmap_map[i].prot_mask);
1883 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1885 if (remap_pfn_range(vma, vma->vm_start + page,
1886 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1907 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1911 for (i = 0; i < 256; i++) {
1912 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1913 if (M64_HAS(EXTRA_BRIGHT))
1915 aty_st_8(DAC_CNTL, tmp, par);
1916 aty_st_8(DAC_MASK, 0xff, par);
1918 writeb(i, &par->aty_cmap_regs->rindex);
1919 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1920 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1921 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1922 writeb(i, &par->aty_cmap_regs->windex);
1923 writeb(atyfb_save.r[1 - enter][i],
1924 &par->aty_cmap_regs->lut);
1925 writeb(atyfb_save.g[1 - enter][i],
1926 &par->aty_cmap_regs->lut);
1927 writeb(atyfb_save.b[1 - enter][i],
1928 &par->aty_cmap_regs->lut);
1932 static void atyfb_palette(int enter)
1934 struct atyfb_par *par;
1935 struct fb_info *info;
1938 for (i = 0; i < FB_MAX; i++) {
1939 info = registered_fb[i];
1940 if (info && info->fbops == &atyfb_ops) {
1941 par = (struct atyfb_par *) info->par;
1943 atyfb_save_palette(par, enter);
1945 atyfb_save.yoffset = info->var.yoffset;
1946 info->var.yoffset = 0;
1947 set_off_pitch(par, info);
1949 info->var.yoffset = atyfb_save.yoffset;
1950 set_off_pitch(par, info);
1952 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1957 #endif /* __sparc__ */
1961 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1963 /* Power management routines. Those are used for PowerBook sleep.
1965 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1970 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1971 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1972 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1973 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1979 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1980 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1982 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1984 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1985 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1990 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1992 if ((--timeout) == 0)
1994 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1998 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2002 pm |= (PWR_BLON | AUTO_PWR_UP);
2003 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2004 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2009 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2011 if ((--timeout) == 0)
2013 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2017 return timeout ? 0 : -EIO;
2020 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2022 struct fb_info *info = pci_get_drvdata(pdev);
2023 struct atyfb_par *par = (struct atyfb_par *) info->par;
2025 #ifndef CONFIG_PPC_PMAC
2026 /* HACK ALERT ! Once I find a proper way to say to each driver
2027 * individually what will happen with it's PCI slot, I'll change
2028 * that. On laptops, the AGP slot is just unclocked, so D2 is
2029 * expected, while on desktops, the card is powered off
2032 #endif /* CONFIG_PPC_PMAC */
2034 if (state.event == pdev->dev.power.power_state.event)
2037 acquire_console_sem();
2039 fb_set_suspend(info, 1);
2041 /* Idle & reset engine */
2043 aty_reset_engine(par);
2045 /* Blank display and LCD */
2046 atyfb_blank(FB_BLANK_POWERDOWN, info);
2049 par->lock_blank = 1;
2051 /* Set chip to "suspend" mode */
2052 if (aty_power_mgmt(1, par)) {
2054 par->lock_blank = 0;
2055 atyfb_blank(FB_BLANK_UNBLANK, info);
2056 fb_set_suspend(info, 0);
2057 release_console_sem();
2061 release_console_sem();
2063 pdev->dev.power.power_state = state;
2068 static int atyfb_pci_resume(struct pci_dev *pdev)
2070 struct fb_info *info = pci_get_drvdata(pdev);
2071 struct atyfb_par *par = (struct atyfb_par *) info->par;
2073 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2076 acquire_console_sem();
2078 if (pdev->dev.power.power_state.event == 2)
2079 aty_power_mgmt(0, par);
2082 /* Restore display */
2083 atyfb_set_par(info);
2086 fb_set_suspend(info, 0);
2089 par->lock_blank = 0;
2090 atyfb_blank(FB_BLANK_UNBLANK, info);
2092 release_console_sem();
2094 pdev->dev.power.power_state = PMSG_ON;
2099 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2101 #ifdef CONFIG_PMAC_BACKLIGHT
2104 * LCD backlight control
2107 static int backlight_conv[] = {
2108 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2109 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2112 static int aty_set_backlight_enable(int on, int level, void *data)
2114 struct fb_info *info = (struct fb_info *) data;
2115 struct atyfb_par *par = (struct atyfb_par *) info->par;
2116 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2118 reg |= (BLMOD_EN | BIASMOD_EN);
2119 if (on && level > BACKLIGHT_OFF) {
2120 reg &= ~BIAS_MOD_LEVEL_MASK;
2121 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2123 reg &= ~BIAS_MOD_LEVEL_MASK;
2124 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2126 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2130 static int aty_set_backlight_level(int level, void *data)
2132 return aty_set_backlight_enable(1, level, data);
2135 static struct backlight_controller aty_backlight_controller = {
2136 aty_set_backlight_enable,
2137 aty_set_backlight_level
2139 #endif /* CONFIG_PMAC_BACKLIGHT */
2141 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2143 const int ragepro_tbl[] = {
2144 44, 50, 55, 66, 75, 80, 100
2146 const int ragexl_tbl[] = {
2147 50, 66, 75, 83, 90, 95, 100, 105,
2148 110, 115, 120, 125, 133, 143, 166
2150 const int *refresh_tbl;
2153 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2154 refresh_tbl = ragexl_tbl;
2155 size = sizeof(ragexl_tbl)/sizeof(int);
2157 refresh_tbl = ragepro_tbl;
2158 size = sizeof(ragepro_tbl)/sizeof(int);
2161 for (i=0; i < size; i++) {
2162 if (xclk < refresh_tbl[i])
2165 par->mem_refresh_rate = i;
2172 static struct fb_info *fb_list = NULL;
2174 static int __init aty_init(struct fb_info *info, const char *name)
2176 struct atyfb_par *par = (struct atyfb_par *) info->par;
2177 const char *ramname = NULL, *xtal;
2179 struct fb_var_screeninfo var;
2182 #if defined(CONFIG_PPC)
2186 init_waitqueue_head(&par->vblank.wait);
2187 spin_lock_init(&par->int_lock);
2189 par->aty_cmap_regs =
2190 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2192 #ifdef CONFIG_PPC_PMAC
2193 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2194 * and set the frequency manually. */
2195 if (machine_is_compatible("PowerBook2,1")) {
2196 par->pll_limits.mclk = 70;
2197 par->pll_limits.xclk = 53;
2201 par->pll_limits.pll_max = pll;
2203 par->pll_limits.mclk = mclk;
2205 par->pll_limits.xclk = xclk;
2207 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2208 par->pll_per = 1000000/par->pll_limits.pll_max;
2209 par->mclk_per = 1000000/par->pll_limits.mclk;
2210 par->xclk_per = 1000000/par->pll_limits.xclk;
2212 par->ref_clk_per = 1000000000000ULL / 14318180;
2215 #ifdef CONFIG_FB_ATY_GX
2216 if (!M64_HAS(INTEGRATED)) {
2218 u8 dac_type, dac_subtype, clk_type;
2219 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2220 par->bus_type = (stat0 >> 0) & 0x07;
2221 par->ram_type = (stat0 >> 3) & 0x07;
2222 ramname = aty_gx_ram[par->ram_type];
2223 /* FIXME: clockchip/RAMDAC probing? */
2224 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2226 clk_type = CLK_ATI18818_1;
2227 dac_type = (stat0 >> 9) & 0x07;
2228 if (dac_type == 0x07)
2229 dac_subtype = DAC_ATT20C408;
2231 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2233 dac_type = DAC_IBMRGB514;
2234 dac_subtype = DAC_IBMRGB514;
2235 clk_type = CLK_IBMRGB514;
2237 switch (dac_subtype) {
2239 par->dac_ops = &aty_dac_ibm514;
2241 case DAC_ATI68860_B:
2242 case DAC_ATI68860_C:
2243 par->dac_ops = &aty_dac_ati68860b;
2247 par->dac_ops = &aty_dac_att21c498;
2250 PRINTKI("aty_init: DAC type not implemented yet!\n");
2251 par->dac_ops = &aty_dac_unsupported;
2255 case CLK_ATI18818_1:
2256 par->pll_ops = &aty_pll_ati18818_1;
2259 par->pll_ops = &aty_pll_stg1703;
2262 par->pll_ops = &aty_pll_ch8398;
2265 par->pll_ops = &aty_pll_att20c408;
2268 par->pll_ops = &aty_pll_ibm514;
2271 PRINTKI("aty_init: CLK type not implemented yet!");
2272 par->pll_ops = &aty_pll_unsupported;
2276 #endif /* CONFIG_FB_ATY_GX */
2277 #ifdef CONFIG_FB_ATY_CT
2278 if (M64_HAS(INTEGRATED)) {
2279 par->dac_ops = &aty_dac_ct;
2280 par->pll_ops = &aty_pll_ct;
2281 par->bus_type = PCI;
2282 #ifdef CONFIG_FB_ATY_XL_INIT
2283 if (IS_XL(par->pci_id))
2284 atyfb_xl_init(info);
2286 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2287 ramname = aty_ct_ram[par->ram_type];
2288 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2289 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2290 par->pll_limits.mclk = 63;
2293 if (M64_HAS(GTB_DSP)
2294 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2296 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2297 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2302 if (diff2 < diff1) {
2303 par->ref_clk_per = 1000000000000ULL / 29498928;
2307 #endif /* CONFIG_FB_ATY_CT */
2309 /* save previous video mode */
2310 aty_get_crtc(par, &saved_crtc);
2311 if(par->pll_ops->get_pll)
2312 par->pll_ops->get_pll(info, &saved_pll);
2314 i = aty_ld_le32(MEM_CNTL, par);
2315 gtb_memsize = M64_HAS(GTB_DSP);
2317 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2319 info->fix.smem_len = 0x80000;
2322 info->fix.smem_len = 0x100000;
2324 case MEM_SIZE_2M_GTB:
2325 info->fix.smem_len = 0x200000;
2327 case MEM_SIZE_4M_GTB:
2328 info->fix.smem_len = 0x400000;
2330 case MEM_SIZE_6M_GTB:
2331 info->fix.smem_len = 0x600000;
2333 case MEM_SIZE_8M_GTB:
2334 info->fix.smem_len = 0x800000;
2337 info->fix.smem_len = 0x80000;
2339 switch (i & MEM_SIZE_ALIAS) {
2341 info->fix.smem_len = 0x80000;
2344 info->fix.smem_len = 0x100000;
2347 info->fix.smem_len = 0x200000;
2350 info->fix.smem_len = 0x400000;
2353 info->fix.smem_len = 0x600000;
2356 info->fix.smem_len = 0x800000;
2359 info->fix.smem_len = 0x80000;
2362 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2363 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2364 info->fix.smem_len += 0x400000;
2368 info->fix.smem_len = vram * 1024;
2369 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2370 if (info->fix.smem_len <= 0x80000)
2372 else if (info->fix.smem_len <= 0x100000)
2374 else if (info->fix.smem_len <= 0x200000)
2375 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2376 else if (info->fix.smem_len <= 0x400000)
2377 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2378 else if (info->fix.smem_len <= 0x600000)
2379 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2381 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2382 aty_st_le32(MEM_CNTL, i, par);
2386 * Reg Block 0 (CT-compatible block) is at mmio_start
2387 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2390 info->fix.mmio_len = 0x400;
2391 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2392 } else if (M64_HAS(CT)) {
2393 info->fix.mmio_len = 0x400;
2394 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2395 } else if (M64_HAS(VT)) {
2396 info->fix.mmio_start -= 0x400;
2397 info->fix.mmio_len = 0x800;
2398 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2400 info->fix.mmio_start -= 0x400;
2401 info->fix.mmio_len = 0x800;
2402 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2405 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2406 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2407 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2408 par->pll_limits.mclk, par->pll_limits.xclk);
2410 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2411 if (M64_HAS(INTEGRATED)) {
2413 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2414 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2415 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2417 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2418 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2419 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2420 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2421 for (i = 0; i < 40; i++)
2422 printk(" %02x", aty_ld_pll_ct(i, par));
2426 if(par->pll_ops->init_pll)
2427 par->pll_ops->init_pll(info, &par->pll);
2430 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2431 * FIXME: we should use the auxiliary aperture instead so we can access
2432 * the full 8 MB of video RAM on 8 MB boards
2435 if (!par->aux_start &&
2436 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2437 info->fix.smem_len -= GUI_RESERVE;
2440 * Disable register access through the linear aperture
2441 * if the auxiliary aperture is used so we can access
2442 * the full 8 MB of video RAM on 8 MB boards.
2445 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2448 par->mtrr_aper = -1;
2451 /* Cover the whole resource. */
2452 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2453 if (par->mtrr_aper >= 0 && !par->aux_start) {
2454 /* Make a hole for mmio. */
2455 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2456 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2457 if (par->mtrr_reg < 0) {
2458 mtrr_del(par->mtrr_aper, 0, 0);
2459 par->mtrr_aper = -1;
2465 info->fbops = &atyfb_ops;
2466 info->pseudo_palette = pseudo_palette;
2467 info->flags = FBINFO_FLAG_DEFAULT;
2469 #ifdef CONFIG_PMAC_BACKLIGHT
2470 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2471 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2472 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2473 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2474 } else if (M64_HAS(MOBIL_BUS))
2475 register_backlight_controller(&aty_backlight_controller, info, "ati");
2476 #endif /* CONFIG_PMAC_BACKLIGHT */
2478 memset(&var, 0, sizeof(var));
2480 if (_machine == _MACH_Pmac) {
2482 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2483 * applies to all Mac video cards
2486 if (!mac_find_mode(&var, info, mode, 8))
2489 if (default_vmode == VMODE_CHOOSE) {
2490 if (M64_HAS(G3_PB_1024x768))
2491 /* G3 PowerBook with 1024x768 LCD */
2492 default_vmode = VMODE_1024_768_60;
2493 else if (machine_is_compatible("iMac"))
2494 default_vmode = VMODE_1024_768_75;
2495 else if (machine_is_compatible
2497 /* iBook with 800x600 LCD */
2498 default_vmode = VMODE_800_600_60;
2500 default_vmode = VMODE_640_480_67;
2501 sense = read_aty_sense(par);
2502 PRINTKI("monitor sense=%x, mode %d\n",
2503 sense, mac_map_monitor_sense(sense));
2505 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2506 default_vmode = VMODE_640_480_60;
2507 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2508 default_cmode = CMODE_8;
2509 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
2513 #endif /* !CONFIG_PPC */
2515 #if defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
2516 /* On Sparc, unless the user gave a specific mode
2517 * specification, use the PROM probed values in
2522 !fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2526 var.accel_flags &= ~FB_ACCELF_TEXT;
2528 var.accel_flags |= FB_ACCELF_TEXT;
2530 if (comp_sync != -1) {
2532 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2534 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2537 if (var.yres == var.yres_virtual) {
2538 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2539 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2540 if (var.yres_virtual < var.yres)
2541 var.yres_virtual = var.yres;
2544 if (atyfb_check_var(&var, info)) {
2545 PRINTKE("can't set default video mode\n");
2550 atyfb_save_palette(par, 0);
2553 #ifdef CONFIG_FB_ATY_CT
2554 if (!noaccel && M64_HAS(INTEGRATED))
2555 aty_init_cursor(info);
2556 #endif /* CONFIG_FB_ATY_CT */
2559 fb_alloc_cmap(&info->cmap, 256, 0);
2561 if (register_framebuffer(info) < 0)
2566 PRINTKI("fb%d: %s frame buffer device on %s\n",
2567 info->node, info->fix.id, name);
2571 /* restore video mode */
2572 aty_set_crtc(par, &saved_crtc);
2573 par->pll_ops->set_pll(info, &saved_pll);
2576 if (par->mtrr_reg >= 0) {
2577 mtrr_del(par->mtrr_reg, 0, 0);
2580 if (par->mtrr_aper >= 0) {
2581 mtrr_del(par->mtrr_aper, 0, 0);
2582 par->mtrr_aper = -1;
2589 static int __init store_video_par(char *video_str, unsigned char m64_num)
2592 unsigned long vmembase, size, guiregbase;
2594 PRINTKI("store_video_par() '%s' \n", video_str);
2596 if (!(p = strsep(&video_str, ";")) || !*p)
2597 goto mach64_invalid;
2598 vmembase = simple_strtoul(p, NULL, 0);
2599 if (!(p = strsep(&video_str, ";")) || !*p)
2600 goto mach64_invalid;
2601 size = simple_strtoul(p, NULL, 0);
2602 if (!(p = strsep(&video_str, ";")) || !*p)
2603 goto mach64_invalid;
2604 guiregbase = simple_strtoul(p, NULL, 0);
2606 phys_vmembase[m64_num] = vmembase;
2607 phys_size[m64_num] = size;
2608 phys_guiregbase[m64_num] = guiregbase;
2609 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2614 phys_vmembase[m64_num] = 0;
2617 #endif /* CONFIG_ATARI */
2620 * Blank the display.
2623 static int atyfb_blank(int blank, struct fb_info *info)
2625 struct atyfb_par *par = (struct atyfb_par *) info->par;
2628 if (par->lock_blank || par->asleep)
2631 #ifdef CONFIG_PMAC_BACKLIGHT
2632 if ((_machine == _MACH_Pmac) && blank)
2633 set_backlight_enable(0);
2634 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2635 if (par->lcd_table && blank &&
2636 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2637 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2639 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2643 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2645 case FB_BLANK_UNBLANK:
2646 gen_cntl &= ~(0x4c);
2648 case FB_BLANK_NORMAL:
2651 case FB_BLANK_VSYNC_SUSPEND:
2654 case FB_BLANK_HSYNC_SUSPEND:
2657 case FB_BLANK_POWERDOWN:
2661 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2663 #ifdef CONFIG_PMAC_BACKLIGHT
2664 if ((_machine == _MACH_Pmac) && !blank)
2665 set_backlight_enable(1);
2666 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2667 if (par->lcd_table && !blank &&
2668 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2669 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2671 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2678 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2679 const struct atyfb_par *par)
2682 out_8(&par->aty_cmap_regs->windex, regno);
2683 out_8(&par->aty_cmap_regs->lut, red);
2684 out_8(&par->aty_cmap_regs->lut, green);
2685 out_8(&par->aty_cmap_regs->lut, blue);
2687 writeb(regno, &par->aty_cmap_regs->windex);
2688 writeb(red, &par->aty_cmap_regs->lut);
2689 writeb(green, &par->aty_cmap_regs->lut);
2690 writeb(blue, &par->aty_cmap_regs->lut);
2695 * Set a single color register. The values supplied are already
2696 * rounded down to the hardware's capabilities (according to the
2697 * entries in the var structure). Return != 0 for invalid regno.
2698 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2701 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2702 u_int transp, struct fb_info *info)
2704 struct atyfb_par *par = (struct atyfb_par *) info->par;
2706 u32 *pal = info->pseudo_palette;
2708 depth = info->var.bits_per_pixel;
2710 depth = (info->var.green.length == 5) ? 15 : 16;
2716 (depth == 16 && regno > 63) ||
2717 (depth == 15 && regno > 31))
2724 par->palette[regno].red = red;
2725 par->palette[regno].green = green;
2726 par->palette[regno].blue = blue;
2731 pal[regno] = (regno << 10) | (regno << 5) | regno;
2734 pal[regno] = (regno << 11) | (regno << 5) | regno;
2737 pal[regno] = (regno << 16) | (regno << 8) | regno;
2740 i = (regno << 8) | regno;
2741 pal[regno] = (i << 16) | i;
2746 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2747 if (M64_HAS(EXTRA_BRIGHT))
2748 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2749 aty_st_8(DAC_CNTL, i, par);
2750 aty_st_8(DAC_MASK, 0xff, par);
2752 if (M64_HAS(INTEGRATED)) {
2755 aty_st_pal(regno << 3, red,
2756 par->palette[regno<<1].green,
2758 red = par->palette[regno>>1].red;
2759 blue = par->palette[regno>>1].blue;
2761 } else if (depth == 15) {
2763 for(i = 0; i < 8; i++) {
2764 aty_st_pal(regno + i, red, green, blue, par);
2768 aty_st_pal(regno, red, green, blue, par);
2777 extern void (*prom_palette) (int);
2779 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2780 struct fb_info *info, unsigned long addr)
2782 extern int con_is_present(void);
2784 struct atyfb_par *par = info->par;
2785 struct pcidev_cookie *pcp;
2787 int node, len, i, j, ret;
2790 /* Do not attach when we have a serial console. */
2791 if (!con_is_present())
2795 * Map memory-mapped registers.
2797 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2798 info->fix.mmio_start = addr + 0x7ffc00UL;
2801 * Map in big-endian aperture.
2803 info->screen_base = (char *) (addr + 0x800000UL);
2804 info->fix.smem_start = addr + 0x800000UL;
2807 * Figure mmap addresses from PCI config space.
2808 * Split Framebuffer in big- and little-endian halfs.
2810 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2814 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2815 if (!par->mmap_map) {
2816 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2819 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2821 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2822 struct resource *rp = &pdev->resource[i];
2823 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2829 io = (rp->flags & IORESOURCE_IO);
2831 size = rp->end - base + 1;
2833 pci_read_config_dword(pdev, breg, &pbase);
2839 * Map the framebuffer a second time, this time without
2840 * the braindead _PAGE_IE setting. This is used by the
2841 * fixed Xserver, but we need to maintain the old mapping
2842 * to stay compatible with older ones...
2845 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2846 par->mmap_map[j].poff = base & PAGE_MASK;
2847 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2848 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2849 par->mmap_map[j].prot_flag = _PAGE_E;
2854 * Here comes the old framebuffer mapping with _PAGE_IE
2855 * set for the big endian half of the framebuffer...
2858 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2859 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2860 par->mmap_map[j].size = 0x800000;
2861 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2862 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2867 par->mmap_map[j].voff = pbase & PAGE_MASK;
2868 par->mmap_map[j].poff = base & PAGE_MASK;
2869 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2870 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2871 par->mmap_map[j].prot_flag = _PAGE_E;
2875 if((ret = correct_chipset(par)))
2878 if (IS_XL(pdev->device)) {
2880 * Fix PROMs idea of MEM_CNTL settings...
2882 mem = aty_ld_le32(MEM_CNTL, par);
2883 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2884 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2885 switch (mem & 0x0f) {
2887 mem = (mem & ~(0x0f)) | 2;
2890 mem = (mem & ~(0x0f)) | 3;
2893 mem = (mem & ~(0x0f)) | 4;
2896 mem = (mem & ~(0x0f)) | 5;
2901 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2902 mem &= ~(0x00700000);
2904 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2905 aty_st_le32(MEM_CNTL, mem, par);
2909 * If this is the console device, we will set default video
2910 * settings to what the PROM left us with.
2912 node = prom_getchild(prom_root_node);
2913 node = prom_searchsiblings(node, "aliases");
2915 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2918 node = prom_finddevice(prop);
2923 pcp = pdev->sysdata;
2924 if (node == pcp->prom_node) {
2925 struct fb_var_screeninfo *var = &default_var;
2926 unsigned int N, P, Q, M, T, R;
2927 u32 v_total, h_total;
2932 crtc.vxres = prom_getintdefault(node, "width", 1024);
2933 crtc.vyres = prom_getintdefault(node, "height", 768);
2934 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2935 var->xoffset = var->yoffset = 0;
2936 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2937 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2938 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2939 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2940 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2941 aty_crtc_to_var(&crtc, var);
2943 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2944 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2947 * Read the PLL to figure actual Refresh Rate.
2949 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2950 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2951 for (i = 0; i < 16; i++)
2952 pll_regs[i] = aty_ld_pll_ct(i, par);
2955 * PLL Reference Divider M:
2960 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2962 N = pll_regs[7 + (clock_cntl & 3)];
2965 * PLL Post Divider P (Dependant on CLOCK_CNTL):
2967 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2981 * where R is XTALIN (= 14318 or 29498 kHz).
2983 if (IS_XL(pdev->device))
2990 default_var.pixclock = 1000000000 / T;
2996 #else /* __sparc__ */
2999 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3000 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3002 u32 driv_inf_tab, sig;
3005 /* To support an LCD panel, we should know it's dimensions and
3006 * it's desired pixel clock.
3007 * There are two ways to do it:
3008 * - Check the startup video mode and calculate the panel
3009 * size from it. This is unreliable.
3010 * - Read it from the driver information table in the video BIOS.
3012 /* Address of driver information table is at offset 0x78. */
3013 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3015 /* Check for the driver information table signature. */
3016 sig = (*(u32 *)driv_inf_tab);
3017 if ((sig == 0x54504c24) || /* Rage LT pro */
3018 (sig == 0x544d5224) || /* Rage mobility */
3019 (sig == 0x54435824) || /* Rage XC */
3020 (sig == 0x544c5824)) { /* Rage XL */
3021 PRINTKI("BIOS contains driver information table.\n");
3022 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3025 par->lcd_table = bios_base + lcd_ofs;
3029 if (par->lcd_table != 0) {
3032 char refresh_rates_buf[100];
3033 int id, tech, f, i, m, default_refresh_rate;
3038 u16 width, height, panel_type, refresh_rates;
3041 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3042 /* The most important information is the panel size at
3043 * offset 25 and 27, but there's some other nice information
3044 * which we print to the screen.
3046 id = *(u8 *)par->lcd_table;
3047 strncpy(model,(char *)par->lcd_table+1,24);
3050 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3051 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3052 panel_type = *(u16 *)(par->lcd_table+29);
3054 txtcolour = "colour";
3056 txtcolour = "monochrome";
3058 txtdual = "dual (split) ";
3061 tech = (panel_type>>2) & 63;
3064 txtmonitor = "passive matrix";
3067 txtmonitor = "active matrix";
3070 txtmonitor = "active addressed STN";
3076 txtmonitor = "plasma";
3079 txtmonitor = "unknown";
3081 format = *(u32 *)(par->lcd_table+57);
3082 if (tech == 0 || tech == 2) {
3083 switch (format & 7) {
3085 txtformat = "12 bit interface";
3088 txtformat = "16 bit interface";
3091 txtformat = "24 bit interface";
3094 txtformat = "unkown format";
3097 switch (format & 7) {
3099 txtformat = "8 colours";
3102 txtformat = "512 colours";
3105 txtformat = "4096 colours";
3108 txtformat = "262144 colours (LT mode)";
3111 txtformat = "16777216 colours";
3114 txtformat = "262144 colours (FDPI-2 mode)";
3117 txtformat = "unkown format";
3120 PRINTKI("%s%s %s monitor detected: %s\n",
3121 txtdual ,txtcolour, txtmonitor, model);
3122 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3123 id, width, height, txtformat);
3124 refresh_rates_buf[0] = 0;
3125 refresh_rates = *(u16 *)(par->lcd_table+62);
3128 for (i=0;i<16;i++) {
3129 if (refresh_rates & m) {
3131 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3134 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3136 strcat(refresh_rates_buf,strbuf);
3140 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3141 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3142 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3143 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3144 /* We now need to determine the crtc parameters for the
3145 * lcd monitor. This is tricky, because they are not stored
3146 * individually in the BIOS. Instead, the BIOS contains a
3147 * table of display modes that work for this monitor.
3149 * The idea is that we search for a mode of the same dimensions
3150 * as the dimensions of the lcd monitor. Say our lcd monitor
3151 * is 800x600 pixels, we search for a 800x600 monitor.
3152 * The CRTC parameters we find here are the ones that we need
3153 * to use to simulate other resolutions on the lcd screen.
3155 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3156 while (*lcdmodeptr != 0) {
3158 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3159 modeptr = bios_base + *lcdmodeptr;
3161 mwidth = *((u16 *)(modeptr+0));
3162 mheight = *((u16 *)(modeptr+2));
3164 if (mwidth == width && mheight == height) {
3165 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3166 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3167 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3168 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3169 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3170 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3172 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3173 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3174 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3175 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3177 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3178 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3179 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3180 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3186 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3187 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3188 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3189 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3195 if (*lcdmodeptr == 0) {
3196 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3197 /* To do: Switch to CRT if possible. */
3199 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3200 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3202 par->lcd_hdisp + par->lcd_right_margin,
3203 par->lcd_hdisp + par->lcd_right_margin
3204 + par->lcd_hsync_dly + par->lcd_hsync_len,
3207 par->lcd_vdisp + par->lcd_lower_margin,
3208 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3210 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3212 par->lcd_hblank_len - (par->lcd_right_margin +
3213 par->lcd_hsync_dly + par->lcd_hsync_len),
3215 par->lcd_right_margin,
3217 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3219 par->lcd_lower_margin,
3220 par->lcd_vsync_len);
3224 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3226 static int __devinit init_from_bios(struct atyfb_par *par)
3228 u32 bios_base, rom_addr;
3231 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3232 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3234 /* The BIOS starts with 0xaa55. */
3235 if (*((u16 *)bios_base) == 0xaa55) {
3238 u16 rom_table_offset, freq_table_offset;
3239 PLL_BLOCK_MACH64 pll_block;
3241 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3243 /* check for frequncy table */
3244 bios_ptr = (u8*)bios_base;
3245 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3246 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3247 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3249 PRINTKI("BIOS frequency table:\n");
3250 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3251 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3252 pll_block.ref_freq, pll_block.ref_divider);
3253 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3254 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3255 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3257 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3258 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3259 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3260 par->pll_limits.ref_div = pll_block.ref_divider;
3261 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3262 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3263 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3264 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3265 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3266 aty_init_lcd(par, bios_base);
3270 PRINTKE("no BIOS frequency table found, use parameters\n");
3273 iounmap((void* __iomem )bios_base);
3277 #endif /* __i386__ */
3279 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3281 struct atyfb_par *par = info->par;
3283 unsigned long raddr;
3284 struct resource *rrp;
3287 raddr = addr + 0x7ff000UL;
3288 rrp = &pdev->resource[2];
3289 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3290 par->aux_start = rrp->start;
3291 par->aux_size = rrp->end - rrp->start + 1;
3293 PRINTKI("using auxiliary register aperture\n");
3296 info->fix.mmio_start = raddr;
3297 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3298 if (par->ati_regbase == 0)
3301 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3302 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3305 * Enable memory-space accesses using config-space
3308 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3309 if (!(tmp & PCI_COMMAND_MEMORY)) {
3310 tmp |= PCI_COMMAND_MEMORY;
3311 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3314 /* Use the big-endian aperture */
3318 /* Map in frame buffer */
3319 info->fix.smem_start = addr;
3320 info->screen_base = ioremap(addr, 0x800000);
3321 if (info->screen_base == NULL) {
3323 goto atyfb_setup_generic_fail;
3326 if((ret = correct_chipset(par)))
3327 goto atyfb_setup_generic_fail;
3329 if((ret = init_from_bios(par)))
3330 goto atyfb_setup_generic_fail;
3332 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3333 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3335 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3337 /* according to ATI, we should use clock 3 for acelerated mode */
3338 par->clk_wr_offset = 3;
3342 atyfb_setup_generic_fail:
3343 iounmap(par->ati_regbase);
3344 par->ati_regbase = NULL;
3348 #endif /* !__sparc__ */
3350 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3352 unsigned long addr, res_start, res_size;
3353 struct fb_info *info;
3354 struct resource *rp;
3355 struct atyfb_par *par;
3356 int i, rc = -ENOMEM;
3358 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3359 if (pdev->device == aty_chips[i].pci_id)
3365 /* Enable device in PCI config */
3366 if (pci_enable_device(pdev)) {
3367 PRINTKE("Cannot enable PCI device\n");
3371 /* Find which resource to use */
3372 rp = &pdev->resource[0];
3373 if (rp->flags & IORESOURCE_IO)
3374 rp = &pdev->resource[1];
3380 res_start = rp->start;
3381 res_size = rp->end - rp->start + 1;
3382 if (!request_mem_region (res_start, res_size, "atyfb"))
3385 /* Allocate framebuffer */
3386 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3388 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3392 info->fix = atyfb_fix;
3393 info->device = &pdev->dev;
3394 par->pci_id = aty_chips[i].pci_id;
3395 par->res_start = res_start;
3396 par->res_size = res_size;
3397 par->irq = pdev->irq;
3399 /* Setup "info" structure */
3401 rc = atyfb_setup_sparc(pdev, info, addr);
3403 rc = atyfb_setup_generic(pdev, info, addr);
3406 goto err_release_mem;
3408 pci_set_drvdata(pdev, info);
3410 /* Init chip & register framebuffer */
3411 if (aty_init(info, "PCI"))
3412 goto err_release_io;
3416 prom_palette = atyfb_palette;
3419 * Add /dev/fb mmap values.
3421 par->mmap_map[0].voff = 0x8000000000000000UL;
3422 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3423 par->mmap_map[0].size = info->fix.smem_len;
3424 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3425 par->mmap_map[0].prot_flag = _PAGE_E;
3426 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3427 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3428 par->mmap_map[1].size = PAGE_SIZE;
3429 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3430 par->mmap_map[1].prot_flag = _PAGE_E;
3431 #endif /* __sparc__ */
3437 kfree(par->mmap_map);
3439 if (par->ati_regbase)
3440 iounmap(par->ati_regbase);
3441 if (info->screen_base)
3442 iounmap(info->screen_base);
3446 release_mem_region(par->aux_start, par->aux_size);
3448 release_mem_region(par->res_start, par->res_size);
3449 framebuffer_release(info);
3454 #endif /* CONFIG_PCI */
3458 static int __devinit atyfb_atari_probe(void)
3460 struct aty_par *par;
3461 struct fb_info *info;
3465 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3466 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3467 !phys_guiregbase[m64_num]) {
3468 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3472 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3474 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3479 info->fix = atyfb_fix;
3481 par->irq = (unsigned int) -1; /* something invalid */
3484 * Map the video memory (physical address given) to somewhere in the
3485 * kernel address space.
3487 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3488 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3489 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3491 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3493 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3494 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3496 switch (clock_r & 0x003F) {
3498 par->clk_wr_offset = 3; /* */
3501 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3504 par->clk_wr_offset = 1; /* */
3507 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3511 if (aty_init(info, "ISA bus")) {
3512 framebuffer_release(info);
3513 /* This is insufficient! kernel_map has added two large chunks!! */
3519 #endif /* CONFIG_ATARI */
3521 static void __devexit atyfb_remove(struct fb_info *info)
3523 struct atyfb_par *par = (struct atyfb_par *) info->par;
3525 /* restore video mode */
3526 aty_set_crtc(par, &saved_crtc);
3527 par->pll_ops->set_pll(info, &saved_pll);
3529 unregister_framebuffer(info);
3532 if (par->mtrr_reg >= 0) {
3533 mtrr_del(par->mtrr_reg, 0, 0);
3536 if (par->mtrr_aper >= 0) {
3537 mtrr_del(par->mtrr_aper, 0, 0);
3538 par->mtrr_aper = -1;
3542 if (par->ati_regbase)
3543 iounmap(par->ati_regbase);
3544 if (info->screen_base)
3545 iounmap(info->screen_base);
3547 if (info->sprite.addr)
3548 iounmap(info->sprite.addr);
3552 kfree(par->mmap_map);
3555 release_mem_region(par->aux_start, par->aux_size);
3558 release_mem_region(par->res_start, par->res_size);
3560 framebuffer_release(info);
3565 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3567 struct fb_info *info = pci_get_drvdata(pdev);
3573 * This driver uses its own matching table. That will be more difficult
3574 * to fix, so for now, we just match against any ATI ID and let the
3575 * probe() function find out what's up. That also mean we don't have
3576 * a module ID table though.
3578 static struct pci_device_id atyfb_pci_tbl[] = {
3579 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3580 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3584 static struct pci_driver atyfb_driver = {
3586 .id_table = atyfb_pci_tbl,
3587 .probe = atyfb_pci_probe,
3588 .remove = __devexit_p(atyfb_pci_remove),
3590 .suspend = atyfb_pci_suspend,
3591 .resume = atyfb_pci_resume,
3592 #endif /* CONFIG_PM */
3595 #endif /* CONFIG_PCI */
3598 static int __init atyfb_setup(char *options)
3602 if (!options || !*options)
3605 while ((this_opt = strsep(&options, ",")) != NULL) {
3606 if (!strncmp(this_opt, "noaccel", 7)) {
3609 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3612 } else if (!strncmp(this_opt, "vram:", 5))
3613 vram = simple_strtoul(this_opt + 5, NULL, 0);
3614 else if (!strncmp(this_opt, "pll:", 4))
3615 pll = simple_strtoul(this_opt + 4, NULL, 0);
3616 else if (!strncmp(this_opt, "mclk:", 5))
3617 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3618 else if (!strncmp(this_opt, "xclk:", 5))
3619 xclk = simple_strtoul(this_opt+5, NULL, 0);
3620 else if (!strncmp(this_opt, "comp_sync:", 10))
3621 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3623 else if (!strncmp(this_opt, "vmode:", 6)) {
3624 unsigned int vmode =
3625 simple_strtoul(this_opt + 6, NULL, 0);
3626 if (vmode > 0 && vmode <= VMODE_MAX)
3627 default_vmode = vmode;
3628 } else if (!strncmp(this_opt, "cmode:", 6)) {
3629 unsigned int cmode =
3630 simple_strtoul(this_opt + 6, NULL, 0);
3634 default_cmode = CMODE_8;
3638 default_cmode = CMODE_16;
3642 default_cmode = CMODE_32;
3649 * Why do we need this silly Mach64 argument?
3650 * We are already here because of mach64= so its redundant.
3652 else if (MACH_IS_ATARI
3653 && (!strncmp(this_opt, "Mach64:", 7))) {
3654 static unsigned char m64_num;
3655 static char mach64_str[80];
3656 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3657 if (!store_video_par(mach64_str, m64_num)) {
3659 mach64_count = m64_num;
3670 static int __init atyfb_init(void)
3673 char *option = NULL;
3675 if (fb_get_options("atyfb", &option))
3677 atyfb_setup(option);
3681 pci_register_driver(&atyfb_driver);
3684 atyfb_atari_probe();
3689 static void __exit atyfb_exit(void)
3692 pci_unregister_driver(&atyfb_driver);
3696 module_init(atyfb_init);
3697 module_exit(atyfb_exit);
3699 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3700 MODULE_LICENSE("GPL");
3701 module_param(noaccel, bool, 0);
3702 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3703 module_param(vram, int, 0);
3704 MODULE_PARM_DESC(vram, "int: override size of video ram");
3705 module_param(pll, int, 0);
3706 MODULE_PARM_DESC(pll, "int: override video clock");
3707 module_param(mclk, int, 0);
3708 MODULE_PARM_DESC(mclk, "int: override memory clock");
3709 module_param(xclk, int, 0);
3710 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3711 module_param(comp_sync, int, 0);
3712 MODULE_PARM_DESC(comp_sync,
3713 "Set composite sync signal to low (0) or high (1)");
3714 module_param(mode, charp, 0);
3715 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3717 module_param(nomtrr, bool, 0);
3718 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob