SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/usb/musb/musbhsdma.c

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33 #include <linux/device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/platform_device.h>
  36 #include "musb_core.h"
  37
  38 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  39 #include "omap2430.h"
  40 #endif
  41
  42 #define MUSB_HSDMA_BASE         0x200
  43 #define MUSB_HSDMA_INTR         (MUSB_HSDMA_BASE + 0)
  44 #define MUSB_HSDMA_CONTROL              0x4
  45 #define MUSB_HSDMA_ADDRESS              0x8
  46 #define MUSB_HSDMA_COUNT                0xc
  47
  48 #define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)           \
  49                 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
  50
  51 /* control register (16-bit): */
  52 #define MUSB_HSDMA_ENABLE_SHIFT         0
  53 #define MUSB_HSDMA_TRANSMIT_SHIFT               1
  54 #define MUSB_HSDMA_MODE1_SHIFT          2
  55 #define MUSB_HSDMA_IRQENABLE_SHIFT              3
  56 #define MUSB_HSDMA_ENDPOINT_SHIFT               4
  57 #define MUSB_HSDMA_BUSERROR_SHIFT               8
  58 #define MUSB_HSDMA_BURSTMODE_SHIFT              9
  59 #define MUSB_HSDMA_BURSTMODE            (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
  60 #define MUSB_HSDMA_BURSTMODE_UNSPEC     0
  61 #define MUSB_HSDMA_BURSTMODE_INCR4      1
  62 #define MUSB_HSDMA_BURSTMODE_INCR8      2
  63 #define MUSB_HSDMA_BURSTMODE_INCR16     3
  64
  65 #define MUSB_HSDMA_CHANNELS             8
  66
  67 struct musb_dma_controller;
  68
  69 struct musb_dma_channel {
  70         struct dma_channel              channel;
  71         struct musb_dma_controller      *controller;
  72         u32                             start_addr;
  73         u32                             len;
  74         u16                             max_packet_sz;
  75         u8                              idx;
  76         u8                              epnum;
  77         u8                              transmit;
  78 };
  79
  80 struct musb_dma_controller {
  81         struct dma_controller           controller;
  82         struct musb_dma_channel         channel[MUSB_HSDMA_CHANNELS];
  83         void                            *private_data;
  84         void __iomem                    *base;
  85         u8                              channel_count;
  86         u8                              used_channels;
  87         u8                              irq;
  88 };
  89
  90 static int dma_controller_start(struct dma_controller *c)
  91 {
  92         /* nothing to do */
  93         return 0;
  94 }
  95
  96 static void dma_channel_release(struct dma_channel *channel);
  97
  98 static int dma_controller_stop(struct dma_controller *c)
  99 {
 100         struct musb_dma_controller *controller = container_of(c,
 101                         struct musb_dma_controller, controller);
 102         struct musb *musb = controller->private_data;
 103         struct dma_channel *channel;
 104         u8 bit;
 105
 106         if (controller->used_channels != 0) {
 107                 dev_err(musb->controller,
 108                         "Stopping DMA controller while channel active\n");
 109
 110                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
 111                         if (controller->used_channels & (1 << bit)) {
 112                                 channel = &controller->channel[bit].channel;
 113                                 dma_channel_release(channel);
 114
 115                                 if (!controller->used_channels)
 116                                         break;
 117                         }
 118                 }
 119         }
 120
 121         return 0;
 122 }
 123
 124 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
 125                                 struct musb_hw_ep *hw_ep, u8 transmit)
 126 {
 127         struct musb_dma_controller *controller = container_of(c,
 128                         struct musb_dma_controller, controller);
 129         struct musb_dma_channel *musb_channel = NULL;
 130         struct dma_channel *channel = NULL;
 131         u8 bit;
 132
 133         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
 134                 if (!(controller->used_channels & (1 << bit))) {
 135                         controller->used_channels |= (1 << bit);
 136                         musb_channel = &(controller->channel[bit]);
 137                         musb_channel->controller = controller;
 138                         musb_channel->idx = bit;
 139                         musb_channel->epnum = hw_ep->epnum;
 140                         musb_channel->transmit = transmit;
 141                         channel = &(musb_channel->channel);
 142                         channel->private_data = musb_channel;
 143                         channel->status = MUSB_DMA_STATUS_FREE;
 144                         channel->max_len = 0x10000;
 145                         /* Tx => mode 1; Rx => mode 0 */
 146                         channel->desired_mode = transmit;
 147                         channel->actual_len = 0;
 148                         break;
 149                 }
 150         }
 151
 152         return channel;
 153 }
 154
 155 static void dma_channel_release(struct dma_channel *channel)
 156 {
 157         struct musb_dma_channel *musb_channel = channel->private_data;
 158
 159         channel->actual_len = 0;
 160         musb_channel->start_addr = 0;
 161         musb_channel->len = 0;
 162
 163         musb_channel->controller->used_channels &=
 164                 ~(1 << musb_channel->idx);
 165
 166         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 167 }
 168
 169 static void configure_channel(struct dma_channel *channel,
 170                                 u16 packet_sz, u8 mode,
 171                                 dma_addr_t dma_addr, u32 len)
 172 {
 173         struct musb_dma_channel *musb_channel = channel->private_data;
 174         struct musb_dma_controller *controller = musb_channel->controller;
 175         void __iomem *mbase = controller->base;
 176         u8 bchannel = musb_channel->idx;
 177         u16 csr = 0;
 178
 179         DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
 180                         channel, packet_sz, dma_addr, len, mode);
 181
 182         if (mode) {
 183                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 184                 BUG_ON(len < packet_sz);
 185
 186                 if (packet_sz >= 64) {
 187                         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 188                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 189                 } else if (packet_sz >= 32) {
 190                         csr |= MUSB_HSDMA_BURSTMODE_INCR8
 191                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 192                 } else if (packet_sz >= 16) {
 193                         csr |= MUSB_HSDMA_BURSTMODE_INCR4
 194                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 195                 }
 196         }
 197
 198         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 199                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 200                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 201                 | (musb_channel->transmit
 202                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 203                                 : 0);
 204
 205         /* address/count */
 206         musb_writel(mbase,
 207                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
 208                 dma_addr);
 209         musb_writel(mbase,
 210                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
 211                 len);
 212
 213         /* control (this should start things) */
 214         musb_writew(mbase,
 215                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 216                 csr);
 217 }
 218
 219 static int dma_channel_program(struct dma_channel *channel,
 220                                 u16 packet_sz, u8 mode,
 221                                 dma_addr_t dma_addr, u32 len)
 222 {
 223         struct musb_dma_channel *musb_channel = channel->private_data;
 224
 225         DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 226                 musb_channel->epnum,
 227                 musb_channel->transmit ? "Tx" : "Rx",
 228                 packet_sz, dma_addr, len, mode);
 229
 230         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 231                 channel->status == MUSB_DMA_STATUS_BUSY);
 232
 233         channel->actual_len = 0;
 234         musb_channel->start_addr = dma_addr;
 235         musb_channel->len = len;
 236         musb_channel->max_packet_sz = packet_sz;
 237         channel->status = MUSB_DMA_STATUS_BUSY;
 238
 239         if ((mode == 1) && (len >= packet_sz))
 240                 configure_channel(channel, packet_sz, 1, dma_addr, len);
 241         else
 242                 configure_channel(channel, packet_sz, 0, dma_addr, len);
 243
 244         return true;
 245 }
 246
 247 static int dma_channel_abort(struct dma_channel *channel)
 248 {
 249         struct musb_dma_channel *musb_channel = channel->private_data;
 250         void __iomem *mbase = musb_channel->controller->base;
 251
 252         u8 bchannel = musb_channel->idx;
 253         u16 csr;
 254
 255         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 256                 if (musb_channel->transmit) {
 257
 258                         csr = musb_readw(mbase,
 259                                 MUSB_EP_OFFSET(musb_channel->epnum,
 260                                                 MUSB_TXCSR));
 261                         csr &= ~(MUSB_TXCSR_AUTOSET |
 262                                  MUSB_TXCSR_DMAENAB |
 263                                  MUSB_TXCSR_DMAMODE);
 264                         musb_writew(mbase,
 265                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
 266                                 csr);
 267                 } else {
 268                         csr = musb_readw(mbase,
 269                                 MUSB_EP_OFFSET(musb_channel->epnum,
 270                                                 MUSB_RXCSR));
 271                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 272                                  MUSB_RXCSR_DMAENAB |
 273                                  MUSB_RXCSR_DMAMODE);
 274                         musb_writew(mbase,
 275                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
 276                                 csr);
 277                 }
 278
 279                 musb_writew(mbase,
 280                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 281                         0);
 282                 musb_writel(mbase,
 283                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS),
 284                         0);
 285                 musb_writel(mbase,
 286                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT),
 287                         0);
 288
 289                 channel->status = MUSB_DMA_STATUS_FREE;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 296 {
 297         struct musb_dma_controller *controller = private_data;
 298         struct musb *musb = controller->private_data;
 299         struct musb_dma_channel *musb_channel;
 300         struct dma_channel *channel;
 301
 302         void __iomem *mbase = controller->base;
 303
 304         irqreturn_t retval = IRQ_NONE;
 305
 306         unsigned long flags;
 307
 308         u8 bchannel;
 309         u8 int_hsdma;
 310
 311         u32 addr;
 312         u16 csr;
 313
 314         spin_lock_irqsave(&musb->lock, flags);
 315
 316         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 317         if (!int_hsdma)
 318                 goto done;
 319
 320         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 321                 if (int_hsdma & (1 << bchannel)) {
 322                         musb_channel = (struct musb_dma_channel *)
 323                                         &(controller->channel[bchannel]);
 324                         channel = &musb_channel->channel;
 325
 326                         csr = musb_readw(mbase,
 327                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 328                                                         MUSB_HSDMA_CONTROL));
 329
 330                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 331                                 musb_channel->channel.status =
 332                                         MUSB_DMA_STATUS_BUS_ABORT;
 333                         } else {
 334                                 u8 devctl;
 335
 336                                 addr = musb_readl(mbase,
 337                                                 MUSB_HSDMA_CHANNEL_OFFSET(
 338                                                         bchannel,
 339                                                         MUSB_HSDMA_ADDRESS));
 340                                 channel->actual_len = addr
 341                                         - musb_channel->start_addr;
 342
 343                                 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
 344                                         channel, musb_channel->start_addr,
 345                                         addr, channel->actual_len,
 346                                         musb_channel->len,
 347                                         (channel->actual_len
 348                                                 < musb_channel->len) ?
 349                                         "=> reconfig 0" : "=> complete");
 350
 351                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 352
 353                                 channel->status = MUSB_DMA_STATUS_FREE;
 354
 355                                 /* completed */
 356                                 if ((devctl & MUSB_DEVCTL_HM)
 357                                         && (musb_channel->transmit)
 358                                         && ((channel->desired_mode == 0)
 359                                             || (channel->actual_len &
 360                                             (musb_channel->max_packet_sz - 1)))
 361                                          ) {
 362                                         /* Send out the packet */
 363                                         musb_ep_select(mbase,
 364                                                 musb_channel->epnum);
 365                                         musb_writew(mbase, MUSB_EP_OFFSET(
 366                                                         musb_channel->epnum,
 367                                                         MUSB_TXCSR),
 368                                                 MUSB_TXCSR_TXPKTRDY);
 369                                 } else {
 370                                         musb_dma_completion(
 371                                                 musb,
 372                                                 musb_channel->epnum,
 373                                                 musb_channel->transmit);
 374                                 }
 375                         }
 376                 }
 377         }
 378         retval = IRQ_HANDLED;
 379 done:
 380         spin_unlock_irqrestore(&musb->lock, flags);
 381         return retval;
 382 }
 383
 384 void dma_controller_destroy(struct dma_controller *c)
 385 {
 386         struct musb_dma_controller *controller = container_of(c,
 387                         struct musb_dma_controller, controller);
 388
 389         if (!controller)
 390                 return;
 391
 392         if (controller->irq)
 393                 free_irq(controller->irq, c);
 394
 395         kfree(controller);
 396 }
 397
 398 struct dma_controller *__init
 399 dma_controller_create(struct musb *musb, void __iomem *base)
 400 {
 401         struct musb_dma_controller *controller;
 402         struct device *dev = musb->controller;
 403         struct platform_device *pdev = to_platform_device(dev);
 404         int irq = platform_get_irq(pdev, 1);
 405
 406         if (irq == 0) {
 407                 dev_err(dev, "No DMA interrupt line!\n");
 408                 return NULL;
 409         }
 410
 411         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 412         if (!controller)
 413                 return NULL;
 414
 415         controller->channel_count = MUSB_HSDMA_CHANNELS;
 416         controller->private_data = musb;
 417         controller->base = base;
 418
 419         controller->controller.start = dma_controller_start;
 420         controller->controller.stop = dma_controller_stop;
 421         controller->controller.channel_alloc = dma_channel_allocate;
 422         controller->controller.channel_release = dma_channel_release;
 423         controller->controller.channel_program = dma_channel_program;
 424         controller->controller.channel_abort = dma_channel_abort;
 425
 426         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
 427                         musb->controller->bus_id, &controller->controller)) {
 428                 dev_err(dev, "request_irq %d failed!\n", irq);
 429                 dma_controller_destroy(&controller->controller);
 430
 431                 return NULL;
 432         }
 433
 434         controller->irq = irq;
 435
 436         return &controller->controller;
 437 }