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   1 /*
   2  * Copyright (c) 2001-2004 by David Brownell
   3  * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /* this file is part of ehci-hcd.c */
  21
  22 /*-------------------------------------------------------------------------*/
  23
  24 /*
  25  * EHCI scheduled transaction support:  interrupt, iso, split iso
  26  * These are called "periodic" transactions in the EHCI spec.
  27  *
  28  * Note that for interrupt transfers, the QH/QTD manipulation is shared
  29  * with the "asynchronous" transaction support (control/bulk transfers).
  30  * The only real difference is in how interrupt transfers are scheduled.
  31  *
  32  * For ISO, we make an "iso_stream" head to serve the same role as a QH.
  33  * It keeps track of every ITD (or SITD) that's linked, and holds enough
  34  * pre-calculated schedule data to make appending to the queue be quick.
  35  */
  36
  37 static int ehci_get_frame (struct usb_hcd *hcd);
  38
  39 /*-------------------------------------------------------------------------*/
  40
  41 /*
  42  * periodic_next_shadow - return "next" pointer on shadow list
  43  * @periodic: host pointer to qh/itd/sitd
  44  * @tag: hardware tag for type of this record
  45  */
  46 static union ehci_shadow *
  47 periodic_next_shadow (union ehci_shadow *periodic, __le32 tag)
  48 {
  49         switch (tag) {
  50         case Q_TYPE_QH:
  51                 return &periodic->qh->qh_next;
  52         case Q_TYPE_FSTN:
  53                 return &periodic->fstn->fstn_next;
  54         case Q_TYPE_ITD:
  55                 return &periodic->itd->itd_next;
  56         // case Q_TYPE_SITD:
  57         default:
  58                 return &periodic->sitd->sitd_next;
  59         }
  60 }
  61
  62 /* caller must hold ehci->lock */
  63 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
  64 {
  65         union ehci_shadow       *prev_p = &ehci->pshadow [frame];
  66         __le32                  *hw_p = &ehci->periodic [frame];
  67         union ehci_shadow       here = *prev_p;
  68
  69         /* find predecessor of "ptr"; hw and shadow lists are in sync */
  70         while (here.ptr && here.ptr != ptr) {
  71                 prev_p = periodic_next_shadow (prev_p, Q_NEXT_TYPE (*hw_p));
  72                 hw_p = here.hw_next;
  73                 here = *prev_p;
  74         }
  75         /* an interrupt entry (at list end) could have been shared */
  76         if (!here.ptr)
  77                 return;
  78
  79         /* update shadow and hardware lists ... the old "next" pointers
  80          * from ptr may still be in use, the caller updates them.
  81          */
  82         *prev_p = *periodic_next_shadow (&here, Q_NEXT_TYPE (*hw_p));
  83         *hw_p = *here.hw_next;
  84 }
  85
  86 /* how many of the uframe's 125 usecs are allocated? */
  87 static unsigned short
  88 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
  89 {
  90         __le32                  *hw_p = &ehci->periodic [frame];
  91         union ehci_shadow       *q = &ehci->pshadow [frame];
  92         unsigned                usecs = 0;
  93
  94         while (q->ptr) {
  95                 switch (Q_NEXT_TYPE (*hw_p)) {
  96                 case Q_TYPE_QH:
  97                         /* is it in the S-mask? */
  98                         if (q->qh->hw_info2 & cpu_to_le32 (1 << uframe))
  99                                 usecs += q->qh->usecs;
 100                         /* ... or C-mask? */
 101                         if (q->qh->hw_info2 & cpu_to_le32 (1 << (8 + uframe)))
 102                                 usecs += q->qh->c_usecs;
 103                         hw_p = &q->qh->hw_next;
 104                         q = &q->qh->qh_next;
 105                         break;
 106                 // case Q_TYPE_FSTN:
 107                 default:
 108                         /* for "save place" FSTNs, count the relevant INTR
 109                          * bandwidth from the previous frame
 110                          */
 111                         if (q->fstn->hw_prev != EHCI_LIST_END) {
 112                                 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
 113                         }
 114                         hw_p = &q->fstn->hw_next;
 115                         q = &q->fstn->fstn_next;
 116                         break;
 117                 case Q_TYPE_ITD:
 118                         usecs += q->itd->usecs [uframe];
 119                         hw_p = &q->itd->hw_next;
 120                         q = &q->itd->itd_next;
 121                         break;
 122                 case Q_TYPE_SITD:
 123                         /* is it in the S-mask?  (count SPLIT, DATA) */
 124                         if (q->sitd->hw_uframe & cpu_to_le32 (1 << uframe)) {
 125                                 if (q->sitd->hw_fullspeed_ep &
 126                                                 __constant_cpu_to_le32 (1<<31))
 127                                         usecs += q->sitd->stream->usecs;
 128                                 else    /* worst case for OUT start-split */
 129                                         usecs += HS_USECS_ISO (188);
 130                         }
 131
 132                         /* ... C-mask?  (count CSPLIT, DATA) */
 133                         if (q->sitd->hw_uframe &
 134                                         cpu_to_le32 (1 << (8 + uframe))) {
 135                                 /* worst case for IN complete-split */
 136                                 usecs += q->sitd->stream->c_usecs;
 137                         }
 138
 139                         hw_p = &q->sitd->hw_next;
 140                         q = &q->sitd->sitd_next;
 141                         break;
 142                 }
 143         }
 144 #ifdef  DEBUG
 145         if (usecs > 100)
 146                 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
 147                         frame * 8 + uframe, usecs);
 148 #endif
 149         return usecs;
 150 }
 151
 152 /*-------------------------------------------------------------------------*/
 153
 154 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
 155 {
 156         if (!dev1->tt || !dev2->tt)
 157                 return 0;
 158         if (dev1->tt != dev2->tt)
 159                 return 0;
 160         if (dev1->tt->multi)
 161                 return dev1->ttport == dev2->ttport;
 162         else
 163                 return 1;
 164 }
 165
 166 /* return true iff the device's transaction translator is available
 167  * for a periodic transfer starting at the specified frame, using
 168  * all the uframes in the mask.
 169  */
 170 static int tt_no_collision (
 171         struct ehci_hcd         *ehci,
 172         unsigned                period,
 173         struct usb_device       *dev,
 174         unsigned                frame,
 175         u32                     uf_mask
 176 )
 177 {
 178         if (period == 0)        /* error */
 179                 return 0;
 180
 181         /* note bandwidth wastage:  split never follows csplit
 182          * (different dev or endpoint) until the next uframe.
 183          * calling convention doesn't make that distinction.
 184          */
 185         for (; frame < ehci->periodic_size; frame += period) {
 186                 union ehci_shadow       here;
 187                 __le32                  type;
 188
 189                 here = ehci->pshadow [frame];
 190                 type = Q_NEXT_TYPE (ehci->periodic [frame]);
 191                 while (here.ptr) {
 192                         switch (type) {
 193                         case Q_TYPE_ITD:
 194                                 type = Q_NEXT_TYPE (here.itd->hw_next);
 195                                 here = here.itd->itd_next;
 196                                 continue;
 197                         case Q_TYPE_QH:
 198                                 if (same_tt (dev, here.qh->dev)) {
 199                                         u32             mask;
 200
 201                                         mask = le32_to_cpu (here.qh->hw_info2);
 202                                         /* "knows" no gap is needed */
 203                                         mask |= mask >> 8;
 204                                         if (mask & uf_mask)
 205                                                 break;
 206                                 }
 207                                 type = Q_NEXT_TYPE (here.qh->hw_next);
 208                                 here = here.qh->qh_next;
 209                                 continue;
 210                         case Q_TYPE_SITD:
 211                                 if (same_tt (dev, here.sitd->urb->dev)) {
 212                                         u16             mask;
 213
 214                                         mask = le32_to_cpu (here.sitd
 215                                                                 ->hw_uframe);
 216                                         /* FIXME assumes no gap for IN! */
 217                                         mask |= mask >> 8;
 218                                         if (mask & uf_mask)
 219                                                 break;
 220                                 }
 221                                 type = Q_NEXT_TYPE (here.sitd->hw_next);
 222                                 here = here.sitd->sitd_next;
 223                                 continue;
 224                         // case Q_TYPE_FSTN:
 225                         default:
 226                                 ehci_dbg (ehci,
 227                                         "periodic frame %d bogus type %d\n",
 228                                         frame, type);
 229                         }
 230
 231                         /* collision or error */
 232                         return 0;
 233                 }
 234         }
 235
 236         /* no collision */
 237         return 1;
 238 }
 239
 240 /*-------------------------------------------------------------------------*/
 241
 242 static int enable_periodic (struct ehci_hcd *ehci)
 243 {
 244         u32     cmd;
 245         int     status;
 246
 247         /* did clearing PSE did take effect yet?
 248          * takes effect only at frame boundaries...
 249          */
 250         status = handshake (&ehci->regs->status, STS_PSS, 0, 9 * 125);
 251         if (status != 0) {
 252                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 253                 return status;
 254         }
 255
 256         cmd = readl (&ehci->regs->command) | CMD_PSE;
 257         writel (cmd, &ehci->regs->command);
 258         /* posted write ... PSS happens later */
 259         ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
 260
 261         /* make sure ehci_work scans these */
 262         ehci->next_uframe = readl (&ehci->regs->frame_index)
 263                                 % (ehci->periodic_size << 3);
 264         return 0;
 265 }
 266
 267 static int disable_periodic (struct ehci_hcd *ehci)
 268 {
 269         u32     cmd;
 270         int     status;
 271
 272         /* did setting PSE not take effect yet?
 273          * takes effect only at frame boundaries...
 274          */
 275         status = handshake (&ehci->regs->status, STS_PSS, STS_PSS, 9 * 125);
 276         if (status != 0) {
 277                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 278                 return status;
 279         }
 280
 281         cmd = readl (&ehci->regs->command) & ~CMD_PSE;
 282         writel (cmd, &ehci->regs->command);
 283         /* posted write ... */
 284
 285         ehci->next_uframe = -1;
 286         return 0;
 287 }
 288
 289 /*-------------------------------------------------------------------------*/
 290
 291 /* periodic schedule slots have iso tds (normal or split) first, then a
 292  * sparse tree for active interrupt transfers.
 293  *
 294  * this just links in a qh; caller guarantees uframe masks are set right.
 295  * no FSTN support (yet; ehci 0.96+)
 296  */
 297 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 298 {
 299         unsigned        i;
 300         unsigned        period = qh->period;
 301
 302         dev_dbg (&qh->dev->dev,
 303                 "link qh%d-%04x/%p start %d [%d/%d us]\n",
 304                 period, le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 305                 qh, qh->start, qh->usecs, qh->c_usecs);
 306
 307         /* high bandwidth, or otherwise every microframe */
 308         if (period == 0)
 309                 period = 1;
 310
 311         for (i = qh->start; i < ehci->periodic_size; i += period) {
 312                 union ehci_shadow       *prev = &ehci->pshadow [i];
 313                 __le32                  *hw_p = &ehci->periodic [i];
 314                 union ehci_shadow       here = *prev;
 315                 __le32                  type = 0;
 316
 317                 /* skip the iso nodes at list head */
 318                 while (here.ptr) {
 319                         type = Q_NEXT_TYPE (*hw_p);
 320                         if (type == Q_TYPE_QH)
 321                                 break;
 322                         prev = periodic_next_shadow (prev, type);
 323                         hw_p = &here.qh->hw_next;
 324                         here = *prev;
 325                 }
 326
 327                 /* sorting each branch by period (slow-->fast)
 328                  * enables sharing interior tree nodes
 329                  */
 330                 while (here.ptr && qh != here.qh) {
 331                         if (qh->period > here.qh->period)
 332                                 break;
 333                         prev = &here.qh->qh_next;
 334                         hw_p = &here.qh->hw_next;
 335                         here = *prev;
 336                 }
 337                 /* link in this qh, unless some earlier pass did that */
 338                 if (qh != here.qh) {
 339                         qh->qh_next = here;
 340                         if (here.qh)
 341                                 qh->hw_next = *hw_p;
 342                         wmb ();
 343                         prev->qh = qh;
 344                         *hw_p = QH_NEXT (qh->qh_dma);
 345                 }
 346         }
 347         qh->qh_state = QH_STATE_LINKED;
 348         qh_get (qh);
 349
 350         /* update per-qh bandwidth for usbfs */
 351         ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
 352                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 353                 : (qh->usecs * 8);
 354
 355         /* maybe enable periodic schedule processing */
 356         if (!ehci->periodic_sched++)
 357                 return enable_periodic (ehci);
 358
 359         return 0;
 360 }
 361
 362 static void qh_unlink_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
 363 {
 364         unsigned        i;
 365         unsigned        period;
 366
 367         // FIXME:
 368         // IF this isn't high speed
 369         //   and this qh is active in the current uframe
 370         //   (and overlay token SplitXstate is false?)
 371         // THEN
 372         //   qh->hw_info1 |= __constant_cpu_to_le32 (1 << 7 /* "ignore" */);
 373
 374         /* high bandwidth, or otherwise part of every microframe */
 375         if ((period = qh->period) == 0)
 376                 period = 1;
 377
 378         for (i = qh->start; i < ehci->periodic_size; i += period)
 379                 periodic_unlink (ehci, i, qh);
 380
 381         /* update per-qh bandwidth for usbfs */
 382         ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
 383                 ? ((qh->usecs + qh->c_usecs) / qh->period)
 384                 : (qh->usecs * 8);
 385
 386         dev_dbg (&qh->dev->dev,
 387                 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
 388                 qh->period,
 389                 le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
 390                 qh, qh->start, qh->usecs, qh->c_usecs);
 391
 392         /* qh->qh_next still "live" to HC */
 393         qh->qh_state = QH_STATE_UNLINK;
 394         qh->qh_next.ptr = NULL;
 395         qh_put (qh);
 396
 397         /* maybe turn off periodic schedule */
 398         ehci->periodic_sched--;
 399         if (!ehci->periodic_sched)
 400                 (void) disable_periodic (ehci);
 401 }
 402
 403 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 404 {
 405         unsigned        wait;
 406
 407         qh_unlink_periodic (ehci, qh);
 408
 409         /* simple/paranoid:  always delay, expecting the HC needs to read
 410          * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
 411          * expect khubd to clean up after any CSPLITs we won't issue.
 412          * active high speed queues may need bigger delays...
 413          */
 414         if (list_empty (&qh->qtd_list)
 415                         || (__constant_cpu_to_le32 (QH_CMASK)
 416                                         & qh->hw_info2) != 0)
 417                 wait = 2;
 418         else
 419                 wait = 55;      /* worst case: 3 * 1024 */
 420
 421         udelay (wait);
 422         qh->qh_state = QH_STATE_IDLE;
 423         qh->hw_next = EHCI_LIST_END;
 424         wmb ();
 425 }
 426
 427 /*-------------------------------------------------------------------------*/
 428
 429 static int check_period (
 430         struct ehci_hcd *ehci,
 431         unsigned        frame,
 432         unsigned        uframe,
 433         unsigned        period,
 434         unsigned        usecs
 435 ) {
 436         int             claimed;
 437
 438         /* complete split running into next frame?
 439          * given FSTN support, we could sometimes check...
 440          */
 441         if (uframe >= 8)
 442                 return 0;
 443
 444         /*
 445          * 80% periodic == 100 usec/uframe available
 446          * convert "usecs we need" to "max already claimed"
 447          */
 448         usecs = 100 - usecs;
 449
 450         /* we "know" 2 and 4 uframe intervals were rejected; so
 451          * for period 0, check _every_ microframe in the schedule.
 452          */
 453         if (unlikely (period == 0)) {
 454                 do {
 455                         for (uframe = 0; uframe < 7; uframe++) {
 456                                 claimed = periodic_usecs (ehci, frame, uframe);
 457                                 if (claimed > usecs)
 458                                         return 0;
 459                         }
 460                 } while ((frame += 1) < ehci->periodic_size);
 461
 462         /* just check the specified uframe, at that period */
 463         } else {
 464                 do {
 465                         claimed = periodic_usecs (ehci, frame, uframe);
 466                         if (claimed > usecs)
 467                                 return 0;
 468                 } while ((frame += period) < ehci->periodic_size);
 469         }
 470
 471         // success!
 472         return 1;
 473 }
 474
 475 static int check_intr_schedule (
 476         struct ehci_hcd         *ehci,
 477         unsigned                frame,
 478         unsigned                uframe,
 479         const struct ehci_qh    *qh,
 480         __le32                  *c_maskp
 481 )
 482 {
 483         int             retval = -ENOSPC;
 484         u8              mask;
 485
 486         if (qh->c_usecs && uframe >= 6)         /* FSTN territory? */
 487                 goto done;
 488
 489         if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
 490                 goto done;
 491         if (!qh->c_usecs) {
 492                 retval = 0;
 493                 *c_maskp = 0;
 494                 goto done;
 495         }
 496
 497         /* Make sure this tt's buffer is also available for CSPLITs.
 498          * We pessimize a bit; probably the typical full speed case
 499          * doesn't need the second CSPLIT.
 500          *
 501          * NOTE:  both SPLIT and CSPLIT could be checked in just
 502          * one smart pass...
 503          */
 504         mask = 0x03 << (uframe + qh->gap_uf);
 505         *c_maskp = cpu_to_le32 (mask << 8);
 506
 507         mask |= 1 << uframe;
 508         if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
 509                 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
 510                                         qh->period, qh->c_usecs))
 511                         goto done;
 512                 if (!check_period (ehci, frame, uframe + qh->gap_uf,
 513                                         qh->period, qh->c_usecs))
 514                         goto done;
 515                 retval = 0;
 516         }
 517 done:
 518         return retval;
 519 }
 520
 521 /* "first fit" scheduling policy used the first time through,
 522  * or when the previous schedule slot can't be re-used.
 523  */
 524 static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
 525 {
 526         int             status;
 527         unsigned        uframe;
 528         __le32          c_mask;
 529         unsigned        frame;          /* 0..(qh->period - 1), or NO_FRAME */
 530
 531         qh_refresh(ehci, qh);
 532         qh->hw_next = EHCI_LIST_END;
 533         frame = qh->start;
 534
 535         /* reuse the previous schedule slots, if we can */
 536         if (frame < qh->period) {
 537                 uframe = ffs (le32_to_cpup (&qh->hw_info2) & QH_SMASK);
 538                 status = check_intr_schedule (ehci, frame, --uframe,
 539                                 qh, &c_mask);
 540         } else {
 541                 uframe = 0;
 542                 c_mask = 0;
 543                 status = -ENOSPC;
 544         }
 545
 546         /* else scan the schedule to find a group of slots such that all
 547          * uframes have enough periodic bandwidth available.
 548          */
 549         if (status) {
 550                 /* "normal" case, uframing flexible except with splits */
 551                 if (qh->period) {
 552                         frame = qh->period - 1;
 553                         do {
 554                                 for (uframe = 0; uframe < 8; uframe++) {
 555                                         status = check_intr_schedule (ehci,
 556                                                         frame, uframe, qh,
 557                                                         &c_mask);
 558                                         if (status == 0)
 559                                                 break;
 560                                 }
 561                         } while (status && frame--);
 562
 563                 /* qh->period == 0 means every uframe */
 564                 } else {
 565                         frame = 0;
 566                         status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
 567                 }
 568                 if (status)
 569                         goto done;
 570                 qh->start = frame;
 571
 572                 /* reset S-frame and (maybe) C-frame masks */
 573                 qh->hw_info2 &= __constant_cpu_to_le32(~(QH_CMASK | QH_SMASK));
 574                 qh->hw_info2 |= qh->period
 575                         ? cpu_to_le32 (1 << uframe)
 576                         : __constant_cpu_to_le32 (QH_SMASK);
 577                 qh->hw_info2 |= c_mask;
 578         } else
 579                 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
 580
 581         /* stuff into the periodic schedule */
 582         status = qh_link_periodic (ehci, qh);
 583 done:
 584         return status;
 585 }
 586
 587 static int intr_submit (
 588         struct ehci_hcd         *ehci,
 589         struct usb_host_endpoint *ep,
 590         struct urb              *urb,
 591         struct list_head        *qtd_list,
 592         gfp_t                   mem_flags
 593 ) {
 594         unsigned                epnum;
 595         unsigned long           flags;
 596         struct ehci_qh          *qh;
 597         int                     status = 0;
 598         struct list_head        empty;
 599
 600         /* get endpoint and transfer/schedule data */
 601         epnum = ep->desc.bEndpointAddress;
 602
 603         spin_lock_irqsave (&ehci->lock, flags);
 604
 605         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
 606                                &ehci_to_hcd(ehci)->flags))) {
 607                 status = -ESHUTDOWN;
 608                 goto done;
 609         }
 610
 611         /* get qh and force any scheduling errors */
 612         INIT_LIST_HEAD (&empty);
 613         qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
 614         if (qh == NULL) {
 615                 status = -ENOMEM;
 616                 goto done;
 617         }
 618         if (qh->qh_state == QH_STATE_IDLE) {
 619                 if ((status = qh_schedule (ehci, qh)) != 0)
 620                         goto done;
 621         }
 622
 623         /* then queue the urb's tds to the qh */
 624         qh = qh_append_tds (ehci, urb, qtd_list, epnum, &ep->hcpriv);
 625         BUG_ON (qh == NULL);
 626
 627         /* ... update usbfs periodic stats */
 628         ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
 629
 630 done:
 631         spin_unlock_irqrestore (&ehci->lock, flags);
 632         if (status)
 633                 qtd_list_free (ehci, urb, qtd_list);
 634
 635         return status;
 636 }
 637
 638 /*-------------------------------------------------------------------------*/
 639
 640 /* ehci_iso_stream ops work with both ITD and SITD */
 641
 642 static struct ehci_iso_stream *
 643 iso_stream_alloc (gfp_t mem_flags)
 644 {
 645         struct ehci_iso_stream *stream;
 646
 647         stream = kzalloc(sizeof *stream, mem_flags);
 648         if (likely (stream != NULL)) {
 649                 INIT_LIST_HEAD(&stream->td_list);
 650                 INIT_LIST_HEAD(&stream->free_list);
 651                 stream->next_uframe = -1;
 652                 stream->refcount = 1;
 653         }
 654         return stream;
 655 }
 656
 657 static void
 658 iso_stream_init (
 659         struct ehci_hcd         *ehci,
 660         struct ehci_iso_stream  *stream,
 661         struct usb_device       *dev,
 662         int                     pipe,
 663         unsigned                interval
 664 )
 665 {
 666         static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
 667
 668         u32                     buf1;
 669         unsigned                epnum, maxp;
 670         int                     is_input;
 671         long                    bandwidth;
 672
 673         /*
 674          * this might be a "high bandwidth" highspeed endpoint,
 675          * as encoded in the ep descriptor's wMaxPacket field
 676          */
 677         epnum = usb_pipeendpoint (pipe);
 678         is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
 679         maxp = usb_maxpacket(dev, pipe, !is_input);
 680         if (is_input) {
 681                 buf1 = (1 << 11);
 682         } else {
 683                 buf1 = 0;
 684         }
 685
 686         /* knows about ITD vs SITD */
 687         if (dev->speed == USB_SPEED_HIGH) {
 688                 unsigned multi = hb_mult(maxp);
 689
 690                 stream->highspeed = 1;
 691
 692                 maxp = max_packet(maxp);
 693                 buf1 |= maxp;
 694                 maxp *= multi;
 695
 696                 stream->buf0 = cpu_to_le32 ((epnum << 8) | dev->devnum);
 697                 stream->buf1 = cpu_to_le32 (buf1);
 698                 stream->buf2 = cpu_to_le32 (multi);
 699
 700                 /* usbfs wants to report the average usecs per frame tied up
 701                  * when transfers on this endpoint are scheduled ...
 702                  */
 703                 stream->usecs = HS_USECS_ISO (maxp);
 704                 bandwidth = stream->usecs * 8;
 705                 bandwidth /= 1 << (interval - 1);
 706
 707         } else {
 708                 u32             addr;
 709                 int             think_time;
 710                 int             hs_transfers;
 711
 712                 addr = dev->ttport << 24;
 713                 if (!ehci_is_TDI(ehci)
 714                                 || (dev->tt->hub !=
 715                                         ehci_to_hcd(ehci)->self.root_hub))
 716                         addr |= dev->tt->hub->devnum << 16;
 717                 addr |= epnum << 8;
 718                 addr |= dev->devnum;
 719                 stream->usecs = HS_USECS_ISO (maxp);
 720                 think_time = dev->tt ? dev->tt->think_time : 0;
 721                 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
 722                                 dev->speed, is_input, 1, maxp));
 723                 hs_transfers = max (1u, (maxp + 187) / 188);
 724                 if (is_input) {
 725                         u32     tmp;
 726
 727                         addr |= 1 << 31;
 728                         stream->c_usecs = stream->usecs;
 729                         stream->usecs = HS_USECS_ISO (1);
 730                         stream->raw_mask = 1;
 731
 732                         /* c-mask as specified in USB 2.0 11.18.4 3.c */
 733                         tmp = (1 << (hs_transfers + 2)) - 1;
 734                         stream->raw_mask |= tmp << (8 + 2);
 735                 } else
 736                         stream->raw_mask = smask_out [hs_transfers - 1];
 737                 bandwidth = stream->usecs + stream->c_usecs;
 738                 bandwidth /= 1 << (interval + 2);
 739
 740                 /* stream->splits gets created from raw_mask later */
 741                 stream->address = cpu_to_le32 (addr);
 742         }
 743         stream->bandwidth = bandwidth;
 744
 745         stream->udev = dev;
 746
 747         stream->bEndpointAddress = is_input | epnum;
 748         stream->interval = interval;
 749         stream->maxp = maxp;
 750 }
 751
 752 static void
 753 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
 754 {
 755         stream->refcount--;
 756
 757         /* free whenever just a dev->ep reference remains.
 758          * not like a QH -- no persistent state (toggle, halt)
 759          */
 760         if (stream->refcount == 1) {
 761                 int             is_in;
 762
 763                 // BUG_ON (!list_empty(&stream->td_list));
 764
 765                 while (!list_empty (&stream->free_list)) {
 766                         struct list_head        *entry;
 767
 768                         entry = stream->free_list.next;
 769                         list_del (entry);
 770
 771                         /* knows about ITD vs SITD */
 772                         if (stream->highspeed) {
 773                                 struct ehci_itd         *itd;
 774
 775                                 itd = list_entry (entry, struct ehci_itd,
 776                                                 itd_list);
 777                                 dma_pool_free (ehci->itd_pool, itd,
 778                                                 itd->itd_dma);
 779                         } else {
 780                                 struct ehci_sitd        *sitd;
 781
 782                                 sitd = list_entry (entry, struct ehci_sitd,
 783                                                 sitd_list);
 784                                 dma_pool_free (ehci->sitd_pool, sitd,
 785                                                 sitd->sitd_dma);
 786                         }
 787                 }
 788
 789                 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
 790                 stream->bEndpointAddress &= 0x0f;
 791                 stream->ep->hcpriv = NULL;
 792
 793                 if (stream->rescheduled) {
 794                         ehci_info (ehci, "ep%d%s-iso rescheduled "
 795                                 "%lu times in %lu seconds\n",
 796                                 stream->bEndpointAddress, is_in ? "in" : "out",
 797                                 stream->rescheduled,
 798                                 ((jiffies - stream->start)/HZ)
 799                                 );
 800                 }
 801
 802                 kfree(stream);
 803         }
 804 }
 805
 806 static inline struct ehci_iso_stream *
 807 iso_stream_get (struct ehci_iso_stream *stream)
 808 {
 809         if (likely (stream != NULL))
 810                 stream->refcount++;
 811         return stream;
 812 }
 813
 814 static struct ehci_iso_stream *
 815 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
 816 {
 817         unsigned                epnum;
 818         struct ehci_iso_stream  *stream;
 819         struct usb_host_endpoint *ep;
 820         unsigned long           flags;
 821
 822         epnum = usb_pipeendpoint (urb->pipe);
 823         if (usb_pipein(urb->pipe))
 824                 ep = urb->dev->ep_in[epnum];
 825         else
 826                 ep = urb->dev->ep_out[epnum];
 827
 828         spin_lock_irqsave (&ehci->lock, flags);
 829         stream = ep->hcpriv;
 830
 831         if (unlikely (stream == NULL)) {
 832                 stream = iso_stream_alloc(GFP_ATOMIC);
 833                 if (likely (stream != NULL)) {
 834                         /* dev->ep owns the initial refcount */
 835                         ep->hcpriv = stream;
 836                         stream->ep = ep;
 837                         iso_stream_init(ehci, stream, urb->dev, urb->pipe,
 838                                         urb->interval);
 839                 }
 840
 841         /* if dev->ep [epnum] is a QH, info1.maxpacket is nonzero */
 842         } else if (unlikely (stream->hw_info1 != 0)) {
 843                 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
 844                         urb->dev->devpath, epnum,
 845                         usb_pipein(urb->pipe) ? "in" : "out");
 846                 stream = NULL;
 847         }
 848
 849         /* caller guarantees an eventual matching iso_stream_put */
 850         stream = iso_stream_get (stream);
 851
 852         spin_unlock_irqrestore (&ehci->lock, flags);
 853         return stream;
 854 }
 855
 856 /*-------------------------------------------------------------------------*/
 857
 858 /* ehci_iso_sched ops can be ITD-only or SITD-only */
 859
 860 static struct ehci_iso_sched *
 861 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
 862 {
 863         struct ehci_iso_sched   *iso_sched;
 864         int                     size = sizeof *iso_sched;
 865
 866         size += packets * sizeof (struct ehci_iso_packet);
 867         iso_sched = kmalloc (size, mem_flags);
 868         if (likely (iso_sched != NULL)) {
 869                 memset(iso_sched, 0, size);
 870                 INIT_LIST_HEAD (&iso_sched->td_list);
 871         }
 872         return iso_sched;
 873 }
 874
 875 static inline void
 876 itd_sched_init (
 877         struct ehci_iso_sched   *iso_sched,
 878         struct ehci_iso_stream  *stream,
 879         struct urb              *urb
 880 )
 881 {
 882         unsigned        i;
 883         dma_addr_t      dma = urb->transfer_dma;
 884
 885         /* how many uframes are needed for these transfers */
 886         iso_sched->span = urb->number_of_packets * stream->interval;
 887
 888         /* figure out per-uframe itd fields that we'll need later
 889          * when we fit new itds into the schedule.
 890          */
 891         for (i = 0; i < urb->number_of_packets; i++) {
 892                 struct ehci_iso_packet  *uframe = &iso_sched->packet [i];
 893                 unsigned                length;
 894                 dma_addr_t              buf;
 895                 u32                     trans;
 896
 897                 length = urb->iso_frame_desc [i].length;
 898                 buf = dma + urb->iso_frame_desc [i].offset;
 899
 900                 trans = EHCI_ISOC_ACTIVE;
 901                 trans |= buf & 0x0fff;
 902                 if (unlikely (((i + 1) == urb->number_of_packets))
 903                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
 904                         trans |= EHCI_ITD_IOC;
 905                 trans |= length << 16;
 906                 uframe->transaction = cpu_to_le32 (trans);
 907
 908                 /* might need to cross a buffer page within a uframe */
 909                 uframe->bufp = (buf & ~(u64)0x0fff);
 910                 buf += length;
 911                 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
 912                         uframe->cross = 1;
 913         }
 914 }
 915
 916 static void
 917 iso_sched_free (
 918         struct ehci_iso_stream  *stream,
 919         struct ehci_iso_sched   *iso_sched
 920 )
 921 {
 922         if (!iso_sched)
 923                 return;
 924         // caller must hold ehci->lock!
 925         list_splice (&iso_sched->td_list, &stream->free_list);
 926         kfree (iso_sched);
 927 }
 928
 929 static int
 930 itd_urb_transaction (
 931         struct ehci_iso_stream  *stream,
 932         struct ehci_hcd         *ehci,
 933         struct urb              *urb,
 934         gfp_t                   mem_flags
 935 )
 936 {
 937         struct ehci_itd         *itd;
 938         dma_addr_t              itd_dma;
 939         int                     i;
 940         unsigned                num_itds;
 941         struct ehci_iso_sched   *sched;
 942         unsigned long           flags;
 943
 944         sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
 945         if (unlikely (sched == NULL))
 946                 return -ENOMEM;
 947
 948         itd_sched_init (sched, stream, urb);
 949
 950         if (urb->interval < 8)
 951                 num_itds = 1 + (sched->span + 7) / 8;
 952         else
 953                 num_itds = urb->number_of_packets;
 954
 955         /* allocate/init ITDs */
 956         spin_lock_irqsave (&ehci->lock, flags);
 957         for (i = 0; i < num_itds; i++) {
 958
 959                 /* free_list.next might be cache-hot ... but maybe
 960                  * the HC caches it too. avoid that issue for now.
 961                  */
 962
 963                 /* prefer previously-allocated itds */
 964                 if (likely (!list_empty(&stream->free_list))) {
 965                         itd = list_entry (stream->free_list.prev,
 966                                          struct ehci_itd, itd_list);
 967                         list_del (&itd->itd_list);
 968                         itd_dma = itd->itd_dma;
 969                 } else
 970                         itd = NULL;
 971
 972                 if (!itd) {
 973                         spin_unlock_irqrestore (&ehci->lock, flags);
 974                         itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
 975                                         &itd_dma);
 976                         spin_lock_irqsave (&ehci->lock, flags);
 977                 }
 978
 979                 if (unlikely (NULL == itd)) {
 980                         iso_sched_free (stream, sched);
 981                         spin_unlock_irqrestore (&ehci->lock, flags);
 982                         return -ENOMEM;
 983                 }
 984                 memset (itd, 0, sizeof *itd);
 985                 itd->itd_dma = itd_dma;
 986                 list_add (&itd->itd_list, &sched->td_list);
 987         }
 988         spin_unlock_irqrestore (&ehci->lock, flags);
 989
 990         /* temporarily store schedule info in hcpriv */
 991         urb->hcpriv = sched;
 992         urb->error_count = 0;
 993         return 0;
 994 }
 995
 996 /*-------------------------------------------------------------------------*/
 997
 998 static inline int
 999 itd_slot_ok (
1000         struct ehci_hcd         *ehci,
1001         u32                     mod,
1002         u32                     uframe,
1003         u8                      usecs,
1004         u32                     period
1005 )
1006 {
1007         uframe %= period;
1008         do {
1009                 /* can't commit more than 80% periodic == 100 usec */
1010                 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1011                                 > (100 - usecs))
1012                         return 0;
1013
1014                 /* we know urb->interval is 2^N uframes */
1015                 uframe += period;
1016         } while (uframe < mod);
1017         return 1;
1018 }
1019
1020 static inline int
1021 sitd_slot_ok (
1022         struct ehci_hcd         *ehci,
1023         u32                     mod,
1024         struct ehci_iso_stream  *stream,
1025         u32                     uframe,
1026         struct ehci_iso_sched   *sched,
1027         u32                     period_uframes
1028 )
1029 {
1030         u32                     mask, tmp;
1031         u32                     frame, uf;
1032
1033         mask = stream->raw_mask << (uframe & 7);
1034
1035         /* for IN, don't wrap CSPLIT into the next frame */
1036         if (mask & ~0xffff)
1037                 return 0;
1038
1039         /* this multi-pass logic is simple, but performance may
1040          * suffer when the schedule data isn't cached.
1041          */
1042
1043         /* check bandwidth */
1044         uframe %= period_uframes;
1045         do {
1046                 u32             max_used;
1047
1048                 frame = uframe >> 3;
1049                 uf = uframe & 7;
1050
1051                 /* tt must be idle for start(s), any gap, and csplit.
1052                  * assume scheduling slop leaves 10+% for control/bulk.
1053                  */
1054                 if (!tt_no_collision (ehci, period_uframes << 3,
1055                                 stream->udev, frame, mask))
1056                         return 0;
1057
1058                 /* check starts (OUT uses more than one) */
1059                 max_used = 100 - stream->usecs;
1060                 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1061                         if (periodic_usecs (ehci, frame, uf) > max_used)
1062                                 return 0;
1063                 }
1064
1065                 /* for IN, check CSPLIT */
1066                 if (stream->c_usecs) {
1067                         uf = uframe & 7;
1068                         max_used = 100 - stream->c_usecs;
1069                         do {
1070                                 tmp = 1 << uf;
1071                                 tmp <<= 8;
1072                                 if ((stream->raw_mask & tmp) == 0)
1073                                         continue;
1074                                 if (periodic_usecs (ehci, frame, uf)
1075                                                 > max_used)
1076                                         return 0;
1077                         } while (++uf < 8);
1078                 }
1079
1080                 /* we know urb->interval is 2^N uframes */
1081                 uframe += period_uframes;
1082         } while (uframe < mod);
1083
1084         stream->splits = cpu_to_le32(stream->raw_mask << (uframe & 7));
1085         return 1;
1086 }
1087
1088 /*
1089  * This scheduler plans almost as far into the future as it has actual
1090  * periodic schedule slots.  (Affected by TUNE_FLS, which defaults to
1091  * "as small as possible" to be cache-friendlier.)  That limits the size
1092  * transfers you can stream reliably; avoid more than 64 msec per urb.
1093  * Also avoid queue depths of less than ehci's worst irq latency (affected
1094  * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1095  * and other factors); or more than about 230 msec total (for portability,
1096  * given EHCI_TUNE_FLS and the slop).  Or, write a smarter scheduler!
1097  */
1098
1099 #define SCHEDULE_SLOP   10      /* frames */
1100
1101 static int
1102 iso_stream_schedule (
1103         struct ehci_hcd         *ehci,
1104         struct urb              *urb,
1105         struct ehci_iso_stream  *stream
1106 )
1107 {
1108         u32                     now, start, max, period;
1109         int                     status;
1110         unsigned                mod = ehci->periodic_size << 3;
1111         struct ehci_iso_sched   *sched = urb->hcpriv;
1112
1113         if (sched->span > (mod - 8 * SCHEDULE_SLOP)) {
1114                 ehci_dbg (ehci, "iso request %p too long\n", urb);
1115                 status = -EFBIG;
1116                 goto fail;
1117         }
1118
1119         if ((stream->depth + sched->span) > mod) {
1120                 ehci_dbg (ehci, "request %p would overflow (%d+%d>%d)\n",
1121                         urb, stream->depth, sched->span, mod);
1122                 status = -EFBIG;
1123                 goto fail;
1124         }
1125
1126         now = readl (&ehci->regs->frame_index) % mod;
1127
1128         /* when's the last uframe this urb could start? */
1129         max = now + mod;
1130
1131         /* typical case: reuse current schedule. stream is still active,
1132          * and no gaps from host falling behind (irq delays etc)
1133          */
1134         if (likely (!list_empty (&stream->td_list))) {
1135                 start = stream->next_uframe;
1136                 if (start < now)
1137                         start += mod;
1138                 if (likely ((start + sched->span) < max))
1139                         goto ready;
1140                 /* else fell behind; someday, try to reschedule */
1141                 status = -EL2NSYNC;
1142                 goto fail;
1143         }
1144
1145         /* need to schedule; when's the next (u)frame we could start?
1146          * this is bigger than ehci->i_thresh allows; scheduling itself
1147          * isn't free, the slop should handle reasonably slow cpus.  it
1148          * can also help high bandwidth if the dma and irq loads don't
1149          * jump until after the queue is primed.
1150          */
1151         start = SCHEDULE_SLOP * 8 + (now & ~0x07);
1152         start %= mod;
1153         stream->next_uframe = start;
1154
1155         /* NOTE:  assumes URB_ISO_ASAP, to limit complexity/bugs */
1156
1157         period = urb->interval;
1158         if (!stream->highspeed)
1159                 period <<= 3;
1160
1161         /* find a uframe slot with enough bandwidth */
1162         for (; start < (stream->next_uframe + period); start++) {
1163                 int             enough_space;
1164
1165                 /* check schedule: enough space? */
1166                 if (stream->highspeed)
1167                         enough_space = itd_slot_ok (ehci, mod, start,
1168                                         stream->usecs, period);
1169                 else {
1170                         if ((start % 8) >= 6)
1171                                 continue;
1172                         enough_space = sitd_slot_ok (ehci, mod, stream,
1173                                         start, sched, period);
1174                 }
1175
1176                 /* schedule it here if there's enough bandwidth */
1177                 if (enough_space) {
1178                         stream->next_uframe = start % mod;
1179                         goto ready;
1180                 }
1181         }
1182
1183         /* no room in the schedule */
1184         ehci_dbg (ehci, "iso %ssched full %p (now %d max %d)\n",
1185                 list_empty (&stream->td_list) ? "" : "re",
1186                 urb, now, max);
1187         status = -ENOSPC;
1188
1189 fail:
1190         iso_sched_free (stream, sched);
1191         urb->hcpriv = NULL;
1192         return status;
1193
1194 ready:
1195         /* report high speed start in uframes; full speed, in frames */
1196         urb->start_frame = stream->next_uframe;
1197         if (!stream->highspeed)
1198                 urb->start_frame >>= 3;
1199         return 0;
1200 }
1201
1202 /*-------------------------------------------------------------------------*/
1203
1204 static inline void
1205 itd_init (struct ehci_iso_stream *stream, struct ehci_itd *itd)
1206 {
1207         int i;
1208
1209         /* it's been recently zeroed */
1210         itd->hw_next = EHCI_LIST_END;
1211         itd->hw_bufp [0] = stream->buf0;
1212         itd->hw_bufp [1] = stream->buf1;
1213         itd->hw_bufp [2] = stream->buf2;
1214
1215         for (i = 0; i < 8; i++)
1216                 itd->index[i] = -1;
1217
1218         /* All other fields are filled when scheduling */
1219 }
1220
1221 static inline void
1222 itd_patch (
1223         struct ehci_itd         *itd,
1224         struct ehci_iso_sched   *iso_sched,
1225         unsigned                index,
1226         u16                     uframe
1227 )
1228 {
1229         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1230         unsigned                pg = itd->pg;
1231
1232         // BUG_ON (pg == 6 && uf->cross);
1233
1234         uframe &= 0x07;
1235         itd->index [uframe] = index;
1236
1237         itd->hw_transaction [uframe] = uf->transaction;
1238         itd->hw_transaction [uframe] |= cpu_to_le32 (pg << 12);
1239         itd->hw_bufp [pg] |= cpu_to_le32 (uf->bufp & ~(u32)0);
1240         itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(uf->bufp >> 32));
1241
1242         /* iso_frame_desc[].offset must be strictly increasing */
1243         if (unlikely (uf->cross)) {
1244                 u64     bufp = uf->bufp + 4096;
1245                 itd->pg = ++pg;
1246                 itd->hw_bufp [pg] |= cpu_to_le32 (bufp & ~(u32)0);
1247                 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(bufp >> 32));
1248         }
1249 }
1250
1251 static inline void
1252 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1253 {
1254         /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1255         itd->itd_next = ehci->pshadow [frame];
1256         itd->hw_next = ehci->periodic [frame];
1257         ehci->pshadow [frame].itd = itd;
1258         itd->frame = frame;
1259         wmb ();
1260         ehci->periodic [frame] = cpu_to_le32 (itd->itd_dma) | Q_TYPE_ITD;
1261 }
1262
1263 /* fit urb's itds into the selected schedule slot; activate as needed */
1264 static int
1265 itd_link_urb (
1266         struct ehci_hcd         *ehci,
1267         struct urb              *urb,
1268         unsigned                mod,
1269         struct ehci_iso_stream  *stream
1270 )
1271 {
1272         int                     packet;
1273         unsigned                next_uframe, uframe, frame;
1274         struct ehci_iso_sched   *iso_sched = urb->hcpriv;
1275         struct ehci_itd         *itd;
1276
1277         next_uframe = stream->next_uframe % mod;
1278
1279         if (unlikely (list_empty(&stream->td_list))) {
1280                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1281                                 += stream->bandwidth;
1282                 ehci_vdbg (ehci,
1283                         "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1284                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1285                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1286                         urb->interval,
1287                         next_uframe >> 3, next_uframe & 0x7);
1288                 stream->start = jiffies;
1289         }
1290         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1291
1292         /* fill iTDs uframe by uframe */
1293         for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1294                 if (itd == NULL) {
1295                         /* ASSERT:  we have all necessary itds */
1296                         // BUG_ON (list_empty (&iso_sched->td_list));
1297
1298                         /* ASSERT:  no itds for this endpoint in this uframe */
1299
1300                         itd = list_entry (iso_sched->td_list.next,
1301                                         struct ehci_itd, itd_list);
1302                         list_move_tail (&itd->itd_list, &stream->td_list);
1303                         itd->stream = iso_stream_get (stream);
1304                         itd->urb = usb_get_urb (urb);
1305                         itd_init (stream, itd);
1306                 }
1307
1308                 uframe = next_uframe & 0x07;
1309                 frame = next_uframe >> 3;
1310
1311                 itd->usecs [uframe] = stream->usecs;
1312                 itd_patch (itd, iso_sched, packet, uframe);
1313
1314                 next_uframe += stream->interval;
1315                 stream->depth += stream->interval;
1316                 next_uframe %= mod;
1317                 packet++;
1318
1319                 /* link completed itds into the schedule */
1320                 if (((next_uframe >> 3) != frame)
1321                                 || packet == urb->number_of_packets) {
1322                         itd_link (ehci, frame % ehci->periodic_size, itd);
1323                         itd = NULL;
1324                 }
1325         }
1326         stream->next_uframe = next_uframe;
1327
1328         /* don't need that schedule data any more */
1329         iso_sched_free (stream, iso_sched);
1330         urb->hcpriv = NULL;
1331
1332         timer_action (ehci, TIMER_IO_WATCHDOG);
1333         if (unlikely (!ehci->periodic_sched++))
1334                 return enable_periodic (ehci);
1335         return 0;
1336 }
1337
1338 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1339
1340 static unsigned
1341 itd_complete (
1342         struct ehci_hcd *ehci,
1343         struct ehci_itd *itd,
1344         struct pt_regs  *regs
1345 ) {
1346         struct urb                              *urb = itd->urb;
1347         struct usb_iso_packet_descriptor        *desc;
1348         u32                                     t;
1349         unsigned                                uframe;
1350         int                                     urb_index = -1;
1351         struct ehci_iso_stream                  *stream = itd->stream;
1352         struct usb_device                       *dev;
1353
1354         /* for each uframe with a packet */
1355         for (uframe = 0; uframe < 8; uframe++) {
1356                 if (likely (itd->index[uframe] == -1))
1357                         continue;
1358                 urb_index = itd->index[uframe];
1359                 desc = &urb->iso_frame_desc [urb_index];
1360
1361                 t = le32_to_cpup (&itd->hw_transaction [uframe]);
1362                 itd->hw_transaction [uframe] = 0;
1363                 stream->depth -= stream->interval;
1364
1365                 /* report transfer status */
1366                 if (unlikely (t & ISO_ERRS)) {
1367                         urb->error_count++;
1368                         if (t & EHCI_ISOC_BUF_ERR)
1369                                 desc->status = usb_pipein (urb->pipe)
1370                                         ? -ENOSR  /* hc couldn't read */
1371                                         : -ECOMM; /* hc couldn't write */
1372                         else if (t & EHCI_ISOC_BABBLE)
1373                                 desc->status = -EOVERFLOW;
1374                         else /* (t & EHCI_ISOC_XACTERR) */
1375                                 desc->status = -EPROTO;
1376
1377                         /* HC need not update length with this error */
1378                         if (!(t & EHCI_ISOC_BABBLE))
1379                                 desc->actual_length = EHCI_ITD_LENGTH (t);
1380                 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1381                         desc->status = 0;
1382                         desc->actual_length = EHCI_ITD_LENGTH (t);
1383                 }
1384         }
1385
1386         usb_put_urb (urb);
1387         itd->urb = NULL;
1388         itd->stream = NULL;
1389         list_move (&itd->itd_list, &stream->free_list);
1390         iso_stream_put (ehci, stream);
1391
1392         /* handle completion now? */
1393         if (likely ((urb_index + 1) != urb->number_of_packets))
1394                 return 0;
1395
1396         /* ASSERT: it's really the last itd for this urb
1397         list_for_each_entry (itd, &stream->td_list, itd_list)
1398                 BUG_ON (itd->urb == urb);
1399          */
1400
1401         /* give urb back to the driver ... can be out-of-order */
1402         dev = usb_get_dev (urb->dev);
1403         ehci_urb_done (ehci, urb, regs);
1404         urb = NULL;
1405
1406         /* defer stopping schedule; completion can submit */
1407         ehci->periodic_sched--;
1408         if (unlikely (!ehci->periodic_sched))
1409                 (void) disable_periodic (ehci);
1410         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1411
1412         if (unlikely (list_empty (&stream->td_list))) {
1413                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1414                                 -= stream->bandwidth;
1415                 ehci_vdbg (ehci,
1416                         "deschedule devp %s ep%d%s-iso\n",
1417                         dev->devpath, stream->bEndpointAddress & 0x0f,
1418                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1419         }
1420         iso_stream_put (ehci, stream);
1421         usb_put_dev (dev);
1422
1423         return 1;
1424 }
1425
1426 /*-------------------------------------------------------------------------*/
1427
1428 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1429         gfp_t mem_flags)
1430 {
1431         int                     status = -EINVAL;
1432         unsigned long           flags;
1433         struct ehci_iso_stream  *stream;
1434
1435         /* Get iso_stream head */
1436         stream = iso_stream_find (ehci, urb);
1437         if (unlikely (stream == NULL)) {
1438                 ehci_dbg (ehci, "can't get iso stream\n");
1439                 return -ENOMEM;
1440         }
1441         if (unlikely (urb->interval != stream->interval)) {
1442                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1443                         stream->interval, urb->interval);
1444                 goto done;
1445         }
1446
1447 #ifdef EHCI_URB_TRACE
1448         ehci_dbg (ehci,
1449                 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1450                 __FUNCTION__, urb->dev->devpath, urb,
1451                 usb_pipeendpoint (urb->pipe),
1452                 usb_pipein (urb->pipe) ? "in" : "out",
1453                 urb->transfer_buffer_length,
1454                 urb->number_of_packets, urb->interval,
1455                 stream);
1456 #endif
1457
1458         /* allocate ITDs w/o locking anything */
1459         status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1460         if (unlikely (status < 0)) {
1461                 ehci_dbg (ehci, "can't init itds\n");
1462                 goto done;
1463         }
1464
1465         /* schedule ... need to lock */
1466         spin_lock_irqsave (&ehci->lock, flags);
1467         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1468                                &ehci_to_hcd(ehci)->flags)))
1469                 status = -ESHUTDOWN;
1470         else
1471                 status = iso_stream_schedule (ehci, urb, stream);
1472         if (likely (status == 0))
1473                 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1474         spin_unlock_irqrestore (&ehci->lock, flags);
1475
1476 done:
1477         if (unlikely (status < 0))
1478                 iso_stream_put (ehci, stream);
1479         return status;
1480 }
1481
1482 #ifdef CONFIG_USB_EHCI_SPLIT_ISO
1483
1484 /*-------------------------------------------------------------------------*/
1485
1486 /*
1487  * "Split ISO TDs" ... used for USB 1.1 devices going through the
1488  * TTs in USB 2.0 hubs.  These need microframe scheduling.
1489  */
1490
1491 static inline void
1492 sitd_sched_init (
1493         struct ehci_iso_sched   *iso_sched,
1494         struct ehci_iso_stream  *stream,
1495         struct urb              *urb
1496 )
1497 {
1498         unsigned        i;
1499         dma_addr_t      dma = urb->transfer_dma;
1500
1501         /* how many frames are needed for these transfers */
1502         iso_sched->span = urb->number_of_packets * stream->interval;
1503
1504         /* figure out per-frame sitd fields that we'll need later
1505          * when we fit new sitds into the schedule.
1506          */
1507         for (i = 0; i < urb->number_of_packets; i++) {
1508                 struct ehci_iso_packet  *packet = &iso_sched->packet [i];
1509                 unsigned                length;
1510                 dma_addr_t              buf;
1511                 u32                     trans;
1512
1513                 length = urb->iso_frame_desc [i].length & 0x03ff;
1514                 buf = dma + urb->iso_frame_desc [i].offset;
1515
1516                 trans = SITD_STS_ACTIVE;
1517                 if (((i + 1) == urb->number_of_packets)
1518                                 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1519                         trans |= SITD_IOC;
1520                 trans |= length << 16;
1521                 packet->transaction = cpu_to_le32 (trans);
1522
1523                 /* might need to cross a buffer page within a td */
1524                 packet->bufp = buf;
1525                 packet->buf1 = (buf + length) & ~0x0fff;
1526                 if (packet->buf1 != (buf & ~(u64)0x0fff))
1527                         packet->cross = 1;
1528
1529                 /* OUT uses multiple start-splits */
1530                 if (stream->bEndpointAddress & USB_DIR_IN)
1531                         continue;
1532                 length = (length + 187) / 188;
1533                 if (length > 1) /* BEGIN vs ALL */
1534                         length |= 1 << 3;
1535                 packet->buf1 |= length;
1536         }
1537 }
1538
1539 static int
1540 sitd_urb_transaction (
1541         struct ehci_iso_stream  *stream,
1542         struct ehci_hcd         *ehci,
1543         struct urb              *urb,
1544         gfp_t                   mem_flags
1545 )
1546 {
1547         struct ehci_sitd        *sitd;
1548         dma_addr_t              sitd_dma;
1549         int                     i;
1550         struct ehci_iso_sched   *iso_sched;
1551         unsigned long           flags;
1552
1553         iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1554         if (iso_sched == NULL)
1555                 return -ENOMEM;
1556
1557         sitd_sched_init (iso_sched, stream, urb);
1558
1559         /* allocate/init sITDs */
1560         spin_lock_irqsave (&ehci->lock, flags);
1561         for (i = 0; i < urb->number_of_packets; i++) {
1562
1563                 /* NOTE:  for now, we don't try to handle wraparound cases
1564                  * for IN (using sitd->hw_backpointer, like a FSTN), which
1565                  * means we never need two sitds for full speed packets.
1566                  */
1567
1568                 /* free_list.next might be cache-hot ... but maybe
1569                  * the HC caches it too. avoid that issue for now.
1570                  */
1571
1572                 /* prefer previously-allocated sitds */
1573                 if (!list_empty(&stream->free_list)) {
1574                         sitd = list_entry (stream->free_list.prev,
1575                                          struct ehci_sitd, sitd_list);
1576                         list_del (&sitd->sitd_list);
1577                         sitd_dma = sitd->sitd_dma;
1578                 } else
1579                         sitd = NULL;
1580
1581                 if (!sitd) {
1582                         spin_unlock_irqrestore (&ehci->lock, flags);
1583                         sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1584                                         &sitd_dma);
1585                         spin_lock_irqsave (&ehci->lock, flags);
1586                 }
1587
1588                 if (!sitd) {
1589                         iso_sched_free (stream, iso_sched);
1590                         spin_unlock_irqrestore (&ehci->lock, flags);
1591                         return -ENOMEM;
1592                 }
1593                 memset (sitd, 0, sizeof *sitd);
1594                 sitd->sitd_dma = sitd_dma;
1595                 list_add (&sitd->sitd_list, &iso_sched->td_list);
1596         }
1597
1598         /* temporarily store schedule info in hcpriv */
1599         urb->hcpriv = iso_sched;
1600         urb->error_count = 0;
1601
1602         spin_unlock_irqrestore (&ehci->lock, flags);
1603         return 0;
1604 }
1605
1606 /*-------------------------------------------------------------------------*/
1607
1608 static inline void
1609 sitd_patch (
1610         struct ehci_iso_stream  *stream,
1611         struct ehci_sitd        *sitd,
1612         struct ehci_iso_sched   *iso_sched,
1613         unsigned                index
1614 )
1615 {
1616         struct ehci_iso_packet  *uf = &iso_sched->packet [index];
1617         u64                     bufp = uf->bufp;
1618
1619         sitd->hw_next = EHCI_LIST_END;
1620         sitd->hw_fullspeed_ep = stream->address;
1621         sitd->hw_uframe = stream->splits;
1622         sitd->hw_results = uf->transaction;
1623         sitd->hw_backpointer = EHCI_LIST_END;
1624
1625         bufp = uf->bufp;
1626         sitd->hw_buf [0] = cpu_to_le32 (bufp);
1627         sitd->hw_buf_hi [0] = cpu_to_le32 (bufp >> 32);
1628
1629         sitd->hw_buf [1] = cpu_to_le32 (uf->buf1);
1630         if (uf->cross)
1631                 bufp += 4096;
1632         sitd->hw_buf_hi [1] = cpu_to_le32 (bufp >> 32);
1633         sitd->index = index;
1634 }
1635
1636 static inline void
1637 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1638 {
1639         /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1640         sitd->sitd_next = ehci->pshadow [frame];
1641         sitd->hw_next = ehci->periodic [frame];
1642         ehci->pshadow [frame].sitd = sitd;
1643         sitd->frame = frame;
1644         wmb ();
1645         ehci->periodic [frame] = cpu_to_le32 (sitd->sitd_dma) | Q_TYPE_SITD;
1646 }
1647
1648 /* fit urb's sitds into the selected schedule slot; activate as needed */
1649 static int
1650 sitd_link_urb (
1651         struct ehci_hcd         *ehci,
1652         struct urb              *urb,
1653         unsigned                mod,
1654         struct ehci_iso_stream  *stream
1655 )
1656 {
1657         int                     packet;
1658         unsigned                next_uframe;
1659         struct ehci_iso_sched   *sched = urb->hcpriv;
1660         struct ehci_sitd        *sitd;
1661
1662         next_uframe = stream->next_uframe;
1663
1664         if (list_empty(&stream->td_list)) {
1665                 /* usbfs ignores TT bandwidth */
1666                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1667                                 += stream->bandwidth;
1668                 ehci_vdbg (ehci,
1669                         "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
1670                         urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1671                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1672                         (next_uframe >> 3) % ehci->periodic_size,
1673                         stream->interval, le32_to_cpu (stream->splits));
1674                 stream->start = jiffies;
1675         }
1676         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1677
1678         /* fill sITDs frame by frame */
1679         for (packet = 0, sitd = NULL;
1680                         packet < urb->number_of_packets;
1681                         packet++) {
1682
1683                 /* ASSERT:  we have all necessary sitds */
1684                 BUG_ON (list_empty (&sched->td_list));
1685
1686                 /* ASSERT:  no itds for this endpoint in this frame */
1687
1688                 sitd = list_entry (sched->td_list.next,
1689                                 struct ehci_sitd, sitd_list);
1690                 list_move_tail (&sitd->sitd_list, &stream->td_list);
1691                 sitd->stream = iso_stream_get (stream);
1692                 sitd->urb = usb_get_urb (urb);
1693
1694                 sitd_patch (stream, sitd, sched, packet);
1695                 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
1696                                 sitd);
1697
1698                 next_uframe += stream->interval << 3;
1699                 stream->depth += stream->interval << 3;
1700         }
1701         stream->next_uframe = next_uframe % mod;
1702
1703         /* don't need that schedule data any more */
1704         iso_sched_free (stream, sched);
1705         urb->hcpriv = NULL;
1706
1707         timer_action (ehci, TIMER_IO_WATCHDOG);
1708         if (!ehci->periodic_sched++)
1709                 return enable_periodic (ehci);
1710         return 0;
1711 }
1712
1713 /*-------------------------------------------------------------------------*/
1714
1715 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
1716                                 | SITD_STS_XACT | SITD_STS_MMF)
1717
1718 static unsigned
1719 sitd_complete (
1720         struct ehci_hcd         *ehci,
1721         struct ehci_sitd        *sitd,
1722         struct pt_regs          *regs
1723 ) {
1724         struct urb                              *urb = sitd->urb;
1725         struct usb_iso_packet_descriptor        *desc;
1726         u32                                     t;
1727         int                                     urb_index = -1;
1728         struct ehci_iso_stream                  *stream = sitd->stream;
1729         struct usb_device                       *dev;
1730
1731         urb_index = sitd->index;
1732         desc = &urb->iso_frame_desc [urb_index];
1733         t = le32_to_cpup (&sitd->hw_results);
1734
1735         /* report transfer status */
1736         if (t & SITD_ERRS) {
1737                 urb->error_count++;
1738                 if (t & SITD_STS_DBE)
1739                         desc->status = usb_pipein (urb->pipe)
1740                                 ? -ENOSR  /* hc couldn't read */
1741                                 : -ECOMM; /* hc couldn't write */
1742                 else if (t & SITD_STS_BABBLE)
1743                         desc->status = -EOVERFLOW;
1744                 else /* XACT, MMF, etc */
1745                         desc->status = -EPROTO;
1746         } else {
1747                 desc->status = 0;
1748                 desc->actual_length = desc->length - SITD_LENGTH (t);
1749         }
1750
1751         usb_put_urb (urb);
1752         sitd->urb = NULL;
1753         sitd->stream = NULL;
1754         list_move (&sitd->sitd_list, &stream->free_list);
1755         stream->depth -= stream->interval << 3;
1756         iso_stream_put (ehci, stream);
1757
1758         /* handle completion now? */
1759         if ((urb_index + 1) != urb->number_of_packets)
1760                 return 0;
1761
1762         /* ASSERT: it's really the last sitd for this urb
1763         list_for_each_entry (sitd, &stream->td_list, sitd_list)
1764                 BUG_ON (sitd->urb == urb);
1765          */
1766
1767         /* give urb back to the driver */
1768         dev = usb_get_dev (urb->dev);
1769         ehci_urb_done (ehci, urb, regs);
1770         urb = NULL;
1771
1772         /* defer stopping schedule; completion can submit */
1773         ehci->periodic_sched--;
1774         if (!ehci->periodic_sched)
1775                 (void) disable_periodic (ehci);
1776         ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1777
1778         if (list_empty (&stream->td_list)) {
1779                 ehci_to_hcd(ehci)->self.bandwidth_allocated
1780                                 -= stream->bandwidth;
1781                 ehci_vdbg (ehci,
1782                         "deschedule devp %s ep%d%s-iso\n",
1783                         dev->devpath, stream->bEndpointAddress & 0x0f,
1784                         (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1785         }
1786         iso_stream_put (ehci, stream);
1787         usb_put_dev (dev);
1788
1789         return 1;
1790 }
1791
1792
1793 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
1794         gfp_t mem_flags)
1795 {
1796         int                     status = -EINVAL;
1797         unsigned long           flags;
1798         struct ehci_iso_stream  *stream;
1799
1800         /* Get iso_stream head */
1801         stream = iso_stream_find (ehci, urb);
1802         if (stream == NULL) {
1803                 ehci_dbg (ehci, "can't get iso stream\n");
1804                 return -ENOMEM;
1805         }
1806         if (urb->interval != stream->interval) {
1807                 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1808                         stream->interval, urb->interval);
1809                 goto done;
1810         }
1811
1812 #ifdef EHCI_URB_TRACE
1813         ehci_dbg (ehci,
1814                 "submit %p dev%s ep%d%s-iso len %d\n",
1815                 urb, urb->dev->devpath,
1816                 usb_pipeendpoint (urb->pipe),
1817                 usb_pipein (urb->pipe) ? "in" : "out",
1818                 urb->transfer_buffer_length);
1819 #endif
1820
1821         /* allocate SITDs */
1822         status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
1823         if (status < 0) {
1824                 ehci_dbg (ehci, "can't init sitds\n");
1825                 goto done;
1826         }
1827
1828         /* schedule ... need to lock */
1829         spin_lock_irqsave (&ehci->lock, flags);
1830         if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
1831                                &ehci_to_hcd(ehci)->flags)))
1832                 status = -ESHUTDOWN;
1833         else
1834                 status = iso_stream_schedule (ehci, urb, stream);
1835         if (status == 0)
1836                 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1837         spin_unlock_irqrestore (&ehci->lock, flags);
1838
1839 done:
1840         if (status < 0)
1841                 iso_stream_put (ehci, stream);
1842         return status;
1843 }
1844
1845 #else
1846
1847 static inline int
1848 sitd_submit (struct ehci_hcd *ehci, struct urb *urb, gfp_t mem_flags)
1849 {
1850         ehci_dbg (ehci, "split iso support is disabled\n");
1851         return -ENOSYS;
1852 }
1853
1854 static inline unsigned
1855 sitd_complete (
1856         struct ehci_hcd         *ehci,
1857         struct ehci_sitd        *sitd,
1858         struct pt_regs          *regs
1859 ) {
1860         ehci_err (ehci, "sitd_complete %p?\n", sitd);
1861         return 0;
1862 }
1863
1864 #endif /* USB_EHCI_SPLIT_ISO */
1865
1866 /*-------------------------------------------------------------------------*/
1867
1868 static void
1869 scan_periodic (struct ehci_hcd *ehci, struct pt_regs *regs)
1870 {
1871         unsigned        frame, clock, now_uframe, mod;
1872         unsigned        modified;
1873
1874         mod = ehci->periodic_size << 3;
1875
1876         /*
1877          * When running, scan from last scan point up to "now"
1878          * else clean up by scanning everything that's left.
1879          * Touches as few pages as possible:  cache-friendly.
1880          */
1881         now_uframe = ehci->next_uframe;
1882         if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
1883                 clock = readl (&ehci->regs->frame_index);
1884         else
1885                 clock = now_uframe + mod - 1;
1886         clock %= mod;
1887
1888         for (;;) {
1889                 union ehci_shadow       q, *q_p;
1890                 __le32                  type, *hw_p;
1891                 unsigned                uframes;
1892
1893                 /* don't scan past the live uframe */
1894                 frame = now_uframe >> 3;
1895                 if (frame == (clock >> 3))
1896                         uframes = now_uframe & 0x07;
1897                 else {
1898                         /* safe to scan the whole frame at once */
1899                         now_uframe |= 0x07;
1900                         uframes = 8;
1901                 }
1902
1903 restart:
1904                 /* scan each element in frame's queue for completions */
1905                 q_p = &ehci->pshadow [frame];
1906                 hw_p = &ehci->periodic [frame];
1907                 q.ptr = q_p->ptr;
1908                 type = Q_NEXT_TYPE (*hw_p);
1909                 modified = 0;
1910
1911                 while (q.ptr != NULL) {
1912                         unsigned                uf;
1913                         union ehci_shadow       temp;
1914                         int                     live;
1915
1916                         live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
1917                         switch (type) {
1918                         case Q_TYPE_QH:
1919                                 /* handle any completions */
1920                                 temp.qh = qh_get (q.qh);
1921                                 type = Q_NEXT_TYPE (q.qh->hw_next);
1922                                 q = q.qh->qh_next;
1923                                 modified = qh_completions (ehci, temp.qh, regs);
1924                                 if (unlikely (list_empty (&temp.qh->qtd_list)))
1925                                         intr_deschedule (ehci, temp.qh);
1926                                 qh_put (temp.qh);
1927                                 break;
1928                         case Q_TYPE_FSTN:
1929                                 /* for "save place" FSTNs, look at QH entries
1930                                  * in the previous frame for completions.
1931                                  */
1932                                 if (q.fstn->hw_prev != EHCI_LIST_END) {
1933                                         dbg ("ignoring completions from FSTNs");
1934                                 }
1935                                 type = Q_NEXT_TYPE (q.fstn->hw_next);
1936                                 q = q.fstn->fstn_next;
1937                                 break;
1938                         case Q_TYPE_ITD:
1939                                 /* skip itds for later in the frame */
1940                                 rmb ();
1941                                 for (uf = live ? uframes : 8; uf < 8; uf++) {
1942                                         if (0 == (q.itd->hw_transaction [uf]
1943                                                         & ITD_ACTIVE))
1944                                                 continue;
1945                                         q_p = &q.itd->itd_next;
1946                                         hw_p = &q.itd->hw_next;
1947                                         type = Q_NEXT_TYPE (q.itd->hw_next);
1948                                         q = *q_p;
1949                                         break;
1950                                 }
1951                                 if (uf != 8)
1952                                         break;
1953
1954                                 /* this one's ready ... HC won't cache the
1955                                  * pointer for much longer, if at all.
1956                                  */
1957                                 *q_p = q.itd->itd_next;
1958                                 *hw_p = q.itd->hw_next;
1959                                 type = Q_NEXT_TYPE (q.itd->hw_next);
1960                                 wmb();
1961                                 modified = itd_complete (ehci, q.itd, regs);
1962                                 q = *q_p;
1963                                 break;
1964                         case Q_TYPE_SITD:
1965                                 if ((q.sitd->hw_results & SITD_ACTIVE)
1966                                                 && live) {
1967                                         q_p = &q.sitd->sitd_next;
1968                                         hw_p = &q.sitd->hw_next;
1969                                         type = Q_NEXT_TYPE (q.sitd->hw_next);
1970                                         q = *q_p;
1971                                         break;
1972                                 }
1973                                 *q_p = q.sitd->sitd_next;
1974                                 *hw_p = q.sitd->hw_next;
1975                                 type = Q_NEXT_TYPE (q.sitd->hw_next);
1976                                 wmb();
1977                                 modified = sitd_complete (ehci, q.sitd, regs);
1978                                 q = *q_p;
1979                                 break;
1980                         default:
1981                                 dbg ("corrupt type %d frame %d shadow %p",
1982                                         type, frame, q.ptr);
1983                                 // BUG ();
1984                                 q.ptr = NULL;
1985                         }
1986
1987                         /* assume completion callbacks modify the queue */
1988                         if (unlikely (modified))
1989                                 goto restart;
1990                 }
1991
1992                 /* stop when we catch up to the HC */
1993
1994                 // FIXME:  this assumes we won't get lapped when
1995                 // latencies climb; that should be rare, but...
1996                 // detect it, and just go all the way around.
1997                 // FLR might help detect this case, so long as latencies
1998                 // don't exceed periodic_size msec (default 1.024 sec).
1999
2000                 // FIXME:  likewise assumes HC doesn't halt mid-scan
2001
2002                 if (now_uframe == clock) {
2003                         unsigned        now;
2004
2005                         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2006                                 break;
2007                         ehci->next_uframe = now_uframe;
2008                         now = readl (&ehci->regs->frame_index) % mod;
2009                         if (now_uframe == now)
2010                                 break;
2011
2012                         /* rescan the rest of this frame, then ... */
2013                         clock = now;
2014                 } else {
2015                         now_uframe++;
2016                         now_uframe %= mod;
2017                 }
2018         }
2019 }