SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/usb/host/ehci-hcd.c

   1 /*
   2  * Copyright (c) 2000-2004 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/dmapool.h>
  22 #include <linux/kernel.h>
  23 #include <linux/delay.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/slab.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/errno.h>
  29 #include <linux/init.h>
  30 #include <linux/timer.h>
  31 #include <linux/ktime.h>
  32 #include <linux/list.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/usb.h>
  35 #include <linux/moduleparam.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/debugfs.h>
  38
  39 #include "../core/hcd.h"
  40
  41 #include <asm/byteorder.h>
  42 #include <asm/io.h>
  43 #include <asm/irq.h>
  44 #include <asm/system.h>
  45 #include <asm/unaligned.h>
  46
  47 /*-------------------------------------------------------------------------*/
  48
  49 /*
  50  * EHCI hc_driver implementation ... experimental, incomplete.
  51  * Based on the final 1.0 register interface specification.
  52  *
  53  * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  54  * First was PCMCIA, like ISA; then CardBus, which is PCI.
  55  * Next comes "CardBay", using USB 2.0 signals.
  56  *
  57  * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  58  * Special thanks to Intel and VIA for providing host controllers to
  59  * test this driver on, and Cypress (including In-System Design) for
  60  * providing early devices for those host controllers to talk to!
  61  */
  62
  63 #define DRIVER_AUTHOR "David Brownell"
  64 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  65
  66 static const char       hcd_name [] = "ehci_hcd";
  67
  68
  69 #undef VERBOSE_DEBUG
  70 #undef EHCI_URB_TRACE
  71
  72 #ifdef DEBUG
  73 #define EHCI_STATS
  74 #endif
  75
  76 /* magic numbers that can affect system performance */
  77 #define EHCI_TUNE_CERR          3       /* 0-3 qtd retries; 0 == don't stop */
  78 #define EHCI_TUNE_RL_HS         4       /* nak throttle; see 4.9 */
  79 #define EHCI_TUNE_RL_TT         0
  80 #define EHCI_TUNE_MULT_HS       1       /* 1-3 transactions/uframe; 4.10.3 */
  81 #define EHCI_TUNE_MULT_TT       1
  82 #define EHCI_TUNE_FLS           2       /* (small) 256 frame schedule */
  83
  84 #define EHCI_IAA_MSECS          10              /* arbitrary */
  85 #define EHCI_IO_JIFFIES         (HZ/10)         /* io watchdog > irq_thresh */
  86 #define EHCI_ASYNC_JIFFIES      (HZ/20)         /* async idle timeout */
  87 #define EHCI_SHRINK_FRAMES      5               /* async qh unlink delay */
  88
  89 /* Initial IRQ latency:  faster than hw default */
  90 static int log2_irq_thresh = 0;         // 0 to 6
  91 module_param (log2_irq_thresh, int, S_IRUGO);
  92 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  93
  94 /* initial park setting:  slower than hw default */
  95 static unsigned park = 0;
  96 module_param (park, uint, S_IRUGO);
  97 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
  98
  99 /* for flakey hardware, ignore overcurrent indicators */
 100 static int ignore_oc = 0;
 101 module_param (ignore_oc, bool, S_IRUGO);
 102 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
 103
 104 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
 105
 106 /*-------------------------------------------------------------------------*/
 107
 108 #include "ehci.h"
 109 #include "ehci-dbg.c"
 110
 111 /*-------------------------------------------------------------------------*/
 112
 113 static void
 114 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
 115 {
 116         /* Don't override timeouts which shrink or (later) disable
 117          * the async ring; just the I/O watchdog.  Note that if a
 118          * SHRINK were pending, OFF would never be requested.
 119          */
 120         if (timer_pending(&ehci->watchdog)
 121                         && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
 122                                 & ehci->actions))
 123                 return;
 124
 125         if (!test_and_set_bit(action, &ehci->actions)) {
 126                 unsigned long t;
 127
 128                 switch (action) {
 129                 case TIMER_IO_WATCHDOG:
 130                         if (!ehci->need_io_watchdog)
 131                                 return;
 132                         t = EHCI_IO_JIFFIES;
 133                         break;
 134                 case TIMER_ASYNC_OFF:
 135                         t = EHCI_ASYNC_JIFFIES;
 136                         break;
 137                 /* case TIMER_ASYNC_SHRINK: */
 138                 default:
 139                         /* add a jiffie since we synch against the
 140                          * 8 KHz uframe counter.
 141                          */
 142                         t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
 143                         break;
 144                 }
 145                 mod_timer(&ehci->watchdog, t + jiffies);
 146         }
 147 }
 148
 149 /*-------------------------------------------------------------------------*/
 150
 151 /*
 152  * handshake - spin reading hc until handshake completes or fails
 153  * @ptr: address of hc register to be read
 154  * @mask: bits to look at in result of read
 155  * @done: value of those bits when handshake succeeds
 156  * @usec: timeout in microseconds
 157  *
 158  * Returns negative errno, or zero on success
 159  *
 160  * Success happens when the "mask" bits have the specified value (hardware
 161  * handshake done).  There are two failure modes:  "usec" have passed (major
 162  * hardware flakeout), or the register reads as all-ones (hardware removed).
 163  *
 164  * That last failure should_only happen in cases like physical cardbus eject
 165  * before driver shutdown. But it also seems to be caused by bugs in cardbus
 166  * bridge shutdown:  shutting down the bridge before the devices using it.
 167  */
 168 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
 169                       u32 mask, u32 done, int usec)
 170 {
 171         u32     result;
 172
 173         do {
 174                 result = ehci_readl(ehci, ptr);
 175                 if (result == ~(u32)0)          /* card removed */
 176                         return -ENODEV;
 177                 result &= mask;
 178                 if (result == done)
 179                         return 0;
 180                 udelay (1);
 181                 usec--;
 182         } while (usec > 0);
 183         return -ETIMEDOUT;
 184 }
 185
 186 /* force HC to halt state from unknown (EHCI spec section 2.3) */
 187 static int ehci_halt (struct ehci_hcd *ehci)
 188 {
 189         u32     temp = ehci_readl(ehci, &ehci->regs->status);
 190
 191         /* disable any irqs left enabled by previous code */
 192         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 193
 194         if ((temp & STS_HALT) != 0)
 195                 return 0;
 196
 197         temp = ehci_readl(ehci, &ehci->regs->command);
 198         temp &= ~CMD_RUN;
 199         ehci_writel(ehci, temp, &ehci->regs->command);
 200         return handshake (ehci, &ehci->regs->status,
 201                           STS_HALT, STS_HALT, 16 * 125);
 202 }
 203
 204 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
 205                                        u32 mask, u32 done, int usec)
 206 {
 207         int error;
 208
 209         error = handshake(ehci, ptr, mask, done, usec);
 210         if (error) {
 211                 ehci_halt(ehci);
 212                 ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 213                 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
 214                         ptr, mask, done, error);
 215         }
 216
 217         return error;
 218 }
 219
 220 /* put TDI/ARC silicon into EHCI mode */
 221 static void tdi_reset (struct ehci_hcd *ehci)
 222 {
 223         u32 __iomem     *reg_ptr;
 224         u32             tmp;
 225
 226         reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
 227         tmp = ehci_readl(ehci, reg_ptr);
 228         tmp |= USBMODE_CM_HC;
 229         /* The default byte access to MMR space is LE after
 230          * controller reset. Set the required endian mode
 231          * for transfer buffers to match the host microprocessor
 232          */
 233         if (ehci_big_endian_mmio(ehci))
 234                 tmp |= USBMODE_BE;
 235         ehci_writel(ehci, tmp, reg_ptr);
 236 }
 237
 238 /* reset a non-running (STS_HALT == 1) controller */
 239 static int ehci_reset (struct ehci_hcd *ehci)
 240 {
 241         int     retval;
 242         u32     command = ehci_readl(ehci, &ehci->regs->command);
 243
 244         /* If the EHCI debug controller is active, special care must be
 245          * taken before and after a host controller reset */
 246         if (ehci->debug && !dbgp_reset_prep())
 247                 ehci->debug = NULL;
 248
 249         command |= CMD_RESET;
 250         dbg_cmd (ehci, "reset", command);
 251         ehci_writel(ehci, command, &ehci->regs->command);
 252         ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 253         ehci->next_statechange = jiffies;
 254         retval = handshake (ehci, &ehci->regs->command,
 255                             CMD_RESET, 0, 250 * 1000);
 256
 257         if (ehci->has_hostpc) {
 258                 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
 259                         (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
 260                 ehci_writel(ehci, TXFIFO_DEFAULT,
 261                         (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
 262         }
 263         if (retval)
 264                 return retval;
 265
 266         if (ehci_is_TDI(ehci))
 267                 tdi_reset (ehci);
 268
 269         if (ehci->debug)
 270                 dbgp_external_startup();
 271
 272         return retval;
 273 }
 274
 275 /* idle the controller (from running) */
 276 static void ehci_quiesce (struct ehci_hcd *ehci)
 277 {
 278         u32     temp;
 279
 280 #ifdef DEBUG
 281         if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
 282                 BUG ();
 283 #endif
 284
 285         /* wait for any schedule enables/disables to take effect */
 286         temp = ehci_readl(ehci, &ehci->regs->command) << 10;
 287         temp &= STS_ASS | STS_PSS;
 288         if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
 289                                         STS_ASS | STS_PSS, temp, 16 * 125))
 290                 return;
 291
 292         /* then disable anything that's still active */
 293         temp = ehci_readl(ehci, &ehci->regs->command);
 294         temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
 295         ehci_writel(ehci, temp, &ehci->regs->command);
 296
 297         /* hardware can take 16 microframes to turn off ... */
 298         handshake_on_error_set_halt(ehci, &ehci->regs->status,
 299                                     STS_ASS | STS_PSS, 0, 16 * 125);
 300 }
 301
 302 /*-------------------------------------------------------------------------*/
 303
 304 static void end_unlink_async(struct ehci_hcd *ehci);
 305 static void ehci_work(struct ehci_hcd *ehci);
 306
 307 #include "ehci-hub.c"
 308 #include "ehci-mem.c"
 309 #include "ehci-q.c"
 310 #include "ehci-sched.c"
 311
 312 /*-------------------------------------------------------------------------*/
 313
 314 static void ehci_iaa_watchdog(unsigned long param)
 315 {
 316         struct ehci_hcd         *ehci = (struct ehci_hcd *) param;
 317         unsigned long           flags;
 318
 319         spin_lock_irqsave (&ehci->lock, flags);
 320
 321         /* Lost IAA irqs wedge things badly; seen first with a vt8235.
 322          * So we need this watchdog, but must protect it against both
 323          * (a) SMP races against real IAA firing and retriggering, and
 324          * (b) clean HC shutdown, when IAA watchdog was pending.
 325          */
 326         if (ehci->reclaim
 327                         && !timer_pending(&ehci->iaa_watchdog)
 328                         && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
 329                 u32 cmd, status;
 330
 331                 /* If we get here, IAA is *REALLY* late.  It's barely
 332                  * conceivable that the system is so busy that CMD_IAAD
 333                  * is still legitimately set, so let's be sure it's
 334                  * clear before we read STS_IAA.  (The HC should clear
 335                  * CMD_IAAD when it sets STS_IAA.)
 336                  */
 337                 cmd = ehci_readl(ehci, &ehci->regs->command);
 338                 if (cmd & CMD_IAAD)
 339                         ehci_writel(ehci, cmd & ~CMD_IAAD,
 340                                         &ehci->regs->command);
 341
 342                 /* If IAA is set here it either legitimately triggered
 343                  * before we cleared IAAD above (but _way_ late, so we'll
 344                  * still count it as lost) ... or a silicon erratum:
 345                  * - VIA seems to set IAA without triggering the IRQ;
 346                  * - IAAD potentially cleared without setting IAA.
 347                  */
 348                 status = ehci_readl(ehci, &ehci->regs->status);
 349                 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
 350                         COUNT (ehci->stats.lost_iaa);
 351                         ehci_writel(ehci, STS_IAA, &ehci->regs->status);
 352                 }
 353
 354                 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
 355                                 status, cmd);
 356                 end_unlink_async(ehci);
 357         }
 358
 359         spin_unlock_irqrestore(&ehci->lock, flags);
 360 }
 361
 362 static void ehci_watchdog(unsigned long param)
 363 {
 364         struct ehci_hcd         *ehci = (struct ehci_hcd *) param;
 365         unsigned long           flags;
 366
 367         spin_lock_irqsave(&ehci->lock, flags);
 368
 369         /* stop async processing after it's idled a bit */
 370         if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
 371                 start_unlink_async (ehci, ehci->async);
 372
 373         /* ehci could run by timer, without IRQs ... */
 374         ehci_work (ehci);
 375
 376         spin_unlock_irqrestore (&ehci->lock, flags);
 377 }
 378
 379 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
 380  * The firmware seems to think that powering off is a wakeup event!
 381  * This routine turns off remote wakeup and everything else, on all ports.
 382  */
 383 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
 384 {
 385         int     port = HCS_N_PORTS(ehci->hcs_params);
 386
 387         while (port--)
 388                 ehci_writel(ehci, PORT_RWC_BITS,
 389                                 &ehci->regs->port_status[port]);
 390 }
 391
 392 /*
 393  * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
 394  * Should be called with ehci->lock held.
 395  */
 396 static void ehci_silence_controller(struct ehci_hcd *ehci)
 397 {
 398         ehci_halt(ehci);
 399         ehci_turn_off_all_ports(ehci);
 400
 401         /* make BIOS/etc use companion controller during reboot */
 402         ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 403
 404         /* unblock posted writes */
 405         ehci_readl(ehci, &ehci->regs->configured_flag);
 406 }
 407
 408 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
 409  * This forcibly disables dma and IRQs, helping kexec and other cases
 410  * where the next system software may expect clean state.
 411  */
 412 static void ehci_shutdown(struct usb_hcd *hcd)
 413 {
 414         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 415
 416         del_timer_sync(&ehci->watchdog);
 417         del_timer_sync(&ehci->iaa_watchdog);
 418
 419         spin_lock_irq(&ehci->lock);
 420         ehci_silence_controller(ehci);
 421         spin_unlock_irq(&ehci->lock);
 422 }
 423
 424 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
 425 {
 426         unsigned port;
 427
 428         if (!HCS_PPC (ehci->hcs_params))
 429                 return;
 430
 431         ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
 432         for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
 433                 (void) ehci_hub_control(ehci_to_hcd(ehci),
 434                                 is_on ? SetPortFeature : ClearPortFeature,
 435                                 USB_PORT_FEAT_POWER,
 436                                 port--, NULL, 0);
 437         /* Flush those writes */
 438         ehci_readl(ehci, &ehci->regs->command);
 439         msleep(20);
 440 }
 441
 442 /*-------------------------------------------------------------------------*/
 443
 444 /*
 445  * ehci_work is called from some interrupts, timers, and so on.
 446  * it calls driver completion functions, after dropping ehci->lock.
 447  */
 448 static void ehci_work (struct ehci_hcd *ehci)
 449 {
 450         timer_action_done (ehci, TIMER_IO_WATCHDOG);
 451
 452         /* another CPU may drop ehci->lock during a schedule scan while
 453          * it reports urb completions.  this flag guards against bogus
 454          * attempts at re-entrant schedule scanning.
 455          */
 456         if (ehci->scanning)
 457                 return;
 458         ehci->scanning = 1;
 459         scan_async (ehci);
 460         if (ehci->next_uframe != -1)
 461                 scan_periodic (ehci);
 462         ehci->scanning = 0;
 463
 464         /* the IO watchdog guards against hardware or driver bugs that
 465          * misplace IRQs, and should let us run completely without IRQs.
 466          * such lossage has been observed on both VT6202 and VT8235.
 467          */
 468         if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
 469                         (ehci->async->qh_next.ptr != NULL ||
 470                          ehci->periodic_sched != 0))
 471                 timer_action (ehci, TIMER_IO_WATCHDOG);
 472 }
 473
 474 /*
 475  * Called when the ehci_hcd module is removed.
 476  */
 477 static void ehci_stop (struct usb_hcd *hcd)
 478 {
 479         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 480
 481         ehci_dbg (ehci, "stop\n");
 482
 483         /* no more interrupts ... */
 484         del_timer_sync (&ehci->watchdog);
 485         del_timer_sync(&ehci->iaa_watchdog);
 486
 487         spin_lock_irq(&ehci->lock);
 488         if (HC_IS_RUNNING (hcd->state))
 489                 ehci_quiesce (ehci);
 490
 491         ehci_silence_controller(ehci);
 492         ehci_reset (ehci);
 493         spin_unlock_irq(&ehci->lock);
 494
 495         remove_companion_file(ehci);
 496         remove_debug_files (ehci);
 497
 498         /* root hub is shut down separately (first, when possible) */
 499         spin_lock_irq (&ehci->lock);
 500         if (ehci->async)
 501                 ehci_work (ehci);
 502         spin_unlock_irq (&ehci->lock);
 503         ehci_mem_cleanup (ehci);
 504
 505 #ifdef  EHCI_STATS
 506         ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
 507                 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
 508                 ehci->stats.lost_iaa);
 509         ehci_dbg (ehci, "complete %ld unlink %ld\n",
 510                 ehci->stats.complete, ehci->stats.unlink);
 511 #endif
 512
 513         dbg_status (ehci, "ehci_stop completed",
 514                     ehci_readl(ehci, &ehci->regs->status));
 515 }
 516
 517 /* one-time init, only for memory state */
 518 static int ehci_init(struct usb_hcd *hcd)
 519 {
 520         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 521         u32                     temp;
 522         int                     retval;
 523         u32                     hcc_params;
 524         struct ehci_qh_hw       *hw;
 525
 526         spin_lock_init(&ehci->lock);
 527
 528         /*
 529          * keep io watchdog by default, those good HCDs could turn off it later
 530          */
 531         ehci->need_io_watchdog = 1;
 532         init_timer(&ehci->watchdog);
 533         ehci->watchdog.function = ehci_watchdog;
 534         ehci->watchdog.data = (unsigned long) ehci;
 535
 536         init_timer(&ehci->iaa_watchdog);
 537         ehci->iaa_watchdog.function = ehci_iaa_watchdog;
 538         ehci->iaa_watchdog.data = (unsigned long) ehci;
 539
 540         /*
 541          * hw default: 1K periodic list heads, one per frame.
 542          * periodic_size can shrink by USBCMD update if hcc_params allows.
 543          */
 544         ehci->periodic_size = DEFAULT_I_TDPS;
 545         INIT_LIST_HEAD(&ehci->cached_itd_list);
 546         if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
 547                 return retval;
 548
 549         /* controllers may cache some of the periodic schedule ... */
 550         hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 551         if (HCC_ISOC_CACHE(hcc_params))         // full frame cache
 552                 ehci->i_thresh = 2 + 8;
 553         else                                    // N microframes cached
 554                 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 555
 556         ehci->reclaim = NULL;
 557         ehci->next_uframe = -1;
 558         ehci->clock_frame = -1;
 559
 560         /*
 561          * dedicate a qh for the async ring head, since we couldn't unlink
 562          * a 'real' qh without stopping the async schedule [4.8].  use it
 563          * as the 'reclamation list head' too.
 564          * its dummy is used in hw_alt_next of many tds, to prevent the qh
 565          * from automatically advancing to the next td after short reads.
 566          */
 567         ehci->async->qh_next.qh = NULL;
 568         hw = ehci->async->hw;
 569         hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
 570         hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
 571         hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
 572         hw->hw_qtd_next = EHCI_LIST_END(ehci);
 573         ehci->async->qh_state = QH_STATE_LINKED;
 574         hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
 575
 576         /* clear interrupt enables, set irq latency */
 577         if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
 578                 log2_irq_thresh = 0;
 579         temp = 1 << (16 + log2_irq_thresh);
 580         if (HCC_CANPARK(hcc_params)) {
 581                 /* HW default park == 3, on hardware that supports it (like
 582                  * NVidia and ALI silicon), maximizes throughput on the async
 583                  * schedule by avoiding QH fetches between transfers.
 584                  *
 585                  * With fast usb storage devices and NForce2, "park" seems to
 586                  * make problems:  throughput reduction (!), data errors...
 587                  */
 588                 if (park) {
 589                         park = min(park, (unsigned) 3);
 590                         temp |= CMD_PARK;
 591                         temp |= park << 8;
 592                 }
 593                 ehci_dbg(ehci, "park %d\n", park);
 594         }
 595         if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
 596                 /* periodic schedule size can be smaller than default */
 597                 temp &= ~(3 << 2);
 598                 temp |= (EHCI_TUNE_FLS << 2);
 599                 switch (EHCI_TUNE_FLS) {
 600                 case 0: ehci->periodic_size = 1024; break;
 601                 case 1: ehci->periodic_size = 512; break;
 602                 case 2: ehci->periodic_size = 256; break;
 603                 default:        BUG();
 604                 }
 605         }
 606         ehci->command = temp;
 607
 608         return 0;
 609 }
 610
 611 /* start HC running; it's halted, ehci_init() has been run (once) */
 612 static int ehci_run (struct usb_hcd *hcd)
 613 {
 614         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 615         int                     retval;
 616         u32                     temp;
 617         u32                     hcc_params;
 618
 619         hcd->uses_new_polling = 1;
 620         hcd->poll_rh = 0;
 621
 622         /* EHCI spec section 4.1 */
 623         if ((retval = ehci_reset(ehci)) != 0) {
 624                 ehci_mem_cleanup(ehci);
 625                 return retval;
 626         }
 627         ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 628         ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 629
 630         /*
 631          * hcc_params controls whether ehci->regs->segment must (!!!)
 632          * be used; it constrains QH/ITD/SITD and QTD locations.
 633          * pci_pool consistent memory always uses segment zero.
 634          * streaming mappings for I/O buffers, like pci_map_single(),
 635          * can return segments above 4GB, if the device allows.
 636          *
 637          * NOTE:  the dma mask is visible through dma_supported(), so
 638          * drivers can pass this info along ... like NETIF_F_HIGHDMA,
 639          * Scsi_Host.highmem_io, and so forth.  It's readonly to all
 640          * host side drivers though.
 641          */
 642         hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 643         if (HCC_64BIT_ADDR(hcc_params)) {
 644                 ehci_writel(ehci, 0, &ehci->regs->segment);
 645 #if 0
 646 // this is deeply broken on almost all architectures
 647                 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
 648                         ehci_info(ehci, "enabled 64bit DMA\n");
 649 #endif
 650         }
 651
 652
 653         // Philips, Intel, and maybe others need CMD_RUN before the
 654         // root hub will detect new devices (why?); NEC doesn't
 655         ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 656         ehci->command |= CMD_RUN;
 657         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 658         dbg_cmd (ehci, "init", ehci->command);
 659
 660         /*
 661          * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
 662          * are explicitly handed to companion controller(s), so no TT is
 663          * involved with the root hub.  (Except where one is integrated,
 664          * and there's no companion controller unless maybe for USB OTG.)
 665          *
 666          * Turning on the CF flag will transfer ownership of all ports
 667          * from the companions to the EHCI controller.  If any of the
 668          * companions are in the middle of a port reset at the time, it
 669          * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
 670          * guarantees that no resets are in progress.  After we set CF,
 671          * a short delay lets the hardware catch up; new resets shouldn't
 672          * be started before the port switching actions could complete.
 673          */
 674         down_write(&ehci_cf_port_reset_rwsem);
 675         hcd->state = HC_STATE_RUNNING;
 676         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 677         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 678         msleep(5);
 679         up_write(&ehci_cf_port_reset_rwsem);
 680         ehci->last_periodic_enable = ktime_get_real();
 681
 682         temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
 683         ehci_info (ehci,
 684                 "USB %x.%x started, EHCI %x.%02x%s\n",
 685                 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
 686                 temp >> 8, temp & 0xff,
 687                 ignore_oc ? ", overcurrent ignored" : "");
 688
 689         ehci_writel(ehci, INTR_MASK,
 690                     &ehci->regs->intr_enable); /* Turn On Interrupts */
 691
 692         /* GRR this is run-once init(), being done every time the HC starts.
 693          * So long as they're part of class devices, we can't do it init()
 694          * since the class device isn't created that early.
 695          */
 696         create_debug_files(ehci);
 697         create_companion_file(ehci);
 698
 699         return 0;
 700 }
 701
 702 /*-------------------------------------------------------------------------*/
 703
 704 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
 705 {
 706         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 707         u32                     status, masked_status, pcd_status = 0, cmd;
 708         int                     bh;
 709
 710         spin_lock (&ehci->lock);
 711
 712         status = ehci_readl(ehci, &ehci->regs->status);
 713
 714         /* e.g. cardbus physical eject */
 715         if (status == ~(u32) 0) {
 716                 ehci_dbg (ehci, "device removed\n");
 717                 goto dead;
 718         }
 719
 720         masked_status = status & INTR_MASK;
 721         if (!masked_status) {           /* irq sharing? */
 722                 spin_unlock(&ehci->lock);
 723                 return IRQ_NONE;
 724         }
 725
 726         /* clear (just) interrupts */
 727         ehci_writel(ehci, masked_status, &ehci->regs->status);
 728         cmd = ehci_readl(ehci, &ehci->regs->command);
 729         bh = 0;
 730
 731 #ifdef  VERBOSE_DEBUG
 732         /* unrequested/ignored: Frame List Rollover */
 733         dbg_status (ehci, "irq", status);
 734 #endif
 735
 736         /* INT, ERR, and IAA interrupt rates can be throttled */
 737
 738         /* normal [4.15.1.2] or error [4.15.1.1] completion */
 739         if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
 740                 if (likely ((status & STS_ERR) == 0))
 741                         COUNT (ehci->stats.normal);
 742                 else
 743                         COUNT (ehci->stats.error);
 744                 bh = 1;
 745         }
 746
 747         /* complete the unlinking of some qh [4.15.2.3] */
 748         if (status & STS_IAA) {
 749                 /* guard against (alleged) silicon errata */
 750                 if (cmd & CMD_IAAD) {
 751                         ehci_writel(ehci, cmd & ~CMD_IAAD,
 752                                         &ehci->regs->command);
 753                         ehci_dbg(ehci, "IAA with IAAD still set?\n");
 754                 }
 755                 if (ehci->reclaim) {
 756                         COUNT(ehci->stats.reclaim);
 757                         end_unlink_async(ehci);
 758                 } else
 759                         ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
 760         }
 761
 762         /* remote wakeup [4.3.1] */
 763         if (status & STS_PCD) {
 764                 unsigned        i = HCS_N_PORTS (ehci->hcs_params);
 765
 766                 /* kick root hub later */
 767                 pcd_status = status;
 768
 769                 /* resume root hub? */
 770                 if (!(cmd & CMD_RUN))
 771                         usb_hcd_resume_root_hub(hcd);
 772
 773                 while (i--) {
 774                         int pstatus = ehci_readl(ehci,
 775                                                  &ehci->regs->port_status [i]);
 776
 777                         if (pstatus & PORT_OWNER)
 778                                 continue;
 779                         if (!(test_bit(i, &ehci->suspended_ports) &&
 780                                         ((pstatus & PORT_RESUME) ||
 781                                                 !(pstatus & PORT_SUSPEND)) &&
 782                                         (pstatus & PORT_PE) &&
 783                                         ehci->reset_done[i] == 0))
 784                                 continue;
 785
 786                         /* start 20 msec resume signaling from this port,
 787                          * and make khubd collect PORT_STAT_C_SUSPEND to
 788                          * stop that signaling.
 789                          */
 790                         ehci->reset_done [i] = jiffies + msecs_to_jiffies (20);
 791                         ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
 792                         mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
 793                 }
 794         }
 795
 796         /* PCI errors [4.15.2.4] */
 797         if (unlikely ((status & STS_FATAL) != 0)) {
 798                 ehci_err(ehci, "fatal error\n");
 799                 dbg_cmd(ehci, "fatal", cmd);
 800                 dbg_status(ehci, "fatal", status);
 801                 ehci_halt(ehci);
 802 dead:
 803                 ehci_reset(ehci);
 804                 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 805                 /* generic layer kills/unlinks all urbs, then
 806                  * uses ehci_stop to clean up the rest
 807                  */
 808                 bh = 1;
 809         }
 810
 811         if (bh)
 812                 ehci_work (ehci);
 813         spin_unlock (&ehci->lock);
 814         if (pcd_status)
 815                 usb_hcd_poll_rh_status(hcd);
 816         return IRQ_HANDLED;
 817 }
 818
 819 /*-------------------------------------------------------------------------*/
 820
 821 /*
 822  * non-error returns are a promise to giveback() the urb later
 823  * we drop ownership so next owner (or urb unlink) can get it
 824  *
 825  * urb + dev is in hcd.self.controller.urb_list
 826  * we're queueing TDs onto software and hardware lists
 827  *
 828  * hcd-specific init for hcpriv hasn't been done yet
 829  *
 830  * NOTE:  control, bulk, and interrupt share the same code to append TDs
 831  * to a (possibly active) QH, and the same QH scanning code.
 832  */
 833 static int ehci_urb_enqueue (
 834         struct usb_hcd  *hcd,
 835         struct urb      *urb,
 836         gfp_t           mem_flags
 837 ) {
 838         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 839         struct list_head        qtd_list;
 840
 841         INIT_LIST_HEAD (&qtd_list);
 842
 843         switch (usb_pipetype (urb->pipe)) {
 844         case PIPE_CONTROL:
 845                 /* qh_completions() code doesn't handle all the fault cases
 846                  * in multi-TD control transfers.  Even 1KB is rare anyway.
 847                  */
 848                 if (urb->transfer_buffer_length > (16 * 1024))
 849                         return -EMSGSIZE;
 850                 /* FALLTHROUGH */
 851         /* case PIPE_BULK: */
 852         default:
 853                 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
 854                         return -ENOMEM;
 855                 return submit_async(ehci, urb, &qtd_list, mem_flags);
 856
 857         case PIPE_INTERRUPT:
 858                 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
 859                         return -ENOMEM;
 860                 return intr_submit(ehci, urb, &qtd_list, mem_flags);
 861
 862         case PIPE_ISOCHRONOUS:
 863                 if (urb->dev->speed == USB_SPEED_HIGH)
 864                         return itd_submit (ehci, urb, mem_flags);
 865                 else
 866                         return sitd_submit (ehci, urb, mem_flags);
 867         }
 868 }
 869
 870 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
 871 {
 872         /* failfast */
 873         if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
 874                 end_unlink_async(ehci);
 875
 876         /* If the QH isn't linked then there's nothing we can do
 877          * unless we were called during a giveback, in which case
 878          * qh_completions() has to deal with it.
 879          */
 880         if (qh->qh_state != QH_STATE_LINKED) {
 881                 if (qh->qh_state == QH_STATE_COMPLETING)
 882                         qh->needs_rescan = 1;
 883                 return;
 884         }
 885
 886         /* defer till later if busy */
 887         if (ehci->reclaim) {
 888                 struct ehci_qh          *last;
 889
 890                 for (last = ehci->reclaim;
 891                                 last->reclaim;
 892                                 last = last->reclaim)
 893                         continue;
 894                 qh->qh_state = QH_STATE_UNLINK_WAIT;
 895                 last->reclaim = qh;
 896
 897         /* start IAA cycle */
 898         } else
 899                 start_unlink_async (ehci, qh);
 900 }
 901
 902 /* remove from hardware lists
 903  * completions normally happen asynchronously
 904  */
 905
 906 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 907 {
 908         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 909         struct ehci_qh          *qh;
 910         unsigned long           flags;
 911         int                     rc;
 912
 913         spin_lock_irqsave (&ehci->lock, flags);
 914         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 915         if (rc)
 916                 goto done;
 917
 918         switch (usb_pipetype (urb->pipe)) {
 919         // case PIPE_CONTROL:
 920         // case PIPE_BULK:
 921         default:
 922                 qh = (struct ehci_qh *) urb->hcpriv;
 923                 if (!qh)
 924                         break;
 925                 switch (qh->qh_state) {
 926                 case QH_STATE_LINKED:
 927                 case QH_STATE_COMPLETING:
 928                         unlink_async(ehci, qh);
 929                         break;
 930                 case QH_STATE_UNLINK:
 931                 case QH_STATE_UNLINK_WAIT:
 932                         /* already started */
 933                         break;
 934                 case QH_STATE_IDLE:
 935                         /* QH might be waiting for a Clear-TT-Buffer */
 936                         qh_completions(ehci, qh);
 937                         break;
 938                 }
 939                 break;
 940
 941         case PIPE_INTERRUPT:
 942                 qh = (struct ehci_qh *) urb->hcpriv;
 943                 if (!qh)
 944                         break;
 945                 switch (qh->qh_state) {
 946                 case QH_STATE_LINKED:
 947                 case QH_STATE_COMPLETING:
 948                         intr_deschedule (ehci, qh);
 949                         break;
 950                 case QH_STATE_IDLE:
 951                         qh_completions (ehci, qh);
 952                         break;
 953                 default:
 954                         ehci_dbg (ehci, "bogus qh %p state %d\n",
 955                                         qh, qh->qh_state);
 956                         goto done;
 957                 }
 958                 break;
 959
 960         case PIPE_ISOCHRONOUS:
 961                 // itd or sitd ...
 962
 963                 // wait till next completion, do it then.
 964                 // completion irqs can wait up to 1024 msec,
 965                 break;
 966         }
 967 done:
 968         spin_unlock_irqrestore (&ehci->lock, flags);
 969         return rc;
 970 }
 971
 972 /*-------------------------------------------------------------------------*/
 973
 974 // bulk qh holds the data toggle
 975
 976 static void
 977 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 978 {
 979         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
 980         unsigned long           flags;
 981         struct ehci_qh          *qh, *tmp;
 982
 983         /* ASSERT:  any requests/urbs are being unlinked */
 984         /* ASSERT:  nobody can be submitting urbs for this any more */
 985
 986 rescan:
 987         spin_lock_irqsave (&ehci->lock, flags);
 988         qh = ep->hcpriv;
 989         if (!qh)
 990                 goto done;
 991
 992         /* endpoints can be iso streams.  for now, we don't
 993          * accelerate iso completions ... so spin a while.
 994          */
 995         if (qh->hw->hw_info1 == 0) {
 996                 ehci_vdbg (ehci, "iso delay\n");
 997                 goto idle_timeout;
 998         }
 999
1000         if (!HC_IS_RUNNING (hcd->state))
1001                 qh->qh_state = QH_STATE_IDLE;
1002         switch (qh->qh_state) {
1003         case QH_STATE_LINKED:
1004         case QH_STATE_COMPLETING:
1005                 for (tmp = ehci->async->qh_next.qh;
1006                                 tmp && tmp != qh;
1007                                 tmp = tmp->qh_next.qh)
1008                         continue;
1009                 /* periodic qh self-unlinks on empty */
1010                 if (!tmp)
1011                         goto nogood;
1012                 unlink_async (ehci, qh);
1013                 /* FALL THROUGH */
1014         case QH_STATE_UNLINK:           /* wait for hw to finish? */
1015         case QH_STATE_UNLINK_WAIT:
1016 idle_timeout:
1017                 spin_unlock_irqrestore (&ehci->lock, flags);
1018                 schedule_timeout_uninterruptible(1);
1019                 goto rescan;
1020         case QH_STATE_IDLE:             /* fully unlinked */
1021                 if (qh->clearing_tt)
1022                         goto idle_timeout;
1023                 if (list_empty (&qh->qtd_list)) {
1024                         qh_put (qh);
1025                         break;
1026                 }
1027                 /* else FALL THROUGH */
1028         default:
1029 nogood:
1030                 /* caller was supposed to have unlinked any requests;
1031                  * that's not our job.  just leak this memory.
1032                  */
1033                 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1034                         qh, ep->desc.bEndpointAddress, qh->qh_state,
1035                         list_empty (&qh->qtd_list) ? "" : "(has tds)");
1036                 break;
1037         }
1038         ep->hcpriv = NULL;
1039 done:
1040         spin_unlock_irqrestore (&ehci->lock, flags);
1041         return;
1042 }
1043
1044 static void
1045 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1046 {
1047         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
1048         struct ehci_qh          *qh;
1049         int                     eptype = usb_endpoint_type(&ep->desc);
1050         int                     epnum = usb_endpoint_num(&ep->desc);
1051         int                     is_out = usb_endpoint_dir_out(&ep->desc);
1052         unsigned long           flags;
1053
1054         if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1055                 return;
1056
1057         spin_lock_irqsave(&ehci->lock, flags);
1058         qh = ep->hcpriv;
1059
1060         /* For Bulk and Interrupt endpoints we maintain the toggle state
1061          * in the hardware; the toggle bits in udev aren't used at all.
1062          * When an endpoint is reset by usb_clear_halt() we must reset
1063          * the toggle bit in the QH.
1064          */
1065         if (qh) {
1066                 usb_settoggle(qh->dev, epnum, is_out, 0);
1067                 if (!list_empty(&qh->qtd_list)) {
1068                         WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1069                 } else if (qh->qh_state == QH_STATE_LINKED ||
1070                                 qh->qh_state == QH_STATE_COMPLETING) {
1071
1072                         /* The toggle value in the QH can't be updated
1073                          * while the QH is active.  Unlink it now;
1074                          * re-linking will call qh_refresh().
1075                          */
1076                         if (eptype == USB_ENDPOINT_XFER_BULK)
1077                                 unlink_async(ehci, qh);
1078                         else
1079                                 intr_deschedule(ehci, qh);
1080                 }
1081         }
1082         spin_unlock_irqrestore(&ehci->lock, flags);
1083 }
1084
1085 static int ehci_get_frame (struct usb_hcd *hcd)
1086 {
1087         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
1088         return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1089                 ehci->periodic_size;
1090 }
1091
1092 /*-------------------------------------------------------------------------*/
1093
1094 MODULE_DESCRIPTION(DRIVER_DESC);
1095 MODULE_AUTHOR (DRIVER_AUTHOR);
1096 MODULE_LICENSE ("GPL");
1097
1098 #ifdef CONFIG_PCI
1099 #include "ehci-pci.c"
1100 #define PCI_DRIVER              ehci_pci_driver
1101 #endif
1102
1103 #ifdef CONFIG_USB_EHCI_FSL
1104 #include "ehci-fsl.c"
1105 #define PLATFORM_DRIVER         ehci_fsl_driver
1106 #endif
1107
1108 #ifdef CONFIG_SOC_AU1200
1109 #include "ehci-au1xxx.c"
1110 #define PLATFORM_DRIVER         ehci_hcd_au1xxx_driver
1111 #endif
1112
1113 #ifdef CONFIG_ARCH_OMAP34XX
1114 #include "ehci-omap.c"
1115 #define        PLATFORM_DRIVER         ehci_hcd_omap_driver
1116 #endif
1117
1118 #ifdef CONFIG_PPC_PS3
1119 #include "ehci-ps3.c"
1120 #define PS3_SYSTEM_BUS_DRIVER   ps3_ehci_driver
1121 #endif
1122
1123 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1124 #include "ehci-ppc-of.c"
1125 #define OF_PLATFORM_DRIVER      ehci_hcd_ppc_of_driver
1126 #endif
1127
1128 #ifdef CONFIG_XPS_USB_HCD_XILINX
1129 #include "ehci-xilinx-of.c"
1130 #define OF_PLATFORM_DRIVER      ehci_hcd_xilinx_of_driver
1131 #endif
1132
1133 #ifdef CONFIG_PLAT_ORION
1134 #include "ehci-orion.c"
1135 #define PLATFORM_DRIVER         ehci_orion_driver
1136 #endif
1137
1138 #ifdef CONFIG_ARCH_IXP4XX
1139 #include "ehci-ixp4xx.c"
1140 #define PLATFORM_DRIVER         ixp4xx_ehci_driver
1141 #endif
1142
1143 #ifdef CONFIG_USB_W90X900_EHCI
1144 #include "ehci-w90x900.c"
1145 #define PLATFORM_DRIVER         ehci_hcd_w90x900_driver
1146 #endif
1147
1148 #ifdef CONFIG_ARCH_AT91
1149 #include "ehci-atmel.c"
1150 #define PLATFORM_DRIVER         ehci_atmel_driver
1151 #endif
1152
1153 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1154     !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
1155 #error "missing bus glue for ehci-hcd"
1156 #endif
1157
1158 static int __init ehci_hcd_init(void)
1159 {
1160         int retval = 0;
1161
1162         if (usb_disabled())
1163                 return -ENODEV;
1164
1165         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1166         set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1167         if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1168                         test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1169                 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1170                                 " before uhci_hcd and ohci_hcd, not after\n");
1171
1172         pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1173                  hcd_name,
1174                  sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1175                  sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1176
1177 #ifdef DEBUG
1178         ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1179         if (!ehci_debug_root) {
1180                 retval = -ENOENT;
1181                 goto err_debug;
1182         }
1183 #endif
1184
1185 #ifdef PLATFORM_DRIVER
1186         retval = platform_driver_register(&PLATFORM_DRIVER);
1187         if (retval < 0)
1188                 goto clean0;
1189 #endif
1190
1191 #ifdef PCI_DRIVER
1192         retval = pci_register_driver(&PCI_DRIVER);
1193         if (retval < 0)
1194                 goto clean1;
1195 #endif
1196
1197 #ifdef PS3_SYSTEM_BUS_DRIVER
1198         retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1199         if (retval < 0)
1200                 goto clean2;
1201 #endif
1202
1203 #ifdef OF_PLATFORM_DRIVER
1204         retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1205         if (retval < 0)
1206                 goto clean3;
1207 #endif
1208         return retval;
1209
1210 #ifdef OF_PLATFORM_DRIVER
1211         /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
1212 clean3:
1213 #endif
1214 #ifdef PS3_SYSTEM_BUS_DRIVER
1215         ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1216 clean2:
1217 #endif
1218 #ifdef PCI_DRIVER
1219         pci_unregister_driver(&PCI_DRIVER);
1220 clean1:
1221 #endif
1222 #ifdef PLATFORM_DRIVER
1223         platform_driver_unregister(&PLATFORM_DRIVER);
1224 clean0:
1225 #endif
1226 #ifdef DEBUG
1227         debugfs_remove(ehci_debug_root);
1228         ehci_debug_root = NULL;
1229 err_debug:
1230 #endif
1231         clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1232         return retval;
1233 }
1234 module_init(ehci_hcd_init);
1235
1236 static void __exit ehci_hcd_cleanup(void)
1237 {
1238 #ifdef OF_PLATFORM_DRIVER
1239         of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1240 #endif
1241 #ifdef PLATFORM_DRIVER
1242         platform_driver_unregister(&PLATFORM_DRIVER);
1243 #endif
1244 #ifdef PCI_DRIVER
1245         pci_unregister_driver(&PCI_DRIVER);
1246 #endif
1247 #ifdef PS3_SYSTEM_BUS_DRIVER
1248         ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1249 #endif
1250 #ifdef DEBUG
1251         debugfs_remove(ehci_debug_root);
1252 #endif
1253         clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1254 }
1255 module_exit(ehci_hcd_cleanup);
1256