2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 * Purpose: Implement functions to access baseband
28 * BBuGetFrameTime - Calculate data frame transmitting time
29 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
30 * BBbReadEmbeded - Embeded read baseband register via MAC
31 * BBbWriteEmbeded - Embeded write baseband register via MAC
32 * BBbIsRegBitsOn - Test if baseband register bits on
33 * BBbIsRegBitsOff - Test if baseband register bits off
34 * BBbVT3253Init - VIA VT3253 baseband chip init code
35 * BBvReadAllRegs - Read All Baseband Registers
36 * BBvLoopbackOn - Turn on BaseBand Loopback mode
37 * BBvLoopbackOff - Turn off BaseBand Loopback mode
40 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
41 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
42 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCaculateParameter().
43 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
45 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
46 * Modified BBvLoopbackOn & BBvLoopbackOff().
49 #if !defined(__TMACRO_H__)
52 #if !defined(__TBIT_H__)
55 #if !defined(__TETHER_H__)
58 #if !defined(__MAC_H__)
61 #if !defined(__BASEBAND_H__)
64 #if !defined(__SROM_H__)
67 #if !defined(__UMEM_H__)
70 #if !defined(__RF_H__)
74 /*--------------------- Static Definitions -------------------------*/
75 //static int msglevel =MSG_LEVEL_DEBUG;
76 static int msglevel =MSG_LEVEL_INFO;
80 /*--------------------- Static Classes ----------------------------*/
82 /*--------------------- Static Variables --------------------------*/
83 /*--------------------- Static Functions --------------------------*/
85 /*--------------------- Export Variables --------------------------*/
87 /*--------------------- Static Definitions -------------------------*/
89 /*--------------------- Static Classes ----------------------------*/
91 /*--------------------- Static Variables --------------------------*/
95 #define CB_VT3253_INIT_FOR_RFMD 446
96 BYTE byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
545 #define CB_VT3253B0_INIT_FOR_RFMD 256
546 BYTE byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
805 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
807 BYTE byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
1005 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
1007 BYTE byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1117 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1269 #define CB_VT3253B0_INIT_FOR_UW2451 256
1271 BYTE byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1381 {0x6c, 0x00}, //RobertYu:20050125, request by JJSue
1531 #define CB_VT3253B0_AGC 193
1533 BYTE byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1729 const WORD awcFrameTime[MAX_RATE] =
1730 {10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216};
1733 /*--------------------- Static Functions --------------------------*/
1737 s_ulGetRatio(PSDevice pDevice);
1753 //printk("Enter s_vChangeAntenna:original RxMode is %d,TxMode is %d\n",pDevice->byRxAntennaMode,pDevice->byTxAntennaMode);
1755 if ( pDevice->dwRxAntennaSel == 0) {
1756 pDevice->dwRxAntennaSel=1;
1757 if (pDevice->bTxRxAntInv == TRUE)
1758 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1760 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1762 pDevice->dwRxAntennaSel=0;
1763 if (pDevice->bTxRxAntInv == TRUE)
1764 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_B);
1766 BBvSetRxAntennaMode(pDevice->PortOffset, ANT_A);
1768 if ( pDevice->dwTxAntennaSel == 0) {
1769 pDevice->dwTxAntennaSel=1;
1770 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_B);
1772 pDevice->dwTxAntennaSel=0;
1773 BBvSetTxAntennaMode(pDevice->PortOffset, ANT_A);
1778 /*--------------------- Export Variables --------------------------*/
1780 * Description: Calculate data frame transmitting time
1784 * byPreambleType - Preamble Type
1785 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1786 * cbFrameLength - Baseband Type
1790 * Return Value: FrameTime
1795 IN BYTE byPreambleType,
1797 IN UINT cbFrameLength,
1804 UINT uRateIdx = (UINT)wRate;
1808 if (uRateIdx > RATE_54M) {
1812 uRate = (UINT)awcFrameTime[uRateIdx];
1814 if (uRateIdx <= 3) { //CCK mode
1816 if (byPreambleType == 1) {//Short
1821 uFrameTime = (cbFrameLength * 80) / uRate; //?????
1822 uTmp = (uFrameTime * uRate) / 80;
1823 if (cbFrameLength != uTmp) {
1827 return (uPreamble + uFrameTime);
1830 uFrameTime = (cbFrameLength * 8 + 22) / uRate; //????????
1831 uTmp = ((uFrameTime * uRate) - 22) / 8;
1832 if(cbFrameLength != uTmp) {
1835 uFrameTime = uFrameTime * 4; //???????
1836 if(byPktType != PK_TYPE_11A) {
1837 uFrameTime += 6; //??????
1839 return (20 + uFrameTime); //??????
1844 * Description: Caculate Length, Service, and Signal fields of Phy for Tx
1848 * pDevice - Device Structure
1849 * cbFrameLength - Tx Frame Length
1852 * pwPhyLen - pointer to Phy Length field
1853 * pbyPhySrv - pointer to Phy Service field
1854 * pbyPhySgn - pointer to Phy Signal field
1856 * Return Value: none
1860 BBvCaculateParameter (
1861 IN PSDevice pDevice,
1862 IN UINT cbFrameLength,
1864 IN BYTE byPacketType,
1866 OUT PBYTE pbyPhySrv,
1874 BYTE byPreambleType = pDevice->byPreambleType;
1875 BOOL bCCK = pDevice->bCCK;
1877 cbBitCount = cbFrameLength * 8;
1882 cbUsCount = cbBitCount;
1887 cbUsCount = cbBitCount / 2;
1888 if (byPreambleType == 1)
1890 else // long preamble
1897 cbUsCount = (cbBitCount * 10) / 55;
1898 cbTmp = (cbUsCount * 55) / 10;
1899 if (cbTmp != cbBitCount)
1901 if (byPreambleType == 1)
1903 else // long preamble
1911 cbUsCount = cbBitCount / 11;
1912 cbTmp = cbUsCount * 11;
1913 if (cbTmp != cbBitCount) {
1915 if ((cbBitCount - cbTmp) <= 3)
1918 if (byPreambleType == 1)
1920 else // long preamble
1925 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1926 *pbyPhySgn = 0x9B; //1001 1011
1929 *pbyPhySgn = 0x8B; //1000 1011
1934 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1935 *pbyPhySgn = 0x9F; //1001 1111
1938 *pbyPhySgn = 0x8F; //1000 1111
1943 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1944 *pbyPhySgn = 0x9A; //1001 1010
1947 *pbyPhySgn = 0x8A; //1000 1010
1952 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1953 *pbyPhySgn = 0x9E; //1001 1110
1956 *pbyPhySgn = 0x8E; //1000 1110
1961 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1962 *pbyPhySgn = 0x99; //1001 1001
1965 *pbyPhySgn = 0x89; //1000 1001
1970 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1971 *pbyPhySgn = 0x9D; //1001 1101
1974 *pbyPhySgn = 0x8D; //1000 1101
1979 if(byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1980 *pbyPhySgn = 0x98; //1001 1000
1983 *pbyPhySgn = 0x88; //1000 1000
1988 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1989 *pbyPhySgn = 0x9C; //1001 1100
1992 *pbyPhySgn = 0x8C; //1000 1100
1997 if (byPacketType == PK_TYPE_11A) {//11a, 5GHZ
1998 *pbyPhySgn = 0x9C; //1001 1100
2001 *pbyPhySgn = 0x8C; //1000 1100
2006 if (byPacketType == PK_TYPE_11B) {
2009 *pbyPhySrv = *pbyPhySrv | 0x80;
2010 *pwPhyLen = (WORD)cbUsCount;
2014 *pwPhyLen = (WORD)cbFrameLength;
2019 * Description: Read a byte from BASEBAND, by embeded programming
2023 * dwIoBase - I/O base address
2024 * byBBAddr - address of register in Baseband
2026 * pbyData - data read
2028 * Return Value: TRUE if succeeded; FALSE if failed.
2031 BOOL BBbReadEmbeded (DWORD_PTR dwIoBase, BYTE byBBAddr, PBYTE pbyData)
2037 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2040 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
2041 // W_MAX_TIMEOUT is the timeout period
2042 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2043 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2044 if (BITbIsBitOn(byValue, BBREGCTL_DONE))
2049 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
2051 if (ww == W_MAX_TIMEOUT) {
2053 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x30)\n");
2061 * Description: Write a Byte to BASEBAND, by embeded programming
2065 * dwIoBase - I/O base address
2066 * byBBAddr - address of register in Baseband
2067 * byData - data to write
2071 * Return Value: TRUE if succeeded; FALSE if failed.
2074 BOOL BBbWriteEmbeded (DWORD_PTR dwIoBase, BYTE byBBAddr, BYTE byData)
2080 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2082 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2084 // turn on BBREGCTL_REGW
2085 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2086 // W_MAX_TIMEOUT is the timeout period
2087 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2088 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2089 if (BITbIsBitOn(byValue, BBREGCTL_DONE))
2093 if (ww == W_MAX_TIMEOUT) {
2095 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO" DBG_PORT80(0x31)\n");
2103 * Description: Test if all bits are set for the Baseband register
2107 * dwIoBase - I/O base address
2108 * byBBAddr - address of register in Baseband
2109 * byTestBits - TestBits
2113 * Return Value: TRUE if all TestBits are set; FALSE otherwise.
2116 BOOL BBbIsRegBitsOn (DWORD_PTR dwIoBase, BYTE byBBAddr, BYTE byTestBits)
2120 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2121 return BITbIsAllBitsOn(byOrgData, byTestBits);
2126 * Description: Test if all bits are clear for the Baseband register
2130 * dwIoBase - I/O base address
2131 * byBBAddr - address of register in Baseband
2132 * byTestBits - TestBits
2136 * Return Value: TRUE if all TestBits are clear; FALSE otherwise.
2139 BOOL BBbIsRegBitsOff (DWORD_PTR dwIoBase, BYTE byBBAddr, BYTE byTestBits)
2143 BBbReadEmbeded(dwIoBase, byBBAddr, &byOrgData);
2144 return BITbIsAllBitsOff(byOrgData, byTestBits);
2148 * Description: VIA VT3253 Baseband chip init function
2152 * dwIoBase - I/O base address
2153 * byRevId - Revision ID
2154 * byRFType - RF type
2158 * Return Value: TRUE if succeeded; FALSE if failed.
2162 BOOL BBbVT3253Init (PSDevice pDevice)
2164 BOOL bResult = TRUE;
2166 DWORD_PTR dwIoBase = pDevice->PortOffset;
2167 BYTE byRFType = pDevice->byRFType;
2168 BYTE byLocalID = pDevice->byLocalID;
2170 if (byRFType == RF_RFMD2959) {
2171 if (byLocalID <= REV_ID_VT3253_A1) {
2172 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++) {
2173 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253InitTab_RFMD[ii][0],byVT3253InitTab_RFMD[ii][1]);
2176 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++) {
2177 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_RFMD[ii][0],byVT3253B0_RFMD[ii][1]);
2179 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++) {
2180 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC4_RFMD2959[ii][0],byVT3253B0_AGC4_RFMD2959[ii][1]);
2182 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2183 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2185 pDevice->abyBBVGA[0] = 0x18;
2186 pDevice->abyBBVGA[1] = 0x0A;
2187 pDevice->abyBBVGA[2] = 0x0;
2188 pDevice->abyBBVGA[3] = 0x0;
2189 pDevice->ldBmThreshold[0] = -70;
2190 pDevice->ldBmThreshold[1] = -50;
2191 pDevice->ldBmThreshold[2] = 0;
2192 pDevice->ldBmThreshold[3] = 0;
2193 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S) ) {
2194 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2195 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2197 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2198 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2200 pDevice->abyBBVGA[0] = 0x1C;
2201 pDevice->abyBBVGA[1] = 0x10;
2202 pDevice->abyBBVGA[2] = 0x0;
2203 pDevice->abyBBVGA[3] = 0x0;
2204 pDevice->ldBmThreshold[0] = -70;
2205 pDevice->ldBmThreshold[1] = -48;
2206 pDevice->ldBmThreshold[2] = 0;
2207 pDevice->ldBmThreshold[3] = 0;
2208 } else if (byRFType == RF_UW2451) {
2209 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2210 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2212 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2213 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2215 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2216 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0);
2218 pDevice->abyBBVGA[0] = 0x14;
2219 pDevice->abyBBVGA[1] = 0x0A;
2220 pDevice->abyBBVGA[2] = 0x0;
2221 pDevice->abyBBVGA[3] = 0x0;
2222 pDevice->ldBmThreshold[0] = -60;
2223 pDevice->ldBmThreshold[1] = -50;
2224 pDevice->ldBmThreshold[2] = 0;
2225 pDevice->ldBmThreshold[3] = 0;
2226 } else if (byRFType == RF_UW2452) {
2227 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++) {
2228 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_UW2451[ii][0],byVT3253B0_UW2451[ii][1]);
2230 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2231 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2232 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2233 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2234 // Select VC1/VC2, CR215 = 0x02->0x06
2235 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2237 //{{RobertYu:20050125, request by Jack
2238 bResult &= BBbWriteEmbeded(dwIoBase,0x90,0x20);
2239 bResult &= BBbWriteEmbeded(dwIoBase,0x97,0xeb);
2242 //{{RobertYu:20050221, request by Jack
2243 bResult &= BBbWriteEmbeded(dwIoBase,0xa6,0x00);
2244 bResult &= BBbWriteEmbeded(dwIoBase,0xa8,0x30);
2246 bResult &= BBbWriteEmbeded(dwIoBase,0xb0,0x58);
2248 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2249 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2251 //VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23); // RobertYu: 20050104, 20050131 disable PA_Delay
2252 //MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); // RobertYu: 20050104, 20050131 disable PA_Delay
2254 pDevice->abyBBVGA[0] = 0x14;
2255 pDevice->abyBBVGA[1] = 0x0A;
2256 pDevice->abyBBVGA[2] = 0x0;
2257 pDevice->abyBBVGA[3] = 0x0;
2258 pDevice->ldBmThreshold[0] = -60;
2259 pDevice->ldBmThreshold[1] = -50;
2260 pDevice->ldBmThreshold[2] = 0;
2261 pDevice->ldBmThreshold[3] = 0;
2264 } else if (byRFType == RF_VT3226) {
2265 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2266 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2268 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2269 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2271 pDevice->abyBBVGA[0] = 0x1C;
2272 pDevice->abyBBVGA[1] = 0x10;
2273 pDevice->abyBBVGA[2] = 0x0;
2274 pDevice->abyBBVGA[3] = 0x0;
2275 pDevice->ldBmThreshold[0] = -70;
2276 pDevice->ldBmThreshold[1] = -48;
2277 pDevice->ldBmThreshold[2] = 0;
2278 pDevice->ldBmThreshold[3] = 0;
2279 // Fix VT3226 DFC system timing issue
2280 MACvSetRFLE_LatchBase(dwIoBase);
2281 //{{ RobertYu: 20050104
2282 } else if (byRFType == RF_AIROHA7230) {
2283 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++) {
2284 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AIROHA2230[ii][0],byVT3253B0_AIROHA2230[ii][1]);
2287 //{{ RobertYu:20050223, request by JerryChung
2288 // Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2289 //bResult &= BBbWriteEmbeded(dwIoBase,0x09,0x41);
2290 // Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2291 //bResult &= BBbWriteEmbeded(dwIoBase,0x0a,0x28);
2292 // Select VC1/VC2, CR215 = 0x02->0x06
2293 bResult &= BBbWriteEmbeded(dwIoBase,0xd7,0x06);
2296 for (ii = 0; ii < CB_VT3253B0_AGC; ii++) {
2297 bResult &= BBbWriteEmbeded(dwIoBase,byVT3253B0_AGC[ii][0],byVT3253B0_AGC[ii][1]);
2299 pDevice->abyBBVGA[0] = 0x1C;
2300 pDevice->abyBBVGA[1] = 0x10;
2301 pDevice->abyBBVGA[2] = 0x0;
2302 pDevice->abyBBVGA[3] = 0x0;
2303 pDevice->ldBmThreshold[0] = -70;
2304 pDevice->ldBmThreshold[1] = -48;
2305 pDevice->ldBmThreshold[2] = 0;
2306 pDevice->ldBmThreshold[3] = 0;
2310 pDevice->bUpdateBBVGA = FALSE;
2311 pDevice->abyBBVGA[0] = 0x1C;
2314 if (byLocalID > REV_ID_VT3253_A1) {
2315 BBbWriteEmbeded(dwIoBase, 0x04, 0x7F);
2316 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);
2325 * Description: Read All Baseband Registers
2329 * dwIoBase - I/O base address
2330 * pbyBBRegs - Point to struct that stores Baseband Registers
2334 * Return Value: none
2337 VOID BBvReadAllRegs (DWORD_PTR dwIoBase, PBYTE pbyBBRegs)
2341 for (ii = 0; ii < BB_MAX_CONTEXT_SIZE; ii++) {
2342 BBbReadEmbeded(dwIoBase, (BYTE)(ii*byBase), pbyBBRegs);
2343 pbyBBRegs += byBase;
2348 * Description: Turn on BaseBand Loopback mode
2352 * dwIoBase - I/O base address
2353 * bCCK - If CCK is set
2357 * Return Value: none
2362 void BBvLoopbackOn (PSDevice pDevice)
2365 DWORD_PTR dwIoBase = pDevice->PortOffset;
2368 BBbReadEmbeded(dwIoBase, 0xC9, &pDevice->byBBCRc9);//CR201
2369 BBbWriteEmbeded(dwIoBase, 0xC9, 0);
2370 BBbReadEmbeded(dwIoBase, 0x4D, &pDevice->byBBCR4d);//CR77
2371 BBbWriteEmbeded(dwIoBase, 0x4D, 0x90);
2373 //CR 88 = 0x02(CCK), 0x03(OFDM)
2374 BBbReadEmbeded(dwIoBase, 0x88, &pDevice->byBBCR88);//CR136
2376 if (pDevice->uConnectionRate <= RATE_11M) { //CCK
2377 // Enable internal digital loopback: CR33 |= 0000 0001
2378 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2379 BBbWriteEmbeded(dwIoBase, 0x21, (BYTE)(byData | 0x01));//CR33
2381 BBbWriteEmbeded(dwIoBase, 0x9A, 0); //CR154
2383 BBbWriteEmbeded(dwIoBase, 0x88, 0x02);//CR239
2386 // Enable internal digital loopback:CR154 |= 0000 0001
2387 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2388 BBbWriteEmbeded(dwIoBase, 0x9A, (BYTE)(byData | 0x01));//CR154
2390 BBbWriteEmbeded(dwIoBase, 0x21, 0); //CR33
2392 BBbWriteEmbeded(dwIoBase, 0x88, 0x03);//CR239
2396 BBbWriteEmbeded(dwIoBase, 0x0E, 0);//CR14
2399 BBbReadEmbeded(pDevice->PortOffset, 0x09, &pDevice->byBBCR09);
2400 BBbWriteEmbeded(pDevice->PortOffset, 0x09, (BYTE)(pDevice->byBBCR09 & 0xDE));
2404 * Description: Turn off BaseBand Loopback mode
2408 * pDevice - Device Structure
2413 * Return Value: none
2416 void BBvLoopbackOff (PSDevice pDevice)
2419 DWORD_PTR dwIoBase = pDevice->PortOffset;
2421 BBbWriteEmbeded(dwIoBase, 0xC9, pDevice->byBBCRc9);//CR201
2422 BBbWriteEmbeded(dwIoBase, 0x88, pDevice->byBBCR88);//CR136
2423 BBbWriteEmbeded(dwIoBase, 0x09, pDevice->byBBCR09);//CR136
2424 BBbWriteEmbeded(dwIoBase, 0x4D, pDevice->byBBCR4d);//CR77
2426 if (pDevice->uConnectionRate <= RATE_11M) { // CCK
2427 // Set the CR33 Bit2 to disable internal Loopback.
2428 BBbReadEmbeded(dwIoBase, 0x21, &byData);//CR33
2429 BBbWriteEmbeded(dwIoBase, 0x21, (BYTE)(byData & 0xFE));//CR33
2432 BBbReadEmbeded(dwIoBase, 0x9A, &byData);//CR154
2433 BBbWriteEmbeded(dwIoBase, 0x9A, (BYTE)(byData & 0xFE));//CR154
2435 BBbReadEmbeded(dwIoBase, 0x0E, &byData);//CR14
2436 BBbWriteEmbeded(dwIoBase, 0x0E, (BYTE)(byData | 0x80));//CR14
2443 * Description: Set ShortSlotTime mode
2447 * pDevice - Device Structure
2451 * Return Value: none
2455 BBvSetShortSlotTime (PSDevice pDevice)
2460 BBbReadEmbeded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2462 if (pDevice->bShortSlotTime) {
2463 byBBRxConf &= 0xDF;//1101 1111
2465 byBBRxConf |= 0x20;//0010 0000
2468 // patch for 3253B0 Baseband with Cardbus module
2469 BBbReadEmbeded(pDevice->PortOffset, 0xE7, &byBBVGA);
2470 if (byBBVGA == pDevice->abyBBVGA[0]) {
2471 byBBRxConf |= 0x20;//0010 0000
2474 BBbWriteEmbeded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2478 VOID BBvSetVGAGainOffset(PSDevice pDevice, BYTE byData)
2482 BBbWriteEmbeded(pDevice->PortOffset, 0xE7, byData);
2484 BBbReadEmbeded(pDevice->PortOffset, 0x0A, &byBBRxConf);//CR10
2485 // patch for 3253B0 Baseband with Cardbus module
2486 if (byData == pDevice->abyBBVGA[0]) {
2487 byBBRxConf |= 0x20;//0010 0000
2488 } else if (pDevice->bShortSlotTime) {
2489 byBBRxConf &= 0xDF;//1101 1111
2491 byBBRxConf |= 0x20;//0010 0000
2493 pDevice->byBBVGACurrent = byData;
2494 BBbWriteEmbeded(pDevice->PortOffset, 0x0A, byBBRxConf);//CR10
2499 * Description: Baseband SoftwareReset
2503 * dwIoBase - I/O base address
2507 * Return Value: none
2511 BBvSoftwareReset (DWORD_PTR dwIoBase)
2513 BBbWriteEmbeded(dwIoBase, 0x50, 0x40);
2514 BBbWriteEmbeded(dwIoBase, 0x50, 0);
2515 BBbWriteEmbeded(dwIoBase, 0x9C, 0x01);
2516 BBbWriteEmbeded(dwIoBase, 0x9C, 0);
2520 * Description: Baseband Power Save Mode ON
2524 * dwIoBase - I/O base address
2528 * Return Value: none
2532 BBvPowerSaveModeON (DWORD_PTR dwIoBase)
2536 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2538 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2542 * Description: Baseband Power Save Mode OFF
2546 * dwIoBase - I/O base address
2550 * Return Value: none
2554 BBvPowerSaveModeOFF (DWORD_PTR dwIoBase)
2558 BBbReadEmbeded(dwIoBase, 0x0D, &byOrgData);
2559 byOrgData &= ~(BIT0);
2560 BBbWriteEmbeded(dwIoBase, 0x0D, byOrgData);
2564 * Description: Set Tx Antenna mode
2568 * pDevice - Device Structure
2569 * byAntennaMode - Antenna Mode
2573 * Return Value: none
2578 BBvSetTxAntennaMode (DWORD_PTR dwIoBase, BYTE byAntennaMode)
2583 //printk("Enter BBvSetTxAntennaMode\n");
2585 BBbReadEmbeded(dwIoBase, 0x09, &byBBTxConf);//CR09
2586 if (byAntennaMode == ANT_DIVERSITY) {
2587 // bit 1 is diversity
2589 } else if (byAntennaMode == ANT_A) {
2591 byBBTxConf &= 0xF9; // 1111 1001
2592 } else if (byAntennaMode == ANT_B) {
2594 //printk("BBvSetTxAntennaMode:ANT_B\n");
2596 byBBTxConf &= 0xFD; // 1111 1101
2599 BBbWriteEmbeded(dwIoBase, 0x09, byBBTxConf);//CR09
2606 * Description: Set Rx Antenna mode
2610 * pDevice - Device Structure
2611 * byAntennaMode - Antenna Mode
2615 * Return Value: none
2620 BBvSetRxAntennaMode (DWORD_PTR dwIoBase, BYTE byAntennaMode)
2624 BBbReadEmbeded(dwIoBase, 0x0A, &byBBRxConf);//CR10
2625 if (byAntennaMode == ANT_DIVERSITY) {
2628 } else if (byAntennaMode == ANT_A) {
2629 byBBRxConf &= 0xFC; // 1111 1100
2630 } else if (byAntennaMode == ANT_B) {
2631 byBBRxConf &= 0xFE; // 1111 1110
2634 BBbWriteEmbeded(dwIoBase, 0x0A, byBBRxConf);//CR10
2639 * Description: BBvSetDeepSleep
2643 * pDevice - Device Structure
2647 * Return Value: none
2651 BBvSetDeepSleep (DWORD_PTR dwIoBase, BYTE byLocalID)
2653 BBbWriteEmbeded(dwIoBase, 0x0C, 0x17);//CR12
2654 BBbWriteEmbeded(dwIoBase, 0x0D, 0xB9);//CR13
2658 BBvExitDeepSleep (DWORD_PTR dwIoBase, BYTE byLocalID)
2660 BBbWriteEmbeded(dwIoBase, 0x0C, 0x00);//CR12
2661 BBbWriteEmbeded(dwIoBase, 0x0D, 0x01);//CR13
2668 s_ulGetRatio (PSDevice pDevice)
2674 //This is a thousand-ratio
2675 ulMaxPacket = pDevice->uNumSQ3[RATE_54M];
2676 if ( pDevice->uNumSQ3[RATE_54M] != 0 ) {
2677 ulPacketNum = pDevice->uNumSQ3[RATE_54M];
2678 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2679 //ulRatio = (pDevice->uNumSQ3[RATE_54M] * 1000 / pDevice->uDiversityCnt);
2680 ulRatio += TOP_RATE_54M;
2682 if ( pDevice->uNumSQ3[RATE_48M] > ulMaxPacket ) {
2683 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M];
2684 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2685 //ulRatio = (pDevice->uNumSQ3[RATE_48M] * 1000 / pDevice->uDiversityCnt);
2686 ulRatio += TOP_RATE_48M;
2687 ulMaxPacket = pDevice->uNumSQ3[RATE_48M];
2689 if ( pDevice->uNumSQ3[RATE_36M] > ulMaxPacket ) {
2690 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2691 pDevice->uNumSQ3[RATE_36M];
2692 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2693 //ulRatio = (pDevice->uNumSQ3[RATE_36M] * 1000 / pDevice->uDiversityCnt);
2694 ulRatio += TOP_RATE_36M;
2695 ulMaxPacket = pDevice->uNumSQ3[RATE_36M];
2697 if ( pDevice->uNumSQ3[RATE_24M] > ulMaxPacket ) {
2698 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2699 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M];
2700 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2701 //ulRatio = (pDevice->uNumSQ3[RATE_24M] * 1000 / pDevice->uDiversityCnt);
2702 ulRatio += TOP_RATE_24M;
2703 ulMaxPacket = pDevice->uNumSQ3[RATE_24M];
2705 if ( pDevice->uNumSQ3[RATE_18M] > ulMaxPacket ) {
2706 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2707 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2708 pDevice->uNumSQ3[RATE_18M];
2709 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2710 //ulRatio = (pDevice->uNumSQ3[RATE_18M] * 1000 / pDevice->uDiversityCnt);
2711 ulRatio += TOP_RATE_18M;
2712 ulMaxPacket = pDevice->uNumSQ3[RATE_18M];
2714 if ( pDevice->uNumSQ3[RATE_12M] > ulMaxPacket ) {
2715 ulPacketNum = pDevice->uNumSQ3[RATE_54M] + pDevice->uNumSQ3[RATE_48M] +
2716 pDevice->uNumSQ3[RATE_36M] + pDevice->uNumSQ3[RATE_24M] +
2717 pDevice->uNumSQ3[RATE_18M] + pDevice->uNumSQ3[RATE_12M];
2718 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2719 //ulRatio = (pDevice->uNumSQ3[RATE_12M] * 1000 / pDevice->uDiversityCnt);
2720 ulRatio += TOP_RATE_12M;
2721 ulMaxPacket = pDevice->uNumSQ3[RATE_12M];
2723 if ( pDevice->uNumSQ3[RATE_11M] > ulMaxPacket ) {
2724 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2725 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2726 pDevice->uNumSQ3[RATE_6M] - pDevice->uNumSQ3[RATE_9M];
2727 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2728 //ulRatio = (pDevice->uNumSQ3[RATE_11M] * 1000 / pDevice->uDiversityCnt);
2729 ulRatio += TOP_RATE_11M;
2730 ulMaxPacket = pDevice->uNumSQ3[RATE_11M];
2732 if ( pDevice->uNumSQ3[RATE_9M] > ulMaxPacket ) {
2733 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2734 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M] -
2735 pDevice->uNumSQ3[RATE_6M];
2736 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2737 //ulRatio = (pDevice->uNumSQ3[RATE_9M] * 1000 / pDevice->uDiversityCnt);
2738 ulRatio += TOP_RATE_9M;
2739 ulMaxPacket = pDevice->uNumSQ3[RATE_9M];
2741 if ( pDevice->uNumSQ3[RATE_6M] > ulMaxPacket ) {
2742 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2743 pDevice->uNumSQ3[RATE_2M] - pDevice->uNumSQ3[RATE_5M];
2744 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2745 //ulRatio = (pDevice->uNumSQ3[RATE_6M] * 1000 / pDevice->uDiversityCnt);
2746 ulRatio += TOP_RATE_6M;
2747 ulMaxPacket = pDevice->uNumSQ3[RATE_6M];
2749 if ( pDevice->uNumSQ3[RATE_5M] > ulMaxPacket ) {
2750 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M] -
2751 pDevice->uNumSQ3[RATE_2M];
2752 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2753 //ulRatio = (pDevice->uNumSQ3[RATE_5M] * 1000 / pDevice->uDiversityCnt);
2754 ulRatio += TOP_RATE_55M;
2755 ulMaxPacket = pDevice->uNumSQ3[RATE_5M];
2757 if ( pDevice->uNumSQ3[RATE_2M] > ulMaxPacket ) {
2758 ulPacketNum = pDevice->uDiversityCnt - pDevice->uNumSQ3[RATE_1M];
2759 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2760 //ulRatio = (pDevice->uNumSQ3[RATE_2M] * 1000 / pDevice->uDiversityCnt);
2761 ulRatio += TOP_RATE_2M;
2762 ulMaxPacket = pDevice->uNumSQ3[RATE_2M];
2764 if ( pDevice->uNumSQ3[RATE_1M] > ulMaxPacket ) {
2765 ulPacketNum = pDevice->uDiversityCnt;
2766 ulRatio = (ulPacketNum * 1000 / pDevice->uDiversityCnt);
2767 //ulRatio = (pDevice->uNumSQ3[RATE_1M] * 1000 / pDevice->uDiversityCnt);
2768 ulRatio += TOP_RATE_1M;
2776 BBvClearAntDivSQ3Value (PSDevice pDevice)
2780 pDevice->uDiversityCnt = 0;
2781 for (ii = 0; ii < MAX_RATE; ii++) {
2782 pDevice->uNumSQ3[ii] = 0;
2788 * Description: Antenna Diversity
2792 * pDevice - Device Structure
2793 * byRSR - RSR from received packet
2794 * bySQ3 - SQ3 value from received packet
2798 * Return Value: none
2803 BBvAntennaDiversity (PSDevice pDevice, BYTE byRxRate, BYTE bySQ3)
2806 if ((byRxRate >= MAX_RATE) || (pDevice->wAntDiversityMaxRate >= MAX_RATE)) {
2809 pDevice->uDiversityCnt++;
2810 // DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO "pDevice->uDiversityCnt = %d\n", (int)pDevice->uDiversityCnt);
2812 pDevice->uNumSQ3[byRxRate]++;
2814 if (pDevice->byAntennaState == 0) {
2816 if (pDevice->uDiversityCnt > pDevice->ulDiversityNValue) {
2817 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"ulDiversityNValue=[%d],54M-[%d]\n",
2818 (int)pDevice->ulDiversityNValue, (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate]);
2820 if (pDevice->uNumSQ3[pDevice->wAntDiversityMaxRate] < pDevice->uDiversityCnt/2) {
2822 pDevice->ulRatio_State0 = s_ulGetRatio(pDevice);
2823 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State0, rate = [%08x]\n", (int)pDevice->ulRatio_State0);
2825 if ( pDevice->byTMax == 0 )
2827 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"1.[%08x], uNumSQ3[%d]=%d, %d\n",
2828 (int)pDevice->ulRatio_State0, (int)pDevice->wAntDiversityMaxRate,
2829 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2831 //printk("BBvAntennaDiversity1:call s_vChangeAntenna\n");
2833 s_vChangeAntenna(pDevice);
2834 pDevice->byAntennaState = 1;
2835 del_timer(&pDevice->TimerSQ3Tmax3);
2836 del_timer(&pDevice->TimerSQ3Tmax2);
2837 pDevice->TimerSQ3Tmax1.expires = RUN_AT(pDevice->byTMax * HZ);
2838 add_timer(&pDevice->TimerSQ3Tmax1);
2842 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2843 add_timer(&pDevice->TimerSQ3Tmax3);
2845 BBvClearAntDivSQ3Value(pDevice);
2848 } else { //byAntennaState == 1
2850 if (pDevice->uDiversityCnt > pDevice->ulDiversityMValue) {
2852 del_timer(&pDevice->TimerSQ3Tmax1);
2854 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2855 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2856 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2858 if (pDevice->ulRatio_State1 < pDevice->ulRatio_State0) {
2859 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2860 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2861 (int)pDevice->wAntDiversityMaxRate,
2862 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2864 //printk("BBvAntennaDiversity2:call s_vChangeAntenna\n");
2866 s_vChangeAntenna(pDevice);
2867 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2868 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2869 add_timer(&pDevice->TimerSQ3Tmax3);
2870 add_timer(&pDevice->TimerSQ3Tmax2);
2872 pDevice->byAntennaState = 0;
2873 BBvClearAntDivSQ3Value(pDevice);
2881 * Timer for SQ3 antenna diversity
2888 * Return Value: none
2894 IN HANDLE hDeviceContext
2897 PSDevice pDevice = (PSDevice)hDeviceContext;
2899 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerSQ3CallBack...");
2902 spin_lock_irq(&pDevice->lock);
2904 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"3.[%08x][%08x], %d\n",(int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1, (int)pDevice->uDiversityCnt);
2906 //printk("TimerSQ3CallBack1:call s_vChangeAntenna\n");
2909 s_vChangeAntenna(pDevice);
2910 pDevice->byAntennaState = 0;
2911 BBvClearAntDivSQ3Value(pDevice);
2913 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2914 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2915 add_timer(&pDevice->TimerSQ3Tmax3);
2916 add_timer(&pDevice->TimerSQ3Tmax2);
2918 spin_unlock_irq(&pDevice->lock);
2927 * Timer for SQ3 antenna diversity
2932 * hDeviceContext - Pointer to the adapter
2938 * Return Value: none
2943 TimerState1CallBack (
2944 IN HANDLE hDeviceContext
2947 PSDevice pDevice = (PSDevice)hDeviceContext;
2949 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"TimerState1CallBack...");
2951 spin_lock_irq(&pDevice->lock);
2952 if (pDevice->uDiversityCnt < pDevice->ulDiversityMValue/100) {
2954 //printk("TimerSQ3CallBack2:call s_vChangeAntenna\n");
2957 s_vChangeAntenna(pDevice);
2958 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2959 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2960 add_timer(&pDevice->TimerSQ3Tmax3);
2961 add_timer(&pDevice->TimerSQ3Tmax2);
2963 pDevice->ulRatio_State1 = s_ulGetRatio(pDevice);
2964 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2965 (int)pDevice->ulRatio_State0,(int)pDevice->ulRatio_State1);
2967 if ( pDevice->ulRatio_State1 < pDevice->ulRatio_State0 ) {
2968 DEVICE_PRT(MSG_LEVEL_DEBUG, KERN_INFO"2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2969 (int)pDevice->ulRatio_State0, (int)pDevice->ulRatio_State1,
2970 (int)pDevice->wAntDiversityMaxRate,
2971 (int)pDevice->uNumSQ3[(int)pDevice->wAntDiversityMaxRate], (int)pDevice->uDiversityCnt);
2973 //printk("TimerSQ3CallBack3:call s_vChangeAntenna\n");
2976 s_vChangeAntenna(pDevice);
2978 pDevice->TimerSQ3Tmax3.expires = RUN_AT(pDevice->byTMax3 * HZ);
2979 pDevice->TimerSQ3Tmax2.expires = RUN_AT(pDevice->byTMax2 * HZ);
2980 add_timer(&pDevice->TimerSQ3Tmax3);
2981 add_timer(&pDevice->TimerSQ3Tmax2);
2984 pDevice->byAntennaState = 0;
2985 BBvClearAntDivSQ3Value(pDevice);
2986 spin_unlock_irq(&pDevice->lock);