2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/proc_fs.h>
22 #include <linux/pci.h>
23 #include <linux/poll.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
34 #include "../vme_bridge.h"
35 #include "vme_tsi148.h"
37 static int __init tsi148_init(void);
38 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39 static void tsi148_remove(struct pci_dev *);
40 static void __exit tsi148_exit(void);
43 /* Module parameter */
47 static char driver_name[] = "vme_tsi148";
49 static const struct pci_device_id tsi148_ids[] = {
50 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
54 static struct pci_driver tsi148_driver = {
56 .id_table = tsi148_ids,
57 .probe = tsi148_probe,
58 .remove = tsi148_remove,
61 static void reg_join(unsigned int high, unsigned int low,
62 unsigned long long *variable)
64 *variable = (unsigned long long)high << 32;
65 *variable |= (unsigned long long)low;
68 static void reg_split(unsigned long long variable, unsigned int *high,
71 *low = (unsigned int)variable & 0xFFFFFFFF;
72 *high = (unsigned int)(variable >> 32);
78 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
83 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
84 wake_up(&(bridge->dma_queue[0]));
85 serviced |= TSI148_LCSR_INTC_DMA0C;
87 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
88 wake_up(&(bridge->dma_queue[1]));
89 serviced |= TSI148_LCSR_INTC_DMA1C;
96 * Wake up location monitor queue
98 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
103 for (i = 0; i < 4; i++) {
104 if (stat & TSI148_LCSR_INTS_LMS[i]) {
105 /* We only enable interrupts if the callback is set */
106 bridge->lm_callback[i](i);
107 serviced |= TSI148_LCSR_INTC_LMC[i];
115 * Wake up mail box queue.
117 * XXX This functionality is not exposed up though API.
119 static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
124 struct tsi148_driver *bridge;
126 bridge = tsi148_bridge->driver_priv;
128 for (i = 0; i < 4; i++) {
129 if (stat & TSI148_LCSR_INTS_MBS[i]) {
130 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
131 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
133 serviced |= TSI148_LCSR_INTC_MBC[i];
141 * Display error & status message when PERR (PCI) exception interrupt occurs.
143 static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
145 struct tsi148_driver *bridge;
147 bridge = tsi148_bridge->driver_priv;
149 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
150 "attributes: %08x\n",
151 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
153 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
155 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
156 "completion reg: %08x\n",
157 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
158 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
160 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
162 return TSI148_LCSR_INTC_PERRC;
166 * Save address and status when VME error interrupt occurs.
168 static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
170 unsigned int error_addr_high, error_addr_low;
171 unsigned long long error_addr;
173 struct vme_bus_error *error;
174 struct tsi148_driver *bridge;
176 bridge = tsi148_bridge->driver_priv;
178 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
179 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
180 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
182 reg_join(error_addr_high, error_addr_low, &error_addr);
184 /* Check for exception register overflow (we have lost error data) */
185 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
186 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
190 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
192 error->address = error_addr;
193 error->attributes = error_attrib;
194 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
196 dev_err(tsi148_bridge->parent, "Unable to alloc memory for "
197 "VMEbus Error reporting\n");
198 dev_err(tsi148_bridge->parent, "VME Bus Error at address: "
199 "0x%llx, attributes: %08x\n", error_addr, error_attrib);
203 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
205 return TSI148_LCSR_INTC_VERRC;
209 * Wake up IACK queue.
211 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
213 wake_up(&(bridge->iack_queue));
215 return TSI148_LCSR_INTC_IACKC;
219 * Calling VME bus interrupt callback if provided.
221 static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
224 int vec, i, serviced = 0;
225 struct tsi148_driver *bridge;
227 bridge = tsi148_bridge->driver_priv;
229 for (i = 7; i > 0; i--) {
230 if (stat & (1 << i)) {
232 * Note: Even though the registers are defined as
233 * 32-bits in the spec, we only want to issue 8-bit
234 * IACK cycles on the bus, read from offset 3.
236 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
238 vme_irq_handler(tsi148_bridge, i, vec);
240 serviced |= (1 << i);
248 * Top level interrupt handler. Clears appropriate interrupt status bits and
249 * then calls appropriate sub handler(s).
251 static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
253 u32 stat, enable, serviced = 0;
254 struct vme_bridge *tsi148_bridge;
255 struct tsi148_driver *bridge;
259 bridge = tsi148_bridge->driver_priv;
261 /* Determine which interrupts are unmasked and set */
262 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
263 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
265 /* Only look at unmasked interrupts */
271 /* Call subhandlers as appropriate */
273 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
274 serviced |= tsi148_DMA_irqhandler(bridge, stat);
276 /* Location monitor irqs */
277 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
278 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
279 serviced |= tsi148_LM_irqhandler(bridge, stat);
282 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
283 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
284 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
287 if (stat & TSI148_LCSR_INTS_PERRS)
288 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
291 if (stat & TSI148_LCSR_INTS_VERRS)
292 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
295 if (stat & TSI148_LCSR_INTS_IACKS)
296 serviced |= tsi148_IACK_irqhandler(bridge);
299 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
300 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
301 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
302 TSI148_LCSR_INTS_IRQ1S))
303 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
305 /* Clear serviced interrupts */
306 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
311 static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
315 struct pci_dev *pdev;
316 struct tsi148_driver *bridge;
318 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
320 bridge = tsi148_bridge->driver_priv;
322 /* Initialise list for VME bus errors */
323 INIT_LIST_HEAD(&(tsi148_bridge->vme_errors));
325 mutex_init(&(tsi148_bridge->irq_mtx));
327 result = request_irq(pdev->irq,
330 driver_name, tsi148_bridge);
332 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
333 "vector %02X\n", pdev->irq);
337 /* Enable and unmask interrupts */
338 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
339 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
340 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
341 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
342 TSI148_LCSR_INTEO_IACKEO;
344 /* This leaves the following interrupts masked.
345 * TSI148_LCSR_INTEO_VIEEO
346 * TSI148_LCSR_INTEO_SYSFLEO
347 * TSI148_LCSR_INTEO_ACFLEO
350 /* Don't enable Location Monitor interrupts here - they will be
351 * enabled when the location monitors are properly configured and
352 * a callback has been attached.
353 * TSI148_LCSR_INTEO_LM0EO
354 * TSI148_LCSR_INTEO_LM1EO
355 * TSI148_LCSR_INTEO_LM2EO
356 * TSI148_LCSR_INTEO_LM3EO
359 /* Don't enable VME interrupts until we add a handler, else the board
360 * will respond to it and we don't want that unless it knows how to
361 * properly deal with it.
362 * TSI148_LCSR_INTEO_IRQ7EO
363 * TSI148_LCSR_INTEO_IRQ6EO
364 * TSI148_LCSR_INTEO_IRQ5EO
365 * TSI148_LCSR_INTEO_IRQ4EO
366 * TSI148_LCSR_INTEO_IRQ3EO
367 * TSI148_LCSR_INTEO_IRQ2EO
368 * TSI148_LCSR_INTEO_IRQ1EO
371 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
372 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
377 static void tsi148_irq_exit(struct tsi148_driver *bridge, struct pci_dev *pdev)
379 /* Turn off interrupts */
380 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
381 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
383 /* Clear all interrupts */
384 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
386 /* Detach interrupt handler */
387 free_irq(pdev->irq, pdev);
391 * Check to see if an IACk has been received, return true (1) or false (0).
393 int tsi148_iack_received(struct tsi148_driver *bridge)
397 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
399 if (tmp & TSI148_LCSR_VICR_IRQS)
406 * Configure VME interrupt
408 void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
411 struct pci_dev *pdev;
413 struct tsi148_driver *bridge;
415 bridge = tsi148_bridge->driver_priv;
417 /* We need to do the ordering differently for enabling and disabling */
419 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
420 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
421 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
424 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
425 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
428 pdev = container_of(tsi148_bridge->parent,
429 struct pci_dev, dev);
431 synchronize_irq(pdev->irq);
434 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
435 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
436 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
438 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
439 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
440 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
445 * Generate a VME bus interrupt at the requested level & vector. Wait for
446 * interrupt to be acked.
448 int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, int statid)
451 struct tsi148_driver *bridge;
453 bridge = tsi148_bridge->driver_priv;
455 mutex_lock(&(bridge->vme_int));
457 /* Read VICR register */
458 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
461 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
462 (statid & TSI148_LCSR_VICR_STID_M);
463 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
465 /* Assert VMEbus IRQ */
466 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
467 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
469 /* XXX Consider implementing a timeout? */
470 wait_event_interruptible(bridge->iack_queue,
471 tsi148_iack_received(bridge));
473 mutex_unlock(&(bridge->vme_int));
479 * Find the first error in this address range
481 static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
482 vme_address_t aspace, unsigned long long address, size_t count)
484 struct list_head *err_pos;
485 struct vme_bus_error *vme_err, *valid = NULL;
486 unsigned long long bound;
488 bound = address + count;
491 * XXX We are currently not looking at the address space when parsing
492 * for errors. This is because parsing the Address Modifier Codes
493 * is going to be quite resource intensive to do properly. We
494 * should be OK just looking at the addresses and this is certainly
495 * much better than what we had before.
498 /* Iterate through errors */
499 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
500 vme_err = list_entry(err_pos, struct vme_bus_error, list);
501 if ((vme_err->address >= address) &&
502 (vme_err->address < bound)) {
513 * Clear errors in the provided address range.
515 static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
516 vme_address_t aspace, unsigned long long address, size_t count)
518 struct list_head *err_pos, *temp;
519 struct vme_bus_error *vme_err;
520 unsigned long long bound;
522 bound = address + count;
525 * XXX We are currently not looking at the address space when parsing
526 * for errors. This is because parsing the Address Modifier Codes
527 * is going to be quite resource intensive to do properly. We
528 * should be OK just looking at the addresses and this is certainly
529 * much better than what we had before.
532 /* Iterate through errors */
533 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
534 vme_err = list_entry(err_pos, struct vme_bus_error, list);
536 if ((vme_err->address >= address) &&
537 (vme_err->address < bound)) {
546 * Initialize a slave window with the requested attributes.
548 int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
549 unsigned long long vme_base, unsigned long long size,
550 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
552 unsigned int i, addr = 0, granularity = 0;
553 unsigned int temp_ctl = 0;
554 unsigned int vme_base_low, vme_base_high;
555 unsigned int vme_bound_low, vme_bound_high;
556 unsigned int pci_offset_low, pci_offset_high;
557 unsigned long long vme_bound, pci_offset;
558 struct vme_bridge *tsi148_bridge;
559 struct tsi148_driver *bridge;
561 tsi148_bridge = image->parent;
562 bridge = tsi148_bridge->driver_priv;
569 addr |= TSI148_LCSR_ITAT_AS_A16;
572 granularity = 0x1000;
573 addr |= TSI148_LCSR_ITAT_AS_A24;
576 granularity = 0x10000;
577 addr |= TSI148_LCSR_ITAT_AS_A32;
580 granularity = 0x10000;
581 addr |= TSI148_LCSR_ITAT_AS_A64;
589 dev_err(tsi148_bridge->parent, "Invalid address space\n");
594 /* Convert 64-bit variables to 2x 32-bit variables */
595 reg_split(vme_base, &vme_base_high, &vme_base_low);
598 * Bound address is a valid address for the window, adjust
601 vme_bound = vme_base + size - granularity;
602 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
603 pci_offset = (unsigned long long)pci_base - vme_base;
604 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
606 if (vme_base_low & (granularity - 1)) {
607 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
610 if (vme_bound_low & (granularity - 1)) {
611 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
614 if (pci_offset_low & (granularity - 1)) {
615 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
620 /* Disable while we are mucking around */
621 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
622 TSI148_LCSR_OFFSET_ITAT);
623 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
624 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
625 TSI148_LCSR_OFFSET_ITAT);
628 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
629 TSI148_LCSR_OFFSET_ITSAU);
630 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
631 TSI148_LCSR_OFFSET_ITSAL);
632 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
633 TSI148_LCSR_OFFSET_ITEAU);
634 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
635 TSI148_LCSR_OFFSET_ITEAL);
636 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
637 TSI148_LCSR_OFFSET_ITOFU);
638 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
639 TSI148_LCSR_OFFSET_ITOFL);
641 /* Setup 2eSST speeds */
642 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
643 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
645 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
648 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
651 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
655 /* Setup cycle types */
656 temp_ctl &= ~(0x1F << 7);
658 temp_ctl |= TSI148_LCSR_ITAT_BLT;
659 if (cycle & VME_MBLT)
660 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
661 if (cycle & VME_2eVME)
662 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
663 if (cycle & VME_2eSST)
664 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
665 if (cycle & VME_2eSSTB)
666 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
668 /* Setup address space */
669 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
673 if (cycle & VME_SUPER)
674 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
675 if (cycle & VME_USER)
676 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
677 if (cycle & VME_PROG)
678 temp_ctl |= TSI148_LCSR_ITAT_PGM;
679 if (cycle & VME_DATA)
680 temp_ctl |= TSI148_LCSR_ITAT_DATA;
682 /* Write ctl reg without enable */
683 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
684 TSI148_LCSR_OFFSET_ITAT);
687 temp_ctl |= TSI148_LCSR_ITAT_EN;
689 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
690 TSI148_LCSR_OFFSET_ITAT);
696 * Get slave window configuration.
698 int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
699 unsigned long long *vme_base, unsigned long long *size,
700 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
702 unsigned int i, granularity = 0, ctl = 0;
703 unsigned int vme_base_low, vme_base_high;
704 unsigned int vme_bound_low, vme_bound_high;
705 unsigned int pci_offset_low, pci_offset_high;
706 unsigned long long vme_bound, pci_offset;
707 struct tsi148_driver *bridge;
709 bridge = image->parent->driver_priv;
714 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
715 TSI148_LCSR_OFFSET_ITAT);
717 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
718 TSI148_LCSR_OFFSET_ITSAU);
719 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
720 TSI148_LCSR_OFFSET_ITSAL);
721 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
722 TSI148_LCSR_OFFSET_ITEAU);
723 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
724 TSI148_LCSR_OFFSET_ITEAL);
725 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
726 TSI148_LCSR_OFFSET_ITOFU);
727 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
728 TSI148_LCSR_OFFSET_ITOFL);
730 /* Convert 64-bit variables to 2x 32-bit variables */
731 reg_join(vme_base_high, vme_base_low, vme_base);
732 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
733 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
735 *pci_base = (dma_addr_t)vme_base + pci_offset;
741 if (ctl & TSI148_LCSR_ITAT_EN)
744 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
748 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
749 granularity = 0x1000;
752 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
753 granularity = 0x10000;
756 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
757 granularity = 0x10000;
761 /* Need granularity before we set the size */
762 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
765 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
766 *cycle |= VME_2eSST160;
767 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
768 *cycle |= VME_2eSST267;
769 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
770 *cycle |= VME_2eSST320;
772 if (ctl & TSI148_LCSR_ITAT_BLT)
774 if (ctl & TSI148_LCSR_ITAT_MBLT)
776 if (ctl & TSI148_LCSR_ITAT_2eVME)
778 if (ctl & TSI148_LCSR_ITAT_2eSST)
780 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
781 *cycle |= VME_2eSSTB;
783 if (ctl & TSI148_LCSR_ITAT_SUPR)
785 if (ctl & TSI148_LCSR_ITAT_NPRIV)
787 if (ctl & TSI148_LCSR_ITAT_PGM)
789 if (ctl & TSI148_LCSR_ITAT_DATA)
796 * Allocate and map PCI Resource
798 static int tsi148_alloc_resource(struct vme_master_resource *image,
799 unsigned long long size)
801 unsigned long long existing_size;
803 struct pci_dev *pdev;
804 struct vme_bridge *tsi148_bridge;
806 tsi148_bridge = image->parent;
808 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
810 existing_size = (unsigned long long)(image->bus_resource.end -
811 image->bus_resource.start);
813 /* If the existing size is OK, return */
814 if ((size != 0) && (existing_size == (size - 1)))
817 if (existing_size != 0) {
818 iounmap(image->kern_base);
819 image->kern_base = NULL;
820 if (image->bus_resource.name != NULL)
821 kfree(image->bus_resource.name);
822 release_resource(&(image->bus_resource));
823 memset(&(image->bus_resource), 0, sizeof(struct resource));
826 /* Exit here if size is zero */
830 if (image->bus_resource.name == NULL) {
831 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
832 if (image->bus_resource.name == NULL) {
833 dev_err(tsi148_bridge->parent, "Unable to allocate "
834 "memory for resource name\n");
840 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
843 image->bus_resource.start = 0;
844 image->bus_resource.end = (unsigned long)size;
845 image->bus_resource.flags = IORESOURCE_MEM;
847 retval = pci_bus_alloc_resource(pdev->bus,
848 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
851 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
852 "resource for window %d size 0x%lx start 0x%lx\n",
853 image->number, (unsigned long)size,
854 (unsigned long)image->bus_resource.start);
858 image->kern_base = ioremap_nocache(
859 image->bus_resource.start, size);
860 if (image->kern_base == NULL) {
861 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
868 iounmap(image->kern_base);
869 image->kern_base = NULL;
871 release_resource(&(image->bus_resource));
873 kfree(image->bus_resource.name);
874 memset(&(image->bus_resource), 0, sizeof(struct resource));
880 * Free and unmap PCI Resource
882 static void tsi148_free_resource(struct vme_master_resource *image)
884 iounmap(image->kern_base);
885 image->kern_base = NULL;
886 release_resource(&(image->bus_resource));
887 kfree(image->bus_resource.name);
888 memset(&(image->bus_resource), 0, sizeof(struct resource));
892 * Set the attributes of an outbound window.
894 int tsi148_master_set(struct vme_master_resource *image, int enabled,
895 unsigned long long vme_base, unsigned long long size,
896 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
900 unsigned int temp_ctl = 0;
901 unsigned int pci_base_low, pci_base_high;
902 unsigned int pci_bound_low, pci_bound_high;
903 unsigned int vme_offset_low, vme_offset_high;
904 unsigned long long pci_bound, vme_offset, pci_base;
905 struct vme_bridge *tsi148_bridge;
906 struct tsi148_driver *bridge;
908 tsi148_bridge = image->parent;
910 bridge = tsi148_bridge->driver_priv;
912 /* Verify input data */
913 if (vme_base & 0xFFFF) {
914 dev_err(tsi148_bridge->parent, "Invalid VME Window "
920 if ((size == 0) && (enabled != 0)) {
921 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
922 "enabled windows\n");
927 spin_lock(&(image->lock));
929 /* Let's allocate the resource here rather than further up the stack as
930 * it avoids pushing loads of bus dependant stuff up the stack. If size
931 * is zero, any existing resource will be freed.
933 retval = tsi148_alloc_resource(image, size);
935 spin_unlock(&(image->lock));
936 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
946 pci_base = (unsigned long long)image->bus_resource.start;
949 * Bound address is a valid address for the window, adjust
950 * according to window granularity.
952 pci_bound = pci_base + (size - 0x10000);
953 vme_offset = vme_base - pci_base;
956 /* Convert 64-bit variables to 2x 32-bit variables */
957 reg_split(pci_base, &pci_base_high, &pci_base_low);
958 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
959 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
961 if (pci_base_low & 0xFFFF) {
962 spin_unlock(&(image->lock));
963 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
967 if (pci_bound_low & 0xFFFF) {
968 spin_unlock(&(image->lock));
969 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
973 if (vme_offset_low & 0xFFFF) {
974 spin_unlock(&(image->lock));
975 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
983 /* Disable while we are mucking around */
984 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
985 TSI148_LCSR_OFFSET_OTAT);
986 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
987 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
988 TSI148_LCSR_OFFSET_OTAT);
990 /* Setup 2eSST speeds */
991 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
992 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
994 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
997 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1000 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1004 /* Setup cycle types */
1005 if (cycle & VME_BLT) {
1006 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1007 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1009 if (cycle & VME_MBLT) {
1010 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1011 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1013 if (cycle & VME_2eVME) {
1014 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1015 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1017 if (cycle & VME_2eSST) {
1018 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1019 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1021 if (cycle & VME_2eSSTB) {
1022 dev_warn(tsi148_bridge->parent, "Currently not setting "
1023 "Broadcast Select Registers\n");
1024 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1025 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1028 /* Setup data width */
1029 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1032 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1035 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1038 spin_unlock(&(image->lock));
1039 dev_err(tsi148_bridge->parent, "Invalid data width\n");
1044 /* Setup address space */
1045 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1048 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1051 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1054 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1057 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1060 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1063 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1066 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1069 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1072 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1075 spin_unlock(&(image->lock));
1076 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1082 temp_ctl &= ~(3<<4);
1083 if (cycle & VME_SUPER)
1084 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1085 if (cycle & VME_PROG)
1086 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1089 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1090 TSI148_LCSR_OFFSET_OTSAU);
1091 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1092 TSI148_LCSR_OFFSET_OTSAL);
1093 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1094 TSI148_LCSR_OFFSET_OTEAU);
1095 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1096 TSI148_LCSR_OFFSET_OTEAL);
1097 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1098 TSI148_LCSR_OFFSET_OTOFU);
1099 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1100 TSI148_LCSR_OFFSET_OTOFL);
1102 /* Write ctl reg without enable */
1103 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1104 TSI148_LCSR_OFFSET_OTAT);
1107 temp_ctl |= TSI148_LCSR_OTAT_EN;
1109 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1110 TSI148_LCSR_OFFSET_OTAT);
1112 spin_unlock(&(image->lock));
1118 tsi148_free_resource(image);
1126 * Set the attributes of an outbound window.
1128 * XXX Not parsing prefetch information.
1130 int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1131 unsigned long long *vme_base, unsigned long long *size,
1132 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1134 unsigned int i, ctl;
1135 unsigned int pci_base_low, pci_base_high;
1136 unsigned int pci_bound_low, pci_bound_high;
1137 unsigned int vme_offset_low, vme_offset_high;
1139 unsigned long long pci_base, pci_bound, vme_offset;
1140 struct tsi148_driver *bridge;
1142 bridge = image->parent->driver_priv;
1146 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1147 TSI148_LCSR_OFFSET_OTAT);
1149 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1150 TSI148_LCSR_OFFSET_OTSAU);
1151 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1152 TSI148_LCSR_OFFSET_OTSAL);
1153 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1154 TSI148_LCSR_OFFSET_OTEAU);
1155 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1156 TSI148_LCSR_OFFSET_OTEAL);
1157 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1158 TSI148_LCSR_OFFSET_OTOFU);
1159 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1160 TSI148_LCSR_OFFSET_OTOFL);
1162 /* Convert 64-bit variables to 2x 32-bit variables */
1163 reg_join(pci_base_high, pci_base_low, &pci_base);
1164 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1165 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1167 *vme_base = pci_base + vme_offset;
1168 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1175 if (ctl & TSI148_LCSR_OTAT_EN)
1178 /* Setup address space */
1179 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1181 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1183 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1185 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1187 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1188 *aspace |= VME_CRCSR;
1189 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1190 *aspace |= VME_USER1;
1191 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1192 *aspace |= VME_USER2;
1193 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1194 *aspace |= VME_USER3;
1195 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1196 *aspace |= VME_USER4;
1198 /* Setup 2eSST speeds */
1199 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1200 *cycle |= VME_2eSST160;
1201 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1202 *cycle |= VME_2eSST267;
1203 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1204 *cycle |= VME_2eSST320;
1206 /* Setup cycle types */
1207 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1209 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1211 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1213 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1214 *cycle |= VME_2eVME;
1215 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1216 *cycle |= VME_2eSST;
1217 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1218 *cycle |= VME_2eSSTB;
1220 if (ctl & TSI148_LCSR_OTAT_SUP)
1221 *cycle |= VME_SUPER;
1225 if (ctl & TSI148_LCSR_OTAT_PGM)
1230 /* Setup data width */
1231 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1233 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1240 int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1241 unsigned long long *vme_base, unsigned long long *size,
1242 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1246 spin_lock(&(image->lock));
1248 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1251 spin_unlock(&(image->lock));
1256 ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1257 size_t count, loff_t offset)
1259 int retval, enabled;
1260 unsigned long long vme_base, size;
1261 vme_address_t aspace;
1264 struct vme_bus_error *vme_err = NULL;
1265 struct vme_bridge *tsi148_bridge;
1267 tsi148_bridge = image->parent;
1269 spin_lock(&(image->lock));
1271 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1277 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1280 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1282 if (vme_err != NULL) {
1283 dev_err(image->parent->parent, "First VME read error detected "
1284 "an at address 0x%llx\n", vme_err->address);
1285 retval = vme_err->address - (vme_base + offset);
1286 /* Clear down save errors in this address range */
1287 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1292 spin_unlock(&(image->lock));
1298 ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1299 size_t count, loff_t offset)
1301 int retval = 0, enabled;
1302 unsigned long long vme_base, size;
1303 vme_address_t aspace;
1307 struct vme_bus_error *vme_err = NULL;
1308 struct vme_bridge *tsi148_bridge;
1309 struct tsi148_driver *bridge;
1311 tsi148_bridge = image->parent;
1313 bridge = tsi148_bridge->driver_priv;
1315 spin_lock(&(image->lock));
1317 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1321 * Writes are posted. We need to do a read on the VME bus to flush out
1322 * all of the writes before we check for errors. We can't guarentee
1323 * that reading the data we have just written is safe. It is believed
1324 * that there isn't any read, write re-ordering, so we can read any
1325 * location in VME space, so lets read the Device ID from the tsi148's
1326 * own registers as mapped into CR/CSR space.
1328 * We check for saved errors in the written address range/space.
1335 * Get window info first, to maximise the time that the buffers may
1336 * fluch on their own
1338 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1341 ioread16(bridge->flush_image->kern_base + 0x7F000);
1343 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1345 if (vme_err != NULL) {
1346 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1347 " an at address 0x%llx\n", vme_err->address);
1348 retval = vme_err->address - (vme_base + offset);
1349 /* Clear down save errors in this address range */
1350 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1355 spin_unlock(&(image->lock));
1361 * Perform an RMW cycle on the VME bus.
1363 * Requires a previously configured master window, returns final value.
1365 unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1366 unsigned int mask, unsigned int compare, unsigned int swap,
1369 unsigned long long pci_addr;
1370 unsigned int pci_addr_high, pci_addr_low;
1373 struct tsi148_driver *bridge;
1375 bridge = image->parent->driver_priv;
1377 /* Find the PCI address that maps to the desired VME address */
1380 /* Locking as we can only do one of these at a time */
1381 mutex_lock(&(bridge->vme_rmw));
1384 spin_lock(&(image->lock));
1386 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1387 TSI148_LCSR_OFFSET_OTSAU);
1388 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1389 TSI148_LCSR_OFFSET_OTSAL);
1391 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1392 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1394 /* Configure registers */
1395 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1396 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1397 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1398 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1399 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1402 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1403 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1404 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1406 /* Kick process off with a read to the required address. */
1407 result = ioread32be(image->kern_base + offset);
1410 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1411 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1412 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1414 spin_unlock(&(image->lock));
1416 mutex_unlock(&(bridge->vme_rmw));
1421 static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr,
1422 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1424 /* Setup 2eSST speeds */
1425 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1427 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1430 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1433 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1437 /* Setup cycle types */
1438 if (cycle & VME_SCT)
1439 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1441 if (cycle & VME_BLT)
1442 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1444 if (cycle & VME_MBLT)
1445 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1447 if (cycle & VME_2eVME)
1448 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1450 if (cycle & VME_2eSST)
1451 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1453 if (cycle & VME_2eSSTB) {
1454 dev_err(dev, "Currently not setting Broadcast Select "
1456 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1459 /* Setup data width */
1462 *attr |= TSI148_LCSR_DSAT_DBW_16;
1465 *attr |= TSI148_LCSR_DSAT_DBW_32;
1468 dev_err(dev, "Invalid data width\n");
1472 /* Setup address space */
1475 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1478 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1481 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1484 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1487 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1490 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1493 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1496 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1499 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1502 dev_err(dev, "Invalid address space\n");
1507 if (cycle & VME_SUPER)
1508 *attr |= TSI148_LCSR_DSAT_SUP;
1509 if (cycle & VME_PROG)
1510 *attr |= TSI148_LCSR_DSAT_PGM;
1515 static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr,
1516 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
1518 /* Setup 2eSST speeds */
1519 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1521 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1524 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1527 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1531 /* Setup cycle types */
1532 if (cycle & VME_SCT)
1533 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1535 if (cycle & VME_BLT)
1536 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1538 if (cycle & VME_MBLT)
1539 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1541 if (cycle & VME_2eVME)
1542 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1544 if (cycle & VME_2eSST)
1545 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1547 if (cycle & VME_2eSSTB) {
1548 dev_err(dev, "Currently not setting Broadcast Select "
1550 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1553 /* Setup data width */
1556 *attr |= TSI148_LCSR_DDAT_DBW_16;
1559 *attr |= TSI148_LCSR_DDAT_DBW_32;
1562 dev_err(dev, "Invalid data width\n");
1566 /* Setup address space */
1569 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1572 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1575 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1578 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1581 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1584 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1587 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1590 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1593 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1596 dev_err(dev, "Invalid address space\n");
1601 if (cycle & VME_SUPER)
1602 *attr |= TSI148_LCSR_DDAT_SUP;
1603 if (cycle & VME_PROG)
1604 *attr |= TSI148_LCSR_DDAT_PGM;
1610 * Add a link list descriptor to the list
1612 int tsi148_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
1613 struct vme_dma_attr *dest, size_t count)
1615 struct tsi148_dma_entry *entry, *prev;
1616 u32 address_high, address_low;
1617 struct vme_dma_pattern *pattern_attr;
1618 struct vme_dma_pci *pci_attr;
1619 struct vme_dma_vme *vme_attr;
1620 dma_addr_t desc_ptr;
1622 struct vme_bridge *tsi148_bridge;
1624 tsi148_bridge = list->parent->parent;
1626 /* Descriptor must be aligned on 64-bit boundaries */
1627 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1628 if (entry == NULL) {
1629 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1630 "dma resource structure\n");
1635 /* Test descriptor alignment */
1636 if ((unsigned long)&(entry->descriptor) & 0x7) {
1637 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1638 "byte boundary as required: %p\n",
1639 &(entry->descriptor));
1644 /* Given we are going to fill out the structure, we probably don't
1645 * need to zero it, but better safe than sorry for now.
1647 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1649 /* Fill out source part */
1650 switch (src->type) {
1651 case VME_DMA_PATTERN:
1652 pattern_attr = (struct vme_dma_pattern *)src->private;
1654 entry->descriptor.dsal = pattern_attr->pattern;
1655 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1656 /* Default behaviour is 32 bit pattern */
1657 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1658 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1660 /* It seems that the default behaviour is to increment */
1661 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1662 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1666 pci_attr = (struct vme_dma_pci *)src->private;
1668 reg_split((unsigned long long)pci_attr->address, &address_high,
1670 entry->descriptor.dsau = address_high;
1671 entry->descriptor.dsal = address_low;
1672 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1675 vme_attr = (struct vme_dma_vme *)src->private;
1677 reg_split((unsigned long long)vme_attr->address, &address_high,
1679 entry->descriptor.dsau = address_high;
1680 entry->descriptor.dsal = address_low;
1681 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1683 retval = tsi148_dma_set_vme_src_attributes(
1684 tsi148_bridge->parent, &(entry->descriptor.dsat),
1685 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1690 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1696 /* Assume last link - this will be over-written by adding another */
1697 entry->descriptor.dnlau = 0;
1698 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1701 /* Fill out destination part */
1702 switch (dest->type) {
1704 pci_attr = (struct vme_dma_pci *)dest->private;
1706 reg_split((unsigned long long)pci_attr->address, &address_high,
1708 entry->descriptor.ddau = address_high;
1709 entry->descriptor.ddal = address_low;
1710 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1713 vme_attr = (struct vme_dma_vme *)dest->private;
1715 reg_split((unsigned long long)vme_attr->address, &address_high,
1717 entry->descriptor.ddau = address_high;
1718 entry->descriptor.ddal = address_low;
1719 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1721 retval = tsi148_dma_set_vme_dest_attributes(
1722 tsi148_bridge->parent, &(entry->descriptor.ddat),
1723 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1728 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1734 /* Fill out count */
1735 entry->descriptor.dcnt = (u32)count;
1738 list_add_tail(&(entry->list), &(list->entries));
1740 /* Fill out previous descriptors "Next Address" */
1741 if (entry->list.prev != &(list->entries)) {
1742 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1744 /* We need the bus address for the pointer */
1745 desc_ptr = virt_to_bus(&(entry->descriptor));
1746 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1747 &(prev->descriptor.dnlal));
1761 * Check to see if the provided DMA channel is busy.
1763 static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1766 struct tsi148_driver *bridge;
1768 bridge = tsi148_bridge->driver_priv;
1770 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1771 TSI148_LCSR_OFFSET_DSTA);
1773 if (tmp & TSI148_LCSR_DSTA_BSY)
1781 * Execute a previously generated link list
1783 * XXX Need to provide control register configuration.
1785 int tsi148_dma_list_exec(struct vme_dma_list *list)
1787 struct vme_dma_resource *ctrlr;
1788 int channel, retval = 0;
1789 struct tsi148_dma_entry *entry;
1790 dma_addr_t bus_addr;
1791 u32 bus_addr_high, bus_addr_low;
1792 u32 val, dctlreg = 0;
1793 struct vme_bridge *tsi148_bridge;
1794 struct tsi148_driver *bridge;
1796 ctrlr = list->parent;
1798 tsi148_bridge = ctrlr->parent;
1800 bridge = tsi148_bridge->driver_priv;
1802 mutex_lock(&(ctrlr->mtx));
1804 channel = ctrlr->number;
1806 if (!list_empty(&(ctrlr->running))) {
1808 * XXX We have an active DMA transfer and currently haven't
1809 * sorted out the mechanism for "pending" DMA transfers.
1812 /* Need to add to pending here */
1813 mutex_unlock(&(ctrlr->mtx));
1816 list_add(&(list->list), &(ctrlr->running));
1819 /* Get first bus address and write into registers */
1820 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1823 bus_addr = virt_to_bus(&(entry->descriptor));
1825 mutex_unlock(&(ctrlr->mtx));
1827 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1829 iowrite32be(bus_addr_high, bridge->base +
1830 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1831 iowrite32be(bus_addr_low, bridge->base +
1832 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1834 /* Start the operation */
1835 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1836 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1838 wait_event_interruptible(bridge->dma_queue[channel],
1839 tsi148_dma_busy(ctrlr->parent, channel));
1841 * Read status register, this register is valid until we kick off a
1844 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1845 TSI148_LCSR_OFFSET_DSTA);
1847 if (val & TSI148_LCSR_DSTA_VBE) {
1848 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1852 /* Remove list from running list */
1853 mutex_lock(&(ctrlr->mtx));
1854 list_del(&(list->list));
1855 mutex_unlock(&(ctrlr->mtx));
1861 * Clean up a previously generated link list
1863 * We have a separate function, don't assume that the chain can't be reused.
1865 int tsi148_dma_list_empty(struct vme_dma_list *list)
1867 struct list_head *pos, *temp;
1868 struct tsi148_dma_entry *entry;
1870 /* detach and free each entry */
1871 list_for_each_safe(pos, temp, &(list->entries)) {
1873 entry = list_entry(pos, struct tsi148_dma_entry, list);
1881 * All 4 location monitors reside at the same base - this is therefore a
1882 * system wide configuration.
1884 * This does not enable the LM monitor - that should be done when the first
1885 * callback is attached and disabled when the last callback is removed.
1887 int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1888 vme_address_t aspace, vme_cycle_t cycle)
1890 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1892 struct vme_bridge *tsi148_bridge;
1893 struct tsi148_driver *bridge;
1895 tsi148_bridge = lm->parent;
1897 bridge = tsi148_bridge->driver_priv;
1899 mutex_lock(&(lm->mtx));
1901 /* If we already have a callback attached, we can't move it! */
1902 for (i = 0; i < lm->monitors; i++) {
1903 if (bridge->lm_callback[i] != NULL) {
1904 mutex_unlock(&(lm->mtx));
1905 dev_err(tsi148_bridge->parent, "Location monitor "
1906 "callback attached, can't reset\n");
1913 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1916 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1919 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1922 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1925 mutex_unlock(&(lm->mtx));
1926 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1931 if (cycle & VME_SUPER)
1932 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1933 if (cycle & VME_USER)
1934 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1935 if (cycle & VME_PROG)
1936 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1937 if (cycle & VME_DATA)
1938 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1940 reg_split(lm_base, &lm_base_high, &lm_base_low);
1942 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1943 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1944 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
1946 mutex_unlock(&(lm->mtx));
1951 /* Get configuration of the callback monitor and return whether it is enabled
1954 int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1955 vme_address_t *aspace, vme_cycle_t *cycle)
1957 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
1958 struct tsi148_driver *bridge;
1960 bridge = lm->parent->driver_priv;
1962 mutex_lock(&(lm->mtx));
1964 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
1965 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
1966 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
1968 reg_join(lm_base_high, lm_base_low, lm_base);
1970 if (lm_ctl & TSI148_LCSR_LMAT_EN)
1973 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
1976 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
1979 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
1982 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
1986 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
1987 *cycle |= VME_SUPER;
1988 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
1990 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
1992 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
1995 mutex_unlock(&(lm->mtx));
2001 * Attach a callback to a specific location monitor.
2003 * Callback will be passed the monitor triggered.
2005 int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2006 void (*callback)(int))
2009 struct vme_bridge *tsi148_bridge;
2010 struct tsi148_driver *bridge;
2012 tsi148_bridge = lm->parent;
2014 bridge = tsi148_bridge->driver_priv;
2016 mutex_lock(&(lm->mtx));
2018 /* Ensure that the location monitor is configured - need PGM or DATA */
2019 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2020 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2021 mutex_unlock(&(lm->mtx));
2022 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2027 /* Check that a callback isn't already attached */
2028 if (bridge->lm_callback[monitor] != NULL) {
2029 mutex_unlock(&(lm->mtx));
2030 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2034 /* Attach callback */
2035 bridge->lm_callback[monitor] = callback;
2037 /* Enable Location Monitor interrupt */
2038 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2039 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2040 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2042 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2043 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2044 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2046 /* Ensure that global Location Monitor Enable set */
2047 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2048 lm_ctl |= TSI148_LCSR_LMAT_EN;
2049 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2052 mutex_unlock(&(lm->mtx));
2058 * Detach a callback function forn a specific location monitor.
2060 int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2063 struct tsi148_driver *bridge;
2065 bridge = lm->parent->driver_priv;
2067 mutex_lock(&(lm->mtx));
2069 /* Disable Location Monitor and ensure previous interrupts are clear */
2070 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2071 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2072 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2074 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2075 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2076 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2078 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2079 bridge->base + TSI148_LCSR_INTC);
2081 /* Detach callback */
2082 bridge->lm_callback[monitor] = NULL;
2084 /* If all location monitors disabled, disable global Location Monitor */
2085 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2086 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2087 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2088 tmp &= ~TSI148_LCSR_LMAT_EN;
2089 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2092 mutex_unlock(&(lm->mtx));
2098 * Determine Geographical Addressing
2100 int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2103 struct tsi148_driver *bridge;
2105 bridge = tsi148_bridge->driver_priv;
2108 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2109 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2116 static int __init tsi148_init(void)
2118 return pci_register_driver(&tsi148_driver);
2122 * Configure CR/CSR space
2124 * Access to the CR/CSR can be configured at power-up. The location of the
2125 * CR/CSR registers in the CR/CSR address space is determined by the boards
2126 * Auto-ID or Geographic address. This function ensures that the window is
2127 * enabled at an offset consistent with the boards geopgraphic address.
2129 * Each board has a 512kB window, with the highest 4kB being used for the
2130 * boards registers, this means there is a fix length 508kB window which must
2131 * be mapped onto PCI memory.
2133 static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2134 struct pci_dev *pdev)
2136 u32 cbar, crat, vstat;
2137 u32 crcsr_bus_high, crcsr_bus_low;
2139 struct tsi148_driver *bridge;
2141 bridge = tsi148_bridge->driver_priv;
2143 /* Allocate mem for CR/CSR image */
2144 bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2145 &(bridge->crcsr_bus));
2146 if (bridge->crcsr_kernel == NULL) {
2147 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2152 memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2154 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2156 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2157 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2159 /* Ensure that the CR/CSR is configured at the correct offset */
2160 cbar = ioread32be(bridge->base + TSI148_CBAR);
2161 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2163 vstat = tsi148_slot_get(tsi148_bridge);
2165 if (cbar != vstat) {
2167 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2168 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2170 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2172 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2173 if (crat & TSI148_LCSR_CRAT_EN) {
2174 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2175 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2176 bridge->base + TSI148_LCSR_CRAT);
2178 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2180 /* If we want flushed, error-checked writes, set up a window
2181 * over the CR/CSR registers. We read from here to safely flush
2182 * through VME writes.
2185 retval = tsi148_master_set(bridge->flush_image, 1,
2186 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2189 dev_err(tsi148_bridge->parent, "Configuring flush image"
2197 static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2198 struct pci_dev *pdev)
2201 struct tsi148_driver *bridge;
2203 bridge = tsi148_bridge->driver_priv;
2205 /* Turn off CR/CSR space */
2206 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2207 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2208 bridge->base + TSI148_LCSR_CRAT);
2211 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2212 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2214 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2218 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2220 int retval, i, master_num;
2222 struct list_head *pos = NULL;
2223 struct vme_bridge *tsi148_bridge;
2224 struct tsi148_driver *tsi148_device;
2225 struct vme_master_resource *master_image;
2226 struct vme_slave_resource *slave_image;
2227 struct vme_dma_resource *dma_ctrlr;
2228 struct vme_lm_resource *lm;
2230 /* If we want to support more than one of each bridge, we need to
2231 * dynamically generate this so we get one per device
2233 tsi148_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
2234 if (tsi148_bridge == NULL) {
2235 dev_err(&pdev->dev, "Failed to allocate memory for device "
2241 memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2243 tsi148_device = kmalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2244 if (tsi148_device == NULL) {
2245 dev_err(&pdev->dev, "Failed to allocate memory for device "
2251 memset(tsi148_device, 0, sizeof(struct tsi148_driver));
2253 tsi148_bridge->driver_priv = tsi148_device;
2255 /* Enable the device */
2256 retval = pci_enable_device(pdev);
2258 dev_err(&pdev->dev, "Unable to enable device\n");
2263 retval = pci_request_regions(pdev, driver_name);
2265 dev_err(&pdev->dev, "Unable to reserve resources\n");
2269 /* map registers in BAR 0 */
2270 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2272 if (!tsi148_device->base) {
2273 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2278 /* Check to see if the mapping worked out */
2279 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2280 if (data != PCI_VENDOR_ID_TUNDRA) {
2281 dev_err(&pdev->dev, "CRG region check failed\n");
2286 /* Initialize wait queues & mutual exclusion flags */
2287 init_waitqueue_head(&(tsi148_device->dma_queue[0]));
2288 init_waitqueue_head(&(tsi148_device->dma_queue[1]));
2289 init_waitqueue_head(&(tsi148_device->iack_queue));
2290 mutex_init(&(tsi148_device->vme_int));
2291 mutex_init(&(tsi148_device->vme_rmw));
2293 tsi148_bridge->parent = &(pdev->dev);
2294 strcpy(tsi148_bridge->name, driver_name);
2297 retval = tsi148_irq_init(tsi148_bridge);
2299 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2303 /* If we are going to flush writes, we need to read from the VME bus.
2304 * We need to do this safely, thus we read the devices own CR/CSR
2305 * register. To do this we must set up a window in CR/CSR space and
2306 * hence have one less master window resource available.
2308 master_num = TSI148_MAX_MASTER;
2312 tsi148_device->flush_image =
2313 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2314 if (tsi148_device->flush_image == NULL) {
2315 dev_err(&pdev->dev, "Failed to allocate memory for "
2316 "flush resource structure\n");
2320 tsi148_device->flush_image->parent = tsi148_bridge;
2321 spin_lock_init(&(tsi148_device->flush_image->lock));
2322 tsi148_device->flush_image->locked = 1;
2323 tsi148_device->flush_image->number = master_num;
2324 tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 |
2326 tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT |
2327 VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB |
2328 VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER |
2329 VME_USER | VME_PROG | VME_DATA;
2330 tsi148_device->flush_image->width_attr = VME_D16 | VME_D32;
2331 memset(&(tsi148_device->flush_image->bus_resource), 0,
2332 sizeof(struct resource));
2333 tsi148_device->flush_image->kern_base = NULL;
2336 /* Add master windows to list */
2337 INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2338 for (i = 0; i < master_num; i++) {
2339 master_image = kmalloc(sizeof(struct vme_master_resource),
2341 if (master_image == NULL) {
2342 dev_err(&pdev->dev, "Failed to allocate memory for "
2343 "master resource structure\n");
2347 master_image->parent = tsi148_bridge;
2348 spin_lock_init(&(master_image->lock));
2349 master_image->locked = 0;
2350 master_image->number = i;
2351 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2353 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2354 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2355 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2356 VME_PROG | VME_DATA;
2357 master_image->width_attr = VME_D16 | VME_D32;
2358 memset(&(master_image->bus_resource), 0,
2359 sizeof(struct resource));
2360 master_image->kern_base = NULL;
2361 list_add_tail(&(master_image->list),
2362 &(tsi148_bridge->master_resources));
2365 /* Add slave windows to list */
2366 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2367 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2368 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2370 if (slave_image == NULL) {
2371 dev_err(&pdev->dev, "Failed to allocate memory for "
2372 "slave resource structure\n");
2376 slave_image->parent = tsi148_bridge;
2377 mutex_init(&(slave_image->mtx));
2378 slave_image->locked = 0;
2379 slave_image->number = i;
2380 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2381 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2382 VME_USER3 | VME_USER4;
2383 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2384 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2385 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2386 VME_PROG | VME_DATA;
2387 list_add_tail(&(slave_image->list),
2388 &(tsi148_bridge->slave_resources));
2391 /* Add dma engines to list */
2392 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2393 for (i = 0; i < TSI148_MAX_DMA; i++) {
2394 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2396 if (dma_ctrlr == NULL) {
2397 dev_err(&pdev->dev, "Failed to allocate memory for "
2398 "dma resource structure\n");
2402 dma_ctrlr->parent = tsi148_bridge;
2403 mutex_init(&(dma_ctrlr->mtx));
2404 dma_ctrlr->locked = 0;
2405 dma_ctrlr->number = i;
2406 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2407 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2408 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2409 VME_DMA_PATTERN_TO_MEM;
2410 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2411 INIT_LIST_HEAD(&(dma_ctrlr->running));
2412 list_add_tail(&(dma_ctrlr->list),
2413 &(tsi148_bridge->dma_resources));
2416 /* Add location monitor to list */
2417 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2418 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2420 dev_err(&pdev->dev, "Failed to allocate memory for "
2421 "location monitor resource structure\n");
2425 lm->parent = tsi148_bridge;
2426 mutex_init(&(lm->mtx));
2430 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2432 tsi148_bridge->slave_get = tsi148_slave_get;
2433 tsi148_bridge->slave_set = tsi148_slave_set;
2434 tsi148_bridge->master_get = tsi148_master_get;
2435 tsi148_bridge->master_set = tsi148_master_set;
2436 tsi148_bridge->master_read = tsi148_master_read;
2437 tsi148_bridge->master_write = tsi148_master_write;
2438 tsi148_bridge->master_rmw = tsi148_master_rmw;
2439 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2440 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2441 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2442 tsi148_bridge->irq_set = tsi148_irq_set;
2443 tsi148_bridge->irq_generate = tsi148_irq_generate;
2444 tsi148_bridge->lm_set = tsi148_lm_set;
2445 tsi148_bridge->lm_get = tsi148_lm_get;
2446 tsi148_bridge->lm_attach = tsi148_lm_attach;
2447 tsi148_bridge->lm_detach = tsi148_lm_detach;
2448 tsi148_bridge->slot_get = tsi148_slot_get;
2450 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2451 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2452 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2454 dev_info(&pdev->dev, "VME geographical address is %d\n",
2455 data & TSI148_LCSR_VSTAT_GA_M);
2457 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2460 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2461 err_chk ? "enabled" : "disabled");
2463 if (tsi148_crcsr_init(tsi148_bridge, pdev))
2464 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2467 retval = vme_register_bridge(tsi148_bridge);
2469 dev_err(&pdev->dev, "Chip Registration failed.\n");
2473 pci_set_drvdata(pdev, tsi148_bridge);
2475 /* Clear VME bus "board fail", and "power-up reset" lines */
2476 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2477 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2478 data |= TSI148_LCSR_VSTAT_CPURST;
2479 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2483 vme_unregister_bridge(tsi148_bridge);
2485 tsi148_crcsr_exit(tsi148_bridge, pdev);
2488 /* resources are stored in link list */
2489 list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2490 lm = list_entry(pos, struct vme_lm_resource, list);
2495 /* resources are stored in link list */
2496 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2497 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2502 /* resources are stored in link list */
2503 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2504 slave_image = list_entry(pos, struct vme_slave_resource, list);
2509 /* resources are stored in link list */
2510 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2511 master_image = list_entry(pos, struct vme_master_resource,
2514 kfree(master_image);
2517 tsi148_irq_exit(tsi148_device, pdev);
2520 iounmap(tsi148_device->base);
2522 pci_release_regions(pdev);
2524 pci_disable_device(pdev);
2526 kfree(tsi148_device);
2528 kfree(tsi148_bridge);
2534 static void tsi148_remove(struct pci_dev *pdev)
2536 struct list_head *pos = NULL;
2537 struct vme_master_resource *master_image;
2538 struct vme_slave_resource *slave_image;
2539 struct vme_dma_resource *dma_ctrlr;
2541 struct tsi148_driver *bridge;
2542 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2544 bridge = tsi148_bridge->driver_priv;
2547 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2550 * Shutdown all inbound and outbound windows.
2552 for (i = 0; i < 8; i++) {
2553 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2554 TSI148_LCSR_OFFSET_ITAT);
2555 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2556 TSI148_LCSR_OFFSET_OTAT);
2560 * Shutdown Location monitor.
2562 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2567 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2570 * Clear error status.
2572 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2573 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2574 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2577 * Remove VIRQ interrupt (if any)
2579 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2580 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2583 * Map all Interrupts to PCI INTA
2585 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2586 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2588 tsi148_irq_exit(bridge, pdev);
2590 vme_unregister_bridge(tsi148_bridge);
2592 tsi148_crcsr_exit(tsi148_bridge, pdev);
2594 /* resources are stored in link list */
2595 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2596 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2601 /* resources are stored in link list */
2602 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2603 slave_image = list_entry(pos, struct vme_slave_resource, list);
2608 /* resources are stored in link list */
2609 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2610 master_image = list_entry(pos, struct vme_master_resource,
2613 kfree(master_image);
2616 tsi148_irq_exit(bridge, pdev);
2618 iounmap(bridge->base);
2620 pci_release_regions(pdev);
2622 pci_disable_device(pdev);
2624 kfree(tsi148_bridge->driver_priv);
2626 kfree(tsi148_bridge);
2629 static void __exit tsi148_exit(void)
2631 pci_unregister_driver(&tsi148_driver);
2634 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2635 module_param(err_chk, bool, 0);
2637 MODULE_PARM_DESC(geoid, "Override geographical addressing");
2638 module_param(geoid, int, 0);
2640 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2641 MODULE_LICENSE("GPL");
2643 module_init(tsi148_init);
2644 module_exit(tsi148_exit);