SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/vme/bridges/vme_ca91cx42.c

   1 /*
   2  * Support for the Tundra Universe I/II VME-PCI Bridge Chips
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   6  *
   7  * Based on work by Tom Armistead and Ajit Prem
   8  * Copyright 2004 Motorola Inc.
   9  *
  10  * Derived from ca91c042.c by Michael Wyrick
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mm.h>
  20 #include <linux/types.h>
  21 #include <linux/errno.h>
  22 #include <linux/pci.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/poll.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29 #include <linux/time.h>
  30 #include <linux/io.h>
  31 #include <linux/uaccess.h>
  32
  33 #include "../vme.h"
  34 #include "../vme_bridge.h"
  35 #include "vme_ca91cx42.h"
  36
  37 static int __init ca91cx42_init(void);
  38 static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *);
  39 static void ca91cx42_remove(struct pci_dev *);
  40 static void __exit ca91cx42_exit(void);
  41
  42 /* Module parameters */
  43 static int geoid;
  44
  45 static char driver_name[] = "vme_ca91cx42";
  46
  47 static const struct pci_device_id ca91cx42_ids[] = {
  48         { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) },
  49         { },
  50 };
  51
  52 static struct pci_driver ca91cx42_driver = {
  53         .name = driver_name,
  54         .id_table = ca91cx42_ids,
  55         .probe = ca91cx42_probe,
  56         .remove = ca91cx42_remove,
  57 };
  58
  59 static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge)
  60 {
  61         wake_up(&(bridge->dma_queue));
  62
  63         return CA91CX42_LINT_DMA;
  64 }
  65
  66 static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat)
  67 {
  68         int i;
  69         u32 serviced = 0;
  70
  71         for (i = 0; i < 4; i++) {
  72                 if (stat & CA91CX42_LINT_LM[i]) {
  73                         /* We only enable interrupts if the callback is set */
  74                         bridge->lm_callback[i](i);
  75                         serviced |= CA91CX42_LINT_LM[i];
  76                 }
  77         }
  78
  79         return serviced;
  80 }
  81
  82 /* XXX This needs to be split into 4 queues */
  83 static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask)
  84 {
  85         wake_up(&(bridge->mbox_queue));
  86
  87         return CA91CX42_LINT_MBOX;
  88 }
  89
  90 static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge)
  91 {
  92         wake_up(&(bridge->iack_queue));
  93
  94         return CA91CX42_LINT_SW_IACK;
  95 }
  96
  97 static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
  98 {
  99         int val;
 100         struct ca91cx42_driver *bridge;
 101
 102         bridge = ca91cx42_bridge->driver_priv;
 103
 104         val = ioread32(bridge->base + DGCS);
 105
 106         if (!(val & 0x00000800)) {
 107                 dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA "
 108                         "Read Error DGCS=%08X\n", val);
 109         }
 110
 111         return CA91CX42_LINT_VERR;
 112 }
 113
 114 static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge)
 115 {
 116         int val;
 117         struct ca91cx42_driver *bridge;
 118
 119         bridge = ca91cx42_bridge->driver_priv;
 120
 121         val = ioread32(bridge->base + DGCS);
 122
 123         if (!(val & 0x00000800))
 124                 dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA "
 125                         "Read Error DGCS=%08X\n", val);
 126
 127         return CA91CX42_LINT_LERR;
 128 }
 129
 130
 131 static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge,
 132         int stat)
 133 {
 134         int vec, i, serviced = 0;
 135         struct ca91cx42_driver *bridge;
 136
 137         bridge = ca91cx42_bridge->driver_priv;
 138
 139
 140         for (i = 7; i > 0; i--) {
 141                 if (stat & (1 << i)) {
 142                         vec = ioread32(bridge->base +
 143                                 CA91CX42_V_STATID[i]) & 0xff;
 144
 145                         vme_irq_handler(ca91cx42_bridge, i, vec);
 146
 147                         serviced |= (1 << i);
 148                 }
 149         }
 150
 151         return serviced;
 152 }
 153
 154 static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr)
 155 {
 156         u32 stat, enable, serviced = 0;
 157         struct vme_bridge *ca91cx42_bridge;
 158         struct ca91cx42_driver *bridge;
 159
 160         ca91cx42_bridge = ptr;
 161
 162         bridge = ca91cx42_bridge->driver_priv;
 163
 164         enable = ioread32(bridge->base + LINT_EN);
 165         stat = ioread32(bridge->base + LINT_STAT);
 166
 167         /* Only look at unmasked interrupts */
 168         stat &= enable;
 169
 170         if (unlikely(!stat))
 171                 return IRQ_NONE;
 172
 173         if (stat & CA91CX42_LINT_DMA)
 174                 serviced |= ca91cx42_DMA_irqhandler(bridge);
 175         if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
 176                         CA91CX42_LINT_LM3))
 177                 serviced |= ca91cx42_LM_irqhandler(bridge, stat);
 178         if (stat & CA91CX42_LINT_MBOX)
 179                 serviced |= ca91cx42_MB_irqhandler(bridge, stat);
 180         if (stat & CA91CX42_LINT_SW_IACK)
 181                 serviced |= ca91cx42_IACK_irqhandler(bridge);
 182         if (stat & CA91CX42_LINT_VERR)
 183                 serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge);
 184         if (stat & CA91CX42_LINT_LERR)
 185                 serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge);
 186         if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 |
 187                         CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 |
 188                         CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 |
 189                         CA91CX42_LINT_VIRQ7))
 190                 serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat);
 191
 192         /* Clear serviced interrupts */
 193         iowrite32(stat, bridge->base + LINT_STAT);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge)
 199 {
 200         int result, tmp;
 201         struct pci_dev *pdev;
 202         struct ca91cx42_driver *bridge;
 203
 204         bridge = ca91cx42_bridge->driver_priv;
 205
 206         /* Need pdev */
 207         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 208
 209         /* Initialise list for VME bus errors */
 210         INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors));
 211
 212         mutex_init(&(ca91cx42_bridge->irq_mtx));
 213
 214         /* Disable interrupts from PCI to VME */
 215         iowrite32(0, bridge->base + VINT_EN);
 216
 217         /* Disable PCI interrupts */
 218         iowrite32(0, bridge->base + LINT_EN);
 219         /* Clear Any Pending PCI Interrupts */
 220         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 221
 222         result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED,
 223                         driver_name, ca91cx42_bridge);
 224         if (result) {
 225                 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
 226                        pdev->irq);
 227                 return result;
 228         }
 229
 230         /* Ensure all interrupts are mapped to PCI Interrupt 0 */
 231         iowrite32(0, bridge->base + LINT_MAP0);
 232         iowrite32(0, bridge->base + LINT_MAP1);
 233         iowrite32(0, bridge->base + LINT_MAP2);
 234
 235         /* Enable DMA, mailbox & LM Interrupts */
 236         tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 |
 237                 CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK |
 238                 CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA;
 239
 240         iowrite32(tmp, bridge->base + LINT_EN);
 241
 242         return 0;
 243 }
 244
 245 static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge,
 246         struct pci_dev *pdev)
 247 {
 248         /* Disable interrupts from PCI to VME */
 249         iowrite32(0, bridge->base + VINT_EN);
 250
 251         /* Disable PCI interrupts */
 252         iowrite32(0, bridge->base + LINT_EN);
 253         /* Clear Any Pending PCI Interrupts */
 254         iowrite32(0x00FFFFFF, bridge->base + LINT_STAT);
 255
 256         free_irq(pdev->irq, pdev);
 257 }
 258
 259 /*
 260  * Set up an VME interrupt
 261  */
 262 void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state,
 263         int sync)
 264
 265 {
 266         struct pci_dev *pdev;
 267         u32 tmp;
 268         struct ca91cx42_driver *bridge;
 269
 270         bridge = ca91cx42_bridge->driver_priv;
 271
 272         /* Enable IRQ level */
 273         tmp = ioread32(bridge->base + LINT_EN);
 274
 275         if (state == 0)
 276                 tmp &= ~CA91CX42_LINT_VIRQ[level];
 277         else
 278                 tmp |= CA91CX42_LINT_VIRQ[level];
 279
 280         iowrite32(tmp, bridge->base + LINT_EN);
 281
 282         if ((state == 0) && (sync != 0)) {
 283                 pdev = container_of(ca91cx42_bridge->parent, struct pci_dev,
 284                         dev);
 285
 286                 synchronize_irq(pdev->irq);
 287         }
 288 }
 289
 290 int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level,
 291         int statid)
 292 {
 293         u32 tmp;
 294         struct ca91cx42_driver *bridge;
 295
 296         bridge = ca91cx42_bridge->driver_priv;
 297
 298         /* Universe can only generate even vectors */
 299         if (statid & 1)
 300                 return -EINVAL;
 301
 302         mutex_lock(&(bridge->vme_int));
 303
 304         tmp = ioread32(bridge->base + VINT_EN);
 305
 306         /* Set Status/ID */
 307         iowrite32(statid << 24, bridge->base + STATID);
 308
 309         /* Assert VMEbus IRQ */
 310         tmp = tmp | (1 << (level + 24));
 311         iowrite32(tmp, bridge->base + VINT_EN);
 312
 313         /* Wait for IACK */
 314         wait_event_interruptible(bridge->iack_queue, 0);
 315
 316         /* Return interrupt to low state */
 317         tmp = ioread32(bridge->base + VINT_EN);
 318         tmp = tmp & ~(1 << (level + 24));
 319         iowrite32(tmp, bridge->base + VINT_EN);
 320
 321         mutex_unlock(&(bridge->vme_int));
 322
 323         return 0;
 324 }
 325
 326 int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled,
 327         unsigned long long vme_base, unsigned long long size,
 328         dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
 329 {
 330         unsigned int i, addr = 0, granularity;
 331         unsigned int temp_ctl = 0;
 332         unsigned int vme_bound, pci_offset;
 333         struct vme_bridge *ca91cx42_bridge;
 334         struct ca91cx42_driver *bridge;
 335
 336         ca91cx42_bridge = image->parent;
 337
 338         bridge = ca91cx42_bridge->driver_priv;
 339
 340         i = image->number;
 341
 342         switch (aspace) {
 343         case VME_A16:
 344                 addr |= CA91CX42_VSI_CTL_VAS_A16;
 345                 break;
 346         case VME_A24:
 347                 addr |= CA91CX42_VSI_CTL_VAS_A24;
 348                 break;
 349         case VME_A32:
 350                 addr |= CA91CX42_VSI_CTL_VAS_A32;
 351                 break;
 352         case VME_USER1:
 353                 addr |= CA91CX42_VSI_CTL_VAS_USER1;
 354                 break;
 355         case VME_USER2:
 356                 addr |= CA91CX42_VSI_CTL_VAS_USER2;
 357                 break;
 358         case VME_A64:
 359         case VME_CRCSR:
 360         case VME_USER3:
 361         case VME_USER4:
 362         default:
 363                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 364                 return -EINVAL;
 365                 break;
 366         }
 367
 368         /*
 369          * Bound address is a valid address for the window, adjust
 370          * accordingly
 371          */
 372         vme_bound = vme_base + size;
 373         pci_offset = pci_base - vme_base;
 374
 375         if ((i == 0) || (i == 4))
 376                 granularity = 0x1000;
 377         else
 378                 granularity = 0x10000;
 379
 380         if (vme_base & (granularity - 1)) {
 381                 dev_err(ca91cx42_bridge->parent, "Invalid VME base "
 382                         "alignment\n");
 383                 return -EINVAL;
 384         }
 385         if (vme_bound & (granularity - 1)) {
 386                 dev_err(ca91cx42_bridge->parent, "Invalid VME bound "
 387                         "alignment\n");
 388                 return -EINVAL;
 389         }
 390         if (pci_offset & (granularity - 1)) {
 391                 dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset "
 392                         "alignment\n");
 393                 return -EINVAL;
 394         }
 395
 396         /* Disable while we are mucking around */
 397         temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 398         temp_ctl &= ~CA91CX42_VSI_CTL_EN;
 399         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 400
 401         /* Setup mapping */
 402         iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]);
 403         iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]);
 404         iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]);
 405
 406         /* Setup address space */
 407         temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
 408         temp_ctl |= addr;
 409
 410         /* Setup cycle types */
 411         temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
 412         if (cycle & VME_SUPER)
 413                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
 414         if (cycle & VME_USER)
 415                 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
 416         if (cycle & VME_PROG)
 417                 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
 418         if (cycle & VME_DATA)
 419                 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
 420
 421         /* Write ctl reg without enable */
 422         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 423
 424         if (enabled)
 425                 temp_ctl |= CA91CX42_VSI_CTL_EN;
 426
 427         iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
 428
 429         return 0;
 430 }
 431
 432 int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled,
 433         unsigned long long *vme_base, unsigned long long *size,
 434         dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
 435 {
 436         unsigned int i, granularity = 0, ctl = 0;
 437         unsigned long long vme_bound, pci_offset;
 438         struct ca91cx42_driver *bridge;
 439
 440         bridge = image->parent->driver_priv;
 441
 442         i = image->number;
 443
 444         if ((i == 0) || (i == 4))
 445                 granularity = 0x1000;
 446         else
 447                 granularity = 0x10000;
 448
 449         /* Read Registers */
 450         ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
 451
 452         *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);
 453         vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]);
 454         pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]);
 455
 456         *pci_base = (dma_addr_t)vme_base + pci_offset;
 457         *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
 458
 459         *enabled = 0;
 460         *aspace = 0;
 461         *cycle = 0;
 462
 463         if (ctl & CA91CX42_VSI_CTL_EN)
 464                 *enabled = 1;
 465
 466         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
 467                 *aspace = VME_A16;
 468         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
 469                 *aspace = VME_A24;
 470         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
 471                 *aspace = VME_A32;
 472         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
 473                 *aspace = VME_USER1;
 474         if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
 475                 *aspace = VME_USER2;
 476
 477         if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
 478                 *cycle |= VME_SUPER;
 479         if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
 480                 *cycle |= VME_USER;
 481         if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
 482                 *cycle |= VME_PROG;
 483         if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
 484                 *cycle |= VME_DATA;
 485
 486         return 0;
 487 }
 488
 489 /*
 490  * Allocate and map PCI Resource
 491  */
 492 static int ca91cx42_alloc_resource(struct vme_master_resource *image,
 493         unsigned long long size)
 494 {
 495         unsigned long long existing_size;
 496         int retval = 0;
 497         struct pci_dev *pdev;
 498         struct vme_bridge *ca91cx42_bridge;
 499
 500         ca91cx42_bridge = image->parent;
 501
 502         /* Find pci_dev container of dev */
 503         if (ca91cx42_bridge->parent == NULL) {
 504                 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
 505                 return -EINVAL;
 506         }
 507         pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev);
 508
 509         existing_size = (unsigned long long)(image->bus_resource.end -
 510                 image->bus_resource.start);
 511
 512         /* If the existing size is OK, return */
 513         if (existing_size == (size - 1))
 514                 return 0;
 515
 516         if (existing_size != 0) {
 517                 iounmap(image->kern_base);
 518                 image->kern_base = NULL;
 519                 if (image->bus_resource.name != NULL)
 520                         kfree(image->bus_resource.name);
 521                 release_resource(&(image->bus_resource));
 522                 memset(&(image->bus_resource), 0, sizeof(struct resource));
 523         }
 524
 525         if (image->bus_resource.name == NULL) {
 526                 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
 527                 if (image->bus_resource.name == NULL) {
 528                         dev_err(ca91cx42_bridge->parent, "Unable to allocate "
 529                                 "memory for resource name\n");
 530                         retval = -ENOMEM;
 531                         goto err_name;
 532                 }
 533         }
 534
 535         sprintf((char *)image->bus_resource.name, "%s.%d",
 536                 ca91cx42_bridge->name, image->number);
 537
 538         image->bus_resource.start = 0;
 539         image->bus_resource.end = (unsigned long)size;
 540         image->bus_resource.flags = IORESOURCE_MEM;
 541
 542         retval = pci_bus_alloc_resource(pdev->bus,
 543                 &(image->bus_resource), size, size, PCIBIOS_MIN_MEM,
 544                 0, NULL, NULL);
 545         if (retval) {
 546                 dev_err(ca91cx42_bridge->parent, "Failed to allocate mem "
 547                         "resource for window %d size 0x%lx start 0x%lx\n",
 548                         image->number, (unsigned long)size,
 549                         (unsigned long)image->bus_resource.start);
 550                 goto err_resource;
 551         }
 552
 553         image->kern_base = ioremap_nocache(
 554                 image->bus_resource.start, size);
 555         if (image->kern_base == NULL) {
 556                 dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n");
 557                 retval = -ENOMEM;
 558                 goto err_remap;
 559         }
 560
 561         return 0;
 562
 563         iounmap(image->kern_base);
 564         image->kern_base = NULL;
 565 err_remap:
 566         release_resource(&(image->bus_resource));
 567 err_resource:
 568         kfree(image->bus_resource.name);
 569         memset(&(image->bus_resource), 0, sizeof(struct resource));
 570 err_name:
 571         return retval;
 572 }
 573
 574 /*
 575  * Free and unmap PCI Resource
 576  */
 577 static void ca91cx42_free_resource(struct vme_master_resource *image)
 578 {
 579         iounmap(image->kern_base);
 580         image->kern_base = NULL;
 581         release_resource(&(image->bus_resource));
 582         kfree(image->bus_resource.name);
 583         memset(&(image->bus_resource), 0, sizeof(struct resource));
 584 }
 585
 586
 587 int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
 588         unsigned long long vme_base, unsigned long long size,
 589         vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
 590 {
 591         int retval = 0;
 592         unsigned int i, granularity = 0;
 593         unsigned int temp_ctl = 0;
 594         unsigned long long pci_bound, vme_offset, pci_base;
 595         struct vme_bridge *ca91cx42_bridge;
 596         struct ca91cx42_driver *bridge;
 597
 598         ca91cx42_bridge = image->parent;
 599
 600         bridge = ca91cx42_bridge->driver_priv;
 601
 602         i = image->number;
 603
 604         if ((i == 0) || (i == 4))
 605                 granularity = 0x1000;
 606         else
 607                 granularity = 0x10000;
 608
 609         /* Verify input data */
 610         if (vme_base & (granularity - 1)) {
 611                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 612                         "alignment\n");
 613                 retval = -EINVAL;
 614                 goto err_window;
 615         }
 616         if (size & (granularity - 1)) {
 617                 dev_err(ca91cx42_bridge->parent, "Invalid VME Window "
 618                         "alignment\n");
 619                 retval = -EINVAL;
 620                 goto err_window;
 621         }
 622
 623         spin_lock(&(image->lock));
 624
 625         /*
 626          * Let's allocate the resource here rather than further up the stack as
 627          * it avoids pushing loads of bus dependant stuff up the stack
 628          */
 629         retval = ca91cx42_alloc_resource(image, size);
 630         if (retval) {
 631                 spin_unlock(&(image->lock));
 632                 dev_err(ca91cx42_bridge->parent, "Unable to allocate memory "
 633                         "for resource name\n");
 634                 retval = -ENOMEM;
 635                 goto err_res;
 636         }
 637
 638         pci_base = (unsigned long long)image->bus_resource.start;
 639
 640         /*
 641          * Bound address is a valid address for the window, adjust
 642          * according to window granularity.
 643          */
 644         pci_bound = pci_base + size;
 645         vme_offset = vme_base - pci_base;
 646
 647         /* Disable while we are mucking around */
 648         temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 649         temp_ctl &= ~CA91CX42_LSI_CTL_EN;
 650         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 651
 652         /* Setup cycle types */
 653         temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
 654         if (cycle & VME_BLT)
 655                 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
 656         if (cycle & VME_MBLT)
 657                 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
 658
 659         /* Setup data width */
 660         temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
 661         switch (dwidth) {
 662         case VME_D8:
 663                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
 664                 break;
 665         case VME_D16:
 666                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
 667                 break;
 668         case VME_D32:
 669                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
 670                 break;
 671         case VME_D64:
 672                 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
 673                 break;
 674         default:
 675                 spin_unlock(&(image->lock));
 676                 dev_err(ca91cx42_bridge->parent, "Invalid data width\n");
 677                 retval = -EINVAL;
 678                 goto err_dwidth;
 679                 break;
 680         }
 681
 682         /* Setup address space */
 683         temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
 684         switch (aspace) {
 685         case VME_A16:
 686                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
 687                 break;
 688         case VME_A24:
 689                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
 690                 break;
 691         case VME_A32:
 692                 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
 693                 break;
 694         case VME_CRCSR:
 695                 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
 696                 break;
 697         case VME_USER1:
 698                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
 699                 break;
 700         case VME_USER2:
 701                 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
 702                 break;
 703         case VME_A64:
 704         case VME_USER3:
 705         case VME_USER4:
 706         default:
 707                 spin_unlock(&(image->lock));
 708                 dev_err(ca91cx42_bridge->parent, "Invalid address space\n");
 709                 retval = -EINVAL;
 710                 goto err_aspace;
 711                 break;
 712         }
 713
 714         temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
 715         if (cycle & VME_SUPER)
 716                 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
 717         if (cycle & VME_PROG)
 718                 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
 719
 720         /* Setup mapping */
 721         iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]);
 722         iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]);
 723         iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]);
 724
 725         /* Write ctl reg without enable */
 726         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 727
 728         if (enabled)
 729                 temp_ctl |= CA91CX42_LSI_CTL_EN;
 730
 731         iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
 732
 733         spin_unlock(&(image->lock));
 734         return 0;
 735
 736 err_aspace:
 737 err_dwidth:
 738         ca91cx42_free_resource(image);
 739 err_res:
 740 err_window:
 741         return retval;
 742 }
 743
 744 int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 745         unsigned long long *vme_base, unsigned long long *size,
 746         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 747 {
 748         unsigned int i, ctl;
 749         unsigned long long pci_base, pci_bound, vme_offset;
 750         struct ca91cx42_driver *bridge;
 751
 752         bridge = image->parent->driver_priv;
 753
 754         i = image->number;
 755
 756         ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
 757
 758         pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]);
 759         vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]);
 760         pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]);
 761
 762         *vme_base = pci_base + vme_offset;
 763         *size = (unsigned long long)(pci_bound - pci_base);
 764
 765         *enabled = 0;
 766         *aspace = 0;
 767         *cycle = 0;
 768         *dwidth = 0;
 769
 770         if (ctl & CA91CX42_LSI_CTL_EN)
 771                 *enabled = 1;
 772
 773         /* Setup address space */
 774         switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
 775         case CA91CX42_LSI_CTL_VAS_A16:
 776                 *aspace = VME_A16;
 777                 break;
 778         case CA91CX42_LSI_CTL_VAS_A24:
 779                 *aspace = VME_A24;
 780                 break;
 781         case CA91CX42_LSI_CTL_VAS_A32:
 782                 *aspace = VME_A32;
 783                 break;
 784         case CA91CX42_LSI_CTL_VAS_CRCSR:
 785                 *aspace = VME_CRCSR;
 786                 break;
 787         case CA91CX42_LSI_CTL_VAS_USER1:
 788                 *aspace = VME_USER1;
 789                 break;
 790         case CA91CX42_LSI_CTL_VAS_USER2:
 791                 *aspace = VME_USER2;
 792                 break;
 793         }
 794
 795         /* XXX Not sure howto check for MBLT */
 796         /* Setup cycle types */
 797         if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
 798                 *cycle |= VME_BLT;
 799         else
 800                 *cycle |= VME_SCT;
 801
 802         if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
 803                 *cycle |= VME_SUPER;
 804         else
 805                 *cycle |= VME_USER;
 806
 807         if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
 808                 *cycle = VME_PROG;
 809         else
 810                 *cycle = VME_DATA;
 811
 812         /* Setup data width */
 813         switch (ctl & CA91CX42_LSI_CTL_VDW_M) {
 814         case CA91CX42_LSI_CTL_VDW_D8:
 815                 *dwidth = VME_D8;
 816                 break;
 817         case CA91CX42_LSI_CTL_VDW_D16:
 818                 *dwidth = VME_D16;
 819                 break;
 820         case CA91CX42_LSI_CTL_VDW_D32:
 821                 *dwidth = VME_D32;
 822                 break;
 823         case CA91CX42_LSI_CTL_VDW_D64:
 824                 *dwidth = VME_D64;
 825                 break;
 826         }
 827
 828         return 0;
 829 }
 830
 831 int ca91cx42_master_get(struct vme_master_resource *image, int *enabled,
 832         unsigned long long *vme_base, unsigned long long *size,
 833         vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
 834 {
 835         int retval;
 836
 837         spin_lock(&(image->lock));
 838
 839         retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace,
 840                 cycle, dwidth);
 841
 842         spin_unlock(&(image->lock));
 843
 844         return retval;
 845 }
 846
 847 ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf,
 848         size_t count, loff_t offset)
 849 {
 850         ssize_t retval;
 851
 852         spin_lock(&(image->lock));
 853
 854         memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
 855         retval = count;
 856
 857         spin_unlock(&(image->lock));
 858
 859         return retval;
 860 }
 861
 862 ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf,
 863         size_t count, loff_t offset)
 864 {
 865         int retval = 0;
 866
 867         spin_lock(&(image->lock));
 868
 869         memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
 870         retval = count;
 871
 872         spin_unlock(&(image->lock));
 873
 874         return retval;
 875 }
 876
 877 unsigned int ca91cx42_master_rmw(struct vme_master_resource *image,
 878         unsigned int mask, unsigned int compare, unsigned int swap,
 879         loff_t offset)
 880 {
 881         u32 pci_addr, result;
 882         int i;
 883         struct ca91cx42_driver *bridge;
 884         struct device *dev;
 885
 886         bridge = image->parent->driver_priv;
 887         dev = image->parent->parent;
 888
 889         /* Find the PCI address that maps to the desired VME address */
 890         i = image->number;
 891
 892         /* Locking as we can only do one of these at a time */
 893         mutex_lock(&(bridge->vme_rmw));
 894
 895         /* Lock image */
 896         spin_lock(&(image->lock));
 897
 898         pci_addr = (u32)image->kern_base + offset;
 899
 900         /* Address must be 4-byte aligned */
 901         if (pci_addr & 0x3) {
 902                 dev_err(dev, "RMW Address not 4-byte aligned\n");
 903                 return -EINVAL;
 904         }
 905
 906         /* Ensure RMW Disabled whilst configuring */
 907         iowrite32(0, bridge->base + SCYC_CTL);
 908
 909         /* Configure registers */
 910         iowrite32(mask, bridge->base + SCYC_EN);
 911         iowrite32(compare, bridge->base + SCYC_CMP);
 912         iowrite32(swap, bridge->base + SCYC_SWP);
 913         iowrite32(pci_addr, bridge->base + SCYC_ADDR);
 914
 915         /* Enable RMW */
 916         iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL);
 917
 918         /* Kick process off with a read to the required address. */
 919         result = ioread32(image->kern_base + offset);
 920
 921         /* Disable RMW */
 922         iowrite32(0, bridge->base + SCYC_CTL);
 923
 924         spin_unlock(&(image->lock));
 925
 926         mutex_unlock(&(bridge->vme_rmw));
 927
 928         return result;
 929 }
 930
 931 int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src,
 932         struct vme_dma_attr *dest, size_t count)
 933 {
 934         struct ca91cx42_dma_entry *entry, *prev;
 935         struct vme_dma_pci *pci_attr;
 936         struct vme_dma_vme *vme_attr;
 937         dma_addr_t desc_ptr;
 938         int retval = 0;
 939         struct device *dev;
 940
 941         dev = list->parent->parent->parent;
 942
 943         /* XXX descriptor must be aligned on 64-bit boundaries */
 944         entry = (struct ca91cx42_dma_entry *)
 945                 kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL);
 946         if (entry == NULL) {
 947                 dev_err(dev, "Failed to allocate memory for dma resource "
 948                         "structure\n");
 949                 retval = -ENOMEM;
 950                 goto err_mem;
 951         }
 952
 953         /* Test descriptor alignment */
 954         if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) {
 955                 dev_err(dev, "Descriptor not aligned to 16 byte boundary as "
 956                         "required: %p\n", &(entry->descriptor));
 957                 retval = -EINVAL;
 958                 goto err_align;
 959         }
 960
 961         memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor));
 962
 963         if (dest->type == VME_DMA_VME) {
 964                 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
 965                 vme_attr = (struct vme_dma_vme *)dest->private;
 966                 pci_attr = (struct vme_dma_pci *)src->private;
 967         } else {
 968                 vme_attr = (struct vme_dma_vme *)src->private;
 969                 pci_attr = (struct vme_dma_pci *)dest->private;
 970         }
 971
 972         /* Check we can do fullfill required attributes */
 973         if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
 974                 VME_USER2)) != 0) {
 975
 976                 dev_err(dev, "Unsupported cycle type\n");
 977                 retval = -EINVAL;
 978                 goto err_aspace;
 979         }
 980
 981         if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER |
 982                 VME_PROG | VME_DATA)) != 0) {
 983
 984                 dev_err(dev, "Unsupported cycle type\n");
 985                 retval = -EINVAL;
 986                 goto err_cycle;
 987         }
 988
 989         /* Check to see if we can fullfill source and destination */
 990         if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
 991                 ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
 992
 993                 dev_err(dev, "Cannot perform transfer with this "
 994                         "source-destination combination\n");
 995                 retval = -EINVAL;
 996                 goto err_direct;
 997         }
 998
 999         /* Setup cycle types */
1000         if (vme_attr->cycle & VME_BLT)
1001                 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1002
1003         /* Setup data width */
1004         switch (vme_attr->dwidth) {
1005         case VME_D8:
1006                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1007                 break;
1008         case VME_D16:
1009                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1010                 break;
1011         case VME_D32:
1012                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1013                 break;
1014         case VME_D64:
1015                 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1016                 break;
1017         default:
1018                 dev_err(dev, "Invalid data width\n");
1019                 return -EINVAL;
1020         }
1021
1022         /* Setup address space */
1023         switch (vme_attr->aspace) {
1024         case VME_A16:
1025                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1026                 break;
1027         case VME_A24:
1028                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1029                 break;
1030         case VME_A32:
1031                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1032                 break;
1033         case VME_USER1:
1034                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1035                 break;
1036         case VME_USER2:
1037                 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1038                 break;
1039         default:
1040                 dev_err(dev, "Invalid address space\n");
1041                 return -EINVAL;
1042                 break;
1043         }
1044
1045         if (vme_attr->cycle & VME_SUPER)
1046                 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1047         if (vme_attr->cycle & VME_PROG)
1048                 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1049
1050         entry->descriptor.dtbc = count;
1051         entry->descriptor.dla = pci_attr->address;
1052         entry->descriptor.dva = vme_attr->address;
1053         entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1054
1055         /* Add to list */
1056         list_add_tail(&(entry->list), &(list->entries));
1057
1058         /* Fill out previous descriptors "Next Address" */
1059         if (entry->list.prev != &(list->entries)) {
1060                 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1061                         list);
1062                 /* We need the bus address for the pointer */
1063                 desc_ptr = virt_to_bus(&(entry->descriptor));
1064                 prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M;
1065         }
1066
1067         return 0;
1068
1069 err_cycle:
1070 err_aspace:
1071 err_direct:
1072 err_align:
1073         kfree(entry);
1074 err_mem:
1075         return retval;
1076 }
1077
1078 static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge)
1079 {
1080         u32 tmp;
1081         struct ca91cx42_driver *bridge;
1082
1083         bridge = ca91cx42_bridge->driver_priv;
1084
1085         tmp = ioread32(bridge->base + DGCS);
1086
1087         if (tmp & CA91CX42_DGCS_ACT)
1088                 return 0;
1089         else
1090                 return 1;
1091 }
1092
1093 int ca91cx42_dma_list_exec(struct vme_dma_list *list)
1094 {
1095         struct vme_dma_resource *ctrlr;
1096         struct ca91cx42_dma_entry *entry;
1097         int retval = 0;
1098         dma_addr_t bus_addr;
1099         u32 val;
1100         struct device *dev;
1101         struct ca91cx42_driver *bridge;
1102
1103         ctrlr = list->parent;
1104
1105         bridge = ctrlr->parent->driver_priv;
1106         dev = ctrlr->parent->parent;
1107
1108         mutex_lock(&(ctrlr->mtx));
1109
1110         if (!(list_empty(&(ctrlr->running)))) {
1111                 /*
1112                  * XXX We have an active DMA transfer and currently haven't
1113                  *     sorted out the mechanism for "pending" DMA transfers.
1114                  *     Return busy.
1115                  */
1116                 /* Need to add to pending here */
1117                 mutex_unlock(&(ctrlr->mtx));
1118                 return -EBUSY;
1119         } else {
1120                 list_add(&(list->list), &(ctrlr->running));
1121         }
1122
1123         /* Get first bus address and write into registers */
1124         entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry,
1125                 list);
1126
1127         bus_addr = virt_to_bus(&(entry->descriptor));
1128
1129         mutex_unlock(&(ctrlr->mtx));
1130
1131         iowrite32(0, bridge->base + DTBC);
1132         iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP);
1133
1134         /* Start the operation */
1135         val = ioread32(bridge->base + DGCS);
1136
1137         /* XXX Could set VMEbus On and Off Counters here */
1138         val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M);
1139
1140         val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT |
1141                 CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1142                 CA91CX42_DGCS_PERR);
1143
1144         iowrite32(val, bridge->base + DGCS);
1145
1146         val |= CA91CX42_DGCS_GO;
1147
1148         iowrite32(val, bridge->base + DGCS);
1149
1150         wait_event_interruptible(bridge->dma_queue,
1151                 ca91cx42_dma_busy(ctrlr->parent));
1152
1153         /*
1154          * Read status register, this register is valid until we kick off a
1155          * new transfer.
1156          */
1157         val = ioread32(bridge->base + DGCS);
1158
1159         if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR |
1160                 CA91CX42_DGCS_PERR)) {
1161
1162                 dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val);
1163                 val = ioread32(bridge->base + DCTL);
1164         }
1165
1166         /* Remove list from running list */
1167         mutex_lock(&(ctrlr->mtx));
1168         list_del(&(list->list));
1169         mutex_unlock(&(ctrlr->mtx));
1170
1171         return retval;
1172
1173 }
1174
1175 int ca91cx42_dma_list_empty(struct vme_dma_list *list)
1176 {
1177         struct list_head *pos, *temp;
1178         struct ca91cx42_dma_entry *entry;
1179
1180         /* detach and free each entry */
1181         list_for_each_safe(pos, temp, &(list->entries)) {
1182                 list_del(pos);
1183                 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1184                 kfree(entry);
1185         }
1186
1187         return 0;
1188 }
1189
1190 /*
1191  * All 4 location monitors reside at the same base - this is therefore a
1192  * system wide configuration.
1193  *
1194  * This does not enable the LM monitor - that should be done when the first
1195  * callback is attached and disabled when the last callback is removed.
1196  */
1197 int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1198         vme_address_t aspace, vme_cycle_t cycle)
1199 {
1200         u32 temp_base, lm_ctl = 0;
1201         int i;
1202         struct ca91cx42_driver *bridge;
1203         struct device *dev;
1204
1205         bridge = lm->parent->driver_priv;
1206         dev = lm->parent->parent;
1207
1208         /* Check the alignment of the location monitor */
1209         temp_base = (u32)lm_base;
1210         if (temp_base & 0xffff) {
1211                 dev_err(dev, "Location monitor must be aligned to 64KB "
1212                         "boundary");
1213                 return -EINVAL;
1214         }
1215
1216         mutex_lock(&(lm->mtx));
1217
1218         /* If we already have a callback attached, we can't move it! */
1219         for (i = 0; i < lm->monitors; i++) {
1220                 if (bridge->lm_callback[i] != NULL) {
1221                         mutex_unlock(&(lm->mtx));
1222                         dev_err(dev, "Location monitor callback attached, "
1223                                 "can't reset\n");
1224                         return -EBUSY;
1225                 }
1226         }
1227
1228         switch (aspace) {
1229         case VME_A16:
1230                 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1231                 break;
1232         case VME_A24:
1233                 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1234                 break;
1235         case VME_A32:
1236                 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1237                 break;
1238         default:
1239                 mutex_unlock(&(lm->mtx));
1240                 dev_err(dev, "Invalid address space\n");
1241                 return -EINVAL;
1242                 break;
1243         }
1244
1245         if (cycle & VME_SUPER)
1246                 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1247         if (cycle & VME_USER)
1248                 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1249         if (cycle & VME_PROG)
1250                 lm_ctl |= CA91CX42_LM_CTL_PGM;
1251         if (cycle & VME_DATA)
1252                 lm_ctl |= CA91CX42_LM_CTL_DATA;
1253
1254         iowrite32(lm_base, bridge->base + LM_BS);
1255         iowrite32(lm_ctl, bridge->base + LM_CTL);
1256
1257         mutex_unlock(&(lm->mtx));
1258
1259         return 0;
1260 }
1261
1262 /* Get configuration of the callback monitor and return whether it is enabled
1263  * or disabled.
1264  */
1265 int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
1266         vme_address_t *aspace, vme_cycle_t *cycle)
1267 {
1268         u32 lm_ctl, enabled = 0;
1269         struct ca91cx42_driver *bridge;
1270
1271         bridge = lm->parent->driver_priv;
1272
1273         mutex_lock(&(lm->mtx));
1274
1275         *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS);
1276         lm_ctl = ioread32(bridge->base + LM_CTL);
1277
1278         if (lm_ctl & CA91CX42_LM_CTL_EN)
1279                 enabled = 1;
1280
1281         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1282                 *aspace = VME_A16;
1283         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1284                 *aspace = VME_A24;
1285         if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1286                 *aspace = VME_A32;
1287
1288         *cycle = 0;
1289         if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1290                 *cycle |= VME_SUPER;
1291         if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1292                 *cycle |= VME_USER;
1293         if (lm_ctl & CA91CX42_LM_CTL_PGM)
1294                 *cycle |= VME_PROG;
1295         if (lm_ctl & CA91CX42_LM_CTL_DATA)
1296                 *cycle |= VME_DATA;
1297
1298         mutex_unlock(&(lm->mtx));
1299
1300         return enabled;
1301 }
1302
1303 /*
1304  * Attach a callback to a specific location monitor.
1305  *
1306  * Callback will be passed the monitor triggered.
1307  */
1308 int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor,
1309         void (*callback)(int))
1310 {
1311         u32 lm_ctl, tmp;
1312         struct ca91cx42_driver *bridge;
1313         struct device *dev;
1314
1315         bridge = lm->parent->driver_priv;
1316         dev = lm->parent->parent;
1317
1318         mutex_lock(&(lm->mtx));
1319
1320         /* Ensure that the location monitor is configured - need PGM or DATA */
1321         lm_ctl = ioread32(bridge->base + LM_CTL);
1322         if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1323                 mutex_unlock(&(lm->mtx));
1324                 dev_err(dev, "Location monitor not properly configured\n");
1325                 return -EINVAL;
1326         }
1327
1328         /* Check that a callback isn't already attached */
1329         if (bridge->lm_callback[monitor] != NULL) {
1330                 mutex_unlock(&(lm->mtx));
1331                 dev_err(dev, "Existing callback attached\n");
1332                 return -EBUSY;
1333         }
1334
1335         /* Attach callback */
1336         bridge->lm_callback[monitor] = callback;
1337
1338         /* Enable Location Monitor interrupt */
1339         tmp = ioread32(bridge->base + LINT_EN);
1340         tmp |= CA91CX42_LINT_LM[monitor];
1341         iowrite32(tmp, bridge->base + LINT_EN);
1342
1343         /* Ensure that global Location Monitor Enable set */
1344         if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1345                 lm_ctl |= CA91CX42_LM_CTL_EN;
1346                 iowrite32(lm_ctl, bridge->base + LM_CTL);
1347         }
1348
1349         mutex_unlock(&(lm->mtx));
1350
1351         return 0;
1352 }
1353
1354 /*
1355  * Detach a callback function forn a specific location monitor.
1356  */
1357 int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor)
1358 {
1359         u32 tmp;
1360         struct ca91cx42_driver *bridge;
1361
1362         bridge = lm->parent->driver_priv;
1363
1364         mutex_lock(&(lm->mtx));
1365
1366         /* Disable Location Monitor and ensure previous interrupts are clear */
1367         tmp = ioread32(bridge->base + LINT_EN);
1368         tmp &= ~CA91CX42_LINT_LM[monitor];
1369         iowrite32(tmp, bridge->base + LINT_EN);
1370
1371         iowrite32(CA91CX42_LINT_LM[monitor],
1372                  bridge->base + LINT_STAT);
1373
1374         /* Detach callback */
1375         bridge->lm_callback[monitor] = NULL;
1376
1377         /* If all location monitors disabled, disable global Location Monitor */
1378         if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 |
1379                         CA91CX42_LINT_LM3)) == 0) {
1380                 tmp = ioread32(bridge->base + LM_CTL);
1381                 tmp &= ~CA91CX42_LM_CTL_EN;
1382                 iowrite32(tmp, bridge->base + LM_CTL);
1383         }
1384
1385         mutex_unlock(&(lm->mtx));
1386
1387         return 0;
1388 }
1389
1390 int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge)
1391 {
1392         u32 slot = 0;
1393         struct ca91cx42_driver *bridge;
1394
1395         bridge = ca91cx42_bridge->driver_priv;
1396
1397         if (!geoid) {
1398                 slot = ioread32(bridge->base + VCSR_BS);
1399                 slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27);
1400         } else
1401                 slot = geoid;
1402
1403         return (int)slot;
1404
1405 }
1406
1407 static int __init ca91cx42_init(void)
1408 {
1409         return pci_register_driver(&ca91cx42_driver);
1410 }
1411
1412 /*
1413  * Configure CR/CSR space
1414  *
1415  * Access to the CR/CSR can be configured at power-up. The location of the
1416  * CR/CSR registers in the CR/CSR address space is determined by the boards
1417  * Auto-ID or Geographic address. This function ensures that the window is
1418  * enabled at an offset consistent with the boards geopgraphic address.
1419  */
1420 static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge,
1421         struct pci_dev *pdev)
1422 {
1423         unsigned int crcsr_addr;
1424         int tmp, slot;
1425         struct ca91cx42_driver *bridge;
1426
1427         bridge = ca91cx42_bridge->driver_priv;
1428
1429         slot = ca91cx42_slot_get(ca91cx42_bridge);
1430
1431         /* Write CSR Base Address if slot ID is supplied as a module param */
1432         if (geoid)
1433                 iowrite32(geoid << 27, bridge->base + VCSR_BS);
1434
1435         dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot);
1436         if (slot == 0) {
1437                 dev_err(&pdev->dev, "Slot number is unset, not configuring "
1438                         "CR/CSR space\n");
1439                 return -EINVAL;
1440         }
1441
1442         /* Allocate mem for CR/CSR image */
1443         bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
1444                 &(bridge->crcsr_bus));
1445         if (bridge->crcsr_kernel == NULL) {
1446                 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
1447                         "image\n");
1448                 return -ENOMEM;
1449         }
1450
1451         memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
1452
1453         crcsr_addr = slot * (512 * 1024);
1454         iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO);
1455
1456         tmp = ioread32(bridge->base + VCSR_CTL);
1457         tmp |= CA91CX42_VCSR_CTL_EN;
1458         iowrite32(tmp, bridge->base + VCSR_CTL);
1459
1460         return 0;
1461 }
1462
1463 static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge,
1464         struct pci_dev *pdev)
1465 {
1466         u32 tmp;
1467         struct ca91cx42_driver *bridge;
1468
1469         bridge = ca91cx42_bridge->driver_priv;
1470
1471         /* Turn off CR/CSR space */
1472         tmp = ioread32(bridge->base + VCSR_CTL);
1473         tmp &= ~CA91CX42_VCSR_CTL_EN;
1474         iowrite32(tmp, bridge->base + VCSR_CTL);
1475
1476         /* Free image */
1477         iowrite32(0, bridge->base + VCSR_TO);
1478
1479         pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
1480                 bridge->crcsr_bus);
1481 }
1482
1483 static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1484 {
1485         int retval, i;
1486         u32 data;
1487         struct list_head *pos = NULL;
1488         struct vme_bridge *ca91cx42_bridge;
1489         struct ca91cx42_driver *ca91cx42_device;
1490         struct vme_master_resource *master_image;
1491         struct vme_slave_resource *slave_image;
1492         struct vme_dma_resource *dma_ctrlr;
1493         struct vme_lm_resource *lm;
1494
1495         /* We want to support more than one of each bridge so we need to
1496          * dynamically allocate the bridge structure
1497          */
1498         ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL);
1499
1500         if (ca91cx42_bridge == NULL) {
1501                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1502                         "structure\n");
1503                 retval = -ENOMEM;
1504                 goto err_struct;
1505         }
1506
1507         memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge));
1508
1509         ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL);
1510
1511         if (ca91cx42_device == NULL) {
1512                 dev_err(&pdev->dev, "Failed to allocate memory for device "
1513                         "structure\n");
1514                 retval = -ENOMEM;
1515                 goto err_driver;
1516         }
1517
1518         memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver));
1519
1520         ca91cx42_bridge->driver_priv = ca91cx42_device;
1521
1522         /* Enable the device */
1523         retval = pci_enable_device(pdev);
1524         if (retval) {
1525                 dev_err(&pdev->dev, "Unable to enable device\n");
1526                 goto err_enable;
1527         }
1528
1529         /* Map Registers */
1530         retval = pci_request_regions(pdev, driver_name);
1531         if (retval) {
1532                 dev_err(&pdev->dev, "Unable to reserve resources\n");
1533                 goto err_resource;
1534         }
1535
1536         /* map registers in BAR 0 */
1537         ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
1538                 4096);
1539         if (!ca91cx42_device->base) {
1540                 dev_err(&pdev->dev, "Unable to remap CRG region\n");
1541                 retval = -EIO;
1542                 goto err_remap;
1543         }
1544
1545         /* Check to see if the mapping worked out */
1546         data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF;
1547         if (data != PCI_VENDOR_ID_TUNDRA) {
1548                 dev_err(&pdev->dev, "PCI_ID check failed\n");
1549                 retval = -EIO;
1550                 goto err_test;
1551         }
1552
1553         /* Initialize wait queues & mutual exclusion flags */
1554         init_waitqueue_head(&(ca91cx42_device->dma_queue));
1555         init_waitqueue_head(&(ca91cx42_device->iack_queue));
1556         mutex_init(&(ca91cx42_device->vme_int));
1557         mutex_init(&(ca91cx42_device->vme_rmw));
1558
1559         ca91cx42_bridge->parent = &(pdev->dev);
1560         strcpy(ca91cx42_bridge->name, driver_name);
1561
1562         /* Setup IRQ */
1563         retval = ca91cx42_irq_init(ca91cx42_bridge);
1564         if (retval != 0) {
1565                 dev_err(&pdev->dev, "Chip Initialization failed.\n");
1566                 goto err_irq;
1567         }
1568
1569         /* Add master windows to list */
1570         INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources));
1571         for (i = 0; i < CA91C142_MAX_MASTER; i++) {
1572                 master_image = kmalloc(sizeof(struct vme_master_resource),
1573                         GFP_KERNEL);
1574                 if (master_image == NULL) {
1575                         dev_err(&pdev->dev, "Failed to allocate memory for "
1576                         "master resource structure\n");
1577                         retval = -ENOMEM;
1578                         goto err_master;
1579                 }
1580                 master_image->parent = ca91cx42_bridge;
1581                 spin_lock_init(&(master_image->lock));
1582                 master_image->locked = 0;
1583                 master_image->number = i;
1584                 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
1585                         VME_CRCSR | VME_USER1 | VME_USER2;
1586                 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1587                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1588                 master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64;
1589                 memset(&(master_image->bus_resource), 0,
1590                         sizeof(struct resource));
1591                 master_image->kern_base  = NULL;
1592                 list_add_tail(&(master_image->list),
1593                         &(ca91cx42_bridge->master_resources));
1594         }
1595
1596         /* Add slave windows to list */
1597         INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources));
1598         for (i = 0; i < CA91C142_MAX_SLAVE; i++) {
1599                 slave_image = kmalloc(sizeof(struct vme_slave_resource),
1600                         GFP_KERNEL);
1601                 if (slave_image == NULL) {
1602                         dev_err(&pdev->dev, "Failed to allocate memory for "
1603                         "slave resource structure\n");
1604                         retval = -ENOMEM;
1605                         goto err_slave;
1606                 }
1607                 slave_image->parent = ca91cx42_bridge;
1608                 mutex_init(&(slave_image->mtx));
1609                 slave_image->locked = 0;
1610                 slave_image->number = i;
1611                 slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 |
1612                         VME_USER2;
1613
1614                 /* Only windows 0 and 4 support A16 */
1615                 if (i == 0 || i == 4)
1616                         slave_image->address_attr |= VME_A16;
1617
1618                 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
1619                         VME_SUPER | VME_USER | VME_PROG | VME_DATA;
1620                 list_add_tail(&(slave_image->list),
1621                         &(ca91cx42_bridge->slave_resources));
1622         }
1623
1624         /* Add dma engines to list */
1625         INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources));
1626         for (i = 0; i < CA91C142_MAX_DMA; i++) {
1627                 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
1628                         GFP_KERNEL);
1629                 if (dma_ctrlr == NULL) {
1630                         dev_err(&pdev->dev, "Failed to allocate memory for "
1631                         "dma resource structure\n");
1632                         retval = -ENOMEM;
1633                         goto err_dma;
1634                 }
1635                 dma_ctrlr->parent = ca91cx42_bridge;
1636                 mutex_init(&(dma_ctrlr->mtx));
1637                 dma_ctrlr->locked = 0;
1638                 dma_ctrlr->number = i;
1639                 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
1640                         VME_DMA_MEM_TO_VME;
1641                 INIT_LIST_HEAD(&(dma_ctrlr->pending));
1642                 INIT_LIST_HEAD(&(dma_ctrlr->running));
1643                 list_add_tail(&(dma_ctrlr->list),
1644                         &(ca91cx42_bridge->dma_resources));
1645         }
1646
1647         /* Add location monitor to list */
1648         INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources));
1649         lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
1650         if (lm == NULL) {
1651                 dev_err(&pdev->dev, "Failed to allocate memory for "
1652                 "location monitor resource structure\n");
1653                 retval = -ENOMEM;
1654                 goto err_lm;
1655         }
1656         lm->parent = ca91cx42_bridge;
1657         mutex_init(&(lm->mtx));
1658         lm->locked = 0;
1659         lm->number = 1;
1660         lm->monitors = 4;
1661         list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources));
1662
1663         ca91cx42_bridge->slave_get = ca91cx42_slave_get;
1664         ca91cx42_bridge->slave_set = ca91cx42_slave_set;
1665         ca91cx42_bridge->master_get = ca91cx42_master_get;
1666         ca91cx42_bridge->master_set = ca91cx42_master_set;
1667         ca91cx42_bridge->master_read = ca91cx42_master_read;
1668         ca91cx42_bridge->master_write = ca91cx42_master_write;
1669         ca91cx42_bridge->master_rmw = ca91cx42_master_rmw;
1670         ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add;
1671         ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec;
1672         ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty;
1673         ca91cx42_bridge->irq_set = ca91cx42_irq_set;
1674         ca91cx42_bridge->irq_generate = ca91cx42_irq_generate;
1675         ca91cx42_bridge->lm_set = ca91cx42_lm_set;
1676         ca91cx42_bridge->lm_get = ca91cx42_lm_get;
1677         ca91cx42_bridge->lm_attach = ca91cx42_lm_attach;
1678         ca91cx42_bridge->lm_detach = ca91cx42_lm_detach;
1679         ca91cx42_bridge->slot_get = ca91cx42_slot_get;
1680
1681         data = ioread32(ca91cx42_device->base + MISC_CTL);
1682         dev_info(&pdev->dev, "Board is%s the VME system controller\n",
1683                 (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not");
1684         dev_info(&pdev->dev, "Slot ID is %d\n",
1685                 ca91cx42_slot_get(ca91cx42_bridge));
1686
1687         if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev))
1688                 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
1689
1690         /* Need to save ca91cx42_bridge pointer locally in link list for use in
1691          * ca91cx42_remove()
1692          */
1693         retval = vme_register_bridge(ca91cx42_bridge);
1694         if (retval != 0) {
1695                 dev_err(&pdev->dev, "Chip Registration failed.\n");
1696                 goto err_reg;
1697         }
1698
1699         pci_set_drvdata(pdev, ca91cx42_bridge);
1700
1701         return 0;
1702
1703         vme_unregister_bridge(ca91cx42_bridge);
1704 err_reg:
1705         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1706 err_lm:
1707         /* resources are stored in link list */
1708         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1709                 lm = list_entry(pos, struct vme_lm_resource, list);
1710                 list_del(pos);
1711                 kfree(lm);
1712         }
1713 err_dma:
1714         /* resources are stored in link list */
1715         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1716                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1717                 list_del(pos);
1718                 kfree(dma_ctrlr);
1719         }
1720 err_slave:
1721         /* resources are stored in link list */
1722         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1723                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1724                 list_del(pos);
1725                 kfree(slave_image);
1726         }
1727 err_master:
1728         /* resources are stored in link list */
1729         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1730                 master_image = list_entry(pos, struct vme_master_resource,
1731                         list);
1732                 list_del(pos);
1733                 kfree(master_image);
1734         }
1735
1736         ca91cx42_irq_exit(ca91cx42_device, pdev);
1737 err_irq:
1738 err_test:
1739         iounmap(ca91cx42_device->base);
1740 err_remap:
1741         pci_release_regions(pdev);
1742 err_resource:
1743         pci_disable_device(pdev);
1744 err_enable:
1745         kfree(ca91cx42_device);
1746 err_driver:
1747         kfree(ca91cx42_bridge);
1748 err_struct:
1749         return retval;
1750
1751 }
1752
1753 void ca91cx42_remove(struct pci_dev *pdev)
1754 {
1755         struct list_head *pos = NULL;
1756         struct vme_master_resource *master_image;
1757         struct vme_slave_resource *slave_image;
1758         struct vme_dma_resource *dma_ctrlr;
1759         struct vme_lm_resource *lm;
1760         struct ca91cx42_driver *bridge;
1761         struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev);
1762
1763         bridge = ca91cx42_bridge->driver_priv;
1764
1765
1766         /* Turn off Ints */
1767         iowrite32(0, bridge->base + LINT_EN);
1768
1769         /* Turn off the windows */
1770         iowrite32(0x00800000, bridge->base + LSI0_CTL);
1771         iowrite32(0x00800000, bridge->base + LSI1_CTL);
1772         iowrite32(0x00800000, bridge->base + LSI2_CTL);
1773         iowrite32(0x00800000, bridge->base + LSI3_CTL);
1774         iowrite32(0x00800000, bridge->base + LSI4_CTL);
1775         iowrite32(0x00800000, bridge->base + LSI5_CTL);
1776         iowrite32(0x00800000, bridge->base + LSI6_CTL);
1777         iowrite32(0x00800000, bridge->base + LSI7_CTL);
1778         iowrite32(0x00F00000, bridge->base + VSI0_CTL);
1779         iowrite32(0x00F00000, bridge->base + VSI1_CTL);
1780         iowrite32(0x00F00000, bridge->base + VSI2_CTL);
1781         iowrite32(0x00F00000, bridge->base + VSI3_CTL);
1782         iowrite32(0x00F00000, bridge->base + VSI4_CTL);
1783         iowrite32(0x00F00000, bridge->base + VSI5_CTL);
1784         iowrite32(0x00F00000, bridge->base + VSI6_CTL);
1785         iowrite32(0x00F00000, bridge->base + VSI7_CTL);
1786
1787         vme_unregister_bridge(ca91cx42_bridge);
1788
1789         ca91cx42_crcsr_exit(ca91cx42_bridge, pdev);
1790
1791         /* resources are stored in link list */
1792         list_for_each(pos, &(ca91cx42_bridge->lm_resources)) {
1793                 lm = list_entry(pos, struct vme_lm_resource, list);
1794                 list_del(pos);
1795                 kfree(lm);
1796         }
1797
1798         /* resources are stored in link list */
1799         list_for_each(pos, &(ca91cx42_bridge->dma_resources)) {
1800                 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
1801                 list_del(pos);
1802                 kfree(dma_ctrlr);
1803         }
1804
1805         /* resources are stored in link list */
1806         list_for_each(pos, &(ca91cx42_bridge->slave_resources)) {
1807                 slave_image = list_entry(pos, struct vme_slave_resource, list);
1808                 list_del(pos);
1809                 kfree(slave_image);
1810         }
1811
1812         /* resources are stored in link list */
1813         list_for_each(pos, &(ca91cx42_bridge->master_resources)) {
1814                 master_image = list_entry(pos, struct vme_master_resource,
1815                         list);
1816                 list_del(pos);
1817                 kfree(master_image);
1818         }
1819
1820         ca91cx42_irq_exit(bridge, pdev);
1821
1822         iounmap(bridge->base);
1823
1824         pci_release_regions(pdev);
1825
1826         pci_disable_device(pdev);
1827
1828         kfree(ca91cx42_bridge);
1829 }
1830
1831 static void __exit ca91cx42_exit(void)
1832 {
1833         pci_unregister_driver(&ca91cx42_driver);
1834 }
1835
1836 MODULE_PARM_DESC(geoid, "Override geographical addressing");
1837 module_param(geoid, int, 0);
1838
1839 MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge");
1840 MODULE_LICENSE("GPL");
1841
1842 module_init(ca91cx42_init);
1843 module_exit(ca91cx42_exit);