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   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to tanks the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 //#include <linux/config.h>
  24 #include <linux/init.h>
  25 #include <linux/ioport.h>
  26 #include <linux/sched.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/netdevice.h>
  30 //#include <linux/pci.h>
  31 #include <linux/usb.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/delay.h>
  34 #include <linux/rtnetlink.h>    //for rtnl_lock()
  35 #include <linux/wireless.h>
  36 #include <linux/timer.h>
  37 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  38 #include <linux/if_arp.h>
  39 #include <linux/random.h>
  40 #include <linux/version.h>
  41 #include <asm/io.h>
  42 #include "ieee80211.h"
  43
  44 #define RTL8192U
  45 #define RTL819xU_MODULE_NAME "rtl819xU"
  46 //added for HW security, john.0629
  47 #define FALSE 0
  48 #define TRUE 1
  49 #define MAX_KEY_LEN     61
  50 #define KEY_BUF_SIZE    5
  51
  52 #define BIT0            0x00000001
  53 #define BIT1            0x00000002
  54 #define BIT2            0x00000004
  55 #define BIT3            0x00000008
  56 #define BIT4            0x00000010
  57 #define BIT5            0x00000020
  58 #define BIT6            0x00000040
  59 #define BIT7            0x00000080
  60 #define BIT8            0x00000100
  61 #define BIT9            0x00000200
  62 #define BIT10           0x00000400
  63 #define BIT11           0x00000800
  64 #define BIT12           0x00001000
  65 #define BIT13           0x00002000
  66 #define BIT14           0x00004000
  67 #define BIT15           0x00008000
  68 #define BIT16           0x00010000
  69 #define BIT17           0x00020000
  70 #define BIT18           0x00040000
  71 #define BIT19           0x00080000
  72 #define BIT20           0x00100000
  73 #define BIT21           0x00200000
  74 #define BIT22           0x00400000
  75 #define BIT23           0x00800000
  76 #define BIT24           0x01000000
  77 #define BIT25           0x02000000
  78 #define BIT26           0x04000000
  79 #define BIT27           0x08000000
  80 #define BIT28           0x10000000
  81 #define BIT29           0x20000000
  82 #define BIT30           0x40000000
  83 #define BIT31           0x80000000
  84
  85 // Rx smooth factor
  86 #define Rx_Smooth_Factor                20
  87 #define DMESG(x,a...)
  88 #define DMESGW(x,a...)
  89 #define DMESGE(x,a...)
  90 extern u32 rt_global_debug_component;
  91 #define RT_TRACE(component, x, args...) \
  92 do { if(rt_global_debug_component & component) \
  93         printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
  94                ##args);\
  95 }while(0);
  96
  97 #define COMP_TRACE                              BIT0            // For function call tracing.
  98 #define COMP_DBG                                BIT1            // Only for temporary debug message.
  99 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
 100
 101
 102 #define COMP_RECV                               BIT3            // Reveive part data path.
 103 #define COMP_SEND                               BIT4            // Send part path.
 104 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 105 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 106 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 107 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 108 #define COMP_POWER_TRACKING                     BIT9    //FOR 8190 TX POWER TRACKING
 109 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 110 #define COMP_QOS                                BIT11   // For QoS.
 111 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
 112 #define COMP_RM                                 BIT13   // For Radio Measurement.
 113 #define COMP_DIG                                BIT14   // For DIG, 2006.09.25, by rcnjko.
 114 #define COMP_PHY                                BIT15
 115 #define COMP_CH                                 BIT16   //channel setting debug
 116 #define COMP_TXAGC                              BIT17   // For Tx power, 060928, by rcnjko.
 117 #define COMP_HIPWR                              BIT18   // For High Power Mechanism, 060928, by rcnjko.
 118 #define COMP_HALDM                              BIT19   // For HW Dynamic Mechanism, 061010, by rcnjko.
 119 #define COMP_SEC                                BIT20   // Event handling
 120 #define COMP_LED                                BIT21   // For LED.
 121 #define COMP_RF                                 BIT22   // For RF.
 122 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 123 #define COMP_RXDESC                             BIT23   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 124 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
 125 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 126
 127 #define COMP_FIRMWARE                           BIT24   //for firmware downloading
 128 #define COMP_HT                                 BIT25   // For 802.11n HT related information. by Emily 2006-8-11
 129 #define COMP_AMSDU                              BIT26   // For A-MSDU Debugging
 130
 131 #define COMP_SCAN                               BIT27
 132 //#define COMP_RESET                            BIT28
 133 #define COMP_DOWN                               BIT29  //for rm driver module
 134 #define COMP_RESET                              BIT30  //for silent reset
 135 #define COMP_ERR                                BIT31 //for error out, always on
 136
 137 #define RTL819x_DEBUG
 138 #ifdef RTL819x_DEBUG
 139 #define assert(expr) \
 140         if (!(expr)) {                                  \
 141                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
 142                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
 143         }
 144 //wb added to debug out data buf
 145 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
 146 #define RT_DEBUG_DATA(level, data, datalen)      \
 147         do{ if ((rt_global_debug_component & (level)) == (level))   \
 148                 {       \
 149                         int i;                                  \
 150                         u8* pdata = (u8*) data;                 \
 151                         printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__);   \
 152                         for(i=0; i<(int)(datalen); i++)                 \
 153                         {                                               \
 154                                 printk("%2x ", pdata[i]);               \
 155                                 if ((i+1)%16 == 0) printk("\n");        \
 156                         }                               \
 157                         printk("\n");                   \
 158                 }                                       \
 159         } while (0)
 160 #else
 161 #define assert(expr) do {} while (0)
 162 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
 163 #endif /* RTL8169_DEBUG */
 164
 165
 166 //
 167 // Queue Select Value in TxDesc
 168 //
 169 #define QSLT_BK                                 0x1
 170 #define QSLT_BE                                 0x0
 171 #define QSLT_VI                                 0x4
 172 #define QSLT_VO                                 0x6
 173 #define QSLT_BEACON                             0x10
 174 #define QSLT_HIGH                               0x11
 175 #define QSLT_MGNT                               0x12
 176 #define QSLT_CMD                                0x13
 177
 178 #define DESC90_RATE1M                           0x00
 179 #define DESC90_RATE2M                           0x01
 180 #define DESC90_RATE5_5M                         0x02
 181 #define DESC90_RATE11M                          0x03
 182 #define DESC90_RATE6M                           0x04
 183 #define DESC90_RATE9M                           0x05
 184 #define DESC90_RATE12M                          0x06
 185 #define DESC90_RATE18M                          0x07
 186 #define DESC90_RATE24M                          0x08
 187 #define DESC90_RATE36M                          0x09
 188 #define DESC90_RATE48M                          0x0a
 189 #define DESC90_RATE54M                          0x0b
 190 #define DESC90_RATEMCS0                         0x00
 191 #define DESC90_RATEMCS1                         0x01
 192 #define DESC90_RATEMCS2                         0x02
 193 #define DESC90_RATEMCS3                         0x03
 194 #define DESC90_RATEMCS4                         0x04
 195 #define DESC90_RATEMCS5                         0x05
 196 #define DESC90_RATEMCS6                         0x06
 197 #define DESC90_RATEMCS7                         0x07
 198 #define DESC90_RATEMCS8                         0x08
 199 #define DESC90_RATEMCS9                         0x09
 200 #define DESC90_RATEMCS10                        0x0a
 201 #define DESC90_RATEMCS11                        0x0b
 202 #define DESC90_RATEMCS12                        0x0c
 203 #define DESC90_RATEMCS13                        0x0d
 204 #define DESC90_RATEMCS14                        0x0e
 205 #define DESC90_RATEMCS15                        0x0f
 206 #define DESC90_RATEMCS32                        0x20
 207
 208 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 209
 210 #define IEEE80211_WATCH_DOG_TIME    2000
 211 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 212 //for txpowertracking by amy
 213 #define         OFDM_Table_Length       19
 214 #define CCK_Table_length        12
 215
 216 /* for rtl819x */
 217 typedef struct _tx_desc_819x_usb {
 218         //DWORD 0
 219         u16     PktSize;
 220         u8      Offset;
 221         u8      Reserved0:3;
 222         u8      CmdInit:1;
 223         u8      LastSeg:1;
 224         u8      FirstSeg:1;
 225         u8      LINIP:1;
 226         u8      OWN:1;
 227
 228         //DWORD 1
 229         u8      TxFWInfoSize;
 230         u8      RATid:3;
 231         u8      DISFB:1;
 232         u8      USERATE:1;
 233         u8      MOREFRAG:1;
 234         u8      NoEnc:1;
 235         u8      PIFS:1;
 236         u8      QueueSelect:5;
 237         u8      NoACM:1;
 238         u8      Reserved1:2;
 239         u8      SecCAMID:5;
 240         u8      SecDescAssign:1;
 241         u8      SecType:2;
 242
 243         //DWORD 2
 244         u16     TxBufferSize;
 245         //u16 Reserved2;
 246         u8      ResvForPaddingLen:7;
 247         u8      Reserved3:1;
 248         u8      Reserved4;
 249
 250         //DWORD 3, 4, 5
 251         u32     Reserved5;
 252         u32     Reserved6;
 253         u32     Reserved7;
 254 }tx_desc_819x_usb, *ptx_desc_819x_usb;
 255
 256 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 257 typedef struct _tx_desc_819x_usb_aggr_subframe {
 258         //DWORD 0
 259         u16     PktSize;
 260         u8      Offset;
 261         u8      TxFWInfoSize;
 262
 263         //DWORD 1
 264         u8      RATid:3;
 265         u8      DISFB:1;
 266         u8      USERATE:1;
 267         u8      MOREFRAG:1;
 268         u8      NoEnc:1;
 269         u8      PIFS:1;
 270         u8      QueueSelect:5;
 271         u8      NoACM:1;
 272         u8      Reserved1:2;
 273         u8      SecCAMID:5;
 274         u8      SecDescAssign:1;
 275         u8      SecType:2;
 276         u8      PacketID:7;
 277         u8      OWN:1;
 278 }tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 279 #endif
 280
 281
 282
 283 typedef struct _tx_desc_cmd_819x_usb {
 284         //DWORD 0
 285         u16     Reserved0;
 286         u8      Reserved1;
 287         u8      Reserved2:3;
 288         u8      CmdInit:1;
 289         u8      LastSeg:1;
 290         u8      FirstSeg:1;
 291         u8      LINIP:1;
 292         u8      OWN:1;
 293
 294         //DOWRD 1
 295         //u32   Reserved3;
 296         u8      TxFWInfoSize;
 297         u8      Reserved3;
 298         u8      QueueSelect;
 299         u8      Reserved4;
 300
 301         //DOWRD 2
 302         u16     TxBufferSize;
 303         u16     Reserved5;
 304
 305        //DWORD 3,4,5
 306         //u32   TxBufferAddr;
 307         //u32   NextDescAddress;
 308         u32     Reserved6;
 309         u32     Reserved7;
 310         u32     Reserved8;
 311 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 312
 313
 314 typedef struct _tx_fwinfo_819x_usb {
 315         //DOWRD 0
 316         u8              TxRate:7;
 317         u8              CtsEnable:1;
 318         u8              RtsRate:7;
 319         u8              RtsEnable:1;
 320         u8              TxHT:1;
 321         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 322         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 323         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 324         u8              STBC:2;
 325         u8              AllowAggregation:1;
 326         u8              RtsHT:1;                //Interpre RtsRate field as high throughput data rate
 327         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 328         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 329         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 330         u8              RtsSTBC:2;
 331         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 332
 333         //DWORD 1
 334         u32             RxMF:2;
 335         u32             RxAMD:3;
 336         u32             TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
 337         u32             Reserved1:2;
 338         u32             TxAGCOffSet:4;
 339         u32             TxAGCSign:1;
 340         u32             Tx_INFO_RSVD:6;
 341         u32             PacketID:13;
 342         //u32                Reserved;
 343 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 344
 345 typedef struct rtl8192_rx_info {
 346         struct urb *urb;
 347         struct net_device *dev;
 348         u8 out_pipe;
 349 }rtl8192_rx_info ;
 350
 351 typedef struct rx_desc_819x_usb{
 352         //DOWRD 0
 353         u16                 Length:14;
 354         u16                 CRC32:1;
 355         u16                 ICV:1;
 356         u8                  RxDrvInfoSize;
 357         u8                  Shift:2;
 358         u8                  PHYStatus:1;
 359         u8                  SWDec:1;
 360         //u8                LastSeg:1;
 361         //u8                FirstSeg:1;
 362         //u8                EOR:1;
 363         //u8                OWN:1;
 364         u8                  Reserved1:4;
 365
 366         //DWORD 1
 367         u32                 Reserved2;
 368
 369         //DWORD 2
 370         //u32               Reserved3;
 371
 372         //DWORD 3
 373         //u32                BufferAddress;
 374
 375 }rx_desc_819x_usb, *prx_desc_819x_usb;
 376
 377 #ifdef USB_RX_AGGREGATION_SUPPORT
 378 typedef struct _rx_desc_819x_usb_aggr_subframe{
 379         //DOWRD 0
 380         u16                     Length:14;
 381         u16                     CRC32:1;
 382         u16                     ICV:1;
 383         u8                      Offset;
 384         u8                      RxDrvInfoSize;
 385         //DOWRD 1
 386         u8                      Shift:2;
 387         u8                      PHYStatus:1;
 388         u8                      SWDec:1;
 389         u8                      Reserved1:4;
 390         u8                      Reserved2;
 391         u16                     Reserved3;
 392         //DWORD 2
 393         //u4Byte                Reserved3;
 394         //DWORD 3
 395         //u4Byte                BufferAddress;
 396 }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 397 #endif
 398
 399 typedef struct rx_drvinfo_819x_usb{
 400         //DWORD 0
 401         u16                 Reserved1:12;
 402         u16                 PartAggr:1;
 403         u16                 FirstAGGR:1;
 404         u16                 Reserved2:2;
 405
 406         u8                  RxRate:7;
 407         u8                  RxHT:1;
 408
 409         u8                  BW:1;
 410         u8                  SPLCP:1;
 411         u8                  Reserved3:2;
 412         u8                  PAM:1;
 413         u8                  Mcast:1;
 414         u8                  Bcast:1;
 415         u8                  Reserved4:1;
 416
 417         //DWORD 1
 418         u32                  TSFL;
 419
 420 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 421
 422
 423 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 424 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 425 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 426 #define ENCRYPTION_MAX_OVERHEAD         128
 427 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 428 #define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 429 #define MAX_FRAGMENT_COUNT              8
 430 #ifdef RTL8192U
 431 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 432 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 433 #else
 434 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 435 #endif
 436 #else
 437 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 438 #endif
 439 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 440 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 441 #endif
 442 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 443
 444 typedef enum rf_optype
 445 {
 446         RF_OP_By_SW_3wire = 0,
 447         RF_OP_By_FW,
 448         RF_OP_MAX
 449 }rf_op_type;
 450 /* 8190 Loopback Mode definition */
 451 typedef enum _rtl819xUsb_loopback{
 452         RTL819xU_NO_LOOPBACK = 0,
 453         RTL819xU_MAC_LOOPBACK = 1,
 454         RTL819xU_DMA_LOOPBACK = 2,
 455         RTL819xU_CCK_LOOPBACK = 3,
 456 }rtl819xUsb_loopback_e;
 457
 458 /* due to rtl8192 firmware */
 459 typedef enum _desc_packet_type_e{
 460         DESC_PACKET_TYPE_INIT = 0,
 461         DESC_PACKET_TYPE_NORMAL = 1,
 462 }desc_packet_type_e;
 463
 464 typedef enum _firmware_source{
 465         FW_SOURCE_IMG_FILE = 0,
 466         FW_SOURCE_HEADER_FILE = 1,              //from header file
 467 }firmware_source_e, *pfirmware_source_e;
 468
 469 typedef enum _firmware_status{
 470         FW_STATUS_0_INIT = 0,
 471         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 472         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 473         FW_STATUS_3_TURNON_CPU = 3,
 474         FW_STATUS_4_MOVE_DATA_CODE = 4,
 475         FW_STATUS_5_READY = 5,
 476 }firmware_status_e;
 477
 478 typedef struct _rt_firmare_seg_container {
 479         u16     seg_size;
 480         u8      *seg_ptr;
 481 }fw_seg_container, *pfw_seg_container;
 482 typedef struct _rt_firmware{
 483         firmware_status_e firmware_status;
 484         u16               cmdpacket_frag_thresold;
 485 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
 486         u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 487         u16               firmware_buf_size;
 488 }rt_firmware, *prt_firmware;
 489
 490 //+by amy 080507
 491 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 492
 493 typedef struct _rt_firmware_info_819xUsb{
 494         u8              sz_info[16];
 495 }rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 496
 497 /* Firmware Queue Layout */
 498 #define NUM_OF_FIRMWARE_QUEUE           10
 499 #define NUM_OF_PAGES_IN_FW              0x100
 500
 501 #ifdef USE_ONE_PIPE
 502 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 503 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 504 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 505 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 506 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 507 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 508 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 509 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 510 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 511 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 512 #else
 513
 514 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 515 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 516 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 517 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 518 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 519 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 520 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 521 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 522 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 523 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 524
 525 #endif
 526
 527 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 528 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 529 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 530 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 531 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 532 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 533 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 534 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 535 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 536 //=================================================================
 537 //=================================================================
 538
 539 #define EPROM_93c46 0
 540 #define EPROM_93c56 1
 541
 542 #define DEFAULT_FRAG_THRESHOLD 2342U
 543 #define MIN_FRAG_THRESHOLD     256U
 544 #define DEFAULT_BEACONINTERVAL 0x64U
 545 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 546
 547 #define DEFAULT_SSID ""
 548 #define DEFAULT_RETRY_RTS 7
 549 #define DEFAULT_RETRY_DATA 7
 550 #define PRISM_HDR_SIZE 64
 551
 552 #define         PHY_RSSI_SLID_WIN_MAX                           100
 553
 554
 555 typedef enum _WIRELESS_MODE {
 556         WIRELESS_MODE_UNKNOWN = 0x00,
 557         WIRELESS_MODE_A = 0x01,
 558         WIRELESS_MODE_B = 0x02,
 559         WIRELESS_MODE_G = 0x04,
 560         WIRELESS_MODE_AUTO = 0x08,
 561         WIRELESS_MODE_N_24G = 0x10,
 562         WIRELESS_MODE_N_5G = 0x20
 563 } WIRELESS_MODE;
 564
 565
 566 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 567
 568 typedef struct buffer
 569 {
 570         struct buffer *next;
 571         u32 *buf;
 572
 573 } buffer;
 574
 575 typedef struct rtl_reg_debug{
 576         unsigned int  cmd;
 577         struct {
 578                 unsigned char type;
 579                 unsigned char addr;
 580                 unsigned char page;
 581                 unsigned char length;
 582         } head;
 583         unsigned char buf[0xff];
 584 }rtl_reg_debug;
 585
 586
 587
 588
 589
 590
 591 typedef struct _rt_9x_tx_rate_history {
 592         u32             cck[4];
 593         u32             ofdm[8];
 594         // HT_MCS[0][]: BW=0 SG=0
 595         // HT_MCS[1][]: BW=1 SG=0
 596         // HT_MCS[2][]: BW=0 SG=1
 597         // HT_MCS[3][]: BW=1 SG=1
 598         u32             ht_mcs[4][16];
 599 }rt_tx_rahis_t, *prt_tx_rahis_t;
 600 typedef struct _RT_SMOOTH_DATA_4RF {
 601         char    elements[4][100];//array to store values
 602         u32     index;                  //index to current array to store
 603         u32     TotalNum;               //num of valid elements
 604         u32     TotalVal[4];            //sum of valid elements
 605 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 606
 607 #define MAX_8192U_RX_SIZE                       8192    // This maybe changed for D-cut larger aggregation size
 608 //stats seems messed up, clean it ASAP
 609 typedef struct Stats
 610 {
 611         unsigned long txrdu;
 612 //      unsigned long rxrdu;
 613         //unsigned long rxnolast;
 614         //unsigned long rxnodata;
 615 //      unsigned long rxreset;
 616 //      unsigned long rxnopointer;
 617         unsigned long rxok;
 618         unsigned long rxframgment;
 619         unsigned long rxcmdpkt[4];              //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
 620         unsigned long rxurberr;
 621         unsigned long rxstaterr;
 622         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
 623         unsigned long received_preamble_GI[2][32];              //0: Long preamble/GI, 1:Short preamble/GI
 624         unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
 625         unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
 626         unsigned long numpacket_matchbssid;     // debug use only.
 627         unsigned long numpacket_toself;         // debug use only.
 628         unsigned long num_process_phyinfo;              // debug use only.
 629         unsigned long numqry_phystatus;
 630         unsigned long numqry_phystatusCCK;
 631         unsigned long numqry_phystatusHT;
 632         unsigned long received_bwtype[5];              //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
 633         unsigned long txnperr;
 634         unsigned long txnpdrop;
 635         unsigned long txresumed;
 636 //      unsigned long rxerr;
 637 //      unsigned long rxoverflow;
 638 //      unsigned long rxint;
 639         unsigned long txnpokint;
 640 //      unsigned long txhpokint;
 641 //      unsigned long txhperr;
 642 //      unsigned long ints;
 643 //      unsigned long shints;
 644         unsigned long txoverflow;
 645 //      unsigned long rxdmafail;
 646 //      unsigned long txbeacon;
 647 //      unsigned long txbeaconerr;
 648         unsigned long txlpokint;
 649         unsigned long txlpdrop;
 650         unsigned long txlperr;
 651         unsigned long txbeokint;
 652         unsigned long txbedrop;
 653         unsigned long txbeerr;
 654         unsigned long txbkokint;
 655         unsigned long txbkdrop;
 656         unsigned long txbkerr;
 657         unsigned long txviokint;
 658         unsigned long txvidrop;
 659         unsigned long txvierr;
 660         unsigned long txvookint;
 661         unsigned long txvodrop;
 662         unsigned long txvoerr;
 663         unsigned long txbeaconokint;
 664         unsigned long txbeacondrop;
 665         unsigned long txbeaconerr;
 666         unsigned long txmanageokint;
 667         unsigned long txmanagedrop;
 668         unsigned long txmanageerr;
 669         unsigned long txdatapkt;
 670         unsigned long txfeedback;
 671         unsigned long txfeedbackok;
 672
 673         unsigned long txoktotal;
 674         unsigned long txokbytestotal;
 675         unsigned long txokinperiod;
 676         unsigned long txmulticast;
 677         unsigned long txbytesmulticast;
 678         unsigned long txbroadcast;
 679         unsigned long txbytesbroadcast;
 680         unsigned long txunicast;
 681         unsigned long txbytesunicast;
 682
 683         unsigned long rxoktotal;
 684         unsigned long rxbytesunicast;
 685         unsigned long txfeedbackfail;
 686         unsigned long txerrtotal;
 687         unsigned long txerrbytestotal;
 688         unsigned long txerrmulticast;
 689         unsigned long txerrbroadcast;
 690         unsigned long txerrunicast;
 691         unsigned long txretrycount;
 692         unsigned long txfeedbackretry;
 693         u8            last_packet_rate;
 694         unsigned long slide_signal_strength[100];
 695         unsigned long slide_evm[100];
 696         unsigned long slide_rssi_total; // For recording sliding window's RSSI value
 697         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 698         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 699         long signal_quality;
 700         long last_signal_strength_inpercent;
 701         long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
 702         u8 rx_rssi_percentage[4];
 703         u8 rx_evm_percentage[2];
 704         long rxSNRdB[4];
 705         rt_tx_rahis_t txrate;
 706         u32 Slide_Beacon_pwdb[100];     //cosa add for beacon rssi
 707         u32 Slide_Beacon_Total;         //cosa add for beacon rssi
 708         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 709
 710         u32     CurrentShowTxate;
 711 } Stats;
 712
 713
 714 // Bandwidth Offset
 715 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 716 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 717 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 718
 719 //+by amy 080507
 720
 721 typedef struct  ChnlAccessSetting {
 722         u16 SIFS_Timer;
 723         u16 DIFS_Timer;
 724         u16 SlotTimeTimer;
 725         u16 EIFS_Timer;
 726         u16 CWminIndex;
 727         u16 CWmaxIndex;
 728 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 729
 730 typedef struct _BB_REGISTER_DEFINITION{
 731         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 732         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 733         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 734         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 735         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 736         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 737         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 738         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 739         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 740         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 741         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 742         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 743         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 744         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 745         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 746         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 747         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 748 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 749
 750 typedef enum _RT_RF_TYPE_819xU{
 751         RF_TYPE_MIN = 0,
 752         RF_8225,
 753         RF_8256,
 754         RF_8258,
 755         RF_PSEUDO_11N = 4,
 756 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 757
 758 typedef struct _rate_adaptive
 759 {
 760         u8                              rate_adaptive_disabled;
 761         u8                              ratr_state;
 762         u16                             reserve;
 763
 764         u32                             high_rssi_thresh_for_ra;
 765         u32                             high2low_rssi_thresh_for_ra;
 766         u8                              low2high_rssi_thresh_for_ra40M;
 767         u32                             low_rssi_thresh_for_ra40M;
 768         u8                              low2high_rssi_thresh_for_ra20M;
 769         u32                             low_rssi_thresh_for_ra20M;
 770         u32                             upper_rssi_threshold_ratr;
 771         u32                             middle_rssi_threshold_ratr;
 772         u32                             low_rssi_threshold_ratr;
 773         u32                             low_rssi_threshold_ratr_40M;
 774         u32                             low_rssi_threshold_ratr_20M;
 775         u8                              ping_rssi_enable;       //cosa add for test
 776         u32                             ping_rssi_ratr; //cosa add for test
 777         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 778         u32                             last_ratr;
 779
 780 } rate_adaptive, *prate_adaptive;
 781
 782 #define TxBBGainTableLength 37
 783 #define CCKTxBBGainTableLength 23
 784
 785 typedef struct _txbbgain_struct
 786 {
 787         long    txbb_iq_amplifygain;
 788         u32     txbbgain_value;
 789 } txbbgain_struct, *ptxbbgain_struct;
 790
 791 typedef struct _ccktxbbgain_struct
 792 {
 793         //The Value is from a22 to a29 one Byte one time is much Safer
 794         u8      ccktxbb_valuearray[8];
 795 } ccktxbbgain_struct,*pccktxbbgain_struct;
 796
 797
 798 typedef struct _init_gain
 799 {
 800         u8                              xaagccore1;
 801         u8                              xbagccore1;
 802         u8                              xcagccore1;
 803         u8                              xdagccore1;
 804         u8                              cca;
 805
 806 } init_gain, *pinit_gain;
 807 //by amy 0606
 808
 809 typedef struct _phy_ofdm_rx_status_report_819xusb
 810 {
 811         u8      trsw_gain_X[4];
 812         u8      pwdb_all;
 813         u8      cfosho_X[4];
 814         u8      cfotail_X[4];
 815         u8      rxevm_X[2];
 816         u8      rxsnr_X[4];
 817         u8      pdsnr_X[2];
 818         u8      csi_current_X[2];
 819         u8      csi_target_X[2];
 820         u8      sigevm;
 821         u8      max_ex_pwr;
 822         u8      sgi_en;
 823         u8  rxsc_sgien_exflg;
 824 }phy_sts_ofdm_819xusb_t;
 825
 826 typedef struct _phy_cck_rx_status_report_819xusb
 827 {
 828         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
 829            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
 830         u8      adc_pwdb_X[4];
 831         u8      sq_rpt;
 832         u8      cck_agc_rpt;
 833 }phy_sts_cck_819xusb_t;
 834
 835
 836 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
 837         u8                      reserved:4;
 838         u8                      rxsc:2;
 839         u8                      sgi_en:1;
 840         u8                      ex_intf_flag:1;
 841 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 842
 843 typedef enum _RT_CUSTOMER_ID
 844 {
 845         RT_CID_DEFAULT = 0,
 846         RT_CID_8187_ALPHA0 = 1,
 847         RT_CID_8187_SERCOMM_PS = 2,
 848         RT_CID_8187_HW_LED = 3,
 849         RT_CID_8187_NETGEAR = 4,
 850         RT_CID_WHQL = 5,
 851         RT_CID_819x_CAMEO  = 6,
 852         RT_CID_819x_RUNTOP = 7,
 853         RT_CID_819x_Senao = 8,
 854         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
 855         RT_CID_819x_Netcore = 10,
 856         RT_CID_Nettronix = 11,
 857         RT_CID_DLINK = 12,
 858         RT_CID_PRONET = 13,
 859 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 860
 861 //================================================================================
 862 // LED customization.
 863 //================================================================================
 864
 865 typedef enum _LED_STRATEGY_8190{
 866         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
 867         SW_LED_MODE1, // SW control for PCI Express
 868         SW_LED_MODE2, // SW control for Cameo.
 869         SW_LED_MODE3, // SW contorl for RunTop.
 870         SW_LED_MODE4, // SW control for Netcore
 871         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
 872 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 873
 874 typedef enum _RESET_TYPE {
 875         RESET_TYPE_NORESET = 0x00,
 876         RESET_TYPE_NORMAL = 0x01,
 877         RESET_TYPE_SILENT = 0x02
 878 } RESET_TYPE;
 879
 880 /* The simple tx command OP code. */
 881 typedef enum _tag_TxCmd_Config_Index{
 882         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 883         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 884         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 885         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 886         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 887         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 888         TXCMD_XXXX_CTRL,
 889 }DCMD_TXCMD_OP;
 890
 891 typedef struct r8192_priv
 892 {
 893         struct usb_device *udev;
 894         //added for maintain info from eeprom
 895         short epromtype;
 896         u16 eeprom_vid;
 897         u16 eeprom_pid;
 898         u8  eeprom_CustomerID;
 899         u8  eeprom_ChannelPlan;
 900         RT_CUSTOMER_ID CustomerID;
 901         LED_STRATEGY_8190       LedStrategy;
 902         u8  txqueue_to_outpipemap[9];
 903         int irq;
 904         struct ieee80211_device *ieee80211;
 905
 906         short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
 907         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
 908 //      short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
 909         short enable_gpio0;
 910         enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
 911         short hw_plcp_len;
 912         short plcp_preamble_mode;
 913
 914         spinlock_t irq_lock;
 915 //      spinlock_t irq_th_lock;
 916         spinlock_t tx_lock;
 917         struct mutex mutex;
 918         //spinlock_t rf_lock; //used to lock rf write operation added by wb
 919
 920         u16 irq_mask;
 921 //      short irq_enabled;
 922 //      struct net_device *dev; //comment this out.
 923         short chan;
 924         short sens;
 925         short max_sens;
 926
 927
 928         //      u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
 929 //      u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
 930 //      u8 cck_txpwr_base;
 931 //      u8 ofdm_txpwr_base;
 932 //      u8 challow[15]; //channels from 1 to 14, 0 not used
 933         short up;
 934         short crcmon; //if 1 allow bad crc frame reception in monitor mode
 935 //      short prism_hdr;
 936
 937 //      struct timer_list scan_timer;
 938         /*short scanpending;
 939         short stopscan;*/
 940 //      spinlock_t scan_lock;
 941 //      u8 active_probe;
 942         //u8 active_scan_num;
 943         struct semaphore wx_sem;
 944         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
 945 //      short hw_wep;
 946
 947 //      short digphy;
 948 //      short antb;
 949 //      short diversity;
 950 //      u8 cs_treshold;
 951 //      short rcr_csense;
 952         u8 rf_type; //0 means 1T2R, 1 means 2T4R
 953         RT_RF_TYPE_819xU rf_chip;
 954
 955 //      u32 key0[4];
 956         short (*rf_set_sens)(struct net_device *dev,short sens);
 957         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 958         void (*rf_close)(struct net_device *dev);
 959         void (*rf_init)(struct net_device *dev);
 960         //short rate;
 961         short promisc;
 962         /*stats*/
 963         struct Stats stats;
 964         struct iw_statistics wstats;
 965         struct proc_dir_entry *dir_dev;
 966
 967         /*RX stuff*/
 968 //      u32 *rxring;
 969 //      u32 *rxringtail;
 970 //      dma_addr_t rxringdma;
 971         struct urb **rx_urb;
 972         struct urb **rx_cmd_urb;
 973 #ifdef THOMAS_BEACON
 974         u32 *oldaddr;
 975 #endif
 976 #ifdef THOMAS_TASKLET
 977         atomic_t irt_counter;//count for irq_rx_tasklet
 978 #endif
 979 #ifdef JACKSON_NEW_RX
 980         struct sk_buff **pp_rxskb;
 981         int     rx_inx;
 982 #endif
 983
 984 /* modified by davad for Rx process */
 985        struct sk_buff_head rx_queue;
 986        struct sk_buff_head skb_queue;
 987        struct work_struct qos_activate;
 988         short  tx_urb_index;
 989         atomic_t tx_pending[0x10];//UART_PRIORITY+1
 990
 991
 992         struct tasklet_struct irq_rx_tasklet;
 993         struct urb *rxurb_task;
 994
 995         //2 Tx Related variables
 996         u16     ShortRetryLimit;
 997         u16     LongRetryLimit;
 998         u32     TransmitConfig;
 999         u8      RegCWinMin;             // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1000
1001         u32     LastRxDescTSFHigh;
1002         u32     LastRxDescTSFLow;
1003
1004
1005         //2 Rx Related variables
1006         u16     EarlyRxThreshold;
1007         u32     ReceiveConfig;
1008         u8      AcmControl;
1009
1010         u8      RFProgType;
1011
1012         u8 retry_data;
1013         u8 retry_rts;
1014         u16 rts;
1015
1016         struct  ChnlAccessSetting  ChannelAccessSetting;
1017         struct work_struct reset_wq;
1018
1019 /**********************************************************/
1020         //for rtl819xUsb
1021         u16     basic_rate;
1022         u8      short_preamble;
1023         u8      slot_time;
1024         bool    bDcut;
1025         bool bCurrentRxAggrEnable;
1026         u8 Rf_Mode; //add for Firmware RF -R/W switch
1027         prt_firmware            pFirmware;
1028         rtl819xUsb_loopback_e   LoopbackMode;
1029         firmware_source_e       firmware_source;
1030         u16 EEPROMTxPowerDiff;
1031         u8 EEPROMThermalMeter;
1032         u8 EEPROMPwDiff;
1033         u8 EEPROMCrystalCap;
1034         u8 EEPROM_Def_Ver;
1035         u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
1036         u8 EEPROMTxPowerLevelCCK_V1[3];
1037         u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
1038         u8 EEPROMTxPowerLevelOFDM5G[24];        // OFDM 5G
1039
1040 /*PHY related*/
1041         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
1042         // Read/write are allow for following hardware information variables
1043         u32     MCSTxPowerLevelOriginalOffset[6];
1044         u32     CCKTxPowerLevelOriginalOffset;
1045         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
1046         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
1047         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
1048         u32     Pwr_Track;
1049         u8      TxPowerDiff;
1050         u8      AntennaTxPwDiff[2];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1051         u8      CrystalCap;                                             // CrystalCap.
1052         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1053
1054         u8      CckPwEnl;
1055         // Use to calculate PWBD.
1056         u8      bCckHighPower;
1057         long    undecorated_smoothed_pwdb;
1058
1059         //for set channel
1060         u8      SwChnlInProgress;
1061         u8      SwChnlStage;
1062         u8      SwChnlStep;
1063         u8      SetBWModeInProgress;
1064         HT_CHANNEL_WIDTH                CurrentChannelBW;
1065         u8      ChannelPlan;
1066         // 8190 40MHz mode
1067         //
1068         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
1069         // Joseph test for shorten RF configuration time.
1070         // We save RF reg0 in this variable to reduce RF reading.
1071         //
1072         u32                                     RfReg0Value[4];
1073         u8                                      NumTotalRFPath;
1074         bool                            brfpath_rxenable[4];
1075         //RF set related
1076         bool                            SetRFPowerStateInProgress;
1077 //+by amy 080507
1078         struct timer_list watch_dog_timer;
1079
1080 //+by amy 080515 for dynamic mechenism
1081         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1082         bool    bdynamic_txpower;  //bDynamicTxPower
1083         bool    bDynamicTxHighPower;  // Tx high power state
1084         bool    bDynamicTxLowPower;  // Tx low power state
1085         bool    bLastDTPFlag_High;
1086         bool    bLastDTPFlag_Low;
1087
1088         bool    bstore_last_dtpflag;
1089         bool    bstart_txctrl_bydtp;   //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1090         //Add by amy for Rate Adaptive
1091         rate_adaptive rate_adaptive;
1092         //Add by amy for TX power tracking
1093         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
1094        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1095         u8                         txpower_count;//For 6 sec do tracking again
1096         bool                       btxpower_trackingInit;
1097         u8                         OFDM_index;
1098         u8                         CCK_index;
1099         //2007/09/10 Mars Add CCK TX Power Tracking
1100         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1101         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1102         u8 rfa_txpowertrackingindex;
1103         u8 rfa_txpowertrackingindex_real;
1104         u8 rfa_txpowertracking_default;
1105         u8 rfc_txpowertrackingindex;
1106         u8 rfc_txpowertrackingindex_real;
1107
1108         s8 cck_present_attentuation;
1109         u8 cck_present_attentuation_20Mdefault;
1110         u8 cck_present_attentuation_40Mdefault;
1111         char cck_present_attentuation_difference;
1112         bool btxpower_tracking;
1113         bool bcck_in_ch14;
1114         bool btxpowerdata_readfromEEPORM;
1115         u16     TSSI_13dBm;
1116         //For Backup Initial Gain
1117         init_gain initgain_backup;
1118         u8 DefaultInitialGain[4];
1119         // For EDCA Turbo mode, Added by amy 080515.
1120         bool            bis_any_nonbepkts;
1121         bool            bcurrent_turbo_EDCA;
1122         bool            bis_cur_rdlstate;
1123         struct timer_list fsync_timer;
1124         bool bfsync_processing; // 500ms Fsync timer is active or not
1125         u32     rate_record;
1126         u32     rateCountDiffRecord;
1127         u32     ContiuneDiffCount;
1128         bool bswitch_fsync;
1129
1130         u8      framesync;
1131         u32     framesyncC34;
1132         u8      framesyncMonitor;
1133                 //Added by amy 080516  for RX related
1134         u16     nrxAMPDU_size;
1135         u8      nrxAMPDU_aggr_num;
1136
1137         //by amy for gpio
1138          bool bHwRadioOff;
1139
1140         //by amy for reset_count
1141         u32 reset_count;
1142         bool bpbc_pressed;
1143         //by amy for debug
1144         u32 txpower_checkcnt;
1145         u32 txpower_tracking_callback_cnt;
1146         u8 thermal_read_val[40];
1147         u8 thermal_readback_index;
1148         u32 ccktxpower_adjustcnt_not_ch14;
1149         u32 ccktxpower_adjustcnt_ch14;
1150         u8 tx_fwinfo_force_subcarriermode;
1151         u8 tx_fwinfo_force_subcarrierval;
1152         //by amy for silent reset
1153         RESET_TYPE      ResetProgress;
1154         bool            bForcedSilentReset;
1155         bool            bDisableNormalResetCheck;
1156         u16             TxCounter;
1157         u16             RxCounter;
1158         int             IrpPendingCount;
1159         bool            bResetInProgress;
1160         bool            force_reset;
1161         u8              InitialGainOperateType;
1162
1163         u16             SifsTime;
1164
1165         //define work item by amy 080526
1166
1167         struct delayed_work update_beacon_wq;
1168         struct delayed_work watch_dog_wq;
1169         struct delayed_work txpower_tracking_wq;
1170         struct delayed_work rfpath_check_wq;
1171         struct delayed_work gpio_change_rf_wq;
1172         struct delayed_work initialgain_operate_wq;
1173         struct workqueue_struct *priv_wq;
1174 }r8192_priv;
1175
1176 // for rtl8187
1177 // now mirging to rtl8187B
1178 /*
1179 typedef enum{
1180         LOW_PRIORITY = 0x02,
1181         NORM_PRIORITY
1182         } priority_t;
1183 */
1184 //for rtl8187B
1185 typedef enum{
1186         BULK_PRIORITY = 0x01,
1187         //RSVD0,
1188         //RSVD1,
1189         LOW_PRIORITY,
1190         NORM_PRIORITY,
1191         VO_PRIORITY,
1192         VI_PRIORITY, //0x05
1193         BE_PRIORITY,
1194         BK_PRIORITY,
1195         RSVD2,
1196         RSVD3,
1197         BEACON_PRIORITY, //0x0A
1198         HIGH_PRIORITY,
1199         MANAGE_PRIORITY,
1200         RSVD4,
1201         RSVD5,
1202         UART_PRIORITY //0x0F
1203 } priority_t;
1204
1205 typedef enum{
1206         NIC_8192U = 1,
1207         NIC_8190P = 2,
1208         NIC_8192E = 3,
1209         } nic_t;
1210
1211
1212 #ifdef JOHN_HWSEC
1213 struct ssid_thread {
1214         struct net_device *dev;
1215         u8 name[IW_ESSID_MAX_SIZE + 1];
1216 };
1217 #endif
1218
1219 bool init_firmware(struct net_device *dev);
1220 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1221 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1222
1223 u32 read_cam(struct net_device *dev, u8 addr);
1224 void write_cam(struct net_device *dev, u8 addr, u32 data);
1225
1226 u8 read_nic_byte(struct net_device *dev, int x);
1227 u8 read_nic_byte_E(struct net_device *dev, int x);
1228 u32 read_nic_dword(struct net_device *dev, int x);
1229 u16 read_nic_word(struct net_device *dev, int x) ;
1230 void write_nic_byte(struct net_device *dev, int x,u8 y);
1231 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1232 void write_nic_word(struct net_device *dev, int x,u16 y);
1233 void write_nic_dword(struct net_device *dev, int x,u32 y);
1234 void force_pci_posting(struct net_device *dev);
1235
1236 void rtl8192_rtx_disable(struct net_device *);
1237 void rtl8192_rx_enable(struct net_device *);
1238 void rtl8192_tx_enable(struct net_device *);
1239
1240 void rtl8192_disassociate(struct net_device *dev);
1241 //void fix_rx_fifo(struct net_device *dev);
1242 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1243
1244 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1245 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1246 void rtl8192_update_msr(struct net_device *dev);
1247 int rtl8192_down(struct net_device *dev);
1248 int rtl8192_up(struct net_device *dev);
1249 void rtl8192_commit(struct net_device *dev);
1250 void rtl8192_set_chan(struct net_device *dev,short ch);
1251 void write_phy(struct net_device *dev, u8 adr, u8 data);
1252 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1253 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1254 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1255 void rtl8192_set_rxconf(struct net_device *dev);
1256 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1257 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16  tx_rate);
1258
1259 void EnableHWSecurityConfig8192(struct net_device *dev);
1260 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1261
1262
1263 #endif