SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_rtl6052.c

   1 /******************************************************************************
   2  *
   3  *     (c) Copyright  2008, RealTEK Technologies Inc. All Rights Reserved.
   4  *
   5  * Module:      HalRf6052.c     ( Source C File)
   6  *
   7  * Note:        Provide RF 6052 series relative API.
   8  *
   9  * Function:
  10  *
  11  * Export:
  12  *
  13  * Abbrev:
  14  *
  15  * History:
  16  * Data                 Who             Remark
  17  *
  18  * 09/25/2008   MHC             Create initial version.
  19  * 11/05/2008   MHC             Add API for tw power setting.
  20  *
  21  *
  22 ******************************************************************************/
  23 #include "r8192U.h"
  24 #include "r8192S_rtl6052.h"
  25
  26 #ifdef RTL8192SU
  27 #include "r8192S_hw.h"
  28 #include "r8192S_phyreg.h"
  29 #include "r8192S_phy.h"
  30 #else
  31 #include "r8192U_hw.h"
  32 #include "r819xU_phyreg.h"
  33 #include "r819xU_phy.h"
  34 #endif
  35
  36
  37 /*---------------------------Define Local Constant---------------------------*/
  38 // Define local structure for debug!!!!!
  39 typedef struct RF_Shadow_Compare_Map {
  40         // Shadow register value
  41         u32             Value;
  42         // Compare or not flag
  43         u8              Compare;
  44         // Record If it had ever modified unpredicted
  45         u8              ErrorOrNot;
  46         // Recorver Flag
  47         u8              Recorver;
  48         //
  49         u8              Driver_Write;
  50 }RF_SHADOW_T;
  51 /*---------------------------Define Local Constant---------------------------*/
  52
  53
  54 /*------------------------Define global variable-----------------------------*/
  55 /*------------------------Define global variable-----------------------------*/
  56
  57
  58
  59
  60 /*---------------------Define local function prototype-----------------------*/
  61 void phy_RF6052_Config_HardCode(struct net_device* dev);
  62
  63 RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev);
  64 /*---------------------Define local function prototype-----------------------*/
  65
  66 /*------------------------Define function prototype--------------------------*/
  67 extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate);
  68
  69 /*------------------------Define function prototype--------------------------*/
  70
  71 /*------------------------Define local variable------------------------------*/
  72 // 2008/11/20 MH For Debug only, RF
  73 static  RF_SHADOW_T     RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM
  74 /*------------------------Define local variable------------------------------*/
  75
  76 /*------------------------Define function prototype--------------------------*/
  77 /*-----------------------------------------------------------------------------
  78  * Function:    RF_ChangeTxPath
  79  *
  80  * Overview:    For RL6052, we must change some RF settign for 1T or 2T.
  81  *
  82  * Input:               u16 DataRate            // 0x80-8f, 0x90-9f
  83  *
  84  * Output:      NONE
  85  *
  86  * Return:      NONE
  87  *
  88  * Revised History:
  89  * When                 Who             Remark
  90  * 09/25/2008   MHC             Create Version 0.
  91  *                                              Firmwaer support the utility later.
  92  *
  93  *---------------------------------------------------------------------------*/
  94 extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate)
  95 {
  96 // We do not support gain table change inACUT now !!!! Delete later !!!
  97 #if 0//(RTL92SE_FPGA_VERIFY == 0)
  98         static  u1Byte  RF_Path_Type = 2;       // 1 = 1T 2= 2T
  99         static  u4Byte  tx_gain_tbl1[6]
 100                         = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
 101         static  u4Byte  tx_gain_tbl2[6]
 102                         = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
 103         u1Byte  i;
 104
 105         if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
 106         {
 107                 // Set TX SYNC power G2G3 loop filter
 108                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 109                                         RF_TXPA_G2, bMask20Bits, 0x0f000);
 110                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 111                                         RF_TXPA_G3, bMask20Bits, 0xeacf1);
 112
 113                 // Change TX AGC gain table
 114                 for (i = 0; i < 6; i++)
 115                         PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 116                                                 RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
 117
 118                 // Set PA to high value
 119                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 120                                         RF_TXPA_G2, bMask20Bits, 0x01e39);
 121         }
 122         else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
 123         {
 124                 // Set TX SYNC power G2G3 loop filter
 125                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 126                                         RF_TXPA_G2, bMask20Bits, 0x04440);
 127                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 128                                         RF_TXPA_G3, bMask20Bits, 0xea4f1);
 129
 130                 // Change TX AGC gain table
 131                 for (i = 0; i < 6; i++)
 132                         PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 133                                                 RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
 134
 135                 // Set PA low gain
 136                 PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A,
 137                                         RF_TXPA_G2, bMask20Bits, 0x01e19);
 138         }
 139 #endif
 140
 141 }       /* RF_ChangeTxPath */
 142
 143
 144 /*-----------------------------------------------------------------------------
 145  * Function:    PHY_RF6052SetBandwidth()
 146  *
 147  * Overview:    This function is called by SetBWModeCallback8190Pci() only
 148  *
 149  * Input:       PADAPTER                                Adapter
 150  *                      WIRELESS_BANDWIDTH_E    Bandwidth       //20M or 40M
 151  *
 152  * Output:      NONE
 153  *
 154  * Return:      NONE
 155  *
 156  * Note:                For RF type 0222D
 157  *---------------------------------------------------------------------------*/
 158 void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
 159 {
 160         //u8                            eRFPath;
 161         //struct r8192_priv     *priv = ieee80211_priv(dev);
 162
 163
 164         //if (priv->card_8192 == NIC_8192SE)
 165 #ifdef RTL8192SU  //YJ,test,090113
 166         {
 167                 switch(Bandwidth)
 168                 {
 169                         case HT_CHANNEL_WIDTH_20:
 170                                 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
 171                                 //      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
 172
 173                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
 174                                 break;
 175                         case HT_CHANNEL_WIDTH_20_40:
 176                                 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
 177                                 //      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
 178
 179                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
 180                                 break;
 181                         default:
 182                                 RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
 183                                 break;
 184                 }
 185         }
 186 //      else
 187 #else
 188         {
 189         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
 190         {
 191                 switch(Bandwidth)
 192                 {
 193                         case HT_CHANNEL_WIDTH_20:
 194                                         //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x01);
 195                                 break;
 196                         case HT_CHANNEL_WIDTH_20_40:
 197                                         //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, (BIT10|BIT11), 0x00);
 198                                 break;
 199                         default:
 200                                         RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
 201                                 break;
 202
 203                 }
 204         }
 205         }
 206 #endif
 207 }
 208
 209
 210 /*-----------------------------------------------------------------------------
 211  * Function:    PHY_RF6052SetCckTxPower
 212  *
 213  * Overview:
 214  *
 215  * Input:       NONE
 216  *
 217  * Output:      NONE
 218  *
 219  * Return:      NONE
 220  *
 221  * Revised History:
 222  * When                 Who             Remark
 223  * 11/05/2008   MHC             Simulate 8192series..
 224  *
 225  *---------------------------------------------------------------------------*/
 226 extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8  powerlevel)
 227 {
 228         struct r8192_priv *priv = ieee80211_priv(dev);
 229         u32                             TxAGC=0;
 230
 231         if(priv->ieee80211->scanning == 1)
 232                 TxAGC = 0x3f;
 233         else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
 234                 TxAGC = 0x22;
 235         else
 236                 TxAGC = powerlevel;
 237
 238         //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
 239         if(priv->bIgnoreDiffRateTxPowerOffset)
 240                 TxAGC = powerlevel;
 241
 242         if(TxAGC > RF6052_MAX_TX_PWR)
 243                 TxAGC = RF6052_MAX_TX_PWR;
 244
 245         //printk("CCK PWR= %x\n", TxAGC);
 246         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 247
 248 }       /* PHY_RF6052SetCckTxPower */
 249
 250
 251
 252 /*-----------------------------------------------------------------------------
 253  * Function:    PHY_RF6052SetOFDMTxPower
 254  *
 255  * Overview:    For legacy and HY OFDM, we must read EEPROM TX power index for
 256  *                      different channel and read original value in TX power register area from
 257  *                      0xe00. We increase offset and original value to be correct tx pwr.
 258  *
 259  * Input:       NONE
 260  *
 261  * Output:      NONE
 262  *
 263  * Return:      NONE
 264  *
 265  * Revised History:
 266  * When                 Who             Remark
 267  * 11/05/2008   MHC             Simulate 8192 series method.
 268 * 01/06/2009    MHC             1. Prevent Path B tx power overflow or underflow dure to
 269  *                                              A/B pwr difference or legacy/HT pwr diff.
 270  *                                              2. We concern with path B legacy/HT OFDM difference.
 271  * 01/22/2009   MHC             Support new EPRO format from SD3.
 272  *---------------------------------------------------------------------------*/
 273  #if 1
 274 extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
 275 {
 276         struct r8192_priv *priv = ieee80211_priv(dev);
 277         u32     writeVal, powerBase0, powerBase1;
 278         u8      index = 0;
 279         u16     RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 280         //u8    byte0, byte1, byte2, byte3;
 281         u8    Channel = priv->ieee80211->current_network.channel;
 282         u8      rfa_pwr[4];
 283         u8      rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/;
 284         u8      i;
 285         u8      rf_pwr_diff = 0;
 286         u8      Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0;
 287         u8      ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0;
 288
 289
 290         // We only care about the path A for legacy.
 291         if (priv->EEPROMVersion != 2)
 292         powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
 293         else if (priv->EEPROMVersion == 2)      // Defined by SD1 Jong
 294         {
 295                 //
 296                 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
 297                 //
 298                 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
 299                 // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B
 300                 // legacy OFDM pwr diff. NO BB register to notify HW.
 301                 powerBase0 = powerlevel + Legacy_pwrdiff;
 302                 //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff));
 303
 304                 // Band Edge scheme is enabled for FCC mode
 305                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
 306                 {
 307                         ofdm_bandedge_chnl_low = 1;
 308                         ofdm_bandedge_chnl_high = 11;
 309                 #if 0//cosa, Todo: check ofdm 40MHz, when lower and duplicate, the bandedge chnl low=3, high=9
 310                         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
 311                         {       // Is it the same with the document?
 312                                 if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 313                                 else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER;
 314                                 else
 315                                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
 316                         }
 317                 #endif
 318                         BandEdge_Pwrdiff = 0;
 319                         if (Channel <= ofdm_bandedge_chnl_low)
 320                                 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0];
 321                         else if (Channel >= ofdm_bandedge_chnl_high)
 322                         {
 323                                 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1];
 324                         }
 325                         powerBase0 -= BandEdge_Pwrdiff;
 326                         if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high)
 327                         {
 328                                 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n",
 329                                 //Channel, BandEdge_Pwrdiff));
 330                         }
 331                 }
 332                 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0));
 333         }
 334         powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
 335
 336         //MCS rates
 337         if(priv->EEPROMVersion == 2)
 338         {
 339                 //Cosa add for new EEPROM content. 02102009
 340
 341                 //Check HT20 to HT40 diff
 342                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 343                 {
 344                         // HT 20<->40 pwr diff
 345                         HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1];
 346
 347                         // Calculate Antenna pwr diff
 348                         if (HT20_pwrdiff < 8)   // 0~+7
 349                                 powerlevel += HT20_pwrdiff;
 350                         else                            // index8-15=-8~-1
 351                                 powerlevel -= (16-HT20_pwrdiff);
 352
 353                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff));
 354                         //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
 355                 }
 356
 357                 // Band Edge scheme is enabled for FCC mode
 358                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
 359                 {
 360                         BandEdge_Pwrdiff = 0;
 361                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
 362                         {
 363                                 if (Channel <= 3)
 364                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0];
 365                                 else if (Channel >= 9)
 366                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1];
 367                                 if (Channel <= 3 || Channel >= 9)
 368                                 {
 369                                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n",
 370                                         //Channel, BandEdge_Pwrdiff));
 371                                 }
 372                         }
 373                         else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 374                         {
 375                                 if (Channel <= 1)
 376                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0];
 377                                 else if (Channel >= 11)
 378                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1];
 379                                 if (Channel <= 1 || Channel >= 11)
 380                                 {
 381                                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n",
 382                                         //Channel, BandEdge_Pwrdiff));
 383                                 }
 384                         }
 385                         powerlevel -= BandEdge_Pwrdiff;
 386                         //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
 387                 }
 388         }
 389         powerBase1 = powerlevel;
 390         powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
 391
 392         //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1));
 393
 394         for(index=0; index<6; index++)
 395         {
 396                 //
 397                 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
 398                 //
 399                 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
 400                 if(priv->bIgnoreDiffRateTxPowerOffset)
 401                         writeVal = ((index<2)?powerBase0:powerBase1);
 402                 else
 403                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
 404
 405                 //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n",
 406                 //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal));
 407
 408                 //
 409                 // If path A and Path B coexist, we must limit Path A tx power.
 410                 // Protect Path B pwr over or under flow. We need to calculate upper and
 411                 // lower bound of path A tx power.
 412                 //
 413                 if (priv->rf_type == RF_2T2R)
 414                 {
 415                 #if 0//cosa, we have only one AntennaTxPwDiff
 416                         // HT OFDM
 417                         if (index > 1)
 418                         {
 419                                 rf_pwr_diff = pHalData->AntennaTxPwDiff[0];
 420                         }
 421                         // Legacy OFDM
 422                         else
 423                         {
 424                                 rf_pwr_diff = pHalData->AntTxPwDiffLegacy[0];
 425                         }
 426                 #endif
 427                         rf_pwr_diff = priv->AntennaTxPwDiff[0];
 428                         //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff));
 429
 430                         if (rf_pwr_diff >= 8)           // Diff=-8~-1
 431                         {       // Prevent underflow!!
 432                                 rfa_lower_bound = 0x10-rf_pwr_diff;
 433                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound));
 434                         }
 435                         else if (rf_pwr_diff >= 0)      // Diff = 0-7
 436                         {
 437                                 rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
 438                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound));
 439                         }
 440                 }
 441
 442                 for (i=  0; i <4; i++)
 443                 {
 444                         rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
 445                         if (rfa_pwr[i]  > RF6052_MAX_TX_PWR)
 446                                 rfa_pwr[i]  = RF6052_MAX_TX_PWR;
 447
 448                         //
 449                         // If path A and Path B coexist, we must limit Path A tx power.
 450                         // Protect Path B pwr over or under flow. We need to calculate upper and
 451                         // lower bound of path A tx power.
 452                         //
 453                         if (priv->rf_type == RF_2T2R)
 454                         {
 455                                 if (rf_pwr_diff >= 8)           // Diff=-8~-1
 456                                 {       // Prevent underflow!!
 457                                         if (rfa_pwr[i] <rfa_lower_bound)
 458                                         {
 459                                                 //RTPRINT(FPHY, PHY_TXPWR, ("Underflow"));
 460                                                 rfa_pwr[i] = rfa_lower_bound;
 461                                         }
 462                                 }
 463                                 else if (rf_pwr_diff >= 1)      // Diff = 0-7
 464                                 {       // Prevent overflow
 465                                         if (rfa_pwr[i] > rfa_upper_bound)
 466                                         {
 467                                                 //RTPRINT(FPHY, PHY_TXPWR, ("Overflow"));
 468                                                 rfa_pwr[i] = rfa_upper_bound;
 469                                         }
 470                                 }
 471                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i]));
 472                         }
 473
 474                 }
 475
 476                 //
 477                 // Add description: PWDB > threshold!!!High power issue!!
 478                 // We must decrease tx power !! Why is the value ???
 479                 //
 480                 if(priv->bDynamicTxHighPower == TRUE)
 481                 {
 482                         // For MCS rate
 483                         if(index > 1)
 484                         {
 485                                 writeVal = 0x03030303;
 486                         }
 487                         // For Legacy rate
 488                         else
 489                         {
 490                                 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
 491                         }
 492                         //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal));
 493                 }
 494                 else
 495                 {
 496                         writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
 497                         //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal));
 498                 }
 499
 500                 //
 501                 // Write different rate set tx power index.
 502                 //
 503                 //if (DCMD_Test_Flag == 0)
 504                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 505         }
 506
 507 }       /* PHY_RF6052SetOFDMTxPower */
 508 #else
 509 extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
 510 {
 511         struct r8192_priv *priv = ieee80211_priv(dev);
 512         u32     writeVal, powerBase0, powerBase1;
 513         u8      index = 0;
 514         u16     RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 515         u8      byte0, byte1, byte2, byte3;
 516         u8    channel = priv->ieee80211->current_network.channel;
 517
 518         //Legacy OFDM rates
 519         powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
 520         powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
 521
 522         //MCS rates HT OFDM
 523         powerBase1 = powerlevel;
 524         powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
 525
 526         //printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1);
 527
 528         for(index=0; index<6; index++)
 529         {
 530                 //
 531                 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
 532                 //
 533                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] +  ((index<2)?powerBase0:powerBase1);
 534
 535                 //printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal);
 536
 537                 byte0 = (u8)(writeVal & 0x7f);
 538                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 539                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 540                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 541
 542                 // Max power index = 0x3F Range = 0-0x3F
 543                 if(byte0 > RF6052_MAX_TX_PWR)
 544                         byte0 = RF6052_MAX_TX_PWR;
 545                 if(byte1 > RF6052_MAX_TX_PWR)
 546                         byte1 = RF6052_MAX_TX_PWR;
 547                 if(byte2 > RF6052_MAX_TX_PWR)
 548                         byte2 = RF6052_MAX_TX_PWR;
 549                 if(byte3 > RF6052_MAX_TX_PWR)
 550                         byte3 = RF6052_MAX_TX_PWR;
 551
 552                 //
 553                 // Add description: PWDB > threshold!!!High power issue!!
 554                 // We must decrease tx power !! Why is the value ???
 555                 //
 556                 if(priv->bDynamicTxHighPower == true)
 557                 {
 558                         // For MCS rate
 559                         if(index > 1)
 560                         {
 561                                 writeVal = 0x03030303;
 562                         }
 563                         // For Legacy rate
 564                         else
 565                         {
 566                                 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 567                         }
 568                 }
 569                 else
 570                 {
 571                         writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 572                 }
 573
 574                 //
 575                 // Write different rate set tx power index.
 576                 //
 577                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 578         }
 579
 580 }       /* PHY_RF6052SetOFDMTxPower */
 581 #endif
 582
 583 RT_STATUS PHY_RF6052_Config(struct net_device* dev)
 584 {
 585         struct r8192_priv                       *priv = ieee80211_priv(dev);
 586         RT_STATUS                               rtStatus = RT_STATUS_SUCCESS;
 587         //RF90_RADIO_PATH_E             eRFPath;
 588         //BB_REGISTER_DEFINITION_T      *pPhyReg;
 589         //u32                                           OrgStoreRFIntSW[RF90_PATH_D+1];
 590
 591         //
 592         // Initialize general global value
 593         //
 594         // TODO: Extend RF_PATH_C and RF_PATH_D in the future
 595         if(priv->rf_type == RF_1T1R)
 596                 priv->NumTotalRFPath = 1;
 597         else
 598                 priv->NumTotalRFPath = 2;
 599
 600         //
 601         // Config BB and RF
 602         //
 603 //      switch( priv->bRegHwParaFile )
 604 //      {
 605 //              case 0:
 606 //                      phy_RF6052_Config_HardCode(dev);
 607 //                      break;
 608
 609 //              case 1:
 610                         rtStatus = phy_RF6052_Config_ParaFile(dev);
 611 //                      break;
 612
 613 //              case 2:
 614                         // Partial Modify.
 615 //                      phy_RF6052_Config_HardCode(dev);
 616 //                      phy_RF6052_Config_ParaFile(dev);
 617 //                      break;
 618
 619 //              default:
 620 //                      phy_RF6052_Config_HardCode(dev);
 621 //                      break;
 622 //      }
 623         return rtStatus;
 624
 625 }
 626
 627 void phy_RF6052_Config_HardCode(struct net_device* dev)
 628 {
 629
 630         // Set Default Bandwidth to 20M
 631         //Adapter->HalFunc      .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
 632
 633         // TODO: Set Default Channel to channel one for RTL8225
 634
 635 }
 636
 637 RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev)
 638 {
 639         u32                     u4RegValue = 0;
 640         //static s1Byte         szRadioAFile[] = RTL819X_PHY_RADIO_A;
 641         //static s1Byte         szRadioBFile[] = RTL819X_PHY_RADIO_B;
 642         //static s1Byte         szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM;
 643         u8                      eRFPath;
 644         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 645         struct r8192_priv       *priv = ieee80211_priv(dev);
 646         BB_REGISTER_DEFINITION_T        *pPhyReg;
 647         //u8                    eCheckItem;
 648
 649
 650         //3//-----------------------------------------------------------------
 651         //3// <2> Initialize RF
 652         //3//-----------------------------------------------------------------
 653         //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
 654         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
 655         {
 656
 657                 pPhyReg = &priv->PHYRegDef[eRFPath];
 658
 659                 /*----Store original RFENV control type----*/
 660                 switch(eRFPath)
 661                 {
 662                 case RF90_PATH_A:
 663                 case RF90_PATH_C:
 664                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 665                         break;
 666                 case RF90_PATH_B :
 667                 case RF90_PATH_D:
 668                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 669                         break;
 670                 }
 671
 672                 /*----Set RF_ENV enable----*/
 673                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 674
 675                 /*----Set RF_ENV output high----*/
 676                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 677
 678                 /* Set bit number of Address and Data for RF register */
 679                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  // Set 1 to 4 bits for 8255
 680                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     // Set 0 to 12  bits for 8255
 681
 682
 683                 /*----Initialize RF fom connfiguration file----*/
 684                 switch(eRFPath)
 685                 {
 686                 case RF90_PATH_A:
 687 #if     RTL8190_Download_Firmware_From_Header
 688                         rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
 689 #else
 690                         rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
 691 #endif
 692                         break;
 693                 case RF90_PATH_B:
 694 #if     RTL8190_Download_Firmware_From_Header
 695                         rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
 696 #else
 697                         if(priv->rf_type == RF_2T2R_GREEN)
 698                                 rtStatus = PHY_ConfigRFWithParaFile(Adapter, (ps1Byte)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath);
 699                         else
 700                                 rtStatus = PHY_ConfigRFWithParaFile(Adapter, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
 701 #endif
 702                         break;
 703                 case RF90_PATH_C:
 704                         break;
 705                 case RF90_PATH_D:
 706                         break;
 707                 }
 708
 709                 /*----Restore RFENV control type----*/;
 710                 switch(eRFPath)
 711                 {
 712                 case RF90_PATH_A:
 713                 case RF90_PATH_C:
 714                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 715                         break;
 716                 case RF90_PATH_B :
 717                 case RF90_PATH_D:
 718                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 719                         break;
 720                 }
 721
 722                 if(rtStatus != RT_STATUS_SUCCESS){
 723                         printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
 724                         goto phy_RF6052_Config_ParaFile_Fail;
 725                 }
 726
 727         }
 728
 729         RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
 730         return rtStatus;
 731
 732 phy_RF6052_Config_ParaFile_Fail:
 733         return rtStatus;
 734 }
 735
 736
 737 //
 738 // ==> RF shadow Operation API Code Section!!!
 739 //
 740 /*-----------------------------------------------------------------------------
 741  * Function:    PHY_RFShadowRead
 742  *                              PHY_RFShadowWrite
 743  *                              PHY_RFShadowCompare
 744  *                              PHY_RFShadowRecorver
 745  *                              PHY_RFShadowCompareAll
 746  *                              PHY_RFShadowRecorverAll
 747  *                              PHY_RFShadowCompareFlagSet
 748  *                              PHY_RFShadowRecorverFlagSet
 749  *
 750  * Overview:    When we set RF register, we must write shadow at first.
 751  *                      When we are running, we must compare shadow abd locate error addr.
 752  *                      Decide to recorver or not.
 753  *
 754  * Input:       NONE
 755  *
 756  * Output:      NONE
 757  *
 758  * Return:      NONE
 759  *
 760  * Revised History:
 761  * When                 Who             Remark
 762  * 11/20/2008   MHC             Create Version 0.
 763  *
 764  *---------------------------------------------------------------------------*/
 765 extern u32 PHY_RFShadowRead(
 766         struct net_device               * dev,
 767         RF90_RADIO_PATH_E       eRFPath,
 768         u32                                     Offset)
 769 {
 770         return  RF_Shadow[eRFPath][Offset].Value;
 771
 772 }       /* PHY_RFShadowRead */
 773
 774
 775 extern void PHY_RFShadowWrite(
 776         struct net_device               * dev,
 777         u32     eRFPath,
 778         u32                                     Offset,
 779         u32                                     Data)
 780 {
 781         //RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits);
 782         RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
 783         RF_Shadow[eRFPath][Offset].Driver_Write = true;
 784
 785 }       /* PHY_RFShadowWrite */
 786
 787
 788 extern void PHY_RFShadowCompare(
 789         struct net_device               * dev,
 790         RF90_RADIO_PATH_E       eRFPath,
 791         u32                                     Offset)
 792 {
 793         u32     reg;
 794
 795         // Check if we need to check the register
 796         if (RF_Shadow[eRFPath][Offset].Compare == true)
 797         {
 798                 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask);
 799                 // Compare shadow and real rf register for 20bits!!
 800                 if (RF_Shadow[eRFPath][Offset].Value != reg)
 801                 {
 802                         // Locate error position.
 803                         RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
 804                         RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg);
 805                 }
 806         }
 807
 808 }       /* PHY_RFShadowCompare */
 809
 810 extern void PHY_RFShadowRecorver(
 811         struct net_device               * dev,
 812         RF90_RADIO_PATH_E       eRFPath,
 813         u32                                     Offset)
 814 {
 815         // Check if the address is error
 816         if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
 817         {
 818                 // Check if we need to recorver the register.
 819                 if (RF_Shadow[eRFPath][Offset].Recorver == true)
 820                 {
 821                         rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value);
 822                         RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
 823                         eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
 824                 }
 825         }
 826
 827 }       /* PHY_RFShadowRecorver */
 828
 829
 830 extern void PHY_RFShadowCompareAll(struct net_device * dev)
 831 {
 832         u32             eRFPath;
 833         u32             Offset;
 834
 835         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 836         {
 837                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 838                 {
 839                         PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
 840                 }
 841         }
 842
 843 }       /* PHY_RFShadowCompareAll */
 844
 845
 846 extern void PHY_RFShadowRecorverAll(struct net_device * dev)
 847 {
 848         u32             eRFPath;
 849         u32             Offset;
 850
 851         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 852         {
 853                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 854                 {
 855                         PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
 856                 }
 857         }
 858
 859 }       /* PHY_RFShadowRecorverAll */
 860
 861
 862 extern void PHY_RFShadowCompareFlagSet(
 863         struct net_device               * dev,
 864         RF90_RADIO_PATH_E       eRFPath,
 865         u32                                     Offset,
 866         u8                                      Type)
 867 {
 868         // Set True or False!!!
 869         RF_Shadow[eRFPath][Offset].Compare = Type;
 870
 871 }       /* PHY_RFShadowCompareFlagSet */
 872
 873
 874 extern void PHY_RFShadowRecorverFlagSet(
 875         struct net_device               * dev,
 876         RF90_RADIO_PATH_E       eRFPath,
 877         u32                                     Offset,
 878         u8                                      Type)
 879 {
 880         // Set True or False!!!
 881         RF_Shadow[eRFPath][Offset].Recorver= Type;
 882
 883 }       /* PHY_RFShadowRecorverFlagSet */
 884
 885
 886 extern void PHY_RFShadowCompareFlagSetAll(struct net_device  * dev)
 887 {
 888         u32             eRFPath;
 889         u32             Offset;
 890
 891         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 892         {
 893                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 894                 {
 895                         // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
 896                         if (Offset != 0x26 && Offset != 0x27)
 897                                 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
 898                         else
 899                                 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
 900                 }
 901         }
 902
 903 }       /* PHY_RFShadowCompareFlagSetAll */
 904
 905
 906 extern void PHY_RFShadowRecorverFlagSetAll(struct net_device  * dev)
 907 {
 908         u32             eRFPath;
 909         u32             Offset;
 910
 911         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 912         {
 913                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 914                 {
 915                         // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
 916                         if (Offset != 0x26 && Offset != 0x27)
 917                                 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
 918                         else
 919                                 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
 920                 }
 921         }
 922
 923 }       /* PHY_RFShadowCompareFlagSetAll */
 924
 925
 926
 927 extern void PHY_RFShadowRefresh(struct net_device  * dev)
 928 {
 929         u32             eRFPath;
 930         u32             Offset;
 931
 932         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 933         {
 934                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 935                 {
 936                         RF_Shadow[eRFPath][Offset].Value = 0;
 937                         RF_Shadow[eRFPath][Offset].Compare = false;
 938                         RF_Shadow[eRFPath][Offset].Recorver  = false;
 939                         RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
 940                         RF_Shadow[eRFPath][Offset].Driver_Write = false;
 941                 }
 942         }
 943
 944 }       /* PHY_RFShadowRead */
 945
 946 /* End of HalRf6052.c */