SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #include "r8180_pm.h"
  34
  35 #include "ieee80211/dot11d.h"
  36
  37
  38 //#define CONFIG_RTL8180_IO_MAP
  39
  40 #define TC_3W_POLL_MAX_TRY_CNT 5
  41 static u8 MAC_REG_TABLE[][2]={
  42                         //PAGA 0:
  43                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  44                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  45                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  46                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  47                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  48                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  49                         {0x94, 0x0F}, {0x95, 0x32},
  50                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  51                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  52                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  53                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  54                         {0xff, 0x00},
  55
  56                         //PAGE 1:
  57                         // For Flextronics system Logo PCIHCT failure:
  58                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  59                         {0x5e, 0x01},
  60                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  61                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  62                         {0x82, 0xFF}, {0x83, 0x03},
  63                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  64                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  65                         {0xe2, 0x00},
  66
  67
  68                         //PAGE 2:
  69                         {0x5e, 0x02},
  70                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  71                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  72                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  73                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  74                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  75                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  76                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  77
  78                         //PAGA 0:
  79                         {0x5e, 0x00},{0x9f, 0x03}
  80                 };
  81
  82
  83 static u8  ZEBRA_AGC[]={
  84                         0,
  85                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  86                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  87                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  88                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  89                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  90                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  91                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  92                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  93                         };
  94
  95 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  96                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  97                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  98                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  99                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 100                         0x0183,0x0163,0x0143,0x0123,0x0103
 101         };
 102
 103 static u8 OFDM_CONFIG[]={
 104                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 105                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 106                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 107
 108                         // 0x00
 109                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 110                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 111                         // 0x10
 112                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 113                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 114                         // 0x20
 115                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 116                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 117                         // 0x30
 118                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 119                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 120                 };
 121
 122 /*---------------------------------------------------------------
 123   * Hardware IO
 124   * the code is ported from Windows source code
 125   ----------------------------------------------------------------*/
 126
 127 void
 128 PlatformIOWrite1Byte(
 129         struct net_device *dev,
 130         u32             offset,
 131         u8              data
 132         )
 133 {
 134 #ifndef CONFIG_RTL8180_IO_MAP
 135         write_nic_byte(dev, offset, data);
 136         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 137
 138 #else // Port IO
 139         u32 Page = (offset >> 8);
 140
 141         switch(Page)
 142         {
 143         case 0: // Page 0
 144                 write_nic_byte(dev, offset, data);
 145                 break;
 146
 147         case 1: // Page 1
 148         case 2: // Page 2
 149         case 3: // Page 3
 150                 {
 151                         u8 psr = read_nic_byte(dev, PSR);
 152
 153                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 154                         write_nic_byte(dev, (offset & 0xff), data);
 155                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 156                 }
 157                 break;
 158
 159         default:
 160                 // Illegal page number.
 161                 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 162                 break;
 163         }
 164 #endif
 165 }
 166
 167 void
 168 PlatformIOWrite2Byte(
 169         struct net_device *dev,
 170         u32             offset,
 171         u16             data
 172         )
 173 {
 174 #ifndef CONFIG_RTL8180_IO_MAP
 175         write_nic_word(dev, offset, data);
 176         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 177
 178
 179 #else // Port IO
 180         u32 Page = (offset >> 8);
 181
 182         switch(Page)
 183         {
 184         case 0: // Page 0
 185                 write_nic_word(dev, offset, data);
 186                 break;
 187
 188         case 1: // Page 1
 189         case 2: // Page 2
 190         case 3: // Page 3
 191                 {
 192                         u8 psr = read_nic_byte(dev, PSR);
 193
 194                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 195                         write_nic_word(dev, (offset & 0xff), data);
 196                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 197                 }
 198                 break;
 199
 200         default:
 201                 // Illegal page number.
 202                 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 203                 break;
 204         }
 205 #endif
 206 }
 207 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 208
 209 void
 210 PlatformIOWrite4Byte(
 211         struct net_device *dev,
 212         u32             offset,
 213         u32             data
 214         )
 215 {
 216 #ifndef CONFIG_RTL8180_IO_MAP
 217 //{by amy 080312
 218 if (offset == PhyAddr)
 219         {//For Base Band configuration.
 220                 unsigned char   cmdByte;
 221                 unsigned long   dataBytes;
 222                 unsigned char   idx;
 223                 u8      u1bTmp;
 224
 225                 cmdByte = (u8)(data & 0x000000ff);
 226                 dataBytes = data>>8;
 227
 228                 //
 229                 // 071010, rcnjko:
 230                 // The critical section is only BB read/write race condition.
 231                 // Assumption:
 232                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 233                 // acquiring the spinlock in such context.
 234                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 235                 //
 236 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 237
 238                 for(idx = 0; idx < 30; idx++)
 239                 { // Make sure command bit is clear before access it.
 240                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 241                         if((u1bTmp & BIT7) == 0)
 242                                 break;
 243                         else
 244                                 mdelay(10);
 245                 }
 246
 247                 for(idx=0; idx < 3; idx++)
 248                 {
 249                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 250                 }
 251                 write_nic_byte(dev, offset, cmdByte);
 252
 253 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 254         }
 255 //by amy 080312}
 256         else{
 257                 write_nic_dword(dev, offset, data);
 258                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 259         }
 260 #else // Port IO
 261         u32 Page = (offset >> 8);
 262
 263         switch(Page)
 264         {
 265         case 0: // Page 0
 266                 write_nic_word(dev, offset, data);
 267                 break;
 268
 269         case 1: // Page 1
 270         case 2: // Page 2
 271         case 3: // Page 3
 272                 {
 273                         u8 psr = read_nic_byte(dev, PSR);
 274
 275                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 276                         write_nic_dword(dev, (offset & 0xff), data);
 277                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 278                 }
 279                 break;
 280
 281         default:
 282                 // Illegal page number.
 283                 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
 284                 break;
 285         }
 286 #endif
 287 }
 288
 289 u8
 290 PlatformIORead1Byte(
 291         struct net_device *dev,
 292         u32             offset
 293         )
 294 {
 295         u8      data = 0;
 296
 297 #ifndef CONFIG_RTL8180_IO_MAP
 298         data = read_nic_byte(dev, offset);
 299
 300 #else // Port IO
 301         u32 Page = (offset >> 8);
 302
 303         switch(Page)
 304         {
 305         case 0: // Page 0
 306                 data = read_nic_byte(dev, offset);
 307                 break;
 308
 309         case 1: // Page 1
 310         case 2: // Page 2
 311         case 3: // Page 3
 312                 {
 313                         u8 psr = read_nic_byte(dev, PSR);
 314
 315                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 316                         data = read_nic_byte(dev, (offset & 0xff));
 317                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 318                 }
 319                 break;
 320
 321         default:
 322                 // Illegal page number.
 323                 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 324                 break;
 325         }
 326 #endif
 327
 328         return data;
 329 }
 330
 331 u16
 332 PlatformIORead2Byte(
 333         struct net_device *dev,
 334         u32             offset
 335         )
 336 {
 337         u16     data = 0;
 338
 339 #ifndef CONFIG_RTL8180_IO_MAP
 340         data = read_nic_word(dev, offset);
 341
 342 #else // Port IO
 343         u32 Page = (offset >> 8);
 344
 345         switch(Page)
 346         {
 347         case 0: // Page 0
 348                 data = read_nic_word(dev, offset);
 349                 break;
 350
 351         case 1: // Page 1
 352         case 2: // Page 2
 353         case 3: // Page 3
 354                 {
 355                         u8 psr = read_nic_byte(dev, PSR);
 356
 357                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 358                         data = read_nic_word(dev, (offset & 0xff));
 359                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 360                 }
 361                 break;
 362
 363         default:
 364                 // Illegal page number.
 365                 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 366                 break;
 367         }
 368 #endif
 369
 370         return data;
 371 }
 372
 373 u32
 374 PlatformIORead4Byte(
 375         struct net_device *dev,
 376         u32             offset
 377         )
 378 {
 379         u32     data = 0;
 380
 381 #ifndef CONFIG_RTL8180_IO_MAP
 382         data = read_nic_dword(dev, offset);
 383
 384 #else // Port IO
 385         u32 Page = (offset >> 8);
 386
 387         switch(Page)
 388         {
 389         case 0: // Page 0
 390                 data = read_nic_dword(dev, offset);
 391                 break;
 392
 393         case 1: // Page 1
 394         case 2: // Page 2
 395         case 3: // Page 3
 396                 {
 397                         u8 psr = read_nic_byte(dev, PSR);
 398
 399                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 400                         data = read_nic_dword(dev, (offset & 0xff));
 401                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 402                 }
 403                 break;
 404
 405         default:
 406                 // Illegal page number.
 407                 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
 408                 break;
 409         }
 410 #endif
 411
 412         return data;
 413 }
 414
 415 void
 416 SetOutputEnableOfRfPins(
 417         struct net_device *dev
 418         )
 419 {
 420         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 421
 422         switch(priv->rf_chip)
 423         {
 424         case RFCHIPID_RTL8225:
 425         case RF_ZEBRA2:
 426         case RF_ZEBRA4:
 427                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 428                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 429                 break;
 430         }
 431 }
 432
 433 void
 434 ZEBRA_RFSerialWrite(
 435         struct net_device *dev,
 436         u32                     data2Write,
 437         u8                      totalLength,
 438         u8                      low2high
 439         )
 440 {
 441         ThreeWireReg            twreg;
 442         int                             i;
 443         u16                             oval,oval2,oval3;
 444         u32                             mask;
 445         u16                             UshortBuffer;
 446
 447         u8                      u1bTmp;
 448         // RTL8187S HSSI Read/Write Function
 449         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 450         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 451         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 452         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 453         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 454
 455         oval2 = read_nic_word(dev, RFPinsEnable);
 456         oval3 = read_nic_word(dev, RFPinsSelect);
 457
 458         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 459         oval3 &= 0xfff8;
 460
 461         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 462         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 463         udelay(10);
 464
 465         // Add this to avoid hardware and software 3-wire conflict.
 466         // 2005.03.01, by rcnjko.
 467         twreg.longData = 0;
 468         twreg.struc.enableB = 1;
 469         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 470         udelay(2);
 471         twreg.struc.enableB = 0;
 472         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 473         udelay(10);
 474
 475         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 476
 477         for(i=0; i<totalLength/2; i++)
 478         {
 479                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 480                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 481                 twreg.struc.clk = 1;
 482                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 483                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 484
 485                 mask = (low2high)?(mask<<1):(mask>>1);
 486                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 487                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 488                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 489                 twreg.struc.clk = 0;
 490                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 491                 mask = (low2high)?(mask<<1):(mask>>1);
 492         }
 493
 494         twreg.struc.enableB = 1;
 495         twreg.struc.clk = 0;
 496         twreg.struc.data = 0;
 497         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 498         udelay(10);
 499
 500         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 501         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 502
 503         SetOutputEnableOfRfPins(dev);
 504 }
 505 //by amy
 506
 507
 508 int
 509 HwHSSIThreeWire(
 510         struct net_device *dev,
 511         u8                      *pDataBuf,
 512         u8                      nDataBufBitCnt,
 513         int                     bSI,
 514         int                     bWrite
 515         )
 516 {
 517         int     bResult = 1;
 518         u8      TryCnt;
 519         u8      u1bTmp;
 520
 521         do
 522         {
 523                 // Check if WE and RE are cleared.
 524                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 525                 {
 526                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 527                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 528                         {
 529                                 break;
 530                         }
 531                         udelay(10);
 532                 }
 533                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 534                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 535
 536                 // RTL8187S HSSI Read/Write Function
 537                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 538
 539                 if(bSI)
 540                 {
 541                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 542                 }else
 543                 {
 544                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 545                 }
 546
 547                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 548
 549                 if(bSI)
 550                 {
 551                         // jong: HW SI read must set reg84[3]=0.
 552                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 553                         u1bTmp &= ~BIT3;
 554                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 555                 }
 556                 // Fill up data buffer for write operation.
 557
 558                 if(bWrite)
 559                 {
 560                         if(nDataBufBitCnt == 16)
 561                         {
 562                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 563                         }
 564                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 565                         {
 566                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 567                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 568                         }
 569                         else
 570                         {
 571                                 int idx;
 572                                 int ByteCnt = nDataBufBitCnt / 8;
 573                                 //printk("%d\n",nDataBufBitCnt);
 574                                 if ((nDataBufBitCnt % 8) != 0)
 575                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 576                                 nDataBufBitCnt);
 577
 578                                if (nDataBufBitCnt > 64)
 579                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 580                                 nDataBufBitCnt);
 581
 582                                 for(idx = 0; idx < ByteCnt; idx++)
 583                                 {
 584                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 585                                 }
 586                         }
 587                 }
 588                 else            //read
 589                 {
 590                         if(bSI)
 591                         {
 592                                 // SI - reg274[3:0] : RF register's Address
 593                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 594                         }
 595                         else
 596                         {
 597                                 // PI - reg274[15:12] : RF register's Address
 598                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 599                         }
 600                 }
 601
 602                 // Set up command: WE or RE.
 603                 if(bWrite)
 604                 {
 605                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 606                 }
 607                 else
 608                 {
 609                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 610                 }
 611
 612                 // Check if DONE is set.
 613                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 614                 {
 615                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 616                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 617                         {
 618                                 break;
 619                         }
 620                         udelay(10);
 621                 }
 622
 623                 write_nic_byte(dev, SW_3W_CMD1, 0);
 624
 625                 // Read back data for read operation.
 626                 if(bWrite == 0)
 627                 {
 628                         if(bSI)
 629                         {
 630                                 //Serial Interface : reg363_362[11:0]
 631                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 632                         }
 633                         else
 634                         {
 635                                 //Parallel Interface : reg361_360[11:0]
 636                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 637                         }
 638
 639                         *((u16*)pDataBuf) &= 0x0FFF;
 640                 }
 641
 642         }while(0);
 643
 644         return bResult;
 645 }
 646 //by amy
 647
 648 int
 649 HwThreeWire(
 650         struct net_device *dev,
 651         u8                      *pDataBuf,
 652         u8                      nDataBufBitCnt,
 653         int                     bHold,
 654         int                     bWrite
 655         )
 656 {
 657         int     bResult = 1;
 658         u8      TryCnt;
 659         u8      u1bTmp;
 660
 661         do
 662         {
 663                 // Check if WE and RE are cleared.
 664                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 665                 {
 666                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 667                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 668                         {
 669                                 break;
 670                         }
 671                         udelay(10);
 672                 }
 673                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 674                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 675
 676                 // Fill up data buffer for write operation.
 677                 if(nDataBufBitCnt == 16)
 678                 {
 679                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 680                 }
 681                 else if(nDataBufBitCnt == 64)
 682                 {
 683                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 684                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 685                 }
 686                 else
 687                 {
 688                         int idx;
 689                         int ByteCnt = nDataBufBitCnt / 8;
 690
 691                         if ((nDataBufBitCnt % 8) != 0)
 692                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 693                                 nDataBufBitCnt);
 694
 695                         if (nDataBufBitCnt > 64)
 696                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 697                                 nDataBufBitCnt);
 698
 699                         for(idx = 0; idx < ByteCnt; idx++)
 700                         {
 701                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 702                         }
 703                 }
 704
 705                 // Fill up length field.
 706                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 707                 if(bHold)
 708                         u1bTmp |= SW_3W_CMD0_HOLD;
 709                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 710
 711                 // Set up command: WE or RE.
 712                 if(bWrite)
 713                 {
 714                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 715                 }
 716                 else
 717                 {
 718                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 719                 }
 720
 721                 // Check if WE and RE are cleared and DONE is set.
 722                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 723                 {
 724                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 725                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 726                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 727                         {
 728                                 break;
 729                         }
 730                         udelay(10);
 731                 }
 732                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 733                 {
 734                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 735                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 736                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 737                         write_nic_byte(dev, SW_3W_CMD1, 0);
 738                 }
 739
 740                 // Read back data for read operation.
 741                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 742                 if(bWrite == 0)
 743                 {
 744                         if(nDataBufBitCnt == 16)
 745                         {
 746                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 747                         }
 748                         else if(nDataBufBitCnt == 64)
 749                         {
 750                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 751                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 752                         }
 753                         else
 754                         {
 755                                 int idx;
 756                                 int ByteCnt = nDataBufBitCnt / 8;
 757
 758                                 if ((nDataBufBitCnt % 8) != 0)
 759                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 760                                         nDataBufBitCnt);
 761
 762                                 if (nDataBufBitCnt > 64)
 763                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 764                                         nDataBufBitCnt);
 765
 766                                 for(idx = 0; idx < ByteCnt; idx++)
 767                                 {
 768                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 769                                 }
 770                         }
 771                 }
 772
 773         }while(0);
 774
 775         return bResult;
 776 }
 777
 778
 779 void
 780 RF_WriteReg(
 781         struct net_device *dev,
 782         u8              offset,
 783         u32             data
 784         )
 785 {
 786         //RFReg                 reg;
 787         u32                     data2Write;
 788         u8                      len;
 789         u8                      low2high;
 790         //u32                   RF_Read = 0;
 791         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 792
 793
 794         switch(priv->rf_chip)
 795         {
 796         case RFCHIPID_RTL8225:
 797         case RF_ZEBRA2:         // Annie 2006-05-12.
 798         case RF_ZEBRA4:        //by amy
 799                 switch(priv->RegThreeWireMode)
 800                 {
 801                 case SW_THREE_WIRE:
 802                         { // Perform SW 3-wire programming by driver.
 803                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 804                                 len = 16;
 805                                 low2high = 0;
 806                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 807                         }
 808                         break;
 809
 810                 case HW_THREE_WIRE:
 811                         { // Pure HW 3-wire.
 812                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 813                                 len = 16;
 814                                 HwThreeWire(
 815                                         dev,
 816                                         (u8 *)(&data2Write),    // pDataBuf,
 817                                         len,                            // nDataBufBitCnt,
 818                                         0,                                      // bHold,
 819                                         1);                                     // bWrite
 820                         }
 821                         break;
 822                         case HW_THREE_WIRE_PI: //Parallel Interface
 823                         { // Pure HW 3-wire.
 824                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 825                                 len = 16;
 826                                         HwHSSIThreeWire(
 827                                                 dev,
 828                                                 (u8*)(&data2Write),     // pDataBuf,
 829                                                 len,                                            // nDataBufBitCnt,
 830                                                 0,                                      // bSI
 831                                                 1);                                     // bWrite
 832
 833                                 //printk("33333\n");
 834                         }
 835                         break;
 836
 837                         case HW_THREE_WIRE_SI: //Serial Interface
 838                         { // Pure HW 3-wire.
 839                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 840                                 len = 16;
 841 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 842 //                                low2high = 0;
 843 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 844
 845                                 HwHSSIThreeWire(
 846                                         dev,
 847                                         (u8*)(&data2Write),     // pDataBuf,
 848                                         len,                                            // nDataBufBitCnt,
 849                                         1,                                      // bSI
 850                                         1);                                     // bWrite
 851
 852 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 853                         }
 854                         break;
 855
 856
 857                 default:
 858                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 859                         break;
 860                 }
 861                 break;
 862
 863         default:
 864                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 865                 break;
 866         }
 867 }
 868
 869
 870 void
 871 ZEBRA_RFSerialRead(
 872         struct net_device *dev,
 873         u32             data2Write,
 874         u8              wLength,
 875         u32             *data2Read,
 876         u8              rLength,
 877         u8              low2high
 878         )
 879 {
 880         ThreeWireReg    twreg;
 881         int                             i;
 882         u16                     oval,oval2,oval3,tmp, wReg80;
 883         u32                     mask;
 884         u8                      u1bTmp;
 885         ThreeWireReg    tdata;
 886         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 887         { // RTL8187S HSSI Read/Write Function
 888                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 889                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 890                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 891         }
 892
 893         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 894         oval2 = read_nic_word(dev, RFPinsEnable);
 895         oval3 = read_nic_word(dev, RFPinsSelect);
 896
 897         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 898         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 899
 900         *data2Read = 0;
 901
 902         // We must clear BIT0-3 here, otherwise,
 903         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 904         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 905         oval &= ~0xf;
 906
 907         // Avoid collision with hardware three-wire.
 908         twreg.longData = 0;
 909         twreg.struc.enableB = 1;
 910         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 911
 912         twreg.longData = 0;
 913         twreg.struc.enableB = 0;
 914         twreg.struc.clk = 0;
 915         twreg.struc.read_write = 0;
 916         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 917
 918         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 919         for(i = 0; i < wLength/2; i++)
 920         {
 921                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 922                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 923                 twreg.struc.clk = 1;
 924                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 925                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 926
 927                 mask = (low2high) ? (mask<<1): (mask>>1);
 928
 929                 if(i == 2)
 930                 {
 931                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 932                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 933                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 934
 935                         twreg.struc.read_write=1;
 936                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 937                         twreg.struc.clk = 0;
 938                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 939                         break;
 940                 }
 941                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 942                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 943                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 944
 945                 twreg.struc.clk = 0;
 946                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 947
 948                 mask = (low2high) ? (mask<<1) : (mask>>1);
 949         }
 950
 951         twreg.struc.clk = 0;
 952         twreg.struc.data = 0;
 953         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 954         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 955
 956         //
 957         // 061016, by rcnjko:
 958         // We must set data pin to HW controled, otherwise RF can't driver it and
 959         // value RF register won't be able to read back properly.
 960         //
 961         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 962
 963         for(i = 0; i < rLength; i++)
 964         {
 965                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 966                 twreg.struc.clk = 1;
 967                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 968                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 969                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 970                 tmp = read_nic_word(dev, RFPinsInput);
 971                 tdata.longData = tmp;
 972                 *data2Read |= tdata.struc.clk ? mask : 0;
 973
 974                 twreg.struc.clk = 0;
 975                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 976
 977                 mask = (low2high) ? (mask<<1) : (mask>>1);
 978         }
 979         twreg.struc.enableB = 1;
 980         twreg.struc.clk = 0;
 981         twreg.struc.data = 0;
 982         twreg.struc.read_write = 1;
 983         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 984
 985         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 986         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 987         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 988         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 989         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 990         write_nic_word(dev, RFPinsOutput, 0x3a0);
 991         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 992 }
 993
 994
 995 u32
 996 RF_ReadReg(
 997         struct net_device *dev,
 998         u8              offset
 999         )
1000 {
1001         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1002         u32                     data2Write;
1003         u8                      wlen;
1004         u8                      rlen;
1005         u8                      low2high;
1006         u32                     dataRead;
1007
1008         switch(priv->rf_chip)
1009         {
1010         case RFCHIPID_RTL8225:
1011         case RF_ZEBRA2:
1012         case RF_ZEBRA4:
1013                 switch(priv->RegThreeWireMode)
1014                 {
1015                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
1016                         {
1017                                 data2Write = ((u32)(offset&0x0f));
1018                                 wlen=16;
1019                                 HwHSSIThreeWire(
1020                                         dev,
1021                                         (u8*)(&data2Write),     // pDataBuf,
1022                                         wlen,                                   // nDataBufBitCnt,
1023                                         0,                                      // bSI
1024                                         0);                                     // bWrite
1025                                 dataRead= data2Write;
1026                         }
1027                         break;
1028
1029                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1030                         {
1031                                 data2Write = ((u32)(offset&0x0f)) ;
1032                                 wlen=16;
1033                                 HwHSSIThreeWire(
1034                                         dev,
1035                                         (u8*)(&data2Write),     // pDataBuf,
1036                                         wlen,                                   // nDataBufBitCnt,
1037                                         1,                                      // bSI
1038                                         0                                       // bWrite
1039                                         );
1040                                 dataRead= data2Write;
1041                         }
1042                         break;
1043
1044                         // Perform SW 3-wire programming by driver.
1045                         default:
1046                         {
1047                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1048                                 wlen = 6;
1049                                 rlen = 12;
1050                                 low2high = 0;
1051                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1052                         }
1053                         break;
1054                 }
1055                 break;
1056         default:
1057                 dataRead = 0;
1058                 break;
1059         }
1060
1061         return dataRead;
1062 }
1063
1064
1065 // by Owen on 04/07/14 for writing BB register successfully
1066 void
1067 WriteBBPortUchar(
1068         struct net_device *dev,
1069         u32             Data
1070         )
1071 {
1072         //u8    TimeoutCounter;
1073         u8      RegisterContent;
1074         u8      UCharData;
1075
1076         UCharData = (u8)((Data & 0x0000ff00) >> 8);
1077         PlatformIOWrite4Byte(dev, PhyAddr, Data);
1078         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1079         {
1080                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1081                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1082                 //if(UCharData == RegisterContent)
1083                 //      break;
1084         }
1085 }
1086
1087 u8
1088 ReadBBPortUchar(
1089         struct net_device *dev,
1090         u32             addr
1091         )
1092 {
1093         //u8    TimeoutCounter;
1094         u8      RegisterContent;
1095
1096         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1097         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1098
1099         return RegisterContent;
1100 }
1101 //{by amy 080312
1102 //
1103 //      Description:
1104 //              Perform Antenna settings with antenna diversity on 87SE.
1105 //    Created by Roger, 2008.01.25.
1106 //
1107 bool
1108 SetAntennaConfig87SE(
1109         struct net_device *dev,
1110         u8                      DefaultAnt,             // 0: Main, 1: Aux.
1111         bool            bAntDiversity   // 1:Enable, 0: Disable.
1112 )
1113 {
1114         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1115         bool   bAntennaSwitched = true;
1116
1117         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1118
1119         // Threshold for antenna diversity.
1120         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1121
1122         if( bAntDiversity )  //  Enable Antenna Diversity.
1123         {
1124                 if( DefaultAnt == 1 )  // aux antenna
1125                 {
1126                         // Mac register, aux antenna
1127                         write_nic_byte(dev, ANTSEL, 0x00);
1128
1129                         // Config CCK RX antenna.
1130                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1131                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1132
1133                         // Config OFDM RX antenna.
1134                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1135                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1136                 }
1137                 else //  use main antenna
1138                 {
1139                         // Mac register, main antenna
1140                         write_nic_byte(dev, ANTSEL, 0x03);
1141                         //base band
1142                         // Config CCK RX antenna.
1143                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1144                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1145
1146                         // Config OFDM RX antenna.
1147                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1148                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1149                 }
1150         }
1151         else   // Disable Antenna Diversity.
1152         {
1153                 if( DefaultAnt == 1 ) // aux Antenna
1154                 {
1155                         // Mac register, aux antenna
1156                         write_nic_byte(dev, ANTSEL, 0x00);
1157
1158                         // Config CCK RX antenna.
1159                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1160                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1161
1162                         // Config OFDM RX antenna.
1163                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1164                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1165                 }
1166                 else // main Antenna
1167                 {
1168                         // Mac register, main antenna
1169                         write_nic_byte(dev, ANTSEL, 0x03);
1170
1171                         // Config CCK RX antenna.
1172                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1173                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1174
1175                         // Config OFDM RX antenna.
1176                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1177                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1178                 }
1179         }
1180         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1181         return  bAntennaSwitched;
1182 }
1183 //by amy 080312
1184 /*---------------------------------------------------------------
1185   * Hardware Initialization.
1186   * the code is ported from Windows source code
1187   ----------------------------------------------------------------*/
1188
1189 void
1190 ZEBRA_Config_85BASIC_HardCode(
1191         struct net_device *dev
1192         )
1193 {
1194
1195         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1196         u32                     i;
1197         u32     addr,data;
1198         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1199        u8                       u1b24E;
1200
1201
1202         //=============================================================================
1203         // 87S_PCIE :: RADIOCFG.TXT
1204         //=============================================================================
1205
1206
1207         // Page1 : reg16-reg30
1208         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1209         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1210         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1211
1212         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1213                 priv->card_8185 = VERSION_8187S_D;
1214
1215         // Page0 : reg0-reg15
1216
1217 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1218         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1219
1220         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1221
1222 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1223         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1224
1225 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1226         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1227
1228         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1229         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1230         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1231         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1232         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1233         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1234         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1235         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1236         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1237         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1238         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1239         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1240
1241
1242         // Page1 : reg16-reg30
1243         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1244
1245         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1246
1247         if(priv->card_8185 < VERSION_8187S_C)
1248         {
1249                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1250                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1251                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1252         }
1253         else
1254         {
1255                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1256                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1257                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1258         }
1259
1260
1261         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1262 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1263 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1264 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1265         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1266         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1267
1268         if(priv->card_8185 == VERSION_8187S_D)
1269         {
1270                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1271                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1272                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1273         }
1274         else
1275         {
1276                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1277                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1278                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1279         }
1280
1281         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1282
1283 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1284         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1285
1286         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1287         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1288         for(i=0;i<=36;i++)
1289         {
1290                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1291                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1292                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1293         }
1294
1295         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1296         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1297         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1298
1299         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1300         mdelay(10);     // Deay 10 ms. //0xfd
1301
1302 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1303         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1304         //mdelay(10);   // Deay 10 ms. //0xfd
1305
1306         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1307         mdelay(10);     // Deay 10 ms. //0xfd
1308
1309         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1310         mdelay(10);     // Deay 10 ms. //0xfd
1311
1312         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1313         mdelay(10);     // Deay 10 ms. //0xfd
1314
1315         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1316         mdelay(10);     // Deay 10 ms. //0xfd
1317
1318         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1319         mdelay(200);    // Deay 200 ms. //0xfd
1320         mdelay(10);     // Deay 10 ms. //0xfd
1321         mdelay(10);     // Deay 10 ms. //0xfd
1322
1323         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1324         mdelay(10);     // Deay 10 ms. //0xfd
1325
1326         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1327         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1328         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1329         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1330
1331         // DAC calibration off 20070702
1332         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1333         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1334 //{by amy 080312
1335         // For crystal calibration, added by Roger, 2007.12.11.
1336         if( priv->bXtalCalibration ) // reg 30.
1337         { // enable crystal calibration.
1338                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1339                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1340                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1341                 // So we should minus 4 BITs offset.
1342                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1343                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1344                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1345         }
1346         else
1347         { // using default value. Xin=6, Xout=6.
1348                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1349         }
1350 //by amy 080312
1351 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1352
1353         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1354 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1355         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1356         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1357         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1358         mdelay(10);     // Deay 10 ms. //0xfe
1359         mdelay(10);     // Deay 10 ms. //0xfe
1360         mdelay(10);     // Deay 10 ms. //0xfe
1361         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1362         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1363         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1364
1365 #if 0//-edward
1366         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1);
1367         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1368         RF_WriteReg(dev, 0x00, 0x009F);                 mdelay(1);
1369 #endif
1370         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1371         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1372         //power save parameters.
1373         u1b24E = read_nic_byte(dev, 0x24E);
1374         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1375
1376         //=============================================================================
1377
1378         //=============================================================================
1379         // CCKCONF.TXT
1380         //=============================================================================
1381
1382         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1383                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1384                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1385                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1386                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1387                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1388         */
1389 #if 0
1390         write_nic_dword(dev, PHY_ADR, 0x0100c880);
1391         write_nic_dword(dev, PHY_ADR, 0x01001c86);
1392         write_nic_dword(dev, PHY_ADR, 0x01007890);
1393         write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1394         write_nic_dword(dev, PHY_ADR, 0x010006af);
1395         write_nic_dword(dev, PHY_ADR, 0x01004681);
1396 #endif
1397         write_phy_cck(dev,0x00,0xc8);
1398         write_phy_cck(dev,0x06,0x1c);
1399         write_phy_cck(dev,0x10,0x78);
1400         write_phy_cck(dev,0x2e,0xd0);
1401         write_phy_cck(dev,0x2f,0x06);
1402         write_phy_cck(dev,0x01,0x46);
1403
1404         // power control
1405         write_nic_byte(dev, CCK_TXAGC, 0x10);
1406         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1407         write_nic_byte(dev, ANTSEL, 0x03);
1408
1409
1410
1411         //=============================================================================
1412         // AGC.txt
1413         //=============================================================================
1414
1415 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1416         write_phy_ofdm(dev, 0x00, 0x12);
1417         //WriteBBPortUchar(dev, 0x00001280);
1418
1419         for (i=0; i<128; i++)
1420         {
1421                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1422
1423                 data = ZEBRA_AGC[i+1];
1424                 data = data << 8;
1425                 data = data | 0x0000008F;
1426
1427                 addr = i + 0x80; //enable writing AGC table
1428                 addr = addr << 8;
1429                 addr = addr | 0x0000008E;
1430
1431                 WriteBBPortUchar(dev, data);
1432                 WriteBBPortUchar(dev, addr);
1433                 WriteBBPortUchar(dev, 0x0000008E);
1434         }
1435
1436         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1437         //WriteBBPortUchar(dev, 0x00001080);
1438
1439         //=============================================================================
1440
1441         //=============================================================================
1442         // OFDMCONF.TXT
1443         //=============================================================================
1444
1445         for(i=0; i<60; i++)
1446         {
1447                 u4bRegOffset=i;
1448                 u4bRegValue=OFDM_CONFIG[i];
1449
1450                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1451
1452                 WriteBBPortUchar(dev,
1453                                                 (0x00000080 |
1454                                                 (u4bRegOffset & 0x7f) |
1455                                                 ((u4bRegValue & 0xff) << 8)));
1456         }
1457
1458         //=============================================================================
1459 //by amy for antenna
1460         //=============================================================================
1461 //{by amy 080312
1462         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1463         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1464 //by amy 080312}
1465 #if 0
1466         // Config Sw/Hw  Antenna Diversity
1467         if( priv->bSwAntennaDiverity )  //  Use SW+Hw Antenna Diversity
1468         {
1469                 if( priv->bDefaultAntenna1 == true )  // aux antenna
1470                 {
1471                         // Mac register, aux antenna
1472                         write_nic_byte(dev, ANTSEL, 0x00);
1473                         // Config CCK RX antenna.
1474                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1475                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1476                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1477                         // Config OFDM RX antenna.
1478                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1479                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1480                 }
1481                 else //  main antenna
1482                 {
1483                         // Mac register, main antenna
1484                         write_nic_byte(dev, ANTSEL, 0x03);
1485                         //base band
1486                         // Config CCK RX antenna.
1487                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1488                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1489                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1490                         // Config OFDM RX antenna.
1491                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1492                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1493                 }
1494         }
1495         else   // Disable Antenna Diversity
1496         {
1497                 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1498                 {
1499                         // Mac register, aux antenna
1500                         write_nic_byte(dev, ANTSEL, 0x00);
1501                         // Config CCK RX antenna.
1502                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1503                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1504                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1505                         // Config OFDM RX antenna.
1506                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1507                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1508                 }
1509                 else // main Antenna
1510                 {
1511                         // Mac register, main antenna
1512                         write_nic_byte(dev, ANTSEL, 0x03);
1513                         // Config CCK RX antenna.
1514                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1515                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1516                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1517                         // Config OFDM RX antenna.
1518                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1519                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1520                 }
1521         }
1522 #endif
1523 //by amy for antenna
1524 }
1525
1526
1527 void
1528 UpdateInitialGain(
1529         struct net_device *dev
1530         )
1531 {
1532         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1533         //unsigned char* IGTable;
1534         //u8                    DIG_CurrentInitialGain = 4;
1535         //unsigned char u1Tmp;
1536
1537         //lzm add 080826
1538         if(priv->eRFPowerState != eRfOn)
1539         {
1540                 //Don't access BB/RF under disable PLL situation.
1541                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1542                 // Back to the original state
1543                 priv->InitialGain= priv->InitialGainBackUp;
1544                 return;
1545         }
1546
1547         switch(priv->rf_chip)
1548         {
1549 #if 0
1550         case RF_ZEBRA2:
1551                 // Dynamic set initial gain, by shien chang, 2006.07.14
1552                 switch(priv->InitialGain)
1553                 {
1554                         case 1: //m861dBm
1555                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1556                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1557                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1558                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1559                                 break;
1560
1561                         case 2: //m862dBm
1562                                 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1563                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1564                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1565                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1566                                 break;
1567
1568                         case 3: //m863dBm
1569                                 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1570                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1571                                 write_nic_dword(dev, PhyAddr, 0x96a4);  mdelay(1);
1572                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1573                                 break;
1574
1575                         case 4: //m864dBm
1576                                 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1577                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1578                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1579                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1580                                 break;
1581
1582                         case 5: //m82dBm
1583                                 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1584                                 write_nic_dword(dev, PhyAddr, 0x3697);  mdelay(1);
1585                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1586                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1587                                 break;
1588
1589                         case 6: //m78dBm
1590                                 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1591                                 write_nic_dword(dev, PhyAddr, 0x4697);  mdelay(1);
1592                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1593                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1594                                 break;
1595
1596                         case 7: //m74dBm
1597                                 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1598                                 write_nic_dword(dev, PhyAddr, 0x5697);  mdelay(1);
1599                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1600                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1601                                 break;
1602
1603                         default:        //MP
1604                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1605                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1606                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1607                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1608                                 break;
1609                 }
1610                 break;
1611 #endif
1612         case RF_ZEBRA4:
1613                 // Dynamic set initial gain, follow 87B
1614                 switch(priv->InitialGain)
1615                 {
1616                         case 1: //m861dBm
1617                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1618                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1619                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1620                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1621                                 break;
1622
1623                         case 2: //m862dBm
1624                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1625                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1626                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1627                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1628                                 break;
1629
1630                         case 3: //m863dBm
1631                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1632                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1633                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1634                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1635                                 break;
1636
1637                         case 4: //m864dBm
1638                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1639                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1640                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1641                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1642                                 break;
1643
1644                         case 5: //m82dBm
1645                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1646                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1647                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1648                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1649                                 break;
1650
1651                         case 6: //m78dBm
1652                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1653                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1654                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1655                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1656                                 break;
1657
1658                         case 7: //m74dBm
1659                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1660                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1661                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1662                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1663                                 break;
1664
1665                         case 8:
1666                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1667                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1668                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1669                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1670                                 break;
1671
1672
1673                         default:        //MP
1674                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1675                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1676                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1677                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1678                                 break;
1679                 }
1680                 break;
1681
1682
1683         default:
1684                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1685                 break;
1686         }
1687 }
1688 //
1689 //      Description:
1690 //              Tx Power tracking mechanism routine on 87SE.
1691 //      Created by Roger, 2007.12.11.
1692 //
1693 void
1694 InitTxPwrTracking87SE(
1695         struct net_device *dev
1696 )
1697 {
1698         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1699         u32     u4bRfReg;
1700
1701         u4bRfReg = RF_ReadReg(dev, 0x02);
1702
1703         // Enable Thermal meter indication.
1704         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1705         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1706 }
1707
1708 void
1709 PhyConfig8185(
1710         struct net_device *dev
1711         )
1712 {
1713         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1714        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1715            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1716         // RF config
1717         switch(priv->rf_chip)
1718         {
1719         case RF_ZEBRA2:
1720         case RF_ZEBRA4:
1721                 ZEBRA_Config_85BASIC_HardCode( dev);
1722                 break;
1723         }
1724 //{by amy 080312
1725         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1726         if(priv->bDigMechanism)
1727         {
1728                 if(priv->InitialGain == 0)
1729                         priv->InitialGain = 4;
1730                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1731         }
1732
1733         //
1734         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1735         // We initialize thermal meter here to avoid unsuccessful configuration.
1736         // Added by Roger, 2007.12.11.
1737         //
1738         if(priv->bTxPowerTrack)
1739                 InitTxPwrTracking87SE(dev);
1740
1741 //by amy 080312}
1742         priv->InitialGainBackUp= priv->InitialGain;
1743         UpdateInitialGain(dev);
1744
1745         return;
1746 }
1747
1748
1749
1750
1751 void
1752 HwConfigureRTL8185(
1753                 struct net_device *dev
1754                 )
1755 {
1756         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1757 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1758         u8              bUNIVERSAL_CONTROL_RL = 0;
1759
1760         u8              bUNIVERSAL_CONTROL_AGC = 1;
1761         u8              bUNIVERSAL_CONTROL_ANT = 1;
1762         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1763         u8              val8;
1764         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1765         //struct ieee80211_device *ieee = priv->ieee80211;
1766         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1767 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1768 //      {
1769 //              write_nic_word(dev, BRSR, 0xffff);
1770 //      }
1771 //      else
1772 //      {
1773 //              write_nic_word(dev, BRSR, 0x000f);
1774 //      }
1775 //by amy 080312}
1776         write_nic_word(dev, BRSR, 0x0fff);
1777         // Retry limit
1778         val8 = read_nic_byte(dev, CW_CONF);
1779
1780         if(bUNIVERSAL_CONTROL_RL)
1781                 val8 = val8 & 0xfd;
1782         else
1783                 val8 = val8 | 0x02;
1784
1785         write_nic_byte(dev, CW_CONF, val8);
1786
1787         // Tx AGC
1788         val8 = read_nic_byte(dev, TXAGC_CTL);
1789         if(bUNIVERSAL_CONTROL_AGC)
1790         {
1791                 write_nic_byte(dev, CCK_TXAGC, 128);
1792                 write_nic_byte(dev, OFDM_TXAGC, 128);
1793                 val8 = val8 & 0xfe;
1794         }
1795         else
1796         {
1797                 val8 = val8 | 0x01 ;
1798         }
1799
1800
1801         write_nic_byte(dev, TXAGC_CTL, val8);
1802
1803         // Tx Antenna including Feedback control
1804         val8 = read_nic_byte(dev, TXAGC_CTL );
1805
1806         if(bUNIVERSAL_CONTROL_ANT)
1807         {
1808                 write_nic_byte(dev, ANTSEL, 0x00);
1809                 val8 = val8 & 0xfd;
1810         }
1811         else
1812         {
1813                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1814         }
1815
1816         write_nic_byte(dev, TXAGC_CTL, val8);
1817
1818         // Auto Rate fallback control
1819         val8 = read_nic_byte(dev, RATE_FALLBACK);
1820         val8 &= 0x7c;
1821         if( bAUTO_RATE_FALLBACK_CTL )
1822         {
1823                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1824
1825                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1826                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1827 //by amy
1828 #if 0
1829                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff);        // set 1M ~ 54M
1830 #endif
1831                 // Aadded by Roger, 2007.11.15.
1832                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1833 //by amy
1834         }
1835         else
1836         {
1837         }
1838         write_nic_byte(dev, RATE_FALLBACK, val8);
1839 }
1840
1841
1842
1843 static void
1844 MacConfig_85BASIC_HardCode(
1845         struct net_device *dev)
1846 {
1847         //============================================================================
1848         // MACREG.TXT
1849         //============================================================================
1850         int                     nLinesRead = 0;
1851
1852         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1853         int     i;
1854
1855         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1856
1857         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1858         {
1859                 u4bRegOffset=MAC_REG_TABLE[i][0];
1860                 u4bRegValue=MAC_REG_TABLE[i][1];
1861
1862                 if(u4bRegOffset == 0x5e)
1863                 {
1864                     u4bPageIndex = u4bRegValue;
1865                 }
1866                 else
1867                 {
1868                     u4bRegOffset |= (u4bPageIndex << 8);
1869                 }
1870                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1871                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1872         }
1873         //============================================================================
1874 }
1875
1876
1877
1878 static void
1879 MacConfig_85BASIC(
1880         struct net_device *dev)
1881 {
1882
1883        u8                       u1DA;
1884         MacConfig_85BASIC_HardCode(dev);
1885
1886         //============================================================================
1887
1888         // Follow TID_AC_MAP of WMac.
1889         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1890
1891         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1892         write_nic_word(dev, IntMig, 0x0000);
1893
1894         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1895         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1896         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1897         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1898
1899         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1900         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1901 //by amy
1902 #if 0
1903         write_nic_dword(dev, RFTiming, 0x00004001);
1904 #endif
1905         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1906
1907         //Enable DA10 TX power saving
1908         u1DA = read_nic_byte(dev, PHYPR);
1909         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1910
1911         //POWER:
1912         write_nic_word(dev, 0x360, 0x1000);
1913         write_nic_word(dev, 0x362, 0x1000);
1914
1915         // AFE.
1916         write_nic_word(dev, 0x370, 0x0560);
1917         write_nic_word(dev, 0x372, 0x0560);
1918         write_nic_word(dev, 0x374, 0x0DA4);
1919         write_nic_word(dev, 0x376, 0x0DA4);
1920         write_nic_word(dev, 0x378, 0x0560);
1921         write_nic_word(dev, 0x37A, 0x0560);
1922         write_nic_word(dev, 0x37C, 0x00EC);
1923 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1924         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1925        write_nic_byte(dev, 0x24E,0x01);
1926 //by amy
1927
1928 }
1929
1930
1931
1932
1933 u8
1934 GetSupportedWirelessMode8185(
1935         struct net_device *dev
1936 )
1937 {
1938         u8                      btSupportedWirelessMode = 0;
1939         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1940
1941         switch(priv->rf_chip)
1942         {
1943         case RF_ZEBRA2:
1944         case RF_ZEBRA4:
1945                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1946                 break;
1947         default:
1948                 btSupportedWirelessMode = WIRELESS_MODE_B;
1949                 break;
1950         }
1951
1952         return btSupportedWirelessMode;
1953 }
1954
1955 void
1956 ActUpdateChannelAccessSetting(
1957         struct net_device *dev,
1958         WIRELESS_MODE                   WirelessMode,
1959         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1960         )
1961 {
1962         struct r8180_priv *priv = ieee80211_priv(dev);
1963         struct ieee80211_device *ieee = priv->ieee80211;
1964         AC_CODING       eACI;
1965         AC_PARAM        AcParam;
1966         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1967         u8      bFollowLegacySetting = 0;
1968         u8   u1bAIFS;
1969
1970         //
1971         // <RJ_TODO_8185B>
1972         // TODO: We still don't know how to set up these registers, just follow WMAC to
1973         // verify 8185B FPAG.
1974         //
1975         // <RJ_TODO_8185B>
1976         // Jong said CWmin/CWmax register are not functional in 8185B,
1977         // so we shall fill channel access realted register into AC parameter registers,
1978         // even in nQBss.
1979         //
1980         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1981         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1982         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1983         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1984         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1985         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1986
1987         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1988         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1989         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1990
1991         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1992
1993         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1994         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1995         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1996         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1997
1998         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1999
2000         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2001
2002 #ifdef TODO
2003         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2004         if( pStaQos->CurrentQosMode > QOS_DISABLE )
2005         { // QoS mode.
2006                 if(pStaQos->QBssWirelessMode == WirelessMode)
2007                 {
2008                         // Follow AC Parameters of the QBSS.
2009                         for(eACI = 0; eACI < AC_MAX; eACI++)
2010                         {
2011                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2012                         }
2013                 }
2014                 else
2015                 {
2016                         // Follow Default WMM AC Parameters.
2017                         bFollowLegacySetting = 1;
2018                 }
2019         }
2020         else
2021 #endif
2022         { // Legacy 802.11.
2023                 bFollowLegacySetting = 1;
2024
2025         }
2026
2027         // this setting is copied from rtl8187B.  xiong-2006-11-13
2028         if(bFollowLegacySetting)
2029         {
2030
2031
2032                 //
2033                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2034                 // 2005.12.01, by rcnjko.
2035                 //
2036                 AcParam.longData = 0;
2037                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2038                 AcParam.f.AciAifsn.f.ACM = 0;
2039                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2040                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2041                 AcParam.f.TXOPLimit = 0;
2042
2043                 //lzm reserved 080826
2044 #if 1
2045                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2046                 if( ieee->current_network.Turbo_Enable == 1 )
2047                         AcParam.f.TXOPLimit = 0x01FF;
2048                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
2049                 if (ieee->iw_mode == IW_MODE_ADHOC)
2050                         AcParam.f.TXOPLimit = 0x0020;
2051 #endif
2052
2053                 for(eACI = 0; eACI < AC_MAX; eACI++)
2054                 {
2055                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2056                         {
2057                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
2058                                 AC_CODING       eACI;
2059                                 u8              u1bAIFS;
2060                                 u32             u4bAcParam;
2061
2062                                 // Retrive paramters to udpate.
2063                                 eACI = pAcParam->f.AciAifsn.f.ACI;
2064                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2065                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
2066                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
2067                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
2068                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2069
2070                                 switch(eACI)
2071                                 {
2072                                         case AC1_BK:
2073                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2074                                                 break;
2075
2076                                         case AC0_BE:
2077                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2078                                                 break;
2079
2080                                         case AC2_VI:
2081                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2082                                                 break;
2083
2084                                         case AC3_VO:
2085                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2086                                                 break;
2087
2088                                         default:
2089                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2090                                                 break;
2091                                 }
2092
2093                                 // Cehck ACM bit.
2094                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2095                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2096                                 {
2097                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2098                                         AC_CODING       eACI = pAciAifsn->f.ACI;
2099
2100                                         //modified Joseph
2101                                         //for 8187B AsynIORead issue
2102 #ifdef TODO
2103                                         u8      AcmCtrl = pHalData->AcmControl;
2104 #else
2105                                         u8      AcmCtrl = 0;
2106 #endif
2107                                         if( pAciAifsn->f.ACM )
2108                                         { // ACM bit is 1.
2109                                                 switch(eACI)
2110                                                 {
2111                                                         case AC0_BE:
2112                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
2113                                                                 break;
2114
2115                                                         case AC2_VI:
2116                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
2117                                                                 break;
2118
2119                                                         case AC3_VO:
2120                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
2121                                                                 break;
2122
2123                                                         default:
2124                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2125                                                                 break;
2126                                                 }
2127                                         }
2128                                         else
2129                                         { // ACM bit is 0.
2130                                                 switch(eACI)
2131                                                 {
2132                                                         case AC0_BE:
2133                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
2134                                                                 break;
2135
2136                                                         case AC2_VI:
2137                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
2138                                                                 break;
2139
2140                                                         case AC3_VO:
2141                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
2142                                                                 break;
2143
2144                                                         default:
2145                                                                 break;
2146                                                 }
2147                                         }
2148
2149                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2150
2151 #ifdef TO_DO
2152                                         pHalData->AcmControl = AcmCtrl;
2153 #endif
2154                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2155                                         write_nic_byte(dev, ACM_CONTROL, 0);
2156                                 }
2157                         }
2158                 }
2159
2160
2161         }
2162 }
2163
2164 void
2165 ActSetWirelessMode8185(
2166         struct net_device *dev,
2167         u8                              btWirelessMode
2168         )
2169 {
2170         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2171         struct ieee80211_device *ieee = priv->ieee80211;
2172         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
2173         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2174
2175         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2176         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2177                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2178                         btWirelessMode, btSupportedWirelessMode);
2179                 return;
2180         }
2181
2182         // 1. Assign wireless mode to swtich if necessary.
2183         if (btWirelessMode == WIRELESS_MODE_AUTO)
2184         {
2185                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2186                 {
2187                         btWirelessMode = WIRELESS_MODE_A;
2188                 }
2189                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2190                 {
2191                         btWirelessMode = WIRELESS_MODE_G;
2192                 }
2193                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2194                 {
2195                         btWirelessMode = WIRELESS_MODE_B;
2196                 }
2197                 else
2198                 {
2199                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2200                                          btSupportedWirelessMode);
2201                         btWirelessMode = WIRELESS_MODE_B;
2202                 }
2203         }
2204
2205
2206         // 2. Swtich band: RF or BB specific actions,
2207         // for example, refresh tables in omc8255, or change initial gain if necessary.
2208         switch(priv->rf_chip)
2209         {
2210         case RF_ZEBRA2:
2211         case RF_ZEBRA4:
2212                 {
2213                         // Nothing to do for Zebra to switch band.
2214                         // Update current wireless mode if we swtich to specified band successfully.
2215                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
2216                 }
2217                 break;
2218
2219         default:
2220                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2221                 break;
2222         }
2223
2224         // 3. Change related setting.
2225         if( ieee->mode == WIRELESS_MODE_A ){
2226                 DMESG("WIRELESS_MODE_A\n");
2227         }
2228         else if( ieee->mode == WIRELESS_MODE_B ){
2229                 DMESG("WIRELESS_MODE_B\n");
2230         }
2231         else if( ieee->mode == WIRELESS_MODE_G ){
2232                 DMESG("WIRELESS_MODE_G\n");
2233         }
2234
2235         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2236 }
2237
2238 void rtl8185b_irq_enable(struct net_device *dev)
2239 {
2240         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2241
2242         priv->irq_enabled = 1;
2243         write_nic_dword(dev, IMR, priv->IntrMask);
2244 }
2245 //by amy for power save
2246 void
2247 DrvIFIndicateDisassociation(
2248         struct net_device *dev,
2249         u16                     reason
2250         )
2251 {
2252         //printk("==> DrvIFIndicateDisassociation()\n");
2253
2254         // nothing is needed after disassociation request.
2255
2256         //printk("<== DrvIFIndicateDisassociation()\n");
2257 }
2258 void
2259 MgntDisconnectIBSS(
2260         struct net_device *dev
2261 )
2262 {
2263         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2264         u8                      i;
2265
2266         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2267
2268         DrvIFIndicateDisassociation(dev, unspec_reason);
2269
2270 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2271         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
2272
2273         priv->ieee80211->state = IEEE80211_NOLINK;
2274
2275         //Stop Beacon.
2276
2277         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2278         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2279         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2280
2281         // Disable Beacon Queue Own bit, suggested by jong
2282 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2283         ieee80211_stop_send_beacons(priv->ieee80211);
2284
2285         priv->ieee80211->link_change(dev);
2286         notify_wx_assoc_event(priv->ieee80211);
2287
2288         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2289 #if 0
2290         if(pMgntInfo->bEnableSwBeaconTimer)
2291         {
2292                 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2293 // comment out by haich, 2007.10.01
2294 //#if DEV_BUS_TYPE==USB_INTERFACE
2295                 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2296 //#endif
2297         }
2298 #endif
2299
2300 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2301
2302 }
2303 void
2304 MlmeDisassociateRequest(
2305         struct net_device *dev,
2306         u8*                     asSta,
2307         u8                      asRsn
2308         )
2309 {
2310         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2311         u8 i;
2312
2313         SendDisassociation(priv->ieee80211, asSta, asRsn );
2314
2315         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2316                 //ShuChen TODO: change media status.
2317                 //ShuChen TODO: What to do when disassociate.
2318                 DrvIFIndicateDisassociation(dev, unspec_reason);
2319
2320
2321         //      pMgntInfo->AsocTimestamp = 0;
2322                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2323 //              pMgntInfo->mBrates.Length = 0;
2324 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2325
2326                 ieee80211_disassociate(priv->ieee80211);
2327
2328
2329         }
2330
2331 }
2332
2333 void
2334 MgntDisconnectAP(
2335         struct net_device *dev,
2336         u8                      asRsn
2337 )
2338 {
2339         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2340
2341 //
2342 // Commented out by rcnjko, 2005.01.27:
2343 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2344 //
2345 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2346 //      SecClearAllKeys(Adapter);
2347
2348         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2349 #ifdef TODO
2350         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2351                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2352         {
2353                 SecClearAllKeys(Adapter);
2354                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2355         }
2356 #endif
2357         // 2004.10.11, by rcnjko.
2358         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2359         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2360
2361         priv->ieee80211->state = IEEE80211_NOLINK;
2362 //      pMgntInfo->AsocTimestamp = 0;
2363 }
2364 bool
2365 MgntDisconnect(
2366         struct net_device *dev,
2367         u8                      asRsn
2368 )
2369 {
2370         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2371         //
2372         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2373         //
2374 #ifdef TODO
2375         if(pMgntInfo->mPss != eAwake)
2376         {
2377                 //
2378                 // Using AwkaeTimer to prevent mismatch ps state.
2379                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2380                 //
2381                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2382                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2383         }
2384 #endif
2385
2386         // Indication of disassociation event.
2387         //DrvIFIndicateDisassociation(Adapter, asRsn);
2388         if(IS_DOT11D_ENABLE(priv->ieee80211))
2389                 Dot11d_Reset(priv->ieee80211);
2390         // In adhoc mode, update beacon frame.
2391         if( priv->ieee80211->state == IEEE80211_LINKED )
2392         {
2393                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2394                 {
2395 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2396                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2397                         MgntDisconnectIBSS(dev);
2398                 }
2399                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2400                 {
2401                         // We clear key here instead of MgntDisconnectAP() because that
2402                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2403                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2404                         // used to handle disassociation related things to AP, e.g. send Disassoc
2405                         // frame to AP.  2005.01.27, by rcnjko.
2406 //                      SecClearAllKeys(Adapter);
2407
2408 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2409                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2410                         MgntDisconnectAP(dev, asRsn);
2411                 }
2412
2413                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2414 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2415         }
2416
2417         return true;
2418 }
2419 //
2420 //      Description:
2421 //              Chang RF Power State.
2422 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2423 //
2424 //      Assumption:
2425 //              PASSIVE LEVEL.
2426 //
2427 bool
2428 SetRFPowerState(
2429         struct net_device *dev,
2430         RT_RF_POWER_STATE       eRFPowerState
2431         )
2432 {
2433         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2434         bool                    bResult = false;
2435
2436 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2437         if(eRFPowerState == priv->eRFPowerState)
2438         {
2439 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2440                 return bResult;
2441         }
2442
2443         switch(priv->rf_chip)
2444         {
2445                 case RF_ZEBRA2:
2446                 case RF_ZEBRA4:
2447                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2448                         break;
2449
2450                 default:
2451                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2452                         break;;
2453 }
2454 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2455
2456         return bResult;
2457 }
2458 void
2459 HalEnableRx8185Dummy(
2460         struct net_device *dev
2461         )
2462 {
2463 }
2464 void
2465 HalDisableRx8185Dummy(
2466         struct net_device *dev
2467         )
2468 {
2469 }
2470
2471 bool
2472 MgntActSet_RF_State(
2473         struct net_device *dev,
2474         RT_RF_POWER_STATE       StateToSet,
2475         u32     ChangeSource
2476         )
2477 {
2478         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2479         bool                            bActionAllowed = false;
2480         bool                            bConnectBySSID = false;
2481         RT_RF_POWER_STATE       rtState;
2482         u16                             RFWaitCounter = 0;
2483         unsigned long flag;
2484 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2485         //
2486         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2487         // Only one thread can change the RF state at one time, and others should wait to be executed.
2488         //
2489 #if 1
2490         while(true)
2491         {
2492 //              down(&priv->rf_state);
2493                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2494                 if(priv->RFChangeInProgress)
2495                 {
2496 //                      printk("====================>haha111111111\n");
2497 //                      up(&priv->rf_state);
2498 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2499                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2500                         // Set RF after the previous action is done.
2501                         while(priv->RFChangeInProgress)
2502                         {
2503                                 RFWaitCounter ++;
2504 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2505                                 udelay(1000); // 1 ms
2506
2507                                 // Wait too long, return FALSE to avoid to be stuck here.
2508                                 if(RFWaitCounter > 1000) // 1sec
2509                                 {
2510 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2511                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2512                                         // TODO: Reset RF state?
2513                                         return false;
2514                                 }
2515                         }
2516                 }
2517                 else
2518                 {
2519 //                      printk("========================>haha2\n");
2520                         priv->RFChangeInProgress = true;
2521 //                      up(&priv->rf_state);
2522                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2523                         break;
2524                 }
2525         }
2526 #endif
2527         rtState = priv->eRFPowerState;
2528
2529
2530         switch(StateToSet)
2531         {
2532         case eRfOn:
2533                 //
2534                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2535                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2536                 //
2537                 priv->RfOffReason &= (~ChangeSource);
2538
2539                 if(! priv->RfOffReason)
2540                 {
2541                         priv->RfOffReason = 0;
2542                         bActionAllowed = true;
2543
2544                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2545                         {
2546                                 bConnectBySSID = true;
2547                         }
2548                 }
2549                 else
2550 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2551                         ;
2552                 break;
2553
2554         case eRfOff:
2555                  // 070125, rcnjko: we always keep connected in AP mode.
2556
2557                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2558                         {
2559                                 //
2560                                 // 060808, Annie:
2561                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2562                                 //
2563
2564                                 //
2565                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2566                                 // because we do NOT need to set ssid to dummy ones.
2567                                 // Revised by Roger, 2007.12.04.
2568                                 //
2569                                 MgntDisconnect( dev, disas_lv_ss );
2570
2571                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2572                                 // 2007.05.28, by shien chang.
2573 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2574 //                              pMgntInfo->NumBssDesc = 0;
2575 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2576 //                              pMgntInfo->NumBssDesc4Query = 0;
2577                         }
2578
2579
2580
2581                 priv->RfOffReason |= ChangeSource;
2582                 bActionAllowed = true;
2583                 break;
2584
2585         case eRfSleep:
2586                 priv->RfOffReason |= ChangeSource;
2587                 bActionAllowed = true;
2588                 break;
2589
2590         default:
2591                 break;
2592         }
2593
2594         if(bActionAllowed)
2595         {
2596 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2597                 // Config HW to the specified mode.
2598 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2599                 SetRFPowerState(dev, StateToSet);
2600
2601                 // Turn on RF.
2602                 if(StateToSet == eRfOn)
2603                 {
2604                         HalEnableRx8185Dummy(dev);
2605                         if(bConnectBySSID)
2606                         {
2607                         // by amy not supported
2608 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2609                         }
2610                 }
2611                 // Turn off RF.
2612                 else if(StateToSet == eRfOff)
2613                 {
2614                         HalDisableRx8185Dummy(dev);
2615                 }
2616         }
2617         else
2618         {
2619         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2620         }
2621
2622         // Release RF spinlock
2623 //      down(&priv->rf_state);
2624         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2625         priv->RFChangeInProgress = false;
2626 //      up(&priv->rf_state);
2627         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2628 //      printk("<===MgntActSet_RF_State()\n");
2629         return bActionAllowed;
2630 }
2631 void
2632 InactivePowerSave(
2633         struct net_device *dev
2634         )
2635 {
2636         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2637         //u8 index = 0;
2638
2639         //
2640         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2641         // is really scheduled.
2642         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2643         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2644         // blocks the IPS procedure of switching RF.
2645         // By Bruce, 2007-12-25.
2646         //
2647         priv->bSwRfProcessing = true;
2648
2649         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2650
2651         //
2652         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2653         //
2654 #if 0
2655         while( index < 4 )
2656         {
2657                 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2658                         (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2659                 {
2660                         if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2661                         pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2662
2663                 }
2664                 index++;
2665         }
2666 #endif
2667         priv->bSwRfProcessing = false;
2668 }
2669
2670 //
2671 //      Description:
2672 //              Enter the inactive power save mode. RF will be off
2673 //      2007.08.17, by shien chang.
2674 //
2675 void
2676 IPSEnter(
2677         struct net_device *dev
2678         )
2679 {
2680         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2681         RT_RF_POWER_STATE rtState;
2682         //printk("==============================>enter IPS\n");
2683         if (priv->bInactivePs)
2684         {
2685                 rtState = priv->eRFPowerState;
2686
2687                 //
2688                 // Added by Bruce, 2007-12-25.
2689                 // Do not enter IPS in the following conditions:
2690                 // (1) RF is already OFF or Sleep
2691                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2692                 // (3) Connectted (only disconnected can trigger IPS)
2693                 // (4) IBSS (send Beacon)
2694                 // (5) AP mode (send Beacon)
2695                 //
2696                 if (rtState == eRfOn && !priv->bSwRfProcessing
2697                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2698                 {
2699         //              printk("IPSEnter(): Turn off RF.\n");
2700                         priv->eInactivePowerState = eRfOff;
2701                         InactivePowerSave(dev);
2702                 }
2703         }
2704 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2705 }
2706 void
2707 IPSLeave(
2708         struct net_device *dev
2709         )
2710 {
2711         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2712         RT_RF_POWER_STATE rtState;
2713         //printk("===================================>leave IPS\n");
2714         if (priv->bInactivePs)
2715         {
2716                 rtState = priv->eRFPowerState;
2717                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2718                 {
2719 //                      printk("IPSLeave(): Turn on RF.\n");
2720                         priv->eInactivePowerState = eRfOn;
2721                         InactivePowerSave(dev);
2722                 }
2723         }
2724 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2725 }
2726 //by amy for power save
2727 void rtl8185b_adapter_start(struct net_device *dev)
2728 {
2729       struct r8180_priv *priv = ieee80211_priv(dev);
2730         struct ieee80211_device *ieee = priv->ieee80211;
2731
2732         u8 SupportedWirelessMode;
2733         u8                      InitWirelessMode;
2734         u8                      bInvalidWirelessMode = 0;
2735         //int i;
2736         u8 tmpu8;
2737         //u8 u1tmp,u2tmp;
2738         u8 btCR9346;
2739         u8 TmpU1b;
2740         u8 btPSR;
2741
2742         //rtl8180_rtx_disable(dev);
2743 //{by amy 080312
2744         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2745 //by amy 080312}
2746         rtl8180_reset(dev);
2747
2748         priv->dma_poll_mask = 0;
2749         priv->dma_poll_stop_mask = 0;
2750
2751         //rtl8180_beacon_tx_disable(dev);
2752
2753         HwConfigureRTL8185(dev);
2754
2755         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2756         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2757
2758         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2759
2760         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2761
2762         write_nic_word(dev, BcnItv, 100);
2763         write_nic_word(dev, AtimWnd, 2);
2764
2765         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2766         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2767
2768         write_nic_byte(dev, WPA_CONFIG, 0);
2769
2770         MacConfig_85BASIC(dev);
2771
2772         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2773         // BT_DEMO_BOARD type
2774         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2775 //by amy
2776 //#ifdef CONFIG_RTL818X_S
2777                 // for jong required
2778 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2779 //#endif
2780 //by amy
2781         //BT_QA_BOARD
2782         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2783
2784         //-----------------------------------------------------------------------------
2785         // Set up PHY related.
2786         //-----------------------------------------------------------------------------
2787         // Enable Config3.PARAM_En to revise AnaaParm.
2788         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2789 //by amy
2790         tmpu8 = read_nic_byte(dev, CONFIG3);
2791         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2792 //by amy
2793         // Turn on Analog power.
2794         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2795         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2796         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2797 //by amy
2798         write_nic_word(dev, ANAPARAM3, 0x0010);
2799 //by amy
2800
2801         write_nic_byte(dev, CONFIG3, tmpu8);
2802         write_nic_byte(dev, CR9346, 0x00);
2803 //{by amy 080312 for led
2804         // enable EEM0 and EEM1 in 9346CR
2805         btCR9346 = read_nic_byte(dev, CR9346);
2806         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2807
2808         // B cut use LED1 to control HW RF on/off
2809         TmpU1b = read_nic_byte(dev, CONFIG5);
2810         TmpU1b = TmpU1b & ~BIT3;
2811         write_nic_byte(dev,CONFIG5, TmpU1b);
2812
2813         // disable EEM0 and EEM1 in 9346CR
2814         btCR9346 &= ~(0xC0);
2815         write_nic_byte(dev, CR9346, btCR9346);
2816
2817         //Enable Led (suggested by Jong)
2818         // B-cut RF Radio on/off  5e[3]=0
2819         btPSR = read_nic_byte(dev, PSR);
2820         write_nic_byte(dev, PSR, (btPSR | BIT3));
2821 //by amy 080312 for led}
2822         // setup initial timing for RFE.
2823         write_nic_word(dev, RFPinsOutput, 0x0480);
2824         SetOutputEnableOfRfPins(dev);
2825         write_nic_word(dev, RFPinsSelect, 0x2488);
2826
2827         // PHY config.
2828         PhyConfig8185(dev);
2829
2830         // We assume RegWirelessMode has already been initialized before,
2831         // however, we has to validate the wireless mode here and provide a reasonble
2832         // initialized value if necessary. 2005.01.13, by rcnjko.
2833         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2834         if(     (ieee->mode != WIRELESS_MODE_B) &&
2835                 (ieee->mode != WIRELESS_MODE_G) &&
2836                 (ieee->mode != WIRELESS_MODE_A) &&
2837                 (ieee->mode != WIRELESS_MODE_AUTO))
2838         { // It should be one of B, G, A, or AUTO.
2839                 bInvalidWirelessMode = 1;
2840         }
2841         else
2842         { // One of B, G, A, or AUTO.
2843                 // Check if the wireless mode is supported by RF.
2844                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2845                         (ieee->mode & SupportedWirelessMode) == 0 )
2846                 {
2847                         bInvalidWirelessMode = 1;
2848                 }
2849         }
2850
2851         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2852         { // Auto or other invalid value.
2853                 // Assigne a wireless mode to initialize.
2854                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2855                 {
2856                         InitWirelessMode = WIRELESS_MODE_A;
2857                 }
2858                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2859                 {
2860                         InitWirelessMode = WIRELESS_MODE_G;
2861                 }
2862                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2863                 {
2864                         InitWirelessMode = WIRELESS_MODE_B;
2865                 }
2866                 else
2867                 {
2868                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2869                                  SupportedWirelessMode);
2870                         InitWirelessMode = WIRELESS_MODE_B;
2871                 }
2872
2873                 // Initialize RegWirelessMode if it is not a valid one.
2874                 if(bInvalidWirelessMode)
2875                 {
2876                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2877                 }
2878         }
2879         else
2880         { // One of B, G, A.
2881                 InitWirelessMode = ieee->mode;
2882         }
2883 //by amy for power save
2884 #ifdef ENABLE_IPS
2885 //      printk("initialize ENABLE_IPS\n");
2886         priv->eRFPowerState = eRfOff;
2887         priv->RfOffReason = 0;
2888         {
2889         //      u32 tmp2;
2890         //      u32 tmp = jiffies;
2891                 MgntActSet_RF_State(dev, eRfOn, 0);
2892         //      tmp2 = jiffies;
2893         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2894         }
2895 //      DrvIFIndicateCurrentPhyStatus(priv);
2896                 //
2897                 // If inactive power mode is enabled, disable rf while in disconnected state.
2898                 // 2007.07.16, by shien chang.
2899                 //
2900         if (priv->bInactivePs)
2901         {
2902         //      u32 tmp2;
2903         //      u32 tmp = jiffies;
2904                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2905         //      tmp2 = jiffies;
2906         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2907
2908         }
2909 #endif
2910 //      IPSEnter(dev);
2911 //by amy for power save
2912 #ifdef TODO
2913         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2914         // We shall turn off RF after setting CMDR, otherwise,
2915         // RF will be turnned on after we enable MAC Tx/Rx.
2916         if(Adapter->MgntInfo.RegRfOff == TRUE)
2917         {
2918                 SetRFPowerState8185(Adapter, RF_OFF);
2919         }
2920         else
2921         {
2922                 SetRFPowerState8185(Adapter, RF_ON);
2923         }
2924 #endif
2925
2926 /*   //these is equal with above TODO.
2927         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2928         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2929         RF_WriteReg(dev, 0x4, 0x9FF);
2930         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2931         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2932         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2933         write_nic_byte(dev, CR9346, 0x00);
2934 */
2935
2936         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2937
2938         //-----------------------------------------------------------------------------
2939
2940         rtl8185b_irq_enable(dev);
2941
2942         netif_start_queue(dev);
2943
2944  }
2945
2946
2947 void rtl8185b_rx_enable(struct net_device *dev)
2948 {
2949         u8 cmd;
2950         //u32 rxconf;
2951         /* for now we accept data, management & ctl frame*/
2952         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2953 #if 0
2954         rxconf=read_nic_dword(dev,RX_CONF);
2955         rxconf = rxconf &~ MAC_FILTER_MASK;
2956         rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
2957         rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
2958         rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
2959         rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
2960 //      rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2961         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2962
2963         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2964            dev->flags & IFF_PROMISC){
2965                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2966         }else{
2967                 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
2968                 if(priv->card_8185 == 0)
2969                         rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2970         }
2971
2972         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2973                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2974                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2975         }*/
2976
2977         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2978                 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
2979                 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
2980                 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
2981         }
2982
2983         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2984                 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2985
2986         //if(!priv->card_8185){
2987                 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
2988                 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
2989         //}
2990
2991         rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
2992         rxconf = rxconf &~ MAX_RX_DMA_MASK;
2993         rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
2994
2995         //if(!priv->card_8185)
2996                 rxconf = rxconf | RCR_ONLYERLPKT;
2997
2998         rxconf = rxconf &~ RCR_CS_MASK;
2999         if(!priv->card_8185)
3000                 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3001 //      rxconf &=~ 0xfff00000;
3002 //      rxconf |= 0x90100000;//9014f76f;
3003         write_nic_dword(dev, RX_CONF, rxconf);
3004 #endif
3005
3006         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3007
3008         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3009            dev->flags & IFF_PROMISC){
3010                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3011                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3012         }
3013
3014         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3015                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3016                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3017         }*/
3018
3019         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3020                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3021         }
3022
3023         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3024                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3025
3026         write_nic_dword(dev, RCR, priv->ReceiveConfig);
3027
3028         fix_rx_fifo(dev);
3029
3030 #ifdef DEBUG_RX
3031         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3032 #endif
3033         cmd=read_nic_byte(dev,CMD);
3034         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3035
3036 }
3037
3038 void rtl8185b_tx_enable(struct net_device *dev)
3039 {
3040         u8 cmd;
3041         //u8 tx_agc_ctl;
3042         u8 byte;
3043         //u32 txconf;
3044         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3045
3046 #if 0
3047         txconf= read_nic_dword(dev,TX_CONF);
3048         if(priv->card_8185){
3049
3050
3051                 byte = read_nic_byte(dev,CW_CONF);
3052                 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3053                 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3054                 write_nic_byte(dev, CW_CONF, byte);
3055
3056                 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3057                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3058                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3059                 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3060                 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3061                 /*
3062                 write_nic_word(dev, 0x5e, 0x01);
3063                 force_pci_posting(dev);
3064                 mdelay(1);
3065                 write_nic_word(dev, 0xfe, 0x10);
3066                 force_pci_posting(dev);
3067                 mdelay(1);
3068                 write_nic_word(dev, 0x5e, 0x00);
3069                 force_pci_posting(dev);
3070                 mdelay(1);
3071                 */
3072                 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3073         }
3074
3075         if(priv->card_8185){
3076
3077                 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3078
3079         }else{
3080
3081                 if(hwseqnum)
3082                         txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3083                 else
3084                         txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3085         }
3086
3087         txconf = txconf &~ TX_LOOPBACK_MASK;
3088         txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3089         txconf = txconf &~ TCR_DPRETRY_MASK;
3090         txconf = txconf &~ TCR_RTSRETRY_MASK;
3091         txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3092         txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3093         txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3094
3095         if(priv->card_8185){
3096                 if(priv->hw_plcp_len)
3097                         txconf = txconf &~ TCR_PLCP_LEN;
3098                 else
3099                         txconf = txconf | TCR_PLCP_LEN;
3100         }else{
3101                 txconf = txconf &~ TCR_SAT;
3102         }
3103         txconf = txconf &~ TCR_MXDMA_MASK;
3104         txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3105         txconf = txconf | TCR_CWMIN;
3106         txconf = txconf | TCR_DISCW;
3107
3108 //      if(priv->ieee80211->hw_wep)
3109 //              txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3110 //      else
3111                 txconf=txconf | (1<<TX_NOICV_SHIFT);
3112
3113         write_nic_dword(dev,TX_CONF,txconf);
3114 #endif
3115
3116         write_nic_dword(dev, TCR, priv->TransmitConfig);
3117         byte = read_nic_byte(dev, MSR);
3118         byte |= MSR_LINK_ENEDCA;
3119         write_nic_byte(dev, MSR, byte);
3120
3121         fix_tx_fifo(dev);
3122
3123 #ifdef DEBUG_TX
3124         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3125 #endif
3126
3127         cmd=read_nic_byte(dev,CMD);
3128         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3129
3130         //write_nic_dword(dev,TX_CONF,txconf);
3131
3132
3133 /*
3134         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3135         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3136         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3137         */
3138 }
3139
3140