2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
8 Hardware Initialization and Hardware IO for RTL8185B
12 ---------- --------------- -------------------------------
13 2006-11-15 Xiong Created
16 This file is ported from RTL8185B Windows driver.
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
25 #include "r8180_sa2400.h" /* PHILIPS Radio frontend */
26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
27 #include "r8180_gct.h" /* GCT Radio frontend */
28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
30 #include "r8180_93cx6.h" /* Card EEPROM */
35 #include "ieee80211/dot11d.h"
37 #ifdef CONFIG_RTL8185B
39 //#define CONFIG_RTL8180_IO_MAP
41 #define TC_3W_POLL_MAX_TRY_CNT 5
42 #ifdef CONFIG_RTL818X_S
43 static u8 MAC_REG_TABLE[][2]={
45 // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
46 // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
47 // 0x1F0~0x1F8 set in MacConfig_85BASIC()
48 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
49 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
50 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
51 {0x94, 0x0F}, {0x95, 0x32},
52 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
53 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
54 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
55 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
59 // For Flextronics system Logo PCIHCT failure:
60 // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
62 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
63 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
64 {0x82, 0xFF}, {0x83, 0x03},
65 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
66 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
72 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
73 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
74 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
75 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
76 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
77 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
78 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
81 {0x5e, 0x00},{0x9f, 0x03}
85 static u8 ZEBRA_AGC[]={
87 0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
88 0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
89 0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
90 0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
91 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
92 0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
93 0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
94 0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
97 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
98 0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
99 0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
100 0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
101 0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
102 0x0183,0x0163,0x0143,0x0123,0x0103
105 static u8 OFDM_CONFIG[]={
106 // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
107 // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
108 // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
111 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
112 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
114 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
115 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
117 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
118 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
120 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
121 0xD8, 0x3C, 0x7B, 0x10, 0x10
124 static u8 MAC_REG_TABLE[][2]={
126 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
127 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
128 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
133 {0x58, 0x4b}, {0x59, 0x00}, {0x5a, 0x4b}, {0x5b, 0x00}, {0x60, 0x4b},
134 {0x61, 0x09}, {0x62, 0x4b}, {0x63, 0x09}, {0xce, 0x0f}, {0xcf, 0x00},
135 {0xe0, 0xff}, {0xe1, 0x0f}, {0xe2, 0x00}, {0xf0, 0x4e}, {0xf1, 0x01},
136 {0xf2, 0x02}, {0xf3, 0x03}, {0xf4, 0x04}, {0xf5, 0x05}, {0xf6, 0x06},
137 {0xf7, 0x07}, {0xf8, 0x08},
142 {0x0c, 0x04}, {0x21, 0x61}, {0x22, 0x68}, {0x23, 0x6f}, {0x24, 0x76},
143 {0x25, 0x7d}, {0x26, 0x84}, {0x27, 0x8d}, {0x4d, 0x08}, {0x4e, 0x00},
144 {0x50, 0x05}, {0x51, 0xf5}, {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0x1f},
145 {0x55, 0x23}, {0x56, 0x45}, {0x57, 0x67}, {0x58, 0x08}, {0x59, 0x08},
146 {0x5a, 0x08}, {0x5b, 0x08}, {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08},
147 {0x63, 0x08}, {0x64, 0xcf}, {0x72, 0x56}, {0x73, 0x9a},
151 {0x34, 0xff}, {0x35, 0x0f}, {0x5b, 0x40}, {0x84, 0x88}, {0x85, 0x24},
152 {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x07}, {0x8d, 0x00}, {0x94, 0x1b},
153 {0x95, 0x12}, {0x96, 0x00}, {0x97, 0x06}, {0x9d, 0x1a}, {0x9f, 0x10},
154 {0xb4, 0x22}, {0xbe, 0x80}, {0xdb, 0x00}, {0xee, 0x00}, {0x5b, 0x42},
170 {0x8c, 0x01}, {0x8d, 0x10},{0x8e, 0x08}, {0x8f, 0x00}
174 static u8 ZEBRA_AGC[]={
176 0x5e,0x5e,0x5e,0x5e,0x5d,0x5b,0x59,0x57,0x55,0x53,0x51,0x4f,0x4d,0x4b,0x49,0x47,
177 0x45,0x43,0x41,0x3f,0x3d,0x3b,0x39,0x37,0x35,0x33,0x31,0x2f,0x2d,0x2b,0x29,0x27,
178 0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x11,0x0f,0x0d,0x0b,0x09,0x07,
179 0x05,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
180 0x19,0x19,0x19,0x019,0x19,0x19,0x19,0x19,0x19,0x19,0x1e,0x1f,0x20,0x21,0x21,0x22,
181 0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,0x28,0x29,0x2a,0x2a,0x2b,
182 0x2b,0x2b,0x2c,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,0x30,0x31,0x31,0x31,0x31,
183 0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31
186 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
188 0x0400,0x0401,0x0402,0x0403,0x0404,0x0405,0x0408,0x0409,
189 0x040a,0x040b,0x0502,0x0503,0x0504,0x0505,0x0540,0x0541,
190 0x0542,0x0543,0x0544,0x0545,0x0580,0x0581,0x0582,0x0583,
191 0x0584,0x0585,0x0588,0x0589,0x058a,0x058b,0x0643,0x0644,
192 0x0645,0x0680,0x0681,0x0682,0x0683,0x0684,0x0685,0x0688,
193 0x0689,0x068a,0x068b,0x068c,0x0742,0x0743,0x0744,0x0745,
194 0x0780,0x0781,0x0782,0x0783,0x0784,0x0785,0x0788,0x0789,
195 0x078a,0x078b,0x078c,0x078d,0x0790,0x0791,0x0792,0x0793,
196 0x0794,0x0795,0x0798,0x0799,0x079a,0x079b,0x079c,0x079d,
197 0x07a0,0x07a1,0x07a2,0x07a3,0x07a4,0x07a5,0x07a8,0x07a9,
198 0x03aa,0x03ab,0x03ac,0x03ad,0x03b0,0x03b1,0x03b2,0x03b3,
199 0x03b4,0x03b5,0x03b8,0x03b9,0x03ba,0x03bb,0x03bb
202 // 2006.07.13, SD3 szuyitasi:
203 // OFDM.0x03=0x0C (original is 0x0F)
204 // Use the new SD3 given param, by shien chang, 2006.07.14
205 static u8 OFDM_CONFIG[]={
206 0x10, 0x0d, 0x01, 0x0C, 0x14, 0xfb, 0x0f, 0x60, 0x00, 0x60,
207 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,
208 0x00, 0x00, 0xa8, 0x46, 0xb2, 0x33, 0x07, 0xa5, 0x6f, 0x55,
209 0xc8, 0xb3, 0x0a, 0xe1, 0x1c, 0x8a, 0xb6, 0x83, 0x34, 0x0f,
210 0x4f, 0x23, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 0xc0, 0xc1,
211 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 0x6d, 0x3c, 0xff, 0x07
215 /*---------------------------------------------------------------
217 * the code is ported from Windows source code
218 ----------------------------------------------------------------*/
221 PlatformIOWrite1Byte(
222 struct net_device *dev,
227 #ifndef CONFIG_RTL8180_IO_MAP
228 write_nic_byte(dev, offset, data);
229 read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
232 u32 Page = (offset >> 8);
237 write_nic_byte(dev, offset, data);
244 u8 psr = read_nic_byte(dev, PSR);
246 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
247 write_nic_byte(dev, (offset & 0xff), data);
248 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
253 // Illegal page number.
254 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
261 PlatformIOWrite2Byte(
262 struct net_device *dev,
267 #ifndef CONFIG_RTL8180_IO_MAP
268 write_nic_word(dev, offset, data);
269 read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
273 u32 Page = (offset >> 8);
278 write_nic_word(dev, offset, data);
285 u8 psr = read_nic_byte(dev, PSR);
287 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
288 write_nic_word(dev, (offset & 0xff), data);
289 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
294 // Illegal page number.
295 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
300 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
303 PlatformIOWrite4Byte(
304 struct net_device *dev,
309 #ifndef CONFIG_RTL8180_IO_MAP
311 if (offset == PhyAddr)
312 {//For Base Band configuration.
313 unsigned char cmdByte;
314 unsigned long dataBytes;
318 cmdByte = (u8)(data & 0x000000ff);
323 // The critical section is only BB read/write race condition.
325 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
326 // acquiring the spinlock in such context.
327 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
329 // NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
331 for(idx = 0; idx < 30; idx++)
332 { // Make sure command bit is clear before access it.
333 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
334 if((u1bTmp & BIT7) == 0)
340 for(idx=0; idx < 3; idx++)
342 PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
344 write_nic_byte(dev, offset, cmdByte);
346 // NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
350 write_nic_dword(dev, offset, data);
351 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
354 u32 Page = (offset >> 8);
359 write_nic_word(dev, offset, data);
366 u8 psr = read_nic_byte(dev, PSR);
368 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
369 write_nic_dword(dev, (offset & 0xff), data);
370 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
375 // Illegal page number.
376 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
384 struct net_device *dev,
390 #ifndef CONFIG_RTL8180_IO_MAP
391 data = read_nic_byte(dev, offset);
394 u32 Page = (offset >> 8);
399 data = read_nic_byte(dev, offset);
406 u8 psr = read_nic_byte(dev, PSR);
408 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
409 data = read_nic_byte(dev, (offset & 0xff));
410 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
415 // Illegal page number.
416 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
426 struct net_device *dev,
432 #ifndef CONFIG_RTL8180_IO_MAP
433 data = read_nic_word(dev, offset);
436 u32 Page = (offset >> 8);
441 data = read_nic_word(dev, offset);
448 u8 psr = read_nic_byte(dev, PSR);
450 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
451 data = read_nic_word(dev, (offset & 0xff));
452 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
457 // Illegal page number.
458 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
468 struct net_device *dev,
474 #ifndef CONFIG_RTL8180_IO_MAP
475 data = read_nic_dword(dev, offset);
478 u32 Page = (offset >> 8);
483 data = read_nic_dword(dev, offset);
490 u8 psr = read_nic_byte(dev, PSR);
492 write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
493 data = read_nic_dword(dev, (offset & 0xff));
494 write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
499 // Illegal page number.
500 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
509 SetOutputEnableOfRfPins(
510 struct net_device *dev
513 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
515 switch(priv->rf_chip)
517 case RFCHIPID_RTL8225:
520 write_nic_word(dev, RFPinsEnable, 0x1bff);
521 //write_nic_word(dev, RFPinsEnable, 0x1fff);
528 struct net_device *dev,
536 u16 oval,oval2,oval3;
541 #ifdef CONFIG_RTL818X_S
542 // RTL8187S HSSI Read/Write Function
543 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
544 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
545 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
547 UshortBuffer = read_nic_word(dev, RFPinsOutput);
548 oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
550 oval2 = read_nic_word(dev, RFPinsEnable);
551 oval3 = read_nic_word(dev, RFPinsSelect);
553 // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
556 write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
557 write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
560 // Add this to avoid hardware and software 3-wire conflict.
561 // 2005.03.01, by rcnjko.
563 twreg.struc.enableB = 1;
564 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
566 twreg.struc.enableB = 0;
567 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
570 mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
572 for(i=0; i<totalLength/2; i++)
574 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
575 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
577 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
578 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
580 mask = (low2high)?(mask<<1):(mask>>1);
581 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
582 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
583 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
585 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
586 mask = (low2high)?(mask<<1):(mask>>1);
589 twreg.struc.enableB = 1;
591 twreg.struc.data = 0;
592 write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
595 write_nic_word(dev, RFPinsOutput, oval|0x0004);
596 write_nic_word(dev, RFPinsSelect, oval3|0x0000);
598 SetOutputEnableOfRfPins(dev);
605 struct net_device *dev,
618 // Check if WE and RE are cleared.
619 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
621 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
622 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
628 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
629 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
631 // RTL8187S HSSI Read/Write Function
632 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
636 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
639 u1bTmp &= ~RF_SW_CFG_SI; //reg08[1]=0 Parallel Interface(PI)
642 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
646 // jong: HW SI read must set reg84[3]=0.
647 u1bTmp = read_nic_byte(dev, RFPinsSelect);
649 write_nic_byte(dev, RFPinsSelect, u1bTmp );
651 // Fill up data buffer for write operation.
655 if(nDataBufBitCnt == 16)
657 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
659 else if(nDataBufBitCnt == 64) // RTL8187S shouldn't enter this case
661 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
662 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
667 int ByteCnt = nDataBufBitCnt / 8;
668 //printk("%d\n",nDataBufBitCnt);
669 if ((nDataBufBitCnt % 8) != 0)
670 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
673 if (nDataBufBitCnt > 64)
674 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
677 for(idx = 0; idx < ByteCnt; idx++)
679 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
687 // SI - reg274[3:0] : RF register's Address
688 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
692 // PI - reg274[15:12] : RF register's Address
693 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
697 // Set up command: WE or RE.
700 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
704 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
707 // Check if DONE is set.
708 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
710 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
711 if( (u1bTmp & SW_3W_CMD1_DONE) != 0 )
718 write_nic_byte(dev, SW_3W_CMD1, 0);
720 // Read back data for read operation.
725 //Serial Interface : reg363_362[11:0]
726 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
730 //Parallel Interface : reg361_360[11:0]
731 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
734 *((u16*)pDataBuf) &= 0x0FFF;
745 struct net_device *dev,
758 // Check if WE and RE are cleared.
759 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
761 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
762 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
768 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
769 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
771 // Fill up data buffer for write operation.
772 if(nDataBufBitCnt == 16)
774 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
776 else if(nDataBufBitCnt == 64)
778 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
779 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
784 int ByteCnt = nDataBufBitCnt / 8;
786 if ((nDataBufBitCnt % 8) != 0)
787 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
790 if (nDataBufBitCnt > 64)
791 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
794 for(idx = 0; idx < ByteCnt; idx++)
796 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
800 // Fill up length field.
801 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
803 u1bTmp |= SW_3W_CMD0_HOLD;
804 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
806 // Set up command: WE or RE.
809 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
813 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
816 // Check if WE and RE are cleared and DONE is set.
817 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
819 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
820 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
821 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
827 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
829 //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
830 // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
831 // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
832 write_nic_byte(dev, SW_3W_CMD1, 0);
835 // Read back data for read operation.
836 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
839 if(nDataBufBitCnt == 16)
841 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
843 else if(nDataBufBitCnt == 64)
845 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
846 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
851 int ByteCnt = nDataBufBitCnt / 8;
853 if ((nDataBufBitCnt % 8) != 0)
854 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
857 if (nDataBufBitCnt > 64)
858 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
861 for(idx = 0; idx < ByteCnt; idx++)
863 *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
876 struct net_device *dev,
886 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
889 switch(priv->rf_chip)
891 case RFCHIPID_RTL8225:
892 case RF_ZEBRA2: // Annie 2006-05-12.
893 case RF_ZEBRA4: //by amy
894 switch(priv->RegThreeWireMode)
897 { // Perform SW 3-wire programming by driver.
898 data2Write = (data << 4) | (u32)(offset & 0x0f);
901 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
907 data2Write = (data << 4) | (u32)(offset & 0x0f);
911 (u8 *)(&data2Write), // pDataBuf,
912 len, // nDataBufBitCnt,
917 #ifdef CONFIG_RTL818X_S
918 case HW_THREE_WIRE_PI: //Parallel Interface
920 data2Write = (data << 4) | (u32)(offset & 0x0f);
924 (u8*)(&data2Write), // pDataBuf,
925 len, // nDataBufBitCnt,
933 case HW_THREE_WIRE_SI: //Serial Interface
935 data2Write = (data << 4) | (u32)(offset & 0x0f);
937 // printk(" enter ZEBRA_RFSerialWrite\n ");
939 // ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
943 (u8*)(&data2Write), // pDataBuf,
944 len, // nDataBufBitCnt,
948 // printk(" exit ZEBRA_RFSerialWrite\n ");
955 DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
961 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
969 struct net_device *dev,
979 u16 oval,oval2,oval3,tmp, wReg80;
983 //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter);
984 #ifdef CONFIG_RTL818X_S
985 { // RTL8187S HSSI Read/Write Function
986 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
987 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
988 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
992 wReg80 = oval = read_nic_word(dev, RFPinsOutput);
993 oval2 = read_nic_word(dev, RFPinsEnable);
994 oval3 = read_nic_word(dev, RFPinsSelect);
996 write_nic_word(dev, RFPinsEnable, oval2|0xf);
997 write_nic_word(dev, RFPinsSelect, oval3|0xf);
1001 // We must clear BIT0-3 here, otherwise,
1002 // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
1003 // which will cause the value read become 0. 2005.04.11, by rcnjko.
1006 // Avoid collision with hardware three-wire.
1008 twreg.struc.enableB = 1;
1009 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
1012 twreg.struc.enableB = 0;
1013 twreg.struc.clk = 0;
1014 twreg.struc.read_write = 0;
1015 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
1017 mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
1018 for(i = 0; i < wLength/2; i++)
1020 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
1021 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1022 twreg.struc.clk = 1;
1023 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1024 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1026 mask = (low2high) ? (mask<<1): (mask>>1);
1030 // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
1031 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable
1032 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
1034 twreg.struc.read_write=1;
1035 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1036 twreg.struc.clk = 0;
1037 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1040 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
1041 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1042 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1044 twreg.struc.clk = 0;
1045 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1047 mask = (low2high) ? (mask<<1) : (mask>>1);
1050 twreg.struc.clk = 0;
1051 twreg.struc.data = 0;
1052 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1053 mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
1056 // 061016, by rcnjko:
1057 // We must set data pin to HW controled, otherwise RF can't driver it and
1058 // value RF register won't be able to read back properly.
1060 write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
1062 for(i = 0; i < rLength; i++)
1064 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1065 twreg.struc.clk = 1;
1066 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1067 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1068 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1069 tmp = read_nic_word(dev, RFPinsInput);
1070 tdata.longData = tmp;
1071 *data2Read |= tdata.struc.clk ? mask : 0;
1073 twreg.struc.clk = 0;
1074 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1076 mask = (low2high) ? (mask<<1) : (mask>>1);
1078 twreg.struc.enableB = 1;
1079 twreg.struc.clk = 0;
1080 twreg.struc.data = 0;
1081 twreg.struc.read_write = 1;
1082 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1084 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable
1085 write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
1086 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
1087 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
1088 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
1089 write_nic_word(dev, RFPinsOutput, 0x3a0);
1090 //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
1096 struct net_device *dev,
1100 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1107 switch(priv->rf_chip)
1109 case RFCHIPID_RTL8225:
1112 switch(priv->RegThreeWireMode)
1114 #ifdef CONFIG_RTL818X_S
1115 case HW_THREE_WIRE_PI: // For 87S Parallel Interface.
1117 data2Write = ((u32)(offset&0x0f));
1121 (u8*)(&data2Write), // pDataBuf,
1122 wlen, // nDataBufBitCnt,
1125 dataRead= data2Write;
1129 case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1131 data2Write = ((u32)(offset&0x0f)) ;
1135 (u8*)(&data2Write), // pDataBuf,
1136 wlen, // nDataBufBitCnt,
1140 dataRead= data2Write;
1145 // Perform SW 3-wire programming by driver.
1148 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1152 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1166 // by Owen on 04/07/14 for writing BB register successfully
1169 struct net_device *dev,
1173 //u8 TimeoutCounter;
1177 UCharData = (u8)((Data & 0x0000ff00) >> 8);
1178 PlatformIOWrite4Byte(dev, PhyAddr, Data);
1179 //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1181 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1182 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1183 //if(UCharData == RegisterContent)
1190 struct net_device *dev,
1194 //u8 TimeoutCounter;
1197 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1198 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1200 return RegisterContent;
1203 #ifdef CONFIG_RTL818X_S
1206 // Perform Antenna settings with antenna diversity on 87SE.
1207 // Created by Roger, 2008.01.25.
1210 SetAntennaConfig87SE(
1211 struct net_device *dev,
1212 u8 DefaultAnt, // 0: Main, 1: Aux.
1213 bool bAntDiversity // 1:Enable, 0: Disable.
1216 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1217 bool bAntennaSwitched = true;
1219 //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1221 // Threshold for antenna diversity.
1222 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1224 if( bAntDiversity ) // Enable Antenna Diversity.
1226 if( DefaultAnt == 1 ) // aux antenna
1228 // Mac register, aux antenna
1229 write_nic_byte(dev, ANTSEL, 0x00);
1231 // Config CCK RX antenna.
1232 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1233 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1235 // Config OFDM RX antenna.
1236 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
1237 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1239 else // use main antenna
1241 // Mac register, main antenna
1242 write_nic_byte(dev, ANTSEL, 0x03);
1244 // Config CCK RX antenna.
1245 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1246 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1248 // Config OFDM RX antenna.
1249 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1250 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1253 else // Disable Antenna Diversity.
1255 if( DefaultAnt == 1 ) // aux Antenna
1257 // Mac register, aux antenna
1258 write_nic_byte(dev, ANTSEL, 0x00);
1260 // Config CCK RX antenna.
1261 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1262 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1264 // Config OFDM RX antenna.
1265 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
1266 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1268 else // main Antenna
1270 // Mac register, main antenna
1271 write_nic_byte(dev, ANTSEL, 0x03);
1273 // Config CCK RX antenna.
1274 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1275 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1277 // Config OFDM RX antenna.
1278 write_phy_ofdm(dev, 0x0D, 0x5c); // Reg0d : 5c
1279 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1282 priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1283 return bAntennaSwitched;
1287 /*---------------------------------------------------------------
1288 * Hardware Initialization.
1289 * the code is ported from Windows source code
1290 ----------------------------------------------------------------*/
1293 ZEBRA_Config_85BASIC_HardCode(
1294 struct net_device *dev
1298 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1301 u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1304 #ifdef CONFIG_RTL818X_S
1306 //=============================================================================
1307 // 87S_PCIE :: RADIOCFG.TXT
1308 //=============================================================================
1311 // Page1 : reg16-reg30
1312 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); // switch to page1
1313 u4bRF23= RF_ReadReg(dev, 0x08); mdelay(1);
1314 u4bRF24= RF_ReadReg(dev, 0x09); mdelay(1);
1316 if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1317 priv->card_8185 = VERSION_8187S_D;
1319 // Page0 : reg0-reg15
1321 // RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1
1322 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1
1324 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
1326 // RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2
1327 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2
1329 // RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3
1330 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3
1332 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
1333 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1334 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
1335 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
1336 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
1337 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
1338 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
1339 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
1340 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
1341 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
1342 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
1343 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
1346 // Page1 : reg16-reg30
1347 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
1349 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
1351 if(priv->card_8185 < VERSION_8187S_C)
1353 RF_WriteReg(dev, 0x04, 0x03f7); mdelay(1);
1354 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
1355 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1359 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
1360 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
1361 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
1365 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
1366 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1367 // RF_WriteReg(dev, 0x08, 0x0597); mdelay(1);
1368 // RF_WriteReg(dev, 0x09, 0x050a); mdelay(1);
1369 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1370 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
1372 if(priv->card_8185 == VERSION_8187S_D)
1374 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1375 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1376 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); // RX LO buffer
1380 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1381 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1382 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); // RX LO buffer
1385 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1387 // RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6
1388 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6
1390 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
1391 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
1394 RF_WriteReg(dev, 0x01, i); mdelay(1);
1395 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1396 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1399 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343
1400 //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400
1401 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400
1403 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137
1404 mdelay(10); // Deay 10 ms. //0xfd
1406 // RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7
1407 //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1);
1408 //mdelay(10); // Deay 10 ms. //0xfd
1410 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392
1411 mdelay(10); // Deay 10 ms. //0xfd
1413 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); // switch to reg0-reg15, and HSSI disable
1414 mdelay(10); // Deay 10 ms. //0xfd
1416 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); // CBC on, Tx Rx disable, High gain
1417 mdelay(10); // Deay 10 ms. //0xfd
1419 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); // Z4 setted channel 1
1420 mdelay(10); // Deay 10 ms. //0xfd
1422 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); // LC calibration
1423 mdelay(200); // Deay 200 ms. //0xfd
1424 mdelay(10); // Deay 10 ms. //0xfd
1425 mdelay(10); // Deay 10 ms. //0xfd
1427 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30 137, and HSSI disable 137
1428 mdelay(10); // Deay 10 ms. //0xfd
1430 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
1431 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
1432 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
1433 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
1435 // DAC calibration off 20070702
1436 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1437 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1439 // For crystal calibration, added by Roger, 2007.12.11.
1440 if( priv->bXtalCalibration ) // reg 30.
1441 { // enable crystal calibration.
1442 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
1443 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1444 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1445 // So we should minus 4 BITs offset.
1446 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1);
1447 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1448 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1451 { // using default value. Xin=6, Xout=6.
1452 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1455 // RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312
1457 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable
1458 // RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward
1459 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward
1460 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off
1461 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode
1462 mdelay(10); // Deay 10 ms. //0xfe
1463 mdelay(10); // Deay 10 ms. //0xfe
1464 mdelay(10); // Deay 10 ms. //0xfe
1465 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); // Rx mode//+edward
1466 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); // Rx mode//+edward
1467 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); // Rx mode//+edward
1470 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1);
1471 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
1472 RF_WriteReg(dev, 0x00, 0x009F); mdelay(1);
1474 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); // Rx mode//+edward
1475 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); // Rx mode//+edward
1476 //power save parameters.
1477 u1b24E = read_nic_byte(dev, 0x24E);
1478 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1480 //=============================================================================
1482 //=============================================================================
1484 //=============================================================================
1486 /* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1487 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1488 CCK reg0x00[6]=1'b1: power saving for RX (default)
1489 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1490 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1491 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1494 write_nic_dword(dev, PHY_ADR, 0x0100c880);
1495 write_nic_dword(dev, PHY_ADR, 0x01001c86);
1496 write_nic_dword(dev, PHY_ADR, 0x01007890);
1497 write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1498 write_nic_dword(dev, PHY_ADR, 0x010006af);
1499 write_nic_dword(dev, PHY_ADR, 0x01004681);
1501 write_phy_cck(dev,0x00,0xc8);
1502 write_phy_cck(dev,0x06,0x1c);
1503 write_phy_cck(dev,0x10,0x78);
1504 write_phy_cck(dev,0x2e,0xd0);
1505 write_phy_cck(dev,0x2f,0x06);
1506 write_phy_cck(dev,0x01,0x46);
1509 write_nic_byte(dev, CCK_TXAGC, 0x10);
1510 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1511 write_nic_byte(dev, ANTSEL, 0x03);
1513 //=============================================================================
1515 //=============================================================================
1517 RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1);
1518 RF_WriteReg(dev, 0x01, 0x0ee0); mdelay(1);
1519 RF_WriteReg(dev, 0x02, 0x044d); mdelay(1);
1520 RF_WriteReg(dev, 0x03, 0x0441); mdelay(1);
1521 RF_WriteReg(dev, 0x04, 0x08c3); mdelay(1);
1522 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1523 RF_WriteReg(dev, 0x06, 0x00e6); mdelay(1);
1524 RF_WriteReg(dev, 0x07, 0x082a); mdelay(1);
1525 RF_WriteReg(dev, 0x08, 0x003f); mdelay(1);
1526 RF_WriteReg(dev, 0x09, 0x0335); mdelay(1);
1527 RF_WriteReg(dev, 0x0a, 0x09d4); mdelay(1);
1528 RF_WriteReg(dev, 0x0b, 0x07bb); mdelay(1);
1529 RF_WriteReg(dev, 0x0c, 0x0850); mdelay(1);
1530 RF_WriteReg(dev, 0x0d, 0x0cdf); mdelay(1);
1531 RF_WriteReg(dev, 0x0e, 0x002b); mdelay(1);
1532 RF_WriteReg(dev, 0x0f, 0x0114); mdelay(1);
1534 RF_WriteReg(dev, 0x00, 0x01b7); mdelay(1);
1539 RF_WriteReg(dev, 0x01, i); mdelay(1);
1540 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1541 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1544 RF_WriteReg(dev, 0x03, 0x0080); mdelay(1); // write reg 18
1545 RF_WriteReg(dev, 0x05, 0x0004); mdelay(1); // write reg 20
1546 RF_WriteReg(dev, 0x00, 0x00b7); mdelay(1); // switch to reg0-reg15
1550 RF_WriteReg(dev, 0x02, 0x0c4d); mdelay(1);
1551 mdelay(100); // Deay 100 ms. //0xfe
1552 mdelay(100); // Deay 100 ms. //0xfe
1553 RF_WriteReg(dev, 0x02, 0x044d); mdelay(1);
1554 RF_WriteReg(dev, 0x00, 0x02bf); mdelay(1); //0x002f disable 6us corner change, 06f--> enable
1556 //=============================================================================
1558 //=============================================================================
1560 //=============================================================================
1562 //=============================================================================
1564 //=============================================================================
1565 // Follow WMAC RTL8225_Config()
1566 //=============================================================================
1569 write_nic_byte(dev, CCK_TXAGC, 0x03);
1570 write_nic_byte(dev, OFDM_TXAGC, 0x07);
1571 write_nic_byte(dev, ANTSEL, 0x03);
1573 //=============================================================================
1576 // SetOutputEnableOfRfPins(dev);//by amy
1581 //=============================================================================
1583 //=============================================================================
1585 // PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05
1586 write_phy_ofdm(dev, 0x00, 0x12);
1587 //WriteBBPortUchar(dev, 0x00001280);
1589 for (i=0; i<128; i++)
1591 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1593 data = ZEBRA_AGC[i+1];
1595 data = data | 0x0000008F;
1597 addr = i + 0x80; //enable writing AGC table
1599 addr = addr | 0x0000008E;
1601 WriteBBPortUchar(dev, data);
1602 WriteBBPortUchar(dev, addr);
1603 WriteBBPortUchar(dev, 0x0000008E);
1606 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05
1607 //WriteBBPortUchar(dev, 0x00001080);
1609 //=============================================================================
1611 //=============================================================================
1613 //=============================================================================
1618 u4bRegValue=OFDM_CONFIG[i];
1620 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1622 WriteBBPortUchar(dev,
1624 (u4bRegOffset & 0x7f) |
1625 ((u4bRegValue & 0xff) << 8)));
1628 //=============================================================================
1629 //by amy for antenna
1630 //=============================================================================
1632 #ifdef CONFIG_RTL818X_S
1633 // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1634 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1638 // Config Sw/Hw Antenna Diversity
1639 if( priv->bSwAntennaDiverity ) // Use SW+Hw Antenna Diversity
1641 if( priv->bDefaultAntenna1 == true ) // aux antenna
1643 // Mac register, aux antenna
1644 write_nic_byte(dev, ANTSEL, 0x00);
1645 // Config CCK RX antenna.
1646 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1647 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1648 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1649 // Config OFDM RX antenna.
1650 write_phy_ofdm(dev, 0x0d, 0x54); // Reg0d : 54
1651 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1653 else // main antenna
1655 // Mac register, main antenna
1656 write_nic_byte(dev, ANTSEL, 0x03);
1658 // Config CCK RX antenna.
1659 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1660 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1661 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1662 // Config OFDM RX antenna.
1663 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1664 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
1667 else // Disable Antenna Diversity
1669 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1671 // Mac register, aux antenna
1672 write_nic_byte(dev, ANTSEL, 0x00);
1673 // Config CCK RX antenna.
1674 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1675 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1676 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1677 // Config OFDM RX antenna.
1678 write_phy_ofdm(dev, 0x0d, 0x54); // Reg0d : 54
1679 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1681 else // main Antenna
1683 // Mac register, main antenna
1684 write_nic_byte(dev, ANTSEL, 0x03);
1685 // Config CCK RX antenna.
1686 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1687 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1688 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1689 // Config OFDM RX antenna.
1690 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
1691 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1695 //by amy for antenna
1701 struct net_device *dev
1704 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1705 //unsigned char* IGTable;
1706 //u8 DIG_CurrentInitialGain = 4;
1707 //unsigned char u1Tmp;
1710 if(priv->eRFPowerState != eRfOn)
1712 //Don't access BB/RF under disable PLL situation.
1713 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1714 // Back to the original state
1715 priv->InitialGain= priv->InitialGainBackUp;
1719 switch(priv->rf_chip)
1723 // Dynamic set initial gain, by shien chang, 2006.07.14
1724 switch(priv->InitialGain)
1727 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1728 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1729 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1730 write_nic_dword(dev, PhyAddr, 0xfa85); mdelay(1);
1734 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1735 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1736 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1737 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1741 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1742 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1743 write_nic_dword(dev, PhyAddr, 0x96a4); mdelay(1);
1744 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1748 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1749 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1750 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1751 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1755 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1756 write_nic_dword(dev, PhyAddr, 0x3697); mdelay(1);
1757 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1758 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1762 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1763 write_nic_dword(dev, PhyAddr, 0x4697); mdelay(1);
1764 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1765 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1769 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1770 write_nic_dword(dev, PhyAddr, 0x5697); mdelay(1);
1771 write_nic_dword(dev, PhyAddr, 0xa6a4); mdelay(1);
1772 write_nic_dword(dev, PhyAddr, 0xfb85); mdelay(1);
1776 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1777 write_nic_dword(dev, PhyAddr, 0x2697); mdelay(1);
1778 write_nic_dword(dev, PhyAddr, 0x86a4); mdelay(1);
1779 write_nic_dword(dev, PhyAddr, 0xfa85); mdelay(1);
1785 // Dynamic set initial gain, follow 87B
1786 switch(priv->InitialGain)
1789 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1790 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1791 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1792 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1796 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1797 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1798 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1799 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1803 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1804 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1805 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1806 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1810 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1811 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1812 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1813 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1817 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1818 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1819 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1820 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1824 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1825 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1826 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1827 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1831 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1832 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1833 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
1834 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1838 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1839 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
1840 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
1841 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1846 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1847 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1848 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1849 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1856 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1860 #ifdef CONFIG_RTL818X_S
1863 // Tx Power tracking mechanism routine on 87SE.
1864 // Created by Roger, 2007.12.11.
1867 InitTxPwrTracking87SE(
1868 struct net_device *dev
1871 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1874 u4bRfReg = RF_ReadReg(dev, 0x02);
1876 // Enable Thermal meter indication.
1877 //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1878 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
1884 struct net_device *dev
1887 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1888 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1889 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1891 switch(priv->rf_chip)
1895 ZEBRA_Config_85BASIC_HardCode( dev);
1899 #ifdef CONFIG_RTL818X_S
1900 // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1901 if(priv->bDigMechanism)
1903 if(priv->InitialGain == 0)
1904 priv->InitialGain = 4;
1905 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1909 // Enable thermal meter indication to implement TxPower tracking on 87SE.
1910 // We initialize thermal meter here to avoid unsuccessful configuration.
1911 // Added by Roger, 2007.12.11.
1913 if(priv->bTxPowerTrack)
1914 InitTxPwrTracking87SE(dev);
1918 priv->InitialGainBackUp= priv->InitialGain;
1919 UpdateInitialGain(dev);
1929 struct net_device *dev
1932 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1933 // u8 bUNIVERSAL_CONTROL_RL = 1;
1934 u8 bUNIVERSAL_CONTROL_RL = 0;
1936 u8 bUNIVERSAL_CONTROL_AGC = 1;
1937 u8 bUNIVERSAL_CONTROL_ANT = 1;
1938 u8 bAUTO_RATE_FALLBACK_CTL = 1;
1940 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1941 //struct ieee80211_device *ieee = priv->ieee80211;
1942 //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1943 //{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1945 // write_nic_word(dev, BRSR, 0xffff);
1949 // write_nic_word(dev, BRSR, 0x000f);
1952 write_nic_word(dev, BRSR, 0x0fff);
1954 val8 = read_nic_byte(dev, CW_CONF);
1956 if(bUNIVERSAL_CONTROL_RL)
1961 write_nic_byte(dev, CW_CONF, val8);
1964 val8 = read_nic_byte(dev, TXAGC_CTL);
1965 if(bUNIVERSAL_CONTROL_AGC)
1967 write_nic_byte(dev, CCK_TXAGC, 128);
1968 write_nic_byte(dev, OFDM_TXAGC, 128);
1973 val8 = val8 | 0x01 ;
1977 write_nic_byte(dev, TXAGC_CTL, val8);
1979 // Tx Antenna including Feedback control
1980 val8 = read_nic_byte(dev, TXAGC_CTL );
1982 if(bUNIVERSAL_CONTROL_ANT)
1984 write_nic_byte(dev, ANTSEL, 0x00);
1989 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1992 write_nic_byte(dev, TXAGC_CTL, val8);
1994 // Auto Rate fallback control
1995 val8 = read_nic_byte(dev, RATE_FALLBACK);
1997 if( bAUTO_RATE_FALLBACK_CTL )
1999 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
2001 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
2002 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
2005 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); // set 1M ~ 54M
2007 #ifdef CONFIG_RTL818X_S
2008 // Aadded by Roger, 2007.11.15.
2009 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
2011 PlatformIOWrite2Byte(dev, ARFR, 0x0c00); //set 48Mbps, 54Mbps.
2012 // By SD3 szuyi's request. by Roger, 2007.03.26.
2019 write_nic_byte(dev, RATE_FALLBACK, val8);
2025 MacConfig_85BASIC_HardCode(
2026 struct net_device *dev)
2028 //============================================================================
2030 //============================================================================
2033 u32 u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
2036 nLinesRead=sizeof(MAC_REG_TABLE)/2;
2038 for(i = 0; i < nLinesRead; i++) //nLinesRead=101
2040 u4bRegOffset=MAC_REG_TABLE[i][0];
2041 u4bRegValue=MAC_REG_TABLE[i][1];
2043 if(u4bRegOffset == 0x5e)
2045 u4bPageIndex = u4bRegValue;
2049 u4bRegOffset |= (u4bPageIndex << 8);
2051 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
2052 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
2054 //============================================================================
2061 struct net_device *dev)
2065 MacConfig_85BASIC_HardCode(dev);
2067 //============================================================================
2069 // Follow TID_AC_MAP of WMac.
2070 write_nic_word(dev, TID_AC_MAP, 0xfa50);
2072 // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
2073 write_nic_word(dev, IntMig, 0x0000);
2075 // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
2076 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
2077 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
2078 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
2080 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
2081 //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
2084 write_nic_dword(dev, RFTiming, 0x00004001);
2086 #ifdef CONFIG_RTL818X_S
2087 // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
2089 //Enable DA10 TX power saving
2090 u1DA = read_nic_byte(dev, PHYPR);
2091 write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
2094 write_nic_word(dev, 0x360, 0x1000);
2095 write_nic_word(dev, 0x362, 0x1000);
2098 write_nic_word(dev, 0x370, 0x0560);
2099 write_nic_word(dev, 0x372, 0x0560);
2100 write_nic_word(dev, 0x374, 0x0DA4);
2101 write_nic_word(dev, 0x376, 0x0DA4);
2102 write_nic_word(dev, 0x378, 0x0560);
2103 write_nic_word(dev, 0x37A, 0x0560);
2104 write_nic_word(dev, 0x37C, 0x00EC);
2105 // write_nic_word(dev, 0x37E, 0x00FE);//-edward
2106 write_nic_word(dev, 0x37E, 0x00EC);//+edward
2108 write_nic_dword(dev, RFTiming, 0x00004003);
2110 write_nic_byte(dev, 0x24E,0x01);
2119 GetSupportedWirelessMode8185(
2120 struct net_device *dev
2123 u8 btSupportedWirelessMode = 0;
2124 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2126 switch(priv->rf_chip)
2130 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
2133 btSupportedWirelessMode = WIRELESS_MODE_B;
2137 return btSupportedWirelessMode;
2141 ActUpdateChannelAccessSetting(
2142 struct net_device *dev,
2143 WIRELESS_MODE WirelessMode,
2144 PCHANNEL_ACCESS_SETTING ChnlAccessSetting
2147 struct r8180_priv *priv = ieee80211_priv(dev);
2148 struct ieee80211_device *ieee = priv->ieee80211;
2151 //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
2152 u8 bFollowLegacySetting = 0;
2157 // TODO: We still don't know how to set up these registers, just follow WMAC to
2158 // verify 8185B FPAG.
2161 // Jong said CWmin/CWmax register are not functional in 8185B,
2162 // so we shall fill channel access realted register into AC parameter registers,
2165 ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
2166 ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
2167 ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
2168 ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2169 ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
2170 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
2172 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
2173 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2174 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2176 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
2178 //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
2179 //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
2180 //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
2181 //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
2183 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
2185 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2188 // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2189 if( pStaQos->CurrentQosMode > QOS_DISABLE )
2191 if(pStaQos->QBssWirelessMode == WirelessMode)
2193 // Follow AC Parameters of the QBSS.
2194 for(eACI = 0; eACI < AC_MAX; eACI++)
2196 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2201 // Follow Default WMM AC Parameters.
2202 bFollowLegacySetting = 1;
2208 bFollowLegacySetting = 1;
2212 // this setting is copied from rtl8187B. xiong-2006-11-13
2213 if(bFollowLegacySetting)
2218 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2219 // 2005.12.01, by rcnjko.
2221 AcParam.longData = 0;
2222 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2223 AcParam.f.AciAifsn.f.ACM = 0;
2224 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2225 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2226 AcParam.f.TXOPLimit = 0;
2228 //lzm reserved 080826
2230 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2231 if( ieee->current_network.Turbo_Enable == 1 )
2232 AcParam.f.TXOPLimit = 0x01FF;
2233 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB)
2234 if (ieee->iw_mode == IW_MODE_ADHOC)
2235 AcParam.f.TXOPLimit = 0x0020;
2238 for(eACI = 0; eACI < AC_MAX; eACI++)
2240 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2242 PAC_PARAM pAcParam = (PAC_PARAM)(&AcParam);
2247 // Retrive paramters to udpate.
2248 eACI = pAcParam->f.AciAifsn.f.ACI;
2249 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2250 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
2251 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
2252 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
2253 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2258 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2262 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2266 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2270 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2274 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2279 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2280 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2282 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2283 AC_CODING eACI = pAciAifsn->f.ACI;
2286 //for 8187B AsynIORead issue
2288 u8 AcmCtrl = pHalData->AcmControl;
2292 if( pAciAifsn->f.ACM )
2297 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); // or 0x21
2301 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); // or 0x42
2305 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); // or 0x84
2309 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2318 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xDE
2322 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xBD
2326 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0x7B
2334 //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2337 pHalData->AcmControl = AcmCtrl;
2339 //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2340 write_nic_byte(dev, ACM_CONTROL, 0);
2350 ActSetWirelessMode8185(
2351 struct net_device *dev,
2355 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2356 struct ieee80211_device *ieee = priv->ieee80211;
2357 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
2358 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2360 if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2361 { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2362 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2363 btWirelessMode, btSupportedWirelessMode);
2367 // 1. Assign wireless mode to swtich if necessary.
2368 if (btWirelessMode == WIRELESS_MODE_AUTO)
2370 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2372 btWirelessMode = WIRELESS_MODE_A;
2374 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2376 btWirelessMode = WIRELESS_MODE_G;
2378 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2380 btWirelessMode = WIRELESS_MODE_B;
2384 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2385 btSupportedWirelessMode);
2386 btWirelessMode = WIRELESS_MODE_B;
2391 // 2. Swtich band: RF or BB specific actions,
2392 // for example, refresh tables in omc8255, or change initial gain if necessary.
2393 switch(priv->rf_chip)
2398 // Nothing to do for Zebra to switch band.
2399 // Update current wireless mode if we swtich to specified band successfully.
2400 ieee->mode = (WIRELESS_MODE)btWirelessMode;
2405 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2409 // 3. Change related setting.
2410 if( ieee->mode == WIRELESS_MODE_A ){
2411 DMESG("WIRELESS_MODE_A\n");
2413 else if( ieee->mode == WIRELESS_MODE_B ){
2414 DMESG("WIRELESS_MODE_B\n");
2416 else if( ieee->mode == WIRELESS_MODE_G ){
2417 DMESG("WIRELESS_MODE_G\n");
2420 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2423 void rtl8185b_irq_enable(struct net_device *dev)
2425 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2427 priv->irq_enabled = 1;
2428 write_nic_dword(dev, IMR, priv->IntrMask);
2430 //by amy for power save
2432 DrvIFIndicateDisassociation(
2433 struct net_device *dev,
2437 //printk("==> DrvIFIndicateDisassociation()\n");
2439 // nothing is needed after disassociation request.
2441 //printk("<== DrvIFIndicateDisassociation()\n");
2445 struct net_device *dev
2448 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2451 //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2453 DrvIFIndicateDisassociation(dev, unspec_reason);
2455 // PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2456 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55;
2458 priv->ieee80211->state = IEEE80211_NOLINK;
2462 // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2463 // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2464 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2466 // Disable Beacon Queue Own bit, suggested by jong
2467 // Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2468 ieee80211_stop_send_beacons(priv->ieee80211);
2470 priv->ieee80211->link_change(dev);
2471 notify_wx_assoc_event(priv->ieee80211);
2473 // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2475 if(pMgntInfo->bEnableSwBeaconTimer)
2477 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2478 // comment out by haich, 2007.10.01
2479 //#if DEV_BUS_TYPE==USB_INTERFACE
2480 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2485 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2489 MlmeDisassociateRequest(
2490 struct net_device *dev,
2495 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2498 SendDisassociation(priv->ieee80211, asSta, asRsn );
2500 if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2501 //ShuChen TODO: change media status.
2502 //ShuChen TODO: What to do when disassociate.
2503 DrvIFIndicateDisassociation(dev, unspec_reason);
2506 // pMgntInfo->AsocTimestamp = 0;
2507 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
2508 // pMgntInfo->mBrates.Length = 0;
2509 // Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2511 ieee80211_disassociate(priv->ieee80211);
2520 struct net_device *dev,
2524 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2527 // Commented out by rcnjko, 2005.01.27:
2528 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2530 // //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2531 // SecClearAllKeys(Adapter);
2533 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2535 if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2536 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key
2538 SecClearAllKeys(Adapter);
2539 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2542 // 2004.10.11, by rcnjko.
2543 //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2544 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2546 priv->ieee80211->state = IEEE80211_NOLINK;
2547 // pMgntInfo->AsocTimestamp = 0;
2551 struct net_device *dev,
2555 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2557 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2560 if(pMgntInfo->mPss != eAwake)
2563 // Using AwkaeTimer to prevent mismatch ps state.
2564 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2566 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2567 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2571 // Indication of disassociation event.
2572 //DrvIFIndicateDisassociation(Adapter, asRsn);
2573 if(IS_DOT11D_ENABLE(priv->ieee80211))
2574 Dot11d_Reset(priv->ieee80211);
2575 // In adhoc mode, update beacon frame.
2576 if( priv->ieee80211->state == IEEE80211_LINKED )
2578 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2580 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2581 //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2582 MgntDisconnectIBSS(dev);
2584 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2586 // We clear key here instead of MgntDisconnectAP() because that
2587 // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2588 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2589 // used to handle disassociation related things to AP, e.g. send Disassoc
2590 // frame to AP. 2005.01.27, by rcnjko.
2591 // SecClearAllKeys(Adapter);
2593 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2594 //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2595 MgntDisconnectAP(dev, asRsn);
2598 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2599 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2606 // Chang RF Power State.
2607 // Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2614 struct net_device *dev,
2615 RT_RF_POWER_STATE eRFPowerState
2618 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2619 bool bResult = false;
2621 // printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2622 if(eRFPowerState == priv->eRFPowerState)
2624 // printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2628 switch(priv->rf_chip)
2632 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2636 printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2639 // printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2644 HalEnableRx8185Dummy(
2645 struct net_device *dev
2650 HalDisableRx8185Dummy(
2651 struct net_device *dev
2657 MgntActSet_RF_State(
2658 struct net_device *dev,
2659 RT_RF_POWER_STATE StateToSet,
2663 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2664 bool bActionAllowed = false;
2665 bool bConnectBySSID = false;
2666 RT_RF_POWER_STATE rtState;
2667 u16 RFWaitCounter = 0;
2669 // printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2671 // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2672 // Only one thread can change the RF state at one time, and others should wait to be executed.
2677 // down(&priv->rf_state);
2678 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2679 if(priv->RFChangeInProgress)
2681 // printk("====================>haha111111111\n");
2682 // up(&priv->rf_state);
2683 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2684 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2685 // Set RF after the previous action is done.
2686 while(priv->RFChangeInProgress)
2689 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2690 udelay(1000); // 1 ms
2692 // Wait too long, return FALSE to avoid to be stuck here.
2693 if(RFWaitCounter > 1000) // 1sec
2695 // RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2696 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2697 // TODO: Reset RF state?
2704 // printk("========================>haha2\n");
2705 priv->RFChangeInProgress = true;
2706 // up(&priv->rf_state);
2707 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2712 rtState = priv->eRFPowerState;
2719 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2720 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2722 priv->RfOffReason &= (~ChangeSource);
2724 if(! priv->RfOffReason)
2726 priv->RfOffReason = 0;
2727 bActionAllowed = true;
2729 if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2731 bConnectBySSID = true;
2735 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2740 // 070125, rcnjko: we always keep connected in AP mode.
2742 if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2746 // Disconnect to current BSS when radio off. Asked by QuanTa.
2750 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2751 // because we do NOT need to set ssid to dummy ones.
2752 // Revised by Roger, 2007.12.04.
2754 MgntDisconnect( dev, disas_lv_ss );
2756 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2757 // 2007.05.28, by shien chang.
2758 // PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2759 // pMgntInfo->NumBssDesc = 0;
2760 // PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2761 // pMgntInfo->NumBssDesc4Query = 0;
2766 priv->RfOffReason |= ChangeSource;
2767 bActionAllowed = true;
2771 priv->RfOffReason |= ChangeSource;
2772 bActionAllowed = true;
2781 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2782 // Config HW to the specified mode.
2783 // printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2784 SetRFPowerState(dev, StateToSet);
2787 if(StateToSet == eRfOn)
2789 HalEnableRx8185Dummy(dev);
2792 // by amy not supported
2793 // MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2797 else if(StateToSet == eRfOff)
2799 HalDisableRx8185Dummy(dev);
2804 // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2807 // Release RF spinlock
2808 // down(&priv->rf_state);
2809 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2810 priv->RFChangeInProgress = false;
2811 // up(&priv->rf_state);
2812 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2813 // printk("<===MgntActSet_RF_State()\n");
2814 return bActionAllowed;
2818 struct net_device *dev
2821 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2825 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2826 // is really scheduled.
2827 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2828 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2829 // blocks the IPS procedure of switching RF.
2830 // By Bruce, 2007-12-25.
2832 priv->bSwRfProcessing = true;
2834 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2837 // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2842 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2843 (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2845 if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2846 pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2852 priv->bSwRfProcessing = false;
2857 // Enter the inactive power save mode. RF will be off
2858 // 2007.08.17, by shien chang.
2862 struct net_device *dev
2865 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2866 RT_RF_POWER_STATE rtState;
2867 //printk("==============================>enter IPS\n");
2868 if (priv->bInactivePs)
2870 rtState = priv->eRFPowerState;
2873 // Added by Bruce, 2007-12-25.
2874 // Do not enter IPS in the following conditions:
2875 // (1) RF is already OFF or Sleep
2876 // (2) bSwRfProcessing (indicates the IPS is still under going)
2877 // (3) Connectted (only disconnected can trigger IPS)
2878 // (4) IBSS (send Beacon)
2879 // (5) AP mode (send Beacon)
2881 if (rtState == eRfOn && !priv->bSwRfProcessing
2882 && (priv->ieee80211->state != IEEE80211_LINKED ))
2884 // printk("IPSEnter(): Turn off RF.\n");
2885 priv->eInactivePowerState = eRfOff;
2886 InactivePowerSave(dev);
2889 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2893 struct net_device *dev
2896 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2897 RT_RF_POWER_STATE rtState;
2898 //printk("===================================>leave IPS\n");
2899 if (priv->bInactivePs)
2901 rtState = priv->eRFPowerState;
2902 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2904 // printk("IPSLeave(): Turn on RF.\n");
2905 priv->eInactivePowerState = eRfOn;
2906 InactivePowerSave(dev);
2909 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2911 //by amy for power save
2912 void rtl8185b_adapter_start(struct net_device *dev)
2914 struct r8180_priv *priv = ieee80211_priv(dev);
2915 struct ieee80211_device *ieee = priv->ieee80211;
2917 u8 SupportedWirelessMode;
2918 u8 InitWirelessMode;
2919 u8 bInvalidWirelessMode = 0;
2927 //rtl8180_rtx_disable(dev);
2929 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2933 priv->dma_poll_mask = 0;
2934 priv->dma_poll_stop_mask = 0;
2936 //rtl8180_beacon_tx_disable(dev);
2938 HwConfigureRTL8185(dev);
2940 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2941 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2943 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link'
2945 //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M
2947 write_nic_word(dev, BcnItv, 100);
2948 write_nic_word(dev, AtimWnd, 2);
2950 //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2951 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2953 write_nic_byte(dev, WPA_CONFIG, 0);
2955 MacConfig_85BASIC(dev);
2957 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2958 // BT_DEMO_BOARD type
2959 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2961 //#ifdef CONFIG_RTL818X_S
2962 // for jong required
2963 // PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2967 //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2969 //-----------------------------------------------------------------------------
2970 // Set up PHY related.
2971 //-----------------------------------------------------------------------------
2972 // Enable Config3.PARAM_En to revise AnaaParm.
2973 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2975 tmpu8 = read_nic_byte(dev, CONFIG3);
2976 #ifdef CONFIG_RTL818X_S
2977 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2979 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En | CONFIG3_CLKRUN_En) );
2982 // Turn on Analog power.
2983 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2984 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2985 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2987 #ifdef CONFIG_RTL818X_S
2988 write_nic_word(dev, ANAPARAM3, 0x0010);
2990 write_nic_byte(dev, ANAPARAM3, 0x00);
2994 write_nic_byte(dev, CONFIG3, tmpu8);
2995 write_nic_byte(dev, CR9346, 0x00);
2996 //{by amy 080312 for led
2997 // enable EEM0 and EEM1 in 9346CR
2998 btCR9346 = read_nic_byte(dev, CR9346);
2999 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
3001 // B cut use LED1 to control HW RF on/off
3002 TmpU1b = read_nic_byte(dev, CONFIG5);
3003 TmpU1b = TmpU1b & ~BIT3;
3004 write_nic_byte(dev,CONFIG5, TmpU1b);
3006 // disable EEM0 and EEM1 in 9346CR
3007 btCR9346 &= ~(0xC0);
3008 write_nic_byte(dev, CR9346, btCR9346);
3010 //Enable Led (suggested by Jong)
3011 // B-cut RF Radio on/off 5e[3]=0
3012 btPSR = read_nic_byte(dev, PSR);
3013 write_nic_byte(dev, PSR, (btPSR | BIT3));
3014 //by amy 080312 for led}
3015 // setup initial timing for RFE.
3016 write_nic_word(dev, RFPinsOutput, 0x0480);
3017 SetOutputEnableOfRfPins(dev);
3018 write_nic_word(dev, RFPinsSelect, 0x2488);
3023 // We assume RegWirelessMode has already been initialized before,
3024 // however, we has to validate the wireless mode here and provide a reasonble
3025 // initialized value if necessary. 2005.01.13, by rcnjko.
3026 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
3027 if( (ieee->mode != WIRELESS_MODE_B) &&
3028 (ieee->mode != WIRELESS_MODE_G) &&
3029 (ieee->mode != WIRELESS_MODE_A) &&
3030 (ieee->mode != WIRELESS_MODE_AUTO))
3031 { // It should be one of B, G, A, or AUTO.
3032 bInvalidWirelessMode = 1;
3035 { // One of B, G, A, or AUTO.
3036 // Check if the wireless mode is supported by RF.
3037 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
3038 (ieee->mode & SupportedWirelessMode) == 0 )
3040 bInvalidWirelessMode = 1;
3044 if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
3045 { // Auto or other invalid value.
3046 // Assigne a wireless mode to initialize.
3047 if((SupportedWirelessMode & WIRELESS_MODE_A))
3049 InitWirelessMode = WIRELESS_MODE_A;
3051 else if((SupportedWirelessMode & WIRELESS_MODE_G))
3053 InitWirelessMode = WIRELESS_MODE_G;
3055 else if((SupportedWirelessMode & WIRELESS_MODE_B))
3057 InitWirelessMode = WIRELESS_MODE_B;
3061 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
3062 SupportedWirelessMode);
3063 InitWirelessMode = WIRELESS_MODE_B;
3066 // Initialize RegWirelessMode if it is not a valid one.
3067 if(bInvalidWirelessMode)
3069 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
3073 { // One of B, G, A.
3074 InitWirelessMode = ieee->mode;
3076 //by amy for power save
3078 // printk("initialize ENABLE_IPS\n");
3079 priv->eRFPowerState = eRfOff;
3080 priv->RfOffReason = 0;
3083 // u32 tmp = jiffies;
3084 MgntActSet_RF_State(dev, eRfOn, 0);
3086 // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3088 // DrvIFIndicateCurrentPhyStatus(priv);
3090 // If inactive power mode is enabled, disable rf while in disconnected state.
3091 // 2007.07.16, by shien chang.
3093 if (priv->bInactivePs)
3096 // u32 tmp = jiffies;
3097 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
3099 // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3104 //by amy for power save
3106 // Turn off RF if necessary. 2005.08.23, by rcnjko.
3107 // We shall turn off RF after setting CMDR, otherwise,
3108 // RF will be turnned on after we enable MAC Tx/Rx.
3109 if(Adapter->MgntInfo.RegRfOff == TRUE)
3111 SetRFPowerState8185(Adapter, RF_OFF);
3115 SetRFPowerState8185(Adapter, RF_ON);
3119 /* //these is equal with above TODO.
3120 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
3121 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
3122 RF_WriteReg(dev, 0x4, 0x9FF);
3123 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
3124 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
3125 write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
3126 write_nic_byte(dev, CR9346, 0x00);
3129 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
3131 //-----------------------------------------------------------------------------
3133 rtl8185b_irq_enable(dev);
3135 netif_start_queue(dev);
3140 void rtl8185b_rx_enable(struct net_device *dev)
3144 /* for now we accept data, management & ctl frame*/
3145 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3147 rxconf=read_nic_dword(dev,RX_CONF);
3148 rxconf = rxconf &~ MAC_FILTER_MASK;
3149 rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
3150 rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
3151 rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
3152 rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
3153 // rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3154 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3156 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3157 dev->flags & IFF_PROMISC){
3158 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3160 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
3161 if(priv->card_8185 == 0)
3162 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3165 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3166 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3167 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3170 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3171 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
3172 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
3173 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
3176 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3177 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3179 //if(!priv->card_8185){
3180 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
3181 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
3184 rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
3185 rxconf = rxconf &~ MAX_RX_DMA_MASK;
3186 rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
3188 //if(!priv->card_8185)
3189 rxconf = rxconf | RCR_ONLYERLPKT;
3191 rxconf = rxconf &~ RCR_CS_MASK;
3192 if(!priv->card_8185)
3193 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3194 // rxconf &=~ 0xfff00000;
3195 // rxconf |= 0x90100000;//9014f76f;
3196 write_nic_dword(dev, RX_CONF, rxconf);
3199 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3201 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3202 dev->flags & IFF_PROMISC){
3203 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3204 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3207 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3208 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3209 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3212 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3213 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3216 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3217 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3219 write_nic_dword(dev, RCR, priv->ReceiveConfig);
3224 DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3226 cmd=read_nic_byte(dev,CMD);
3227 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3231 void rtl8185b_tx_enable(struct net_device *dev)
3237 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3240 txconf= read_nic_dword(dev,TX_CONF);
3241 if(priv->card_8185){
3244 byte = read_nic_byte(dev,CW_CONF);
3245 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3246 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3247 write_nic_byte(dev, CW_CONF, byte);
3249 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3250 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3251 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3252 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3253 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3255 write_nic_word(dev, 0x5e, 0x01);
3256 force_pci_posting(dev);
3258 write_nic_word(dev, 0xfe, 0x10);
3259 force_pci_posting(dev);
3261 write_nic_word(dev, 0x5e, 0x00);
3262 force_pci_posting(dev);
3265 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3268 if(priv->card_8185){
3270 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3275 txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3277 txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3280 txconf = txconf &~ TX_LOOPBACK_MASK;
3281 txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3282 txconf = txconf &~ TCR_DPRETRY_MASK;
3283 txconf = txconf &~ TCR_RTSRETRY_MASK;
3284 txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3285 txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3286 txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3288 if(priv->card_8185){
3289 if(priv->hw_plcp_len)
3290 txconf = txconf &~ TCR_PLCP_LEN;
3292 txconf = txconf | TCR_PLCP_LEN;
3294 txconf = txconf &~ TCR_SAT;
3296 txconf = txconf &~ TCR_MXDMA_MASK;
3297 txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3298 txconf = txconf | TCR_CWMIN;
3299 txconf = txconf | TCR_DISCW;
3301 // if(priv->ieee80211->hw_wep)
3302 // txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3304 txconf=txconf | (1<<TX_NOICV_SHIFT);
3306 write_nic_dword(dev,TX_CONF,txconf);
3309 write_nic_dword(dev, TCR, priv->TransmitConfig);
3310 byte = read_nic_byte(dev, MSR);
3311 byte |= MSR_LINK_ENEDCA;
3312 write_nic_byte(dev, MSR, byte);
3317 DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3320 cmd=read_nic_byte(dev,CMD);
3321 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3323 //write_nic_dword(dev,TX_CONF,txconf);
3327 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3328 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3329 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);