SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28
  29 #include "r8180_pm.h"
  30
  31 #include "ieee80211/dot11d.h"
  32
  33
  34 //#define CONFIG_RTL8180_IO_MAP
  35
  36 #define TC_3W_POLL_MAX_TRY_CNT 5
  37 static u8 MAC_REG_TABLE[][2]={
  38                         //PAGA 0:
  39                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  40                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  41                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  42                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  43                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  44                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  45                         {0x94, 0x0F}, {0x95, 0x32},
  46                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  47                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  48                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  49                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  50                         {0xff, 0x00},
  51
  52                         //PAGE 1:
  53                         // For Flextronics system Logo PCIHCT failure:
  54                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  55                         {0x5e, 0x01},
  56                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  57                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  58                         {0x82, 0xFF}, {0x83, 0x03},
  59                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  60                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  61                         {0xe2, 0x00},
  62
  63
  64                         //PAGE 2:
  65                         {0x5e, 0x02},
  66                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  67                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  68                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  69                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  70                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  71                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  72                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  73
  74                         //PAGA 0:
  75                         {0x5e, 0x00},{0x9f, 0x03}
  76                 };
  77
  78
  79 static u8  ZEBRA_AGC[]={
  80                         0,
  81                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  82                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  83                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  84                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  85                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  86                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  87                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  88                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  89                         };
  90
  91 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  92                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  93                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  94                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  95                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
  96                         0x0183,0x0163,0x0143,0x0123,0x0103
  97         };
  98
  99 static u8 OFDM_CONFIG[]={
 100                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 101                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 102                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 103
 104                         // 0x00
 105                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 106                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 107                         // 0x10
 108                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 109                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 110                         // 0x20
 111                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 112                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 113                         // 0x30
 114                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 115                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 116                 };
 117
 118 /*---------------------------------------------------------------
 119   * Hardware IO
 120   * the code is ported from Windows source code
 121   ----------------------------------------------------------------*/
 122
 123 void
 124 PlatformIOWrite1Byte(
 125         struct net_device *dev,
 126         u32             offset,
 127         u8              data
 128         )
 129 {
 130         write_nic_byte(dev, offset, data);
 131         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 132
 133 }
 134
 135 void
 136 PlatformIOWrite2Byte(
 137         struct net_device *dev,
 138         u32             offset,
 139         u16             data
 140         )
 141 {
 142         write_nic_word(dev, offset, data);
 143         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 144
 145
 146 }
 147 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 148
 149 void
 150 PlatformIOWrite4Byte(
 151         struct net_device *dev,
 152         u32             offset,
 153         u32             data
 154         )
 155 {
 156 //{by amy 080312
 157 if (offset == PhyAddr)
 158         {//For Base Band configuration.
 159                 unsigned char   cmdByte;
 160                 unsigned long   dataBytes;
 161                 unsigned char   idx;
 162                 u8      u1bTmp;
 163
 164                 cmdByte = (u8)(data & 0x000000ff);
 165                 dataBytes = data>>8;
 166
 167                 //
 168                 // 071010, rcnjko:
 169                 // The critical section is only BB read/write race condition.
 170                 // Assumption:
 171                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 172                 // acquiring the spinlock in such context.
 173                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 174                 //
 175 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 176
 177                 for(idx = 0; idx < 30; idx++)
 178                 { // Make sure command bit is clear before access it.
 179                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 180                         if((u1bTmp & BIT7) == 0)
 181                                 break;
 182                         else
 183                                 mdelay(10);
 184                 }
 185
 186                 for(idx=0; idx < 3; idx++)
 187                 {
 188                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 189                 }
 190                 write_nic_byte(dev, offset, cmdByte);
 191
 192 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 193         }
 194 //by amy 080312}
 195         else{
 196                 write_nic_dword(dev, offset, data);
 197                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 198         }
 199 }
 200
 201 u8
 202 PlatformIORead1Byte(
 203         struct net_device *dev,
 204         u32             offset
 205         )
 206 {
 207         u8      data = 0;
 208
 209         data = read_nic_byte(dev, offset);
 210
 211
 212         return data;
 213 }
 214
 215 u16
 216 PlatformIORead2Byte(
 217         struct net_device *dev,
 218         u32             offset
 219         )
 220 {
 221         u16     data = 0;
 222
 223         data = read_nic_word(dev, offset);
 224
 225
 226         return data;
 227 }
 228
 229 u32
 230 PlatformIORead4Byte(
 231         struct net_device *dev,
 232         u32             offset
 233         )
 234 {
 235         u32     data = 0;
 236
 237         data = read_nic_dword(dev, offset);
 238
 239
 240         return data;
 241 }
 242
 243 void
 244 SetOutputEnableOfRfPins(
 245         struct net_device *dev
 246         )
 247 {
 248         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 249
 250         switch(priv->rf_chip)
 251         {
 252         case RFCHIPID_RTL8225:
 253         case RF_ZEBRA2:
 254         case RF_ZEBRA4:
 255                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 256                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 257                 break;
 258         }
 259 }
 260
 261 void
 262 ZEBRA_RFSerialWrite(
 263         struct net_device *dev,
 264         u32                     data2Write,
 265         u8                      totalLength,
 266         u8                      low2high
 267         )
 268 {
 269         ThreeWireReg            twreg;
 270         int                             i;
 271         u16                             oval,oval2,oval3;
 272         u32                             mask;
 273         u16                             UshortBuffer;
 274
 275         u8                      u1bTmp;
 276         // RTL8187S HSSI Read/Write Function
 277         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 278         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 279         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 280         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 281         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 282
 283         oval2 = read_nic_word(dev, RFPinsEnable);
 284         oval3 = read_nic_word(dev, RFPinsSelect);
 285
 286         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 287         oval3 &= 0xfff8;
 288
 289         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 290         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 291         udelay(10);
 292
 293         // Add this to avoid hardware and software 3-wire conflict.
 294         // 2005.03.01, by rcnjko.
 295         twreg.longData = 0;
 296         twreg.struc.enableB = 1;
 297         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 298         udelay(2);
 299         twreg.struc.enableB = 0;
 300         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 301         udelay(10);
 302
 303         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 304
 305         for(i=0; i<totalLength/2; i++)
 306         {
 307                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 308                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 309                 twreg.struc.clk = 1;
 310                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 311                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 312
 313                 mask = (low2high)?(mask<<1):(mask>>1);
 314                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 315                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 316                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 317                 twreg.struc.clk = 0;
 318                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 319                 mask = (low2high)?(mask<<1):(mask>>1);
 320         }
 321
 322         twreg.struc.enableB = 1;
 323         twreg.struc.clk = 0;
 324         twreg.struc.data = 0;
 325         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 326         udelay(10);
 327
 328         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 329         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 330
 331         SetOutputEnableOfRfPins(dev);
 332 }
 333 //by amy
 334
 335
 336 int
 337 HwHSSIThreeWire(
 338         struct net_device *dev,
 339         u8                      *pDataBuf,
 340         u8                      nDataBufBitCnt,
 341         int                     bSI,
 342         int                     bWrite
 343         )
 344 {
 345         int     bResult = 1;
 346         u8      TryCnt;
 347         u8      u1bTmp;
 348
 349         do
 350         {
 351                 // Check if WE and RE are cleared.
 352                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 353                 {
 354                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 355                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 356                         {
 357                                 break;
 358                         }
 359                         udelay(10);
 360                 }
 361                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 362                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 363
 364                 // RTL8187S HSSI Read/Write Function
 365                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 366
 367                 if(bSI)
 368                 {
 369                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 370                 }else
 371                 {
 372                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 373                 }
 374
 375                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 376
 377                 if(bSI)
 378                 {
 379                         // jong: HW SI read must set reg84[3]=0.
 380                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 381                         u1bTmp &= ~BIT3;
 382                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 383                 }
 384                 // Fill up data buffer for write operation.
 385
 386                 if(bWrite)
 387                 {
 388                         if(nDataBufBitCnt == 16)
 389                         {
 390                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 391                         }
 392                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 393                         {
 394                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 395                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 396                         }
 397                         else
 398                         {
 399                                 int idx;
 400                                 int ByteCnt = nDataBufBitCnt / 8;
 401                                 //printk("%d\n",nDataBufBitCnt);
 402                                 if ((nDataBufBitCnt % 8) != 0)
 403                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 404                                 nDataBufBitCnt);
 405
 406                                if (nDataBufBitCnt > 64)
 407                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 408                                 nDataBufBitCnt);
 409
 410                                 for(idx = 0; idx < ByteCnt; idx++)
 411                                 {
 412                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 413                                 }
 414                         }
 415                 }
 416                 else            //read
 417                 {
 418                         if(bSI)
 419                         {
 420                                 // SI - reg274[3:0] : RF register's Address
 421                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 422                         }
 423                         else
 424                         {
 425                                 // PI - reg274[15:12] : RF register's Address
 426                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 427                         }
 428                 }
 429
 430                 // Set up command: WE or RE.
 431                 if(bWrite)
 432                 {
 433                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 434                 }
 435                 else
 436                 {
 437                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 438                 }
 439
 440                 // Check if DONE is set.
 441                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 442                 {
 443                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 444                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 445                         {
 446                                 break;
 447                         }
 448                         udelay(10);
 449                 }
 450
 451                 write_nic_byte(dev, SW_3W_CMD1, 0);
 452
 453                 // Read back data for read operation.
 454                 if(bWrite == 0)
 455                 {
 456                         if(bSI)
 457                         {
 458                                 //Serial Interface : reg363_362[11:0]
 459                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 460                         }
 461                         else
 462                         {
 463                                 //Parallel Interface : reg361_360[11:0]
 464                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 465                         }
 466
 467                         *((u16*)pDataBuf) &= 0x0FFF;
 468                 }
 469
 470         }while(0);
 471
 472         return bResult;
 473 }
 474 //by amy
 475
 476 int
 477 HwThreeWire(
 478         struct net_device *dev,
 479         u8                      *pDataBuf,
 480         u8                      nDataBufBitCnt,
 481         int                     bHold,
 482         int                     bWrite
 483         )
 484 {
 485         int     bResult = 1;
 486         u8      TryCnt;
 487         u8      u1bTmp;
 488
 489         do
 490         {
 491                 // Check if WE and RE are cleared.
 492                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 493                 {
 494                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 495                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 496                         {
 497                                 break;
 498                         }
 499                         udelay(10);
 500                 }
 501                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 502                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 503
 504                 // Fill up data buffer for write operation.
 505                 if(nDataBufBitCnt == 16)
 506                 {
 507                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 508                 }
 509                 else if(nDataBufBitCnt == 64)
 510                 {
 511                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 512                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 513                 }
 514                 else
 515                 {
 516                         int idx;
 517                         int ByteCnt = nDataBufBitCnt / 8;
 518
 519                         if ((nDataBufBitCnt % 8) != 0)
 520                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 521                                 nDataBufBitCnt);
 522
 523                         if (nDataBufBitCnt > 64)
 524                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 525                                 nDataBufBitCnt);
 526
 527                         for(idx = 0; idx < ByteCnt; idx++)
 528                         {
 529                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 530                         }
 531                 }
 532
 533                 // Fill up length field.
 534                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 535                 if(bHold)
 536                         u1bTmp |= SW_3W_CMD0_HOLD;
 537                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 538
 539                 // Set up command: WE or RE.
 540                 if(bWrite)
 541                 {
 542                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 543                 }
 544                 else
 545                 {
 546                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 547                 }
 548
 549                 // Check if WE and RE are cleared and DONE is set.
 550                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 551                 {
 552                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 553                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 554                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 555                         {
 556                                 break;
 557                         }
 558                         udelay(10);
 559                 }
 560                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 561                 {
 562                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 563                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 564                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 565                         write_nic_byte(dev, SW_3W_CMD1, 0);
 566                 }
 567
 568                 // Read back data for read operation.
 569                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 570                 if(bWrite == 0)
 571                 {
 572                         if(nDataBufBitCnt == 16)
 573                         {
 574                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 575                         }
 576                         else if(nDataBufBitCnt == 64)
 577                         {
 578                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 579                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 580                         }
 581                         else
 582                         {
 583                                 int idx;
 584                                 int ByteCnt = nDataBufBitCnt / 8;
 585
 586                                 if ((nDataBufBitCnt % 8) != 0)
 587                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 588                                         nDataBufBitCnt);
 589
 590                                 if (nDataBufBitCnt > 64)
 591                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 592                                         nDataBufBitCnt);
 593
 594                                 for(idx = 0; idx < ByteCnt; idx++)
 595                                 {
 596                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 597                                 }
 598                         }
 599                 }
 600
 601         }while(0);
 602
 603         return bResult;
 604 }
 605
 606
 607 void
 608 RF_WriteReg(
 609         struct net_device *dev,
 610         u8              offset,
 611         u32             data
 612         )
 613 {
 614         //RFReg                 reg;
 615         u32                     data2Write;
 616         u8                      len;
 617         u8                      low2high;
 618         //u32                   RF_Read = 0;
 619         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 620
 621
 622         switch(priv->rf_chip)
 623         {
 624         case RFCHIPID_RTL8225:
 625         case RF_ZEBRA2:         // Annie 2006-05-12.
 626         case RF_ZEBRA4:        //by amy
 627                 switch(priv->RegThreeWireMode)
 628                 {
 629                 case SW_THREE_WIRE:
 630                         { // Perform SW 3-wire programming by driver.
 631                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 632                                 len = 16;
 633                                 low2high = 0;
 634                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 635                         }
 636                         break;
 637
 638                 case HW_THREE_WIRE:
 639                         { // Pure HW 3-wire.
 640                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 641                                 len = 16;
 642                                 HwThreeWire(
 643                                         dev,
 644                                         (u8 *)(&data2Write),    // pDataBuf,
 645                                         len,                            // nDataBufBitCnt,
 646                                         0,                                      // bHold,
 647                                         1);                                     // bWrite
 648                         }
 649                         break;
 650                         case HW_THREE_WIRE_PI: //Parallel Interface
 651                         { // Pure HW 3-wire.
 652                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 653                                 len = 16;
 654                                         HwHSSIThreeWire(
 655                                                 dev,
 656                                                 (u8*)(&data2Write),     // pDataBuf,
 657                                                 len,                                            // nDataBufBitCnt,
 658                                                 0,                                      // bSI
 659                                                 1);                                     // bWrite
 660
 661                                 //printk("33333\n");
 662                         }
 663                         break;
 664
 665                         case HW_THREE_WIRE_SI: //Serial Interface
 666                         { // Pure HW 3-wire.
 667                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 668                                 len = 16;
 669 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 670 //                                low2high = 0;
 671 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 672
 673                                 HwHSSIThreeWire(
 674                                         dev,
 675                                         (u8*)(&data2Write),     // pDataBuf,
 676                                         len,                                            // nDataBufBitCnt,
 677                                         1,                                      // bSI
 678                                         1);                                     // bWrite
 679
 680 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 681                         }
 682                         break;
 683
 684
 685                 default:
 686                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 687                         break;
 688                 }
 689                 break;
 690
 691         default:
 692                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 693                 break;
 694         }
 695 }
 696
 697
 698 void
 699 ZEBRA_RFSerialRead(
 700         struct net_device *dev,
 701         u32             data2Write,
 702         u8              wLength,
 703         u32             *data2Read,
 704         u8              rLength,
 705         u8              low2high
 706         )
 707 {
 708         ThreeWireReg    twreg;
 709         int                             i;
 710         u16                     oval,oval2,oval3,tmp, wReg80;
 711         u32                     mask;
 712         u8                      u1bTmp;
 713         ThreeWireReg    tdata;
 714         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 715         { // RTL8187S HSSI Read/Write Function
 716                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 717                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 718                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 719         }
 720
 721         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 722         oval2 = read_nic_word(dev, RFPinsEnable);
 723         oval3 = read_nic_word(dev, RFPinsSelect);
 724
 725         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 726         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 727
 728         *data2Read = 0;
 729
 730         // We must clear BIT0-3 here, otherwise,
 731         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 732         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 733         oval &= ~0xf;
 734
 735         // Avoid collision with hardware three-wire.
 736         twreg.longData = 0;
 737         twreg.struc.enableB = 1;
 738         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 739
 740         twreg.longData = 0;
 741         twreg.struc.enableB = 0;
 742         twreg.struc.clk = 0;
 743         twreg.struc.read_write = 0;
 744         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 745
 746         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 747         for(i = 0; i < wLength/2; i++)
 748         {
 749                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 750                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 751                 twreg.struc.clk = 1;
 752                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 753                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 754
 755                 mask = (low2high) ? (mask<<1): (mask>>1);
 756
 757                 if(i == 2)
 758                 {
 759                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 760                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 761                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 762
 763                         twreg.struc.read_write=1;
 764                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 765                         twreg.struc.clk = 0;
 766                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 767                         break;
 768                 }
 769                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 770                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 771                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 772
 773                 twreg.struc.clk = 0;
 774                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 775
 776                 mask = (low2high) ? (mask<<1) : (mask>>1);
 777         }
 778
 779         twreg.struc.clk = 0;
 780         twreg.struc.data = 0;
 781         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 782         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 783
 784         //
 785         // 061016, by rcnjko:
 786         // We must set data pin to HW controled, otherwise RF can't driver it and
 787         // value RF register won't be able to read back properly.
 788         //
 789         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 790
 791         for(i = 0; i < rLength; i++)
 792         {
 793                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 794                 twreg.struc.clk = 1;
 795                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 796                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 797                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 798                 tmp = read_nic_word(dev, RFPinsInput);
 799                 tdata.longData = tmp;
 800                 *data2Read |= tdata.struc.clk ? mask : 0;
 801
 802                 twreg.struc.clk = 0;
 803                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 804
 805                 mask = (low2high) ? (mask<<1) : (mask>>1);
 806         }
 807         twreg.struc.enableB = 1;
 808         twreg.struc.clk = 0;
 809         twreg.struc.data = 0;
 810         twreg.struc.read_write = 1;
 811         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 812
 813         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 814         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 815         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 816         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 817         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 818         write_nic_word(dev, RFPinsOutput, 0x3a0);
 819         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 820 }
 821
 822
 823 u32
 824 RF_ReadReg(
 825         struct net_device *dev,
 826         u8              offset
 827         )
 828 {
 829         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 830         u32                     data2Write;
 831         u8                      wlen;
 832         u8                      rlen;
 833         u8                      low2high;
 834         u32                     dataRead;
 835
 836         switch(priv->rf_chip)
 837         {
 838         case RFCHIPID_RTL8225:
 839         case RF_ZEBRA2:
 840         case RF_ZEBRA4:
 841                 switch(priv->RegThreeWireMode)
 842                 {
 843                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
 844                         {
 845                                 data2Write = ((u32)(offset&0x0f));
 846                                 wlen=16;
 847                                 HwHSSIThreeWire(
 848                                         dev,
 849                                         (u8*)(&data2Write),     // pDataBuf,
 850                                         wlen,                                   // nDataBufBitCnt,
 851                                         0,                                      // bSI
 852                                         0);                                     // bWrite
 853                                 dataRead= data2Write;
 854                         }
 855                         break;
 856
 857                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
 858                         {
 859                                 data2Write = ((u32)(offset&0x0f)) ;
 860                                 wlen=16;
 861                                 HwHSSIThreeWire(
 862                                         dev,
 863                                         (u8*)(&data2Write),     // pDataBuf,
 864                                         wlen,                                   // nDataBufBitCnt,
 865                                         1,                                      // bSI
 866                                         0                                       // bWrite
 867                                         );
 868                                 dataRead= data2Write;
 869                         }
 870                         break;
 871
 872                         // Perform SW 3-wire programming by driver.
 873                         default:
 874                         {
 875                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
 876                                 wlen = 6;
 877                                 rlen = 12;
 878                                 low2high = 0;
 879                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
 880                         }
 881                         break;
 882                 }
 883                 break;
 884         default:
 885                 dataRead = 0;
 886                 break;
 887         }
 888
 889         return dataRead;
 890 }
 891
 892
 893 // by Owen on 04/07/14 for writing BB register successfully
 894 void
 895 WriteBBPortUchar(
 896         struct net_device *dev,
 897         u32             Data
 898         )
 899 {
 900         //u8    TimeoutCounter;
 901         u8      RegisterContent;
 902         u8      UCharData;
 903
 904         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 905         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 906         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
 907         {
 908                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 909                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 910                 //if(UCharData == RegisterContent)
 911                 //      break;
 912         }
 913 }
 914
 915 u8
 916 ReadBBPortUchar(
 917         struct net_device *dev,
 918         u32             addr
 919         )
 920 {
 921         //u8    TimeoutCounter;
 922         u8      RegisterContent;
 923
 924         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 925         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 926
 927         return RegisterContent;
 928 }
 929 //{by amy 080312
 930 //
 931 //      Description:
 932 //              Perform Antenna settings with antenna diversity on 87SE.
 933 //    Created by Roger, 2008.01.25.
 934 //
 935 bool
 936 SetAntennaConfig87SE(
 937         struct net_device *dev,
 938         u8                      DefaultAnt,             // 0: Main, 1: Aux.
 939         bool            bAntDiversity   // 1:Enable, 0: Disable.
 940 )
 941 {
 942         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 943         bool   bAntennaSwitched = true;
 944
 945         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
 946
 947         // Threshold for antenna diversity.
 948         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
 949
 950         if( bAntDiversity )  //  Enable Antenna Diversity.
 951         {
 952                 if( DefaultAnt == 1 )  // aux antenna
 953                 {
 954                         // Mac register, aux antenna
 955                         write_nic_byte(dev, ANTSEL, 0x00);
 956
 957                         // Config CCK RX antenna.
 958                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 959                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 960
 961                         // Config OFDM RX antenna.
 962                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 963                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 964                 }
 965                 else //  use main antenna
 966                 {
 967                         // Mac register, main antenna
 968                         write_nic_byte(dev, ANTSEL, 0x03);
 969                         //base band
 970                         // Config CCK RX antenna.
 971                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 972                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 973
 974                         // Config OFDM RX antenna.
 975                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
 976                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 977                 }
 978         }
 979         else   // Disable Antenna Diversity.
 980         {
 981                 if( DefaultAnt == 1 ) // aux Antenna
 982                 {
 983                         // Mac register, aux antenna
 984                         write_nic_byte(dev, ANTSEL, 0x00);
 985
 986                         // Config CCK RX antenna.
 987                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 988                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 989
 990                         // Config OFDM RX antenna.
 991                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 992                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 993                 }
 994                 else // main Antenna
 995                 {
 996                         // Mac register, main antenna
 997                         write_nic_byte(dev, ANTSEL, 0x03);
 998
 999                         // Config CCK RX antenna.
1000                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1001                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1002
1003                         // Config OFDM RX antenna.
1004                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1005                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1006                 }
1007         }
1008         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1009         return  bAntennaSwitched;
1010 }
1011 //by amy 080312
1012 /*---------------------------------------------------------------
1013   * Hardware Initialization.
1014   * the code is ported from Windows source code
1015   ----------------------------------------------------------------*/
1016
1017 void
1018 ZEBRA_Config_85BASIC_HardCode(
1019         struct net_device *dev
1020         )
1021 {
1022
1023         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1024         u32                     i;
1025         u32     addr,data;
1026         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1027        u8                       u1b24E;
1028
1029
1030         //=============================================================================
1031         // 87S_PCIE :: RADIOCFG.TXT
1032         //=============================================================================
1033
1034
1035         // Page1 : reg16-reg30
1036         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1037         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1038         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1039
1040         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1041                 priv->card_8185 = VERSION_8187S_D;
1042
1043         // Page0 : reg0-reg15
1044
1045 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1046         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1047
1048         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1049
1050 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1051         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1052
1053 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1054         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1055
1056         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1057         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1058         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1059         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1060         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1061         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1062         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1063         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1064         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1065         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1066         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1067         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1068
1069
1070         // Page1 : reg16-reg30
1071         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1072
1073         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1074
1075         if(priv->card_8185 < VERSION_8187S_C)
1076         {
1077                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1078                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1079                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1080         }
1081         else
1082         {
1083                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1084                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1085                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1086         }
1087
1088
1089         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1090 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1091 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1092 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1093         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1094         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1095
1096         if(priv->card_8185 == VERSION_8187S_D)
1097         {
1098                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1099                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1100                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1101         }
1102         else
1103         {
1104                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1105                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1106                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1107         }
1108
1109         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1110
1111 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1112         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1113
1114         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1115         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1116         for(i=0;i<=36;i++)
1117         {
1118                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1119                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1120                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1121         }
1122
1123         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1124         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1125         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1126
1127         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1128         mdelay(10);     // Deay 10 ms. //0xfd
1129
1130 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1131         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1132         //mdelay(10);   // Deay 10 ms. //0xfd
1133
1134         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1135         mdelay(10);     // Deay 10 ms. //0xfd
1136
1137         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1138         mdelay(10);     // Deay 10 ms. //0xfd
1139
1140         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1141         mdelay(10);     // Deay 10 ms. //0xfd
1142
1143         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1144         mdelay(10);     // Deay 10 ms. //0xfd
1145
1146         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1147         mdelay(200);    // Deay 200 ms. //0xfd
1148         mdelay(10);     // Deay 10 ms. //0xfd
1149         mdelay(10);     // Deay 10 ms. //0xfd
1150
1151         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1152         mdelay(10);     // Deay 10 ms. //0xfd
1153
1154         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1155         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1156         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1157         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1158
1159         // DAC calibration off 20070702
1160         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1161         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1162 //{by amy 080312
1163         // For crystal calibration, added by Roger, 2007.12.11.
1164         if( priv->bXtalCalibration ) // reg 30.
1165         { // enable crystal calibration.
1166                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1167                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1168                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1169                 // So we should minus 4 BITs offset.
1170                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1171                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1172                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1173         }
1174         else
1175         { // using default value. Xin=6, Xout=6.
1176                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1177         }
1178 //by amy 080312
1179 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1180
1181         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1182 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1183         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1184         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1185         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1186         mdelay(10);     // Deay 10 ms. //0xfe
1187         mdelay(10);     // Deay 10 ms. //0xfe
1188         mdelay(10);     // Deay 10 ms. //0xfe
1189         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1190         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1191         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1192
1193         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1194         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1195         //power save parameters.
1196         u1b24E = read_nic_byte(dev, 0x24E);
1197         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1198
1199         //=============================================================================
1200
1201         //=============================================================================
1202         // CCKCONF.TXT
1203         //=============================================================================
1204
1205         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1206                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1207                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1208                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1209                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1210                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1211         */
1212
1213         write_phy_cck(dev,0x00,0xc8);
1214         write_phy_cck(dev,0x06,0x1c);
1215         write_phy_cck(dev,0x10,0x78);
1216         write_phy_cck(dev,0x2e,0xd0);
1217         write_phy_cck(dev,0x2f,0x06);
1218         write_phy_cck(dev,0x01,0x46);
1219
1220         // power control
1221         write_nic_byte(dev, CCK_TXAGC, 0x10);
1222         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1223         write_nic_byte(dev, ANTSEL, 0x03);
1224
1225
1226
1227         //=============================================================================
1228         // AGC.txt
1229         //=============================================================================
1230
1231 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1232         write_phy_ofdm(dev, 0x00, 0x12);
1233         //WriteBBPortUchar(dev, 0x00001280);
1234
1235         for (i=0; i<128; i++)
1236         {
1237                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1238
1239                 data = ZEBRA_AGC[i+1];
1240                 data = data << 8;
1241                 data = data | 0x0000008F;
1242
1243                 addr = i + 0x80; //enable writing AGC table
1244                 addr = addr << 8;
1245                 addr = addr | 0x0000008E;
1246
1247                 WriteBBPortUchar(dev, data);
1248                 WriteBBPortUchar(dev, addr);
1249                 WriteBBPortUchar(dev, 0x0000008E);
1250         }
1251
1252         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1253         //WriteBBPortUchar(dev, 0x00001080);
1254
1255         //=============================================================================
1256
1257         //=============================================================================
1258         // OFDMCONF.TXT
1259         //=============================================================================
1260
1261         for(i=0; i<60; i++)
1262         {
1263                 u4bRegOffset=i;
1264                 u4bRegValue=OFDM_CONFIG[i];
1265
1266                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1267
1268                 WriteBBPortUchar(dev,
1269                                                 (0x00000080 |
1270                                                 (u4bRegOffset & 0x7f) |
1271                                                 ((u4bRegValue & 0xff) << 8)));
1272         }
1273
1274         //=============================================================================
1275 //by amy for antenna
1276         //=============================================================================
1277 //{by amy 080312
1278         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1279         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1280 //by amy 080312}
1281 //by amy for antenna
1282 }
1283
1284
1285 void
1286 UpdateInitialGain(
1287         struct net_device *dev
1288         )
1289 {
1290         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1291         //unsigned char* IGTable;
1292         //u8                    DIG_CurrentInitialGain = 4;
1293         //unsigned char u1Tmp;
1294
1295         //lzm add 080826
1296         if(priv->eRFPowerState != eRfOn)
1297         {
1298                 //Don't access BB/RF under disable PLL situation.
1299                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1300                 // Back to the original state
1301                 priv->InitialGain= priv->InitialGainBackUp;
1302                 return;
1303         }
1304
1305         switch(priv->rf_chip)
1306         {
1307         case RF_ZEBRA4:
1308                 // Dynamic set initial gain, follow 87B
1309                 switch(priv->InitialGain)
1310                 {
1311                         case 1: //m861dBm
1312                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1313                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1314                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1315                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1316                                 break;
1317
1318                         case 2: //m862dBm
1319                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1320                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1321                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1322                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1323                                 break;
1324
1325                         case 3: //m863dBm
1326                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1327                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1328                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1329                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1330                                 break;
1331
1332                         case 4: //m864dBm
1333                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1334                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1335                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1336                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1337                                 break;
1338
1339                         case 5: //m82dBm
1340                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1341                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1342                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1343                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1344                                 break;
1345
1346                         case 6: //m78dBm
1347                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1348                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1349                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1350                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1351                                 break;
1352
1353                         case 7: //m74dBm
1354                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1355                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1356                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1357                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1358                                 break;
1359
1360                         case 8:
1361                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1362                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1363                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1364                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1365                                 break;
1366
1367
1368                         default:        //MP
1369                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1370                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1371                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1372                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1373                                 break;
1374                 }
1375                 break;
1376
1377
1378         default:
1379                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1380                 break;
1381         }
1382 }
1383 //
1384 //      Description:
1385 //              Tx Power tracking mechanism routine on 87SE.
1386 //      Created by Roger, 2007.12.11.
1387 //
1388 void
1389 InitTxPwrTracking87SE(
1390         struct net_device *dev
1391 )
1392 {
1393         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1394         u32     u4bRfReg;
1395
1396         u4bRfReg = RF_ReadReg(dev, 0x02);
1397
1398         // Enable Thermal meter indication.
1399         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1400         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1401 }
1402
1403 void
1404 PhyConfig8185(
1405         struct net_device *dev
1406         )
1407 {
1408         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1409        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1410            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1411         // RF config
1412         switch(priv->rf_chip)
1413         {
1414         case RF_ZEBRA2:
1415         case RF_ZEBRA4:
1416                 ZEBRA_Config_85BASIC_HardCode( dev);
1417                 break;
1418         }
1419 //{by amy 080312
1420         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1421         if(priv->bDigMechanism)
1422         {
1423                 if(priv->InitialGain == 0)
1424                         priv->InitialGain = 4;
1425                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1426         }
1427
1428         //
1429         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1430         // We initialize thermal meter here to avoid unsuccessful configuration.
1431         // Added by Roger, 2007.12.11.
1432         //
1433         if(priv->bTxPowerTrack)
1434                 InitTxPwrTracking87SE(dev);
1435
1436 //by amy 080312}
1437         priv->InitialGainBackUp= priv->InitialGain;
1438         UpdateInitialGain(dev);
1439
1440         return;
1441 }
1442
1443
1444
1445
1446 void
1447 HwConfigureRTL8185(
1448                 struct net_device *dev
1449                 )
1450 {
1451         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1452 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1453         u8              bUNIVERSAL_CONTROL_RL = 0;
1454
1455         u8              bUNIVERSAL_CONTROL_AGC = 1;
1456         u8              bUNIVERSAL_CONTROL_ANT = 1;
1457         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1458         u8              val8;
1459         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1460         //struct ieee80211_device *ieee = priv->ieee80211;
1461         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1462 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1463 //      {
1464 //              write_nic_word(dev, BRSR, 0xffff);
1465 //      }
1466 //      else
1467 //      {
1468 //              write_nic_word(dev, BRSR, 0x000f);
1469 //      }
1470 //by amy 080312}
1471         write_nic_word(dev, BRSR, 0x0fff);
1472         // Retry limit
1473         val8 = read_nic_byte(dev, CW_CONF);
1474
1475         if(bUNIVERSAL_CONTROL_RL)
1476                 val8 = val8 & 0xfd;
1477         else
1478                 val8 = val8 | 0x02;
1479
1480         write_nic_byte(dev, CW_CONF, val8);
1481
1482         // Tx AGC
1483         val8 = read_nic_byte(dev, TXAGC_CTL);
1484         if(bUNIVERSAL_CONTROL_AGC)
1485         {
1486                 write_nic_byte(dev, CCK_TXAGC, 128);
1487                 write_nic_byte(dev, OFDM_TXAGC, 128);
1488                 val8 = val8 & 0xfe;
1489         }
1490         else
1491         {
1492                 val8 = val8 | 0x01 ;
1493         }
1494
1495
1496         write_nic_byte(dev, TXAGC_CTL, val8);
1497
1498         // Tx Antenna including Feedback control
1499         val8 = read_nic_byte(dev, TXAGC_CTL );
1500
1501         if(bUNIVERSAL_CONTROL_ANT)
1502         {
1503                 write_nic_byte(dev, ANTSEL, 0x00);
1504                 val8 = val8 & 0xfd;
1505         }
1506         else
1507         {
1508                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1509         }
1510
1511         write_nic_byte(dev, TXAGC_CTL, val8);
1512
1513         // Auto Rate fallback control
1514         val8 = read_nic_byte(dev, RATE_FALLBACK);
1515         val8 &= 0x7c;
1516         if( bAUTO_RATE_FALLBACK_CTL )
1517         {
1518                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1519
1520                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1521                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1522 //by amy
1523                 // Aadded by Roger, 2007.11.15.
1524                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1525 //by amy
1526         }
1527         else
1528         {
1529         }
1530         write_nic_byte(dev, RATE_FALLBACK, val8);
1531 }
1532
1533
1534
1535 static void
1536 MacConfig_85BASIC_HardCode(
1537         struct net_device *dev)
1538 {
1539         //============================================================================
1540         // MACREG.TXT
1541         //============================================================================
1542         int                     nLinesRead = 0;
1543
1544         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1545         int     i;
1546
1547         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1548
1549         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1550         {
1551                 u4bRegOffset=MAC_REG_TABLE[i][0];
1552                 u4bRegValue=MAC_REG_TABLE[i][1];
1553
1554                 if(u4bRegOffset == 0x5e)
1555                 {
1556                     u4bPageIndex = u4bRegValue;
1557                 }
1558                 else
1559                 {
1560                     u4bRegOffset |= (u4bPageIndex << 8);
1561                 }
1562                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1563                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1564         }
1565         //============================================================================
1566 }
1567
1568
1569
1570 static void
1571 MacConfig_85BASIC(
1572         struct net_device *dev)
1573 {
1574
1575        u8                       u1DA;
1576         MacConfig_85BASIC_HardCode(dev);
1577
1578         //============================================================================
1579
1580         // Follow TID_AC_MAP of WMac.
1581         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1582
1583         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1584         write_nic_word(dev, IntMig, 0x0000);
1585
1586         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1587         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1588         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1589         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1590
1591         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1592         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1593 //by amy
1594         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1595
1596         //Enable DA10 TX power saving
1597         u1DA = read_nic_byte(dev, PHYPR);
1598         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1599
1600         //POWER:
1601         write_nic_word(dev, 0x360, 0x1000);
1602         write_nic_word(dev, 0x362, 0x1000);
1603
1604         // AFE.
1605         write_nic_word(dev, 0x370, 0x0560);
1606         write_nic_word(dev, 0x372, 0x0560);
1607         write_nic_word(dev, 0x374, 0x0DA4);
1608         write_nic_word(dev, 0x376, 0x0DA4);
1609         write_nic_word(dev, 0x378, 0x0560);
1610         write_nic_word(dev, 0x37A, 0x0560);
1611         write_nic_word(dev, 0x37C, 0x00EC);
1612 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1613         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1614        write_nic_byte(dev, 0x24E,0x01);
1615 //by amy
1616
1617 }
1618
1619
1620
1621
1622 u8
1623 GetSupportedWirelessMode8185(
1624         struct net_device *dev
1625 )
1626 {
1627         u8                      btSupportedWirelessMode = 0;
1628         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1629
1630         switch(priv->rf_chip)
1631         {
1632         case RF_ZEBRA2:
1633         case RF_ZEBRA4:
1634                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1635                 break;
1636         default:
1637                 btSupportedWirelessMode = WIRELESS_MODE_B;
1638                 break;
1639         }
1640
1641         return btSupportedWirelessMode;
1642 }
1643
1644 void
1645 ActUpdateChannelAccessSetting(
1646         struct net_device *dev,
1647         WIRELESS_MODE                   WirelessMode,
1648         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1649         )
1650 {
1651         struct r8180_priv *priv = ieee80211_priv(dev);
1652         struct ieee80211_device *ieee = priv->ieee80211;
1653         AC_CODING       eACI;
1654         AC_PARAM        AcParam;
1655         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1656         u8      bFollowLegacySetting = 0;
1657         u8   u1bAIFS;
1658
1659         //
1660         // <RJ_TODO_8185B>
1661         // TODO: We still don't know how to set up these registers, just follow WMAC to
1662         // verify 8185B FPAG.
1663         //
1664         // <RJ_TODO_8185B>
1665         // Jong said CWmin/CWmax register are not functional in 8185B,
1666         // so we shall fill channel access realted register into AC parameter registers,
1667         // even in nQBss.
1668         //
1669         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1670         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1671         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1672         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1673         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1674         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1675
1676         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1677         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1678         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1679
1680         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1681
1682         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1683         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1684         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1685         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1686
1687         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1688
1689         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1690
1691 #ifdef TODO
1692         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1693         if( pStaQos->CurrentQosMode > QOS_DISABLE )
1694         { // QoS mode.
1695                 if(pStaQos->QBssWirelessMode == WirelessMode)
1696                 {
1697                         // Follow AC Parameters of the QBSS.
1698                         for(eACI = 0; eACI < AC_MAX; eACI++)
1699                         {
1700                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1701                         }
1702                 }
1703                 else
1704                 {
1705                         // Follow Default WMM AC Parameters.
1706                         bFollowLegacySetting = 1;
1707                 }
1708         }
1709         else
1710 #endif
1711         { // Legacy 802.11.
1712                 bFollowLegacySetting = 1;
1713
1714         }
1715
1716         // this setting is copied from rtl8187B.  xiong-2006-11-13
1717         if(bFollowLegacySetting)
1718         {
1719
1720
1721                 //
1722                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1723                 // 2005.12.01, by rcnjko.
1724                 //
1725                 AcParam.longData = 0;
1726                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1727                 AcParam.f.AciAifsn.f.ACM = 0;
1728                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1729                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1730                 AcParam.f.TXOPLimit = 0;
1731
1732                 //lzm reserved 080826
1733 #if 1
1734                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1735                 if( ieee->current_network.Turbo_Enable == 1 )
1736                         AcParam.f.TXOPLimit = 0x01FF;
1737                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
1738                 if (ieee->iw_mode == IW_MODE_ADHOC)
1739                         AcParam.f.TXOPLimit = 0x0020;
1740 #endif
1741
1742                 for(eACI = 0; eACI < AC_MAX; eACI++)
1743                 {
1744                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1745                         {
1746                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1747                                 AC_CODING       eACI;
1748                                 u8              u1bAIFS;
1749                                 u32             u4bAcParam;
1750
1751                                 // Retrive paramters to udpate.
1752                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1753                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1754                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
1755                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1756                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1757                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1758
1759                                 switch(eACI)
1760                                 {
1761                                         case AC1_BK:
1762                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1763                                                 break;
1764
1765                                         case AC0_BE:
1766                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1767                                                 break;
1768
1769                                         case AC2_VI:
1770                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1771                                                 break;
1772
1773                                         case AC3_VO:
1774                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1775                                                 break;
1776
1777                                         default:
1778                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1779                                                 break;
1780                                 }
1781
1782                                 // Cehck ACM bit.
1783                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1784                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1785                                 {
1786                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1787                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1788
1789                                         //modified Joseph
1790                                         //for 8187B AsynIORead issue
1791 #ifdef TODO
1792                                         u8      AcmCtrl = pHalData->AcmControl;
1793 #else
1794                                         u8      AcmCtrl = 0;
1795 #endif
1796                                         if( pAciAifsn->f.ACM )
1797                                         { // ACM bit is 1.
1798                                                 switch(eACI)
1799                                                 {
1800                                                         case AC0_BE:
1801                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
1802                                                                 break;
1803
1804                                                         case AC2_VI:
1805                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
1806                                                                 break;
1807
1808                                                         case AC3_VO:
1809                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
1810                                                                 break;
1811
1812                                                         default:
1813                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1814                                                                 break;
1815                                                 }
1816                                         }
1817                                         else
1818                                         { // ACM bit is 0.
1819                                                 switch(eACI)
1820                                                 {
1821                                                         case AC0_BE:
1822                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
1823                                                                 break;
1824
1825                                                         case AC2_VI:
1826                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
1827                                                                 break;
1828
1829                                                         case AC3_VO:
1830                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
1831                                                                 break;
1832
1833                                                         default:
1834                                                                 break;
1835                                                 }
1836                                         }
1837
1838                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1839
1840 #ifdef TO_DO
1841                                         pHalData->AcmControl = AcmCtrl;
1842 #endif
1843                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1844                                         write_nic_byte(dev, ACM_CONTROL, 0);
1845                                 }
1846                         }
1847                 }
1848
1849
1850         }
1851 }
1852
1853 void
1854 ActSetWirelessMode8185(
1855         struct net_device *dev,
1856         u8                              btWirelessMode
1857         )
1858 {
1859         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1860         struct ieee80211_device *ieee = priv->ieee80211;
1861         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
1862         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1863
1864         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1865         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1866                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1867                         btWirelessMode, btSupportedWirelessMode);
1868                 return;
1869         }
1870
1871         // 1. Assign wireless mode to swtich if necessary.
1872         if (btWirelessMode == WIRELESS_MODE_AUTO)
1873         {
1874                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1875                 {
1876                         btWirelessMode = WIRELESS_MODE_A;
1877                 }
1878                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1879                 {
1880                         btWirelessMode = WIRELESS_MODE_G;
1881                 }
1882                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1883                 {
1884                         btWirelessMode = WIRELESS_MODE_B;
1885                 }
1886                 else
1887                 {
1888                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1889                                          btSupportedWirelessMode);
1890                         btWirelessMode = WIRELESS_MODE_B;
1891                 }
1892         }
1893
1894
1895         // 2. Swtich band: RF or BB specific actions,
1896         // for example, refresh tables in omc8255, or change initial gain if necessary.
1897         switch(priv->rf_chip)
1898         {
1899         case RF_ZEBRA2:
1900         case RF_ZEBRA4:
1901                 {
1902                         // Nothing to do for Zebra to switch band.
1903                         // Update current wireless mode if we swtich to specified band successfully.
1904                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1905                 }
1906                 break;
1907
1908         default:
1909                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
1910                 break;
1911         }
1912
1913         // 3. Change related setting.
1914         if( ieee->mode == WIRELESS_MODE_A ){
1915                 DMESG("WIRELESS_MODE_A\n");
1916         }
1917         else if( ieee->mode == WIRELESS_MODE_B ){
1918                 DMESG("WIRELESS_MODE_B\n");
1919         }
1920         else if( ieee->mode == WIRELESS_MODE_G ){
1921                 DMESG("WIRELESS_MODE_G\n");
1922         }
1923
1924         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1925 }
1926
1927 void rtl8185b_irq_enable(struct net_device *dev)
1928 {
1929         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1930
1931         priv->irq_enabled = 1;
1932         write_nic_dword(dev, IMR, priv->IntrMask);
1933 }
1934 //by amy for power save
1935 void
1936 DrvIFIndicateDisassociation(
1937         struct net_device *dev,
1938         u16                     reason
1939         )
1940 {
1941         //printk("==> DrvIFIndicateDisassociation()\n");
1942
1943         // nothing is needed after disassociation request.
1944
1945         //printk("<== DrvIFIndicateDisassociation()\n");
1946 }
1947 void
1948 MgntDisconnectIBSS(
1949         struct net_device *dev
1950 )
1951 {
1952         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1953         u8                      i;
1954
1955         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1956
1957         DrvIFIndicateDisassociation(dev, unspec_reason);
1958
1959 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1960         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
1961
1962         priv->ieee80211->state = IEEE80211_NOLINK;
1963
1964         //Stop Beacon.
1965
1966         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1967         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1968         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1969
1970         // Disable Beacon Queue Own bit, suggested by jong
1971 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1972         ieee80211_stop_send_beacons(priv->ieee80211);
1973
1974         priv->ieee80211->link_change(dev);
1975         notify_wx_assoc_event(priv->ieee80211);
1976
1977         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1978
1979 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1980
1981 }
1982 void
1983 MlmeDisassociateRequest(
1984         struct net_device *dev,
1985         u8*                     asSta,
1986         u8                      asRsn
1987         )
1988 {
1989         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1990         u8 i;
1991
1992         SendDisassociation(priv->ieee80211, asSta, asRsn );
1993
1994         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
1995                 //ShuChen TODO: change media status.
1996                 //ShuChen TODO: What to do when disassociate.
1997                 DrvIFIndicateDisassociation(dev, unspec_reason);
1998
1999
2000         //      pMgntInfo->AsocTimestamp = 0;
2001                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2002 //              pMgntInfo->mBrates.Length = 0;
2003 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2004
2005                 ieee80211_disassociate(priv->ieee80211);
2006
2007
2008         }
2009
2010 }
2011
2012 void
2013 MgntDisconnectAP(
2014         struct net_device *dev,
2015         u8                      asRsn
2016 )
2017 {
2018         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2019
2020 //
2021 // Commented out by rcnjko, 2005.01.27:
2022 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2023 //
2024 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2025 //      SecClearAllKeys(Adapter);
2026
2027         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2028 #ifdef TODO
2029         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2030                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2031         {
2032                 SecClearAllKeys(Adapter);
2033                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2034         }
2035 #endif
2036         // 2004.10.11, by rcnjko.
2037         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2038         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2039
2040         priv->ieee80211->state = IEEE80211_NOLINK;
2041 //      pMgntInfo->AsocTimestamp = 0;
2042 }
2043 bool
2044 MgntDisconnect(
2045         struct net_device *dev,
2046         u8                      asRsn
2047 )
2048 {
2049         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2050         //
2051         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2052         //
2053 #ifdef TODO
2054         if(pMgntInfo->mPss != eAwake)
2055         {
2056                 //
2057                 // Using AwkaeTimer to prevent mismatch ps state.
2058                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2059                 //
2060                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2061                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2062         }
2063 #endif
2064
2065         // Indication of disassociation event.
2066         //DrvIFIndicateDisassociation(Adapter, asRsn);
2067         if(IS_DOT11D_ENABLE(priv->ieee80211))
2068                 Dot11d_Reset(priv->ieee80211);
2069         // In adhoc mode, update beacon frame.
2070         if( priv->ieee80211->state == IEEE80211_LINKED )
2071         {
2072                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2073                 {
2074 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2075                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2076                         MgntDisconnectIBSS(dev);
2077                 }
2078                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2079                 {
2080                         // We clear key here instead of MgntDisconnectAP() because that
2081                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2082                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2083                         // used to handle disassociation related things to AP, e.g. send Disassoc
2084                         // frame to AP.  2005.01.27, by rcnjko.
2085 //                      SecClearAllKeys(Adapter);
2086
2087 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2088                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2089                         MgntDisconnectAP(dev, asRsn);
2090                 }
2091
2092                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2093 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2094         }
2095
2096         return true;
2097 }
2098 //
2099 //      Description:
2100 //              Chang RF Power State.
2101 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2102 //
2103 //      Assumption:
2104 //              PASSIVE LEVEL.
2105 //
2106 bool
2107 SetRFPowerState(
2108         struct net_device *dev,
2109         RT_RF_POWER_STATE       eRFPowerState
2110         )
2111 {
2112         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2113         bool                    bResult = false;
2114
2115 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2116         if(eRFPowerState == priv->eRFPowerState)
2117         {
2118 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2119                 return bResult;
2120         }
2121
2122         switch(priv->rf_chip)
2123         {
2124                 case RF_ZEBRA2:
2125                 case RF_ZEBRA4:
2126                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2127                         break;
2128
2129                 default:
2130                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2131                         break;;
2132 }
2133 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2134
2135         return bResult;
2136 }
2137 void
2138 HalEnableRx8185Dummy(
2139         struct net_device *dev
2140         )
2141 {
2142 }
2143 void
2144 HalDisableRx8185Dummy(
2145         struct net_device *dev
2146         )
2147 {
2148 }
2149
2150 bool
2151 MgntActSet_RF_State(
2152         struct net_device *dev,
2153         RT_RF_POWER_STATE       StateToSet,
2154         u32     ChangeSource
2155         )
2156 {
2157         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2158         bool                            bActionAllowed = false;
2159         bool                            bConnectBySSID = false;
2160         RT_RF_POWER_STATE       rtState;
2161         u16                             RFWaitCounter = 0;
2162         unsigned long flag;
2163 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2164         //
2165         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2166         // Only one thread can change the RF state at one time, and others should wait to be executed.
2167         //
2168 #if 1
2169         while(true)
2170         {
2171 //              down(&priv->rf_state);
2172                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2173                 if(priv->RFChangeInProgress)
2174                 {
2175 //                      printk("====================>haha111111111\n");
2176 //                      up(&priv->rf_state);
2177 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2178                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2179                         // Set RF after the previous action is done.
2180                         while(priv->RFChangeInProgress)
2181                         {
2182                                 RFWaitCounter ++;
2183 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2184                                 udelay(1000); // 1 ms
2185
2186                                 // Wait too long, return FALSE to avoid to be stuck here.
2187                                 if(RFWaitCounter > 1000) // 1sec
2188                                 {
2189 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2190                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2191                                         // TODO: Reset RF state?
2192                                         return false;
2193                                 }
2194                         }
2195                 }
2196                 else
2197                 {
2198 //                      printk("========================>haha2\n");
2199                         priv->RFChangeInProgress = true;
2200 //                      up(&priv->rf_state);
2201                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2202                         break;
2203                 }
2204         }
2205 #endif
2206         rtState = priv->eRFPowerState;
2207
2208
2209         switch(StateToSet)
2210         {
2211         case eRfOn:
2212                 //
2213                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2214                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2215                 //
2216                 priv->RfOffReason &= (~ChangeSource);
2217
2218                 if(! priv->RfOffReason)
2219                 {
2220                         priv->RfOffReason = 0;
2221                         bActionAllowed = true;
2222
2223                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2224                         {
2225                                 bConnectBySSID = true;
2226                         }
2227                 }
2228                 else
2229 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2230                         ;
2231                 break;
2232
2233         case eRfOff:
2234                  // 070125, rcnjko: we always keep connected in AP mode.
2235
2236                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2237                         {
2238                                 //
2239                                 // 060808, Annie:
2240                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2241                                 //
2242
2243                                 //
2244                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2245                                 // because we do NOT need to set ssid to dummy ones.
2246                                 // Revised by Roger, 2007.12.04.
2247                                 //
2248                                 MgntDisconnect( dev, disas_lv_ss );
2249
2250                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2251                                 // 2007.05.28, by shien chang.
2252 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2253 //                              pMgntInfo->NumBssDesc = 0;
2254 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2255 //                              pMgntInfo->NumBssDesc4Query = 0;
2256                         }
2257
2258
2259
2260                 priv->RfOffReason |= ChangeSource;
2261                 bActionAllowed = true;
2262                 break;
2263
2264         case eRfSleep:
2265                 priv->RfOffReason |= ChangeSource;
2266                 bActionAllowed = true;
2267                 break;
2268
2269         default:
2270                 break;
2271         }
2272
2273         if(bActionAllowed)
2274         {
2275 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2276                 // Config HW to the specified mode.
2277 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2278                 SetRFPowerState(dev, StateToSet);
2279
2280                 // Turn on RF.
2281                 if(StateToSet == eRfOn)
2282                 {
2283                         HalEnableRx8185Dummy(dev);
2284                         if(bConnectBySSID)
2285                         {
2286                         // by amy not supported
2287 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2288                         }
2289                 }
2290                 // Turn off RF.
2291                 else if(StateToSet == eRfOff)
2292                 {
2293                         HalDisableRx8185Dummy(dev);
2294                 }
2295         }
2296         else
2297         {
2298         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2299         }
2300
2301         // Release RF spinlock
2302 //      down(&priv->rf_state);
2303         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2304         priv->RFChangeInProgress = false;
2305 //      up(&priv->rf_state);
2306         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2307 //      printk("<===MgntActSet_RF_State()\n");
2308         return bActionAllowed;
2309 }
2310 void
2311 InactivePowerSave(
2312         struct net_device *dev
2313         )
2314 {
2315         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2316         //u8 index = 0;
2317
2318         //
2319         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2320         // is really scheduled.
2321         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2322         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2323         // blocks the IPS procedure of switching RF.
2324         // By Bruce, 2007-12-25.
2325         //
2326         priv->bSwRfProcessing = true;
2327
2328         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2329
2330         //
2331         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2332         //
2333
2334         priv->bSwRfProcessing = false;
2335 }
2336
2337 //
2338 //      Description:
2339 //              Enter the inactive power save mode. RF will be off
2340 //      2007.08.17, by shien chang.
2341 //
2342 void
2343 IPSEnter(
2344         struct net_device *dev
2345         )
2346 {
2347         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2348         RT_RF_POWER_STATE rtState;
2349         //printk("==============================>enter IPS\n");
2350         if (priv->bInactivePs)
2351         {
2352                 rtState = priv->eRFPowerState;
2353
2354                 //
2355                 // Added by Bruce, 2007-12-25.
2356                 // Do not enter IPS in the following conditions:
2357                 // (1) RF is already OFF or Sleep
2358                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2359                 // (3) Connectted (only disconnected can trigger IPS)
2360                 // (4) IBSS (send Beacon)
2361                 // (5) AP mode (send Beacon)
2362                 //
2363                 if (rtState == eRfOn && !priv->bSwRfProcessing
2364                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2365                 {
2366         //              printk("IPSEnter(): Turn off RF.\n");
2367                         priv->eInactivePowerState = eRfOff;
2368                         InactivePowerSave(dev);
2369                 }
2370         }
2371 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2372 }
2373 void
2374 IPSLeave(
2375         struct net_device *dev
2376         )
2377 {
2378         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2379         RT_RF_POWER_STATE rtState;
2380         //printk("===================================>leave IPS\n");
2381         if (priv->bInactivePs)
2382         {
2383                 rtState = priv->eRFPowerState;
2384                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2385                 {
2386 //                      printk("IPSLeave(): Turn on RF.\n");
2387                         priv->eInactivePowerState = eRfOn;
2388                         InactivePowerSave(dev);
2389                 }
2390         }
2391 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2392 }
2393 //by amy for power save
2394 void rtl8185b_adapter_start(struct net_device *dev)
2395 {
2396       struct r8180_priv *priv = ieee80211_priv(dev);
2397         struct ieee80211_device *ieee = priv->ieee80211;
2398
2399         u8 SupportedWirelessMode;
2400         u8                      InitWirelessMode;
2401         u8                      bInvalidWirelessMode = 0;
2402         //int i;
2403         u8 tmpu8;
2404         //u8 u1tmp,u2tmp;
2405         u8 btCR9346;
2406         u8 TmpU1b;
2407         u8 btPSR;
2408
2409         //rtl8180_rtx_disable(dev);
2410 //{by amy 080312
2411         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2412 //by amy 080312}
2413         rtl8180_reset(dev);
2414
2415         priv->dma_poll_mask = 0;
2416         priv->dma_poll_stop_mask = 0;
2417
2418         //rtl8180_beacon_tx_disable(dev);
2419
2420         HwConfigureRTL8185(dev);
2421
2422         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2423         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2424
2425         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2426
2427         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2428
2429         write_nic_word(dev, BcnItv, 100);
2430         write_nic_word(dev, AtimWnd, 2);
2431
2432         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2433         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2434
2435         write_nic_byte(dev, WPA_CONFIG, 0);
2436
2437         MacConfig_85BASIC(dev);
2438
2439         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2440         // BT_DEMO_BOARD type
2441         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2442 //by amy
2443 //#ifdef CONFIG_RTL818X_S
2444                 // for jong required
2445 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2446 //#endif
2447 //by amy
2448         //BT_QA_BOARD
2449         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2450
2451         //-----------------------------------------------------------------------------
2452         // Set up PHY related.
2453         //-----------------------------------------------------------------------------
2454         // Enable Config3.PARAM_En to revise AnaaParm.
2455         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2456 //by amy
2457         tmpu8 = read_nic_byte(dev, CONFIG3);
2458         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2459 //by amy
2460         // Turn on Analog power.
2461         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2462         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2463         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2464 //by amy
2465         write_nic_word(dev, ANAPARAM3, 0x0010);
2466 //by amy
2467
2468         write_nic_byte(dev, CONFIG3, tmpu8);
2469         write_nic_byte(dev, CR9346, 0x00);
2470 //{by amy 080312 for led
2471         // enable EEM0 and EEM1 in 9346CR
2472         btCR9346 = read_nic_byte(dev, CR9346);
2473         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2474
2475         // B cut use LED1 to control HW RF on/off
2476         TmpU1b = read_nic_byte(dev, CONFIG5);
2477         TmpU1b = TmpU1b & ~BIT3;
2478         write_nic_byte(dev,CONFIG5, TmpU1b);
2479
2480         // disable EEM0 and EEM1 in 9346CR
2481         btCR9346 &= ~(0xC0);
2482         write_nic_byte(dev, CR9346, btCR9346);
2483
2484         //Enable Led (suggested by Jong)
2485         // B-cut RF Radio on/off  5e[3]=0
2486         btPSR = read_nic_byte(dev, PSR);
2487         write_nic_byte(dev, PSR, (btPSR | BIT3));
2488 //by amy 080312 for led}
2489         // setup initial timing for RFE.
2490         write_nic_word(dev, RFPinsOutput, 0x0480);
2491         SetOutputEnableOfRfPins(dev);
2492         write_nic_word(dev, RFPinsSelect, 0x2488);
2493
2494         // PHY config.
2495         PhyConfig8185(dev);
2496
2497         // We assume RegWirelessMode has already been initialized before,
2498         // however, we has to validate the wireless mode here and provide a reasonble
2499         // initialized value if necessary. 2005.01.13, by rcnjko.
2500         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2501         if(     (ieee->mode != WIRELESS_MODE_B) &&
2502                 (ieee->mode != WIRELESS_MODE_G) &&
2503                 (ieee->mode != WIRELESS_MODE_A) &&
2504                 (ieee->mode != WIRELESS_MODE_AUTO))
2505         { // It should be one of B, G, A, or AUTO.
2506                 bInvalidWirelessMode = 1;
2507         }
2508         else
2509         { // One of B, G, A, or AUTO.
2510                 // Check if the wireless mode is supported by RF.
2511                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2512                         (ieee->mode & SupportedWirelessMode) == 0 )
2513                 {
2514                         bInvalidWirelessMode = 1;
2515                 }
2516         }
2517
2518         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2519         { // Auto or other invalid value.
2520                 // Assigne a wireless mode to initialize.
2521                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2522                 {
2523                         InitWirelessMode = WIRELESS_MODE_A;
2524                 }
2525                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2526                 {
2527                         InitWirelessMode = WIRELESS_MODE_G;
2528                 }
2529                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2530                 {
2531                         InitWirelessMode = WIRELESS_MODE_B;
2532                 }
2533                 else
2534                 {
2535                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2536                                  SupportedWirelessMode);
2537                         InitWirelessMode = WIRELESS_MODE_B;
2538                 }
2539
2540                 // Initialize RegWirelessMode if it is not a valid one.
2541                 if(bInvalidWirelessMode)
2542                 {
2543                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2544                 }
2545         }
2546         else
2547         { // One of B, G, A.
2548                 InitWirelessMode = ieee->mode;
2549         }
2550 //by amy for power save
2551 #ifdef ENABLE_IPS
2552 //      printk("initialize ENABLE_IPS\n");
2553         priv->eRFPowerState = eRfOff;
2554         priv->RfOffReason = 0;
2555         {
2556         //      u32 tmp2;
2557         //      u32 tmp = jiffies;
2558                 MgntActSet_RF_State(dev, eRfOn, 0);
2559         //      tmp2 = jiffies;
2560         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2561         }
2562 //      DrvIFIndicateCurrentPhyStatus(priv);
2563                 //
2564                 // If inactive power mode is enabled, disable rf while in disconnected state.
2565                 // 2007.07.16, by shien chang.
2566                 //
2567         if (priv->bInactivePs)
2568         {
2569         //      u32 tmp2;
2570         //      u32 tmp = jiffies;
2571                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2572         //      tmp2 = jiffies;
2573         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2574
2575         }
2576 #endif
2577 //      IPSEnter(dev);
2578 //by amy for power save
2579 #ifdef TODO
2580         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2581         // We shall turn off RF after setting CMDR, otherwise,
2582         // RF will be turnned on after we enable MAC Tx/Rx.
2583         if(Adapter->MgntInfo.RegRfOff == TRUE)
2584         {
2585                 SetRFPowerState8185(Adapter, RF_OFF);
2586         }
2587         else
2588         {
2589                 SetRFPowerState8185(Adapter, RF_ON);
2590         }
2591 #endif
2592
2593 /*   //these is equal with above TODO.
2594         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2595         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2596         RF_WriteReg(dev, 0x4, 0x9FF);
2597         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2598         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2599         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2600         write_nic_byte(dev, CR9346, 0x00);
2601 */
2602
2603         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2604
2605         //-----------------------------------------------------------------------------
2606
2607         rtl8185b_irq_enable(dev);
2608
2609         netif_start_queue(dev);
2610
2611  }
2612
2613
2614 void rtl8185b_rx_enable(struct net_device *dev)
2615 {
2616         u8 cmd;
2617         //u32 rxconf;
2618         /* for now we accept data, management & ctl frame*/
2619         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2620
2621         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2622
2623         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2624            dev->flags & IFF_PROMISC){
2625                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2626                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2627         }
2628
2629         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2630                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2631                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2632         }*/
2633
2634         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2635                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2636         }
2637
2638         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2639                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2640
2641         write_nic_dword(dev, RCR, priv->ReceiveConfig);
2642
2643         fix_rx_fifo(dev);
2644
2645 #ifdef DEBUG_RX
2646         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2647 #endif
2648         cmd=read_nic_byte(dev,CMD);
2649         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2650
2651 }
2652
2653 void rtl8185b_tx_enable(struct net_device *dev)
2654 {
2655         u8 cmd;
2656         //u8 tx_agc_ctl;
2657         u8 byte;
2658         //u32 txconf;
2659         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2660
2661         write_nic_dword(dev, TCR, priv->TransmitConfig);
2662         byte = read_nic_byte(dev, MSR);
2663         byte |= MSR_LINK_ENEDCA;
2664         write_nic_byte(dev, MSR, byte);
2665
2666         fix_tx_fifo(dev);
2667
2668 #ifdef DEBUG_TX
2669         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2670 #endif
2671
2672         cmd=read_nic_byte(dev,CMD);
2673         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2674
2675         //write_nic_dword(dev,TX_CONF,txconf);
2676
2677
2678 /*
2679         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2680         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2681         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2682         */
2683 }
2684
2685