SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #include "r8180_pm.h"
  34
  35 #include "ieee80211/dot11d.h"
  36
  37
  38 //#define CONFIG_RTL8180_IO_MAP
  39
  40 #define TC_3W_POLL_MAX_TRY_CNT 5
  41 static u8 MAC_REG_TABLE[][2]={
  42                         //PAGA 0:
  43                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  44                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  45                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  46                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  47                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  48                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  49                         {0x94, 0x0F}, {0x95, 0x32},
  50                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  51                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  52                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  53                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  54                         {0xff, 0x00},
  55
  56                         //PAGE 1:
  57                         // For Flextronics system Logo PCIHCT failure:
  58                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  59                         {0x5e, 0x01},
  60                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  61                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  62                         {0x82, 0xFF}, {0x83, 0x03},
  63                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  64                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  65                         {0xe2, 0x00},
  66
  67
  68                         //PAGE 2:
  69                         {0x5e, 0x02},
  70                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  71                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  72                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  73                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  74                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  75                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  76                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  77
  78                         //PAGA 0:
  79                         {0x5e, 0x00},{0x9f, 0x03}
  80                 };
  81
  82
  83 static u8  ZEBRA_AGC[]={
  84                         0,
  85                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  86                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  87                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  88                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  89                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  90                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  91                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  92                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  93                         };
  94
  95 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  96                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  97                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  98                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  99                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 100                         0x0183,0x0163,0x0143,0x0123,0x0103
 101         };
 102
 103 static u8 OFDM_CONFIG[]={
 104                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 105                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 106                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 107
 108                         // 0x00
 109                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 110                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 111                         // 0x10
 112                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 113                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 114                         // 0x20
 115                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 116                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 117                         // 0x30
 118                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 119                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 120                 };
 121
 122 /*---------------------------------------------------------------
 123   * Hardware IO
 124   * the code is ported from Windows source code
 125   ----------------------------------------------------------------*/
 126
 127 void
 128 PlatformIOWrite1Byte(
 129         struct net_device *dev,
 130         u32             offset,
 131         u8              data
 132         )
 133 {
 134         write_nic_byte(dev, offset, data);
 135         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 136
 137 }
 138
 139 void
 140 PlatformIOWrite2Byte(
 141         struct net_device *dev,
 142         u32             offset,
 143         u16             data
 144         )
 145 {
 146         write_nic_word(dev, offset, data);
 147         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 148
 149
 150 }
 151 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 152
 153 void
 154 PlatformIOWrite4Byte(
 155         struct net_device *dev,
 156         u32             offset,
 157         u32             data
 158         )
 159 {
 160 //{by amy 080312
 161 if (offset == PhyAddr)
 162         {//For Base Band configuration.
 163                 unsigned char   cmdByte;
 164                 unsigned long   dataBytes;
 165                 unsigned char   idx;
 166                 u8      u1bTmp;
 167
 168                 cmdByte = (u8)(data & 0x000000ff);
 169                 dataBytes = data>>8;
 170
 171                 //
 172                 // 071010, rcnjko:
 173                 // The critical section is only BB read/write race condition.
 174                 // Assumption:
 175                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 176                 // acquiring the spinlock in such context.
 177                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 178                 //
 179 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 180
 181                 for(idx = 0; idx < 30; idx++)
 182                 { // Make sure command bit is clear before access it.
 183                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 184                         if((u1bTmp & BIT7) == 0)
 185                                 break;
 186                         else
 187                                 mdelay(10);
 188                 }
 189
 190                 for(idx=0; idx < 3; idx++)
 191                 {
 192                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 193                 }
 194                 write_nic_byte(dev, offset, cmdByte);
 195
 196 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 197         }
 198 //by amy 080312}
 199         else{
 200                 write_nic_dword(dev, offset, data);
 201                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 202         }
 203 }
 204
 205 u8
 206 PlatformIORead1Byte(
 207         struct net_device *dev,
 208         u32             offset
 209         )
 210 {
 211         u8      data = 0;
 212
 213         data = read_nic_byte(dev, offset);
 214
 215
 216         return data;
 217 }
 218
 219 u16
 220 PlatformIORead2Byte(
 221         struct net_device *dev,
 222         u32             offset
 223         )
 224 {
 225         u16     data = 0;
 226
 227         data = read_nic_word(dev, offset);
 228
 229
 230         return data;
 231 }
 232
 233 u32
 234 PlatformIORead4Byte(
 235         struct net_device *dev,
 236         u32             offset
 237         )
 238 {
 239         u32     data = 0;
 240
 241         data = read_nic_dword(dev, offset);
 242
 243
 244         return data;
 245 }
 246
 247 void
 248 SetOutputEnableOfRfPins(
 249         struct net_device *dev
 250         )
 251 {
 252         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 253
 254         switch(priv->rf_chip)
 255         {
 256         case RFCHIPID_RTL8225:
 257         case RF_ZEBRA2:
 258         case RF_ZEBRA4:
 259                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 260                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 261                 break;
 262         }
 263 }
 264
 265 void
 266 ZEBRA_RFSerialWrite(
 267         struct net_device *dev,
 268         u32                     data2Write,
 269         u8                      totalLength,
 270         u8                      low2high
 271         )
 272 {
 273         ThreeWireReg            twreg;
 274         int                             i;
 275         u16                             oval,oval2,oval3;
 276         u32                             mask;
 277         u16                             UshortBuffer;
 278
 279         u8                      u1bTmp;
 280         // RTL8187S HSSI Read/Write Function
 281         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 282         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 283         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 284         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 285         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 286
 287         oval2 = read_nic_word(dev, RFPinsEnable);
 288         oval3 = read_nic_word(dev, RFPinsSelect);
 289
 290         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 291         oval3 &= 0xfff8;
 292
 293         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 294         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 295         udelay(10);
 296
 297         // Add this to avoid hardware and software 3-wire conflict.
 298         // 2005.03.01, by rcnjko.
 299         twreg.longData = 0;
 300         twreg.struc.enableB = 1;
 301         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 302         udelay(2);
 303         twreg.struc.enableB = 0;
 304         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 305         udelay(10);
 306
 307         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 308
 309         for(i=0; i<totalLength/2; i++)
 310         {
 311                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 312                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 313                 twreg.struc.clk = 1;
 314                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 315                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 316
 317                 mask = (low2high)?(mask<<1):(mask>>1);
 318                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 319                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 320                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 321                 twreg.struc.clk = 0;
 322                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 323                 mask = (low2high)?(mask<<1):(mask>>1);
 324         }
 325
 326         twreg.struc.enableB = 1;
 327         twreg.struc.clk = 0;
 328         twreg.struc.data = 0;
 329         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 330         udelay(10);
 331
 332         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 333         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 334
 335         SetOutputEnableOfRfPins(dev);
 336 }
 337 //by amy
 338
 339
 340 int
 341 HwHSSIThreeWire(
 342         struct net_device *dev,
 343         u8                      *pDataBuf,
 344         u8                      nDataBufBitCnt,
 345         int                     bSI,
 346         int                     bWrite
 347         )
 348 {
 349         int     bResult = 1;
 350         u8      TryCnt;
 351         u8      u1bTmp;
 352
 353         do
 354         {
 355                 // Check if WE and RE are cleared.
 356                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 357                 {
 358                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 359                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 360                         {
 361                                 break;
 362                         }
 363                         udelay(10);
 364                 }
 365                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 366                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 367
 368                 // RTL8187S HSSI Read/Write Function
 369                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 370
 371                 if(bSI)
 372                 {
 373                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 374                 }else
 375                 {
 376                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 377                 }
 378
 379                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 380
 381                 if(bSI)
 382                 {
 383                         // jong: HW SI read must set reg84[3]=0.
 384                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 385                         u1bTmp &= ~BIT3;
 386                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 387                 }
 388                 // Fill up data buffer for write operation.
 389
 390                 if(bWrite)
 391                 {
 392                         if(nDataBufBitCnt == 16)
 393                         {
 394                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 395                         }
 396                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 397                         {
 398                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 399                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 400                         }
 401                         else
 402                         {
 403                                 int idx;
 404                                 int ByteCnt = nDataBufBitCnt / 8;
 405                                 //printk("%d\n",nDataBufBitCnt);
 406                                 if ((nDataBufBitCnt % 8) != 0)
 407                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 408                                 nDataBufBitCnt);
 409
 410                                if (nDataBufBitCnt > 64)
 411                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 412                                 nDataBufBitCnt);
 413
 414                                 for(idx = 0; idx < ByteCnt; idx++)
 415                                 {
 416                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 417                                 }
 418                         }
 419                 }
 420                 else            //read
 421                 {
 422                         if(bSI)
 423                         {
 424                                 // SI - reg274[3:0] : RF register's Address
 425                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 426                         }
 427                         else
 428                         {
 429                                 // PI - reg274[15:12] : RF register's Address
 430                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 431                         }
 432                 }
 433
 434                 // Set up command: WE or RE.
 435                 if(bWrite)
 436                 {
 437                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 438                 }
 439                 else
 440                 {
 441                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 442                 }
 443
 444                 // Check if DONE is set.
 445                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 446                 {
 447                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 448                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 449                         {
 450                                 break;
 451                         }
 452                         udelay(10);
 453                 }
 454
 455                 write_nic_byte(dev, SW_3W_CMD1, 0);
 456
 457                 // Read back data for read operation.
 458                 if(bWrite == 0)
 459                 {
 460                         if(bSI)
 461                         {
 462                                 //Serial Interface : reg363_362[11:0]
 463                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 464                         }
 465                         else
 466                         {
 467                                 //Parallel Interface : reg361_360[11:0]
 468                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 469                         }
 470
 471                         *((u16*)pDataBuf) &= 0x0FFF;
 472                 }
 473
 474         }while(0);
 475
 476         return bResult;
 477 }
 478 //by amy
 479
 480 int
 481 HwThreeWire(
 482         struct net_device *dev,
 483         u8                      *pDataBuf,
 484         u8                      nDataBufBitCnt,
 485         int                     bHold,
 486         int                     bWrite
 487         )
 488 {
 489         int     bResult = 1;
 490         u8      TryCnt;
 491         u8      u1bTmp;
 492
 493         do
 494         {
 495                 // Check if WE and RE are cleared.
 496                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 497                 {
 498                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 499                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 500                         {
 501                                 break;
 502                         }
 503                         udelay(10);
 504                 }
 505                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 506                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 507
 508                 // Fill up data buffer for write operation.
 509                 if(nDataBufBitCnt == 16)
 510                 {
 511                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 512                 }
 513                 else if(nDataBufBitCnt == 64)
 514                 {
 515                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 516                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 517                 }
 518                 else
 519                 {
 520                         int idx;
 521                         int ByteCnt = nDataBufBitCnt / 8;
 522
 523                         if ((nDataBufBitCnt % 8) != 0)
 524                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 525                                 nDataBufBitCnt);
 526
 527                         if (nDataBufBitCnt > 64)
 528                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 529                                 nDataBufBitCnt);
 530
 531                         for(idx = 0; idx < ByteCnt; idx++)
 532                         {
 533                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 534                         }
 535                 }
 536
 537                 // Fill up length field.
 538                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 539                 if(bHold)
 540                         u1bTmp |= SW_3W_CMD0_HOLD;
 541                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 542
 543                 // Set up command: WE or RE.
 544                 if(bWrite)
 545                 {
 546                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 547                 }
 548                 else
 549                 {
 550                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 551                 }
 552
 553                 // Check if WE and RE are cleared and DONE is set.
 554                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 555                 {
 556                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 557                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 558                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 559                         {
 560                                 break;
 561                         }
 562                         udelay(10);
 563                 }
 564                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 565                 {
 566                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 567                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 568                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 569                         write_nic_byte(dev, SW_3W_CMD1, 0);
 570                 }
 571
 572                 // Read back data for read operation.
 573                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 574                 if(bWrite == 0)
 575                 {
 576                         if(nDataBufBitCnt == 16)
 577                         {
 578                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 579                         }
 580                         else if(nDataBufBitCnt == 64)
 581                         {
 582                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 583                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 584                         }
 585                         else
 586                         {
 587                                 int idx;
 588                                 int ByteCnt = nDataBufBitCnt / 8;
 589
 590                                 if ((nDataBufBitCnt % 8) != 0)
 591                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 592                                         nDataBufBitCnt);
 593
 594                                 if (nDataBufBitCnt > 64)
 595                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 596                                         nDataBufBitCnt);
 597
 598                                 for(idx = 0; idx < ByteCnt; idx++)
 599                                 {
 600                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 601                                 }
 602                         }
 603                 }
 604
 605         }while(0);
 606
 607         return bResult;
 608 }
 609
 610
 611 void
 612 RF_WriteReg(
 613         struct net_device *dev,
 614         u8              offset,
 615         u32             data
 616         )
 617 {
 618         //RFReg                 reg;
 619         u32                     data2Write;
 620         u8                      len;
 621         u8                      low2high;
 622         //u32                   RF_Read = 0;
 623         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 624
 625
 626         switch(priv->rf_chip)
 627         {
 628         case RFCHIPID_RTL8225:
 629         case RF_ZEBRA2:         // Annie 2006-05-12.
 630         case RF_ZEBRA4:        //by amy
 631                 switch(priv->RegThreeWireMode)
 632                 {
 633                 case SW_THREE_WIRE:
 634                         { // Perform SW 3-wire programming by driver.
 635                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 636                                 len = 16;
 637                                 low2high = 0;
 638                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 639                         }
 640                         break;
 641
 642                 case HW_THREE_WIRE:
 643                         { // Pure HW 3-wire.
 644                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 645                                 len = 16;
 646                                 HwThreeWire(
 647                                         dev,
 648                                         (u8 *)(&data2Write),    // pDataBuf,
 649                                         len,                            // nDataBufBitCnt,
 650                                         0,                                      // bHold,
 651                                         1);                                     // bWrite
 652                         }
 653                         break;
 654                         case HW_THREE_WIRE_PI: //Parallel Interface
 655                         { // Pure HW 3-wire.
 656                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 657                                 len = 16;
 658                                         HwHSSIThreeWire(
 659                                                 dev,
 660                                                 (u8*)(&data2Write),     // pDataBuf,
 661                                                 len,                                            // nDataBufBitCnt,
 662                                                 0,                                      // bSI
 663                                                 1);                                     // bWrite
 664
 665                                 //printk("33333\n");
 666                         }
 667                         break;
 668
 669                         case HW_THREE_WIRE_SI: //Serial Interface
 670                         { // Pure HW 3-wire.
 671                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 672                                 len = 16;
 673 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 674 //                                low2high = 0;
 675 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 676
 677                                 HwHSSIThreeWire(
 678                                         dev,
 679                                         (u8*)(&data2Write),     // pDataBuf,
 680                                         len,                                            // nDataBufBitCnt,
 681                                         1,                                      // bSI
 682                                         1);                                     // bWrite
 683
 684 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 685                         }
 686                         break;
 687
 688
 689                 default:
 690                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 691                         break;
 692                 }
 693                 break;
 694
 695         default:
 696                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 697                 break;
 698         }
 699 }
 700
 701
 702 void
 703 ZEBRA_RFSerialRead(
 704         struct net_device *dev,
 705         u32             data2Write,
 706         u8              wLength,
 707         u32             *data2Read,
 708         u8              rLength,
 709         u8              low2high
 710         )
 711 {
 712         ThreeWireReg    twreg;
 713         int                             i;
 714         u16                     oval,oval2,oval3,tmp, wReg80;
 715         u32                     mask;
 716         u8                      u1bTmp;
 717         ThreeWireReg    tdata;
 718         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 719         { // RTL8187S HSSI Read/Write Function
 720                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 721                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 722                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 723         }
 724
 725         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 726         oval2 = read_nic_word(dev, RFPinsEnable);
 727         oval3 = read_nic_word(dev, RFPinsSelect);
 728
 729         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 730         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 731
 732         *data2Read = 0;
 733
 734         // We must clear BIT0-3 here, otherwise,
 735         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 736         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 737         oval &= ~0xf;
 738
 739         // Avoid collision with hardware three-wire.
 740         twreg.longData = 0;
 741         twreg.struc.enableB = 1;
 742         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 743
 744         twreg.longData = 0;
 745         twreg.struc.enableB = 0;
 746         twreg.struc.clk = 0;
 747         twreg.struc.read_write = 0;
 748         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 749
 750         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 751         for(i = 0; i < wLength/2; i++)
 752         {
 753                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 754                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 755                 twreg.struc.clk = 1;
 756                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 757                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 758
 759                 mask = (low2high) ? (mask<<1): (mask>>1);
 760
 761                 if(i == 2)
 762                 {
 763                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 764                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 765                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 766
 767                         twreg.struc.read_write=1;
 768                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 769                         twreg.struc.clk = 0;
 770                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 771                         break;
 772                 }
 773                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 774                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 775                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 776
 777                 twreg.struc.clk = 0;
 778                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 779
 780                 mask = (low2high) ? (mask<<1) : (mask>>1);
 781         }
 782
 783         twreg.struc.clk = 0;
 784         twreg.struc.data = 0;
 785         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 786         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 787
 788         //
 789         // 061016, by rcnjko:
 790         // We must set data pin to HW controled, otherwise RF can't driver it and
 791         // value RF register won't be able to read back properly.
 792         //
 793         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 794
 795         for(i = 0; i < rLength; i++)
 796         {
 797                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 798                 twreg.struc.clk = 1;
 799                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 800                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 801                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 802                 tmp = read_nic_word(dev, RFPinsInput);
 803                 tdata.longData = tmp;
 804                 *data2Read |= tdata.struc.clk ? mask : 0;
 805
 806                 twreg.struc.clk = 0;
 807                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 808
 809                 mask = (low2high) ? (mask<<1) : (mask>>1);
 810         }
 811         twreg.struc.enableB = 1;
 812         twreg.struc.clk = 0;
 813         twreg.struc.data = 0;
 814         twreg.struc.read_write = 1;
 815         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 816
 817         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 818         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 819         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 820         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 821         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 822         write_nic_word(dev, RFPinsOutput, 0x3a0);
 823         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 824 }
 825
 826
 827 u32
 828 RF_ReadReg(
 829         struct net_device *dev,
 830         u8              offset
 831         )
 832 {
 833         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 834         u32                     data2Write;
 835         u8                      wlen;
 836         u8                      rlen;
 837         u8                      low2high;
 838         u32                     dataRead;
 839
 840         switch(priv->rf_chip)
 841         {
 842         case RFCHIPID_RTL8225:
 843         case RF_ZEBRA2:
 844         case RF_ZEBRA4:
 845                 switch(priv->RegThreeWireMode)
 846                 {
 847                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
 848                         {
 849                                 data2Write = ((u32)(offset&0x0f));
 850                                 wlen=16;
 851                                 HwHSSIThreeWire(
 852                                         dev,
 853                                         (u8*)(&data2Write),     // pDataBuf,
 854                                         wlen,                                   // nDataBufBitCnt,
 855                                         0,                                      // bSI
 856                                         0);                                     // bWrite
 857                                 dataRead= data2Write;
 858                         }
 859                         break;
 860
 861                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
 862                         {
 863                                 data2Write = ((u32)(offset&0x0f)) ;
 864                                 wlen=16;
 865                                 HwHSSIThreeWire(
 866                                         dev,
 867                                         (u8*)(&data2Write),     // pDataBuf,
 868                                         wlen,                                   // nDataBufBitCnt,
 869                                         1,                                      // bSI
 870                                         0                                       // bWrite
 871                                         );
 872                                 dataRead= data2Write;
 873                         }
 874                         break;
 875
 876                         // Perform SW 3-wire programming by driver.
 877                         default:
 878                         {
 879                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
 880                                 wlen = 6;
 881                                 rlen = 12;
 882                                 low2high = 0;
 883                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
 884                         }
 885                         break;
 886                 }
 887                 break;
 888         default:
 889                 dataRead = 0;
 890                 break;
 891         }
 892
 893         return dataRead;
 894 }
 895
 896
 897 // by Owen on 04/07/14 for writing BB register successfully
 898 void
 899 WriteBBPortUchar(
 900         struct net_device *dev,
 901         u32             Data
 902         )
 903 {
 904         //u8    TimeoutCounter;
 905         u8      RegisterContent;
 906         u8      UCharData;
 907
 908         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 909         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 910         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
 911         {
 912                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 913                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 914                 //if(UCharData == RegisterContent)
 915                 //      break;
 916         }
 917 }
 918
 919 u8
 920 ReadBBPortUchar(
 921         struct net_device *dev,
 922         u32             addr
 923         )
 924 {
 925         //u8    TimeoutCounter;
 926         u8      RegisterContent;
 927
 928         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 929         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 930
 931         return RegisterContent;
 932 }
 933 //{by amy 080312
 934 //
 935 //      Description:
 936 //              Perform Antenna settings with antenna diversity on 87SE.
 937 //    Created by Roger, 2008.01.25.
 938 //
 939 bool
 940 SetAntennaConfig87SE(
 941         struct net_device *dev,
 942         u8                      DefaultAnt,             // 0: Main, 1: Aux.
 943         bool            bAntDiversity   // 1:Enable, 0: Disable.
 944 )
 945 {
 946         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 947         bool   bAntennaSwitched = true;
 948
 949         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
 950
 951         // Threshold for antenna diversity.
 952         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
 953
 954         if( bAntDiversity )  //  Enable Antenna Diversity.
 955         {
 956                 if( DefaultAnt == 1 )  // aux antenna
 957                 {
 958                         // Mac register, aux antenna
 959                         write_nic_byte(dev, ANTSEL, 0x00);
 960
 961                         // Config CCK RX antenna.
 962                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 963                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 964
 965                         // Config OFDM RX antenna.
 966                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 967                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 968                 }
 969                 else //  use main antenna
 970                 {
 971                         // Mac register, main antenna
 972                         write_nic_byte(dev, ANTSEL, 0x03);
 973                         //base band
 974                         // Config CCK RX antenna.
 975                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 976                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 977
 978                         // Config OFDM RX antenna.
 979                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
 980                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 981                 }
 982         }
 983         else   // Disable Antenna Diversity.
 984         {
 985                 if( DefaultAnt == 1 ) // aux Antenna
 986                 {
 987                         // Mac register, aux antenna
 988                         write_nic_byte(dev, ANTSEL, 0x00);
 989
 990                         // Config CCK RX antenna.
 991                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 992                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 993
 994                         // Config OFDM RX antenna.
 995                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 996                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 997                 }
 998                 else // main Antenna
 999                 {
1000                         // Mac register, main antenna
1001                         write_nic_byte(dev, ANTSEL, 0x03);
1002
1003                         // Config CCK RX antenna.
1004                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1005                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1006
1007                         // Config OFDM RX antenna.
1008                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1009                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1010                 }
1011         }
1012         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1013         return  bAntennaSwitched;
1014 }
1015 //by amy 080312
1016 /*---------------------------------------------------------------
1017   * Hardware Initialization.
1018   * the code is ported from Windows source code
1019   ----------------------------------------------------------------*/
1020
1021 void
1022 ZEBRA_Config_85BASIC_HardCode(
1023         struct net_device *dev
1024         )
1025 {
1026
1027         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1028         u32                     i;
1029         u32     addr,data;
1030         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1031        u8                       u1b24E;
1032
1033
1034         //=============================================================================
1035         // 87S_PCIE :: RADIOCFG.TXT
1036         //=============================================================================
1037
1038
1039         // Page1 : reg16-reg30
1040         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1041         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1042         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1043
1044         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1045                 priv->card_8185 = VERSION_8187S_D;
1046
1047         // Page0 : reg0-reg15
1048
1049 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1050         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1051
1052         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1053
1054 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1055         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1056
1057 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1058         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1059
1060         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1061         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1062         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1063         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1064         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1065         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1066         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1067         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1068         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1069         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1070         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1071         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1072
1073
1074         // Page1 : reg16-reg30
1075         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1076
1077         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1078
1079         if(priv->card_8185 < VERSION_8187S_C)
1080         {
1081                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1082                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1083                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1084         }
1085         else
1086         {
1087                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1088                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1089                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1090         }
1091
1092
1093         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1094 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1095 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1096 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1097         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1098         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1099
1100         if(priv->card_8185 == VERSION_8187S_D)
1101         {
1102                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1103                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1104                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1105         }
1106         else
1107         {
1108                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1109                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1110                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1111         }
1112
1113         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1114
1115 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1116         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1117
1118         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1119         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1120         for(i=0;i<=36;i++)
1121         {
1122                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1123                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1124                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1125         }
1126
1127         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1128         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1129         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1130
1131         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1132         mdelay(10);     // Deay 10 ms. //0xfd
1133
1134 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1135         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1136         //mdelay(10);   // Deay 10 ms. //0xfd
1137
1138         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1139         mdelay(10);     // Deay 10 ms. //0xfd
1140
1141         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1142         mdelay(10);     // Deay 10 ms. //0xfd
1143
1144         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1145         mdelay(10);     // Deay 10 ms. //0xfd
1146
1147         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1148         mdelay(10);     // Deay 10 ms. //0xfd
1149
1150         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1151         mdelay(200);    // Deay 200 ms. //0xfd
1152         mdelay(10);     // Deay 10 ms. //0xfd
1153         mdelay(10);     // Deay 10 ms. //0xfd
1154
1155         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1156         mdelay(10);     // Deay 10 ms. //0xfd
1157
1158         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1159         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1160         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1161         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1162
1163         // DAC calibration off 20070702
1164         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1165         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1166 //{by amy 080312
1167         // For crystal calibration, added by Roger, 2007.12.11.
1168         if( priv->bXtalCalibration ) // reg 30.
1169         { // enable crystal calibration.
1170                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1171                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1172                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1173                 // So we should minus 4 BITs offset.
1174                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1175                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1176                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1177         }
1178         else
1179         { // using default value. Xin=6, Xout=6.
1180                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1181         }
1182 //by amy 080312
1183 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1184
1185         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1186 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1187         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1188         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1189         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1190         mdelay(10);     // Deay 10 ms. //0xfe
1191         mdelay(10);     // Deay 10 ms. //0xfe
1192         mdelay(10);     // Deay 10 ms. //0xfe
1193         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1194         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1195         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1196
1197 #if 0//-edward
1198         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1);
1199         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1200         RF_WriteReg(dev, 0x00, 0x009F);                 mdelay(1);
1201 #endif
1202         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1203         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1204         //power save parameters.
1205         u1b24E = read_nic_byte(dev, 0x24E);
1206         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1207
1208         //=============================================================================
1209
1210         //=============================================================================
1211         // CCKCONF.TXT
1212         //=============================================================================
1213
1214         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1215                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1216                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1217                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1218                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1219                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1220         */
1221 #if 0
1222         write_nic_dword(dev, PHY_ADR, 0x0100c880);
1223         write_nic_dword(dev, PHY_ADR, 0x01001c86);
1224         write_nic_dword(dev, PHY_ADR, 0x01007890);
1225         write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1226         write_nic_dword(dev, PHY_ADR, 0x010006af);
1227         write_nic_dword(dev, PHY_ADR, 0x01004681);
1228 #endif
1229         write_phy_cck(dev,0x00,0xc8);
1230         write_phy_cck(dev,0x06,0x1c);
1231         write_phy_cck(dev,0x10,0x78);
1232         write_phy_cck(dev,0x2e,0xd0);
1233         write_phy_cck(dev,0x2f,0x06);
1234         write_phy_cck(dev,0x01,0x46);
1235
1236         // power control
1237         write_nic_byte(dev, CCK_TXAGC, 0x10);
1238         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1239         write_nic_byte(dev, ANTSEL, 0x03);
1240
1241
1242
1243         //=============================================================================
1244         // AGC.txt
1245         //=============================================================================
1246
1247 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1248         write_phy_ofdm(dev, 0x00, 0x12);
1249         //WriteBBPortUchar(dev, 0x00001280);
1250
1251         for (i=0; i<128; i++)
1252         {
1253                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1254
1255                 data = ZEBRA_AGC[i+1];
1256                 data = data << 8;
1257                 data = data | 0x0000008F;
1258
1259                 addr = i + 0x80; //enable writing AGC table
1260                 addr = addr << 8;
1261                 addr = addr | 0x0000008E;
1262
1263                 WriteBBPortUchar(dev, data);
1264                 WriteBBPortUchar(dev, addr);
1265                 WriteBBPortUchar(dev, 0x0000008E);
1266         }
1267
1268         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1269         //WriteBBPortUchar(dev, 0x00001080);
1270
1271         //=============================================================================
1272
1273         //=============================================================================
1274         // OFDMCONF.TXT
1275         //=============================================================================
1276
1277         for(i=0; i<60; i++)
1278         {
1279                 u4bRegOffset=i;
1280                 u4bRegValue=OFDM_CONFIG[i];
1281
1282                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1283
1284                 WriteBBPortUchar(dev,
1285                                                 (0x00000080 |
1286                                                 (u4bRegOffset & 0x7f) |
1287                                                 ((u4bRegValue & 0xff) << 8)));
1288         }
1289
1290         //=============================================================================
1291 //by amy for antenna
1292         //=============================================================================
1293 //{by amy 080312
1294         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1295         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1296 //by amy 080312}
1297 #if 0
1298         // Config Sw/Hw  Antenna Diversity
1299         if( priv->bSwAntennaDiverity )  //  Use SW+Hw Antenna Diversity
1300         {
1301                 if( priv->bDefaultAntenna1 == true )  // aux antenna
1302                 {
1303                         // Mac register, aux antenna
1304                         write_nic_byte(dev, ANTSEL, 0x00);
1305                         // Config CCK RX antenna.
1306                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1307                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1308                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1309                         // Config OFDM RX antenna.
1310                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1311                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1312                 }
1313                 else //  main antenna
1314                 {
1315                         // Mac register, main antenna
1316                         write_nic_byte(dev, ANTSEL, 0x03);
1317                         //base band
1318                         // Config CCK RX antenna.
1319                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1320                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1321                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1322                         // Config OFDM RX antenna.
1323                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1324                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1325                 }
1326         }
1327         else   // Disable Antenna Diversity
1328         {
1329                 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1330                 {
1331                         // Mac register, aux antenna
1332                         write_nic_byte(dev, ANTSEL, 0x00);
1333                         // Config CCK RX antenna.
1334                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1335                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1336                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1337                         // Config OFDM RX antenna.
1338                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1339                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1340                 }
1341                 else // main Antenna
1342                 {
1343                         // Mac register, main antenna
1344                         write_nic_byte(dev, ANTSEL, 0x03);
1345                         // Config CCK RX antenna.
1346                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1347                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1348                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1349                         // Config OFDM RX antenna.
1350                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1351                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1352                 }
1353         }
1354 #endif
1355 //by amy for antenna
1356 }
1357
1358
1359 void
1360 UpdateInitialGain(
1361         struct net_device *dev
1362         )
1363 {
1364         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1365         //unsigned char* IGTable;
1366         //u8                    DIG_CurrentInitialGain = 4;
1367         //unsigned char u1Tmp;
1368
1369         //lzm add 080826
1370         if(priv->eRFPowerState != eRfOn)
1371         {
1372                 //Don't access BB/RF under disable PLL situation.
1373                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1374                 // Back to the original state
1375                 priv->InitialGain= priv->InitialGainBackUp;
1376                 return;
1377         }
1378
1379         switch(priv->rf_chip)
1380         {
1381 #if 0
1382         case RF_ZEBRA2:
1383                 // Dynamic set initial gain, by shien chang, 2006.07.14
1384                 switch(priv->InitialGain)
1385                 {
1386                         case 1: //m861dBm
1387                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1388                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1389                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1390                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1391                                 break;
1392
1393                         case 2: //m862dBm
1394                                 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1395                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1396                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1397                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1398                                 break;
1399
1400                         case 3: //m863dBm
1401                                 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1402                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1403                                 write_nic_dword(dev, PhyAddr, 0x96a4);  mdelay(1);
1404                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1405                                 break;
1406
1407                         case 4: //m864dBm
1408                                 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1409                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1410                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1411                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1412                                 break;
1413
1414                         case 5: //m82dBm
1415                                 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1416                                 write_nic_dword(dev, PhyAddr, 0x3697);  mdelay(1);
1417                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1418                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1419                                 break;
1420
1421                         case 6: //m78dBm
1422                                 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1423                                 write_nic_dword(dev, PhyAddr, 0x4697);  mdelay(1);
1424                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1425                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1426                                 break;
1427
1428                         case 7: //m74dBm
1429                                 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1430                                 write_nic_dword(dev, PhyAddr, 0x5697);  mdelay(1);
1431                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1432                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1433                                 break;
1434
1435                         default:        //MP
1436                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1437                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1438                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1439                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1440                                 break;
1441                 }
1442                 break;
1443 #endif
1444         case RF_ZEBRA4:
1445                 // Dynamic set initial gain, follow 87B
1446                 switch(priv->InitialGain)
1447                 {
1448                         case 1: //m861dBm
1449                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1450                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1451                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1452                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1453                                 break;
1454
1455                         case 2: //m862dBm
1456                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1457                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1458                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1459                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1460                                 break;
1461
1462                         case 3: //m863dBm
1463                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1464                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1465                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1466                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1467                                 break;
1468
1469                         case 4: //m864dBm
1470                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1471                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1472                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1473                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1474                                 break;
1475
1476                         case 5: //m82dBm
1477                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1478                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1479                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1480                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1481                                 break;
1482
1483                         case 6: //m78dBm
1484                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1485                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1486                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1487                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1488                                 break;
1489
1490                         case 7: //m74dBm
1491                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1492                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1493                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1494                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1495                                 break;
1496
1497                         case 8:
1498                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1499                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1500                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1501                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1502                                 break;
1503
1504
1505                         default:        //MP
1506                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1507                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1508                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1509                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1510                                 break;
1511                 }
1512                 break;
1513
1514
1515         default:
1516                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1517                 break;
1518         }
1519 }
1520 //
1521 //      Description:
1522 //              Tx Power tracking mechanism routine on 87SE.
1523 //      Created by Roger, 2007.12.11.
1524 //
1525 void
1526 InitTxPwrTracking87SE(
1527         struct net_device *dev
1528 )
1529 {
1530         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1531         u32     u4bRfReg;
1532
1533         u4bRfReg = RF_ReadReg(dev, 0x02);
1534
1535         // Enable Thermal meter indication.
1536         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1537         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1538 }
1539
1540 void
1541 PhyConfig8185(
1542         struct net_device *dev
1543         )
1544 {
1545         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1546        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1547            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1548         // RF config
1549         switch(priv->rf_chip)
1550         {
1551         case RF_ZEBRA2:
1552         case RF_ZEBRA4:
1553                 ZEBRA_Config_85BASIC_HardCode( dev);
1554                 break;
1555         }
1556 //{by amy 080312
1557         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1558         if(priv->bDigMechanism)
1559         {
1560                 if(priv->InitialGain == 0)
1561                         priv->InitialGain = 4;
1562                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1563         }
1564
1565         //
1566         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1567         // We initialize thermal meter here to avoid unsuccessful configuration.
1568         // Added by Roger, 2007.12.11.
1569         //
1570         if(priv->bTxPowerTrack)
1571                 InitTxPwrTracking87SE(dev);
1572
1573 //by amy 080312}
1574         priv->InitialGainBackUp= priv->InitialGain;
1575         UpdateInitialGain(dev);
1576
1577         return;
1578 }
1579
1580
1581
1582
1583 void
1584 HwConfigureRTL8185(
1585                 struct net_device *dev
1586                 )
1587 {
1588         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1589 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1590         u8              bUNIVERSAL_CONTROL_RL = 0;
1591
1592         u8              bUNIVERSAL_CONTROL_AGC = 1;
1593         u8              bUNIVERSAL_CONTROL_ANT = 1;
1594         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1595         u8              val8;
1596         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1597         //struct ieee80211_device *ieee = priv->ieee80211;
1598         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1599 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1600 //      {
1601 //              write_nic_word(dev, BRSR, 0xffff);
1602 //      }
1603 //      else
1604 //      {
1605 //              write_nic_word(dev, BRSR, 0x000f);
1606 //      }
1607 //by amy 080312}
1608         write_nic_word(dev, BRSR, 0x0fff);
1609         // Retry limit
1610         val8 = read_nic_byte(dev, CW_CONF);
1611
1612         if(bUNIVERSAL_CONTROL_RL)
1613                 val8 = val8 & 0xfd;
1614         else
1615                 val8 = val8 | 0x02;
1616
1617         write_nic_byte(dev, CW_CONF, val8);
1618
1619         // Tx AGC
1620         val8 = read_nic_byte(dev, TXAGC_CTL);
1621         if(bUNIVERSAL_CONTROL_AGC)
1622         {
1623                 write_nic_byte(dev, CCK_TXAGC, 128);
1624                 write_nic_byte(dev, OFDM_TXAGC, 128);
1625                 val8 = val8 & 0xfe;
1626         }
1627         else
1628         {
1629                 val8 = val8 | 0x01 ;
1630         }
1631
1632
1633         write_nic_byte(dev, TXAGC_CTL, val8);
1634
1635         // Tx Antenna including Feedback control
1636         val8 = read_nic_byte(dev, TXAGC_CTL );
1637
1638         if(bUNIVERSAL_CONTROL_ANT)
1639         {
1640                 write_nic_byte(dev, ANTSEL, 0x00);
1641                 val8 = val8 & 0xfd;
1642         }
1643         else
1644         {
1645                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1646         }
1647
1648         write_nic_byte(dev, TXAGC_CTL, val8);
1649
1650         // Auto Rate fallback control
1651         val8 = read_nic_byte(dev, RATE_FALLBACK);
1652         val8 &= 0x7c;
1653         if( bAUTO_RATE_FALLBACK_CTL )
1654         {
1655                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1656
1657                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1658                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1659 //by amy
1660 #if 0
1661                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff);        // set 1M ~ 54M
1662 #endif
1663                 // Aadded by Roger, 2007.11.15.
1664                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1665 //by amy
1666         }
1667         else
1668         {
1669         }
1670         write_nic_byte(dev, RATE_FALLBACK, val8);
1671 }
1672
1673
1674
1675 static void
1676 MacConfig_85BASIC_HardCode(
1677         struct net_device *dev)
1678 {
1679         //============================================================================
1680         // MACREG.TXT
1681         //============================================================================
1682         int                     nLinesRead = 0;
1683
1684         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1685         int     i;
1686
1687         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1688
1689         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1690         {
1691                 u4bRegOffset=MAC_REG_TABLE[i][0];
1692                 u4bRegValue=MAC_REG_TABLE[i][1];
1693
1694                 if(u4bRegOffset == 0x5e)
1695                 {
1696                     u4bPageIndex = u4bRegValue;
1697                 }
1698                 else
1699                 {
1700                     u4bRegOffset |= (u4bPageIndex << 8);
1701                 }
1702                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1703                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1704         }
1705         //============================================================================
1706 }
1707
1708
1709
1710 static void
1711 MacConfig_85BASIC(
1712         struct net_device *dev)
1713 {
1714
1715        u8                       u1DA;
1716         MacConfig_85BASIC_HardCode(dev);
1717
1718         //============================================================================
1719
1720         // Follow TID_AC_MAP of WMac.
1721         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1722
1723         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1724         write_nic_word(dev, IntMig, 0x0000);
1725
1726         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1727         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1728         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1729         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1730
1731         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1732         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1733 //by amy
1734 #if 0
1735         write_nic_dword(dev, RFTiming, 0x00004001);
1736 #endif
1737         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1738
1739         //Enable DA10 TX power saving
1740         u1DA = read_nic_byte(dev, PHYPR);
1741         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1742
1743         //POWER:
1744         write_nic_word(dev, 0x360, 0x1000);
1745         write_nic_word(dev, 0x362, 0x1000);
1746
1747         // AFE.
1748         write_nic_word(dev, 0x370, 0x0560);
1749         write_nic_word(dev, 0x372, 0x0560);
1750         write_nic_word(dev, 0x374, 0x0DA4);
1751         write_nic_word(dev, 0x376, 0x0DA4);
1752         write_nic_word(dev, 0x378, 0x0560);
1753         write_nic_word(dev, 0x37A, 0x0560);
1754         write_nic_word(dev, 0x37C, 0x00EC);
1755 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1756         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1757        write_nic_byte(dev, 0x24E,0x01);
1758 //by amy
1759
1760 }
1761
1762
1763
1764
1765 u8
1766 GetSupportedWirelessMode8185(
1767         struct net_device *dev
1768 )
1769 {
1770         u8                      btSupportedWirelessMode = 0;
1771         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1772
1773         switch(priv->rf_chip)
1774         {
1775         case RF_ZEBRA2:
1776         case RF_ZEBRA4:
1777                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1778                 break;
1779         default:
1780                 btSupportedWirelessMode = WIRELESS_MODE_B;
1781                 break;
1782         }
1783
1784         return btSupportedWirelessMode;
1785 }
1786
1787 void
1788 ActUpdateChannelAccessSetting(
1789         struct net_device *dev,
1790         WIRELESS_MODE                   WirelessMode,
1791         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1792         )
1793 {
1794         struct r8180_priv *priv = ieee80211_priv(dev);
1795         struct ieee80211_device *ieee = priv->ieee80211;
1796         AC_CODING       eACI;
1797         AC_PARAM        AcParam;
1798         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1799         u8      bFollowLegacySetting = 0;
1800         u8   u1bAIFS;
1801
1802         //
1803         // <RJ_TODO_8185B>
1804         // TODO: We still don't know how to set up these registers, just follow WMAC to
1805         // verify 8185B FPAG.
1806         //
1807         // <RJ_TODO_8185B>
1808         // Jong said CWmin/CWmax register are not functional in 8185B,
1809         // so we shall fill channel access realted register into AC parameter registers,
1810         // even in nQBss.
1811         //
1812         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1813         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1814         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1815         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1816         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1817         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1818
1819         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1820         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1821         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1822
1823         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1824
1825         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1826         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1827         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1828         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1829
1830         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1831
1832         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1833
1834 #ifdef TODO
1835         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1836         if( pStaQos->CurrentQosMode > QOS_DISABLE )
1837         { // QoS mode.
1838                 if(pStaQos->QBssWirelessMode == WirelessMode)
1839                 {
1840                         // Follow AC Parameters of the QBSS.
1841                         for(eACI = 0; eACI < AC_MAX; eACI++)
1842                         {
1843                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1844                         }
1845                 }
1846                 else
1847                 {
1848                         // Follow Default WMM AC Parameters.
1849                         bFollowLegacySetting = 1;
1850                 }
1851         }
1852         else
1853 #endif
1854         { // Legacy 802.11.
1855                 bFollowLegacySetting = 1;
1856
1857         }
1858
1859         // this setting is copied from rtl8187B.  xiong-2006-11-13
1860         if(bFollowLegacySetting)
1861         {
1862
1863
1864                 //
1865                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1866                 // 2005.12.01, by rcnjko.
1867                 //
1868                 AcParam.longData = 0;
1869                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1870                 AcParam.f.AciAifsn.f.ACM = 0;
1871                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1872                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1873                 AcParam.f.TXOPLimit = 0;
1874
1875                 //lzm reserved 080826
1876 #if 1
1877                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1878                 if( ieee->current_network.Turbo_Enable == 1 )
1879                         AcParam.f.TXOPLimit = 0x01FF;
1880                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
1881                 if (ieee->iw_mode == IW_MODE_ADHOC)
1882                         AcParam.f.TXOPLimit = 0x0020;
1883 #endif
1884
1885                 for(eACI = 0; eACI < AC_MAX; eACI++)
1886                 {
1887                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1888                         {
1889                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1890                                 AC_CODING       eACI;
1891                                 u8              u1bAIFS;
1892                                 u32             u4bAcParam;
1893
1894                                 // Retrive paramters to udpate.
1895                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1896                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1897                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
1898                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1899                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1900                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1901
1902                                 switch(eACI)
1903                                 {
1904                                         case AC1_BK:
1905                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1906                                                 break;
1907
1908                                         case AC0_BE:
1909                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1910                                                 break;
1911
1912                                         case AC2_VI:
1913                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1914                                                 break;
1915
1916                                         case AC3_VO:
1917                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1918                                                 break;
1919
1920                                         default:
1921                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1922                                                 break;
1923                                 }
1924
1925                                 // Cehck ACM bit.
1926                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1927                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1928                                 {
1929                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1930                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1931
1932                                         //modified Joseph
1933                                         //for 8187B AsynIORead issue
1934 #ifdef TODO
1935                                         u8      AcmCtrl = pHalData->AcmControl;
1936 #else
1937                                         u8      AcmCtrl = 0;
1938 #endif
1939                                         if( pAciAifsn->f.ACM )
1940                                         { // ACM bit is 1.
1941                                                 switch(eACI)
1942                                                 {
1943                                                         case AC0_BE:
1944                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
1945                                                                 break;
1946
1947                                                         case AC2_VI:
1948                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
1949                                                                 break;
1950
1951                                                         case AC3_VO:
1952                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
1953                                                                 break;
1954
1955                                                         default:
1956                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1957                                                                 break;
1958                                                 }
1959                                         }
1960                                         else
1961                                         { // ACM bit is 0.
1962                                                 switch(eACI)
1963                                                 {
1964                                                         case AC0_BE:
1965                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
1966                                                                 break;
1967
1968                                                         case AC2_VI:
1969                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
1970                                                                 break;
1971
1972                                                         case AC3_VO:
1973                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
1974                                                                 break;
1975
1976                                                         default:
1977                                                                 break;
1978                                                 }
1979                                         }
1980
1981                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1982
1983 #ifdef TO_DO
1984                                         pHalData->AcmControl = AcmCtrl;
1985 #endif
1986                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1987                                         write_nic_byte(dev, ACM_CONTROL, 0);
1988                                 }
1989                         }
1990                 }
1991
1992
1993         }
1994 }
1995
1996 void
1997 ActSetWirelessMode8185(
1998         struct net_device *dev,
1999         u8                              btWirelessMode
2000         )
2001 {
2002         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2003         struct ieee80211_device *ieee = priv->ieee80211;
2004         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
2005         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2006
2007         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2008         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2009                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2010                         btWirelessMode, btSupportedWirelessMode);
2011                 return;
2012         }
2013
2014         // 1. Assign wireless mode to swtich if necessary.
2015         if (btWirelessMode == WIRELESS_MODE_AUTO)
2016         {
2017                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2018                 {
2019                         btWirelessMode = WIRELESS_MODE_A;
2020                 }
2021                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2022                 {
2023                         btWirelessMode = WIRELESS_MODE_G;
2024                 }
2025                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2026                 {
2027                         btWirelessMode = WIRELESS_MODE_B;
2028                 }
2029                 else
2030                 {
2031                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2032                                          btSupportedWirelessMode);
2033                         btWirelessMode = WIRELESS_MODE_B;
2034                 }
2035         }
2036
2037
2038         // 2. Swtich band: RF or BB specific actions,
2039         // for example, refresh tables in omc8255, or change initial gain if necessary.
2040         switch(priv->rf_chip)
2041         {
2042         case RF_ZEBRA2:
2043         case RF_ZEBRA4:
2044                 {
2045                         // Nothing to do for Zebra to switch band.
2046                         // Update current wireless mode if we swtich to specified band successfully.
2047                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
2048                 }
2049                 break;
2050
2051         default:
2052                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2053                 break;
2054         }
2055
2056         // 3. Change related setting.
2057         if( ieee->mode == WIRELESS_MODE_A ){
2058                 DMESG("WIRELESS_MODE_A\n");
2059         }
2060         else if( ieee->mode == WIRELESS_MODE_B ){
2061                 DMESG("WIRELESS_MODE_B\n");
2062         }
2063         else if( ieee->mode == WIRELESS_MODE_G ){
2064                 DMESG("WIRELESS_MODE_G\n");
2065         }
2066
2067         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2068 }
2069
2070 void rtl8185b_irq_enable(struct net_device *dev)
2071 {
2072         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2073
2074         priv->irq_enabled = 1;
2075         write_nic_dword(dev, IMR, priv->IntrMask);
2076 }
2077 //by amy for power save
2078 void
2079 DrvIFIndicateDisassociation(
2080         struct net_device *dev,
2081         u16                     reason
2082         )
2083 {
2084         //printk("==> DrvIFIndicateDisassociation()\n");
2085
2086         // nothing is needed after disassociation request.
2087
2088         //printk("<== DrvIFIndicateDisassociation()\n");
2089 }
2090 void
2091 MgntDisconnectIBSS(
2092         struct net_device *dev
2093 )
2094 {
2095         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2096         u8                      i;
2097
2098         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2099
2100         DrvIFIndicateDisassociation(dev, unspec_reason);
2101
2102 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2103         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
2104
2105         priv->ieee80211->state = IEEE80211_NOLINK;
2106
2107         //Stop Beacon.
2108
2109         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2110         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2111         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2112
2113         // Disable Beacon Queue Own bit, suggested by jong
2114 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2115         ieee80211_stop_send_beacons(priv->ieee80211);
2116
2117         priv->ieee80211->link_change(dev);
2118         notify_wx_assoc_event(priv->ieee80211);
2119
2120         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2121 #if 0
2122         if(pMgntInfo->bEnableSwBeaconTimer)
2123         {
2124                 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2125 // comment out by haich, 2007.10.01
2126 //#if DEV_BUS_TYPE==USB_INTERFACE
2127                 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2128 //#endif
2129         }
2130 #endif
2131
2132 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2133
2134 }
2135 void
2136 MlmeDisassociateRequest(
2137         struct net_device *dev,
2138         u8*                     asSta,
2139         u8                      asRsn
2140         )
2141 {
2142         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2143         u8 i;
2144
2145         SendDisassociation(priv->ieee80211, asSta, asRsn );
2146
2147         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2148                 //ShuChen TODO: change media status.
2149                 //ShuChen TODO: What to do when disassociate.
2150                 DrvIFIndicateDisassociation(dev, unspec_reason);
2151
2152
2153         //      pMgntInfo->AsocTimestamp = 0;
2154                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2155 //              pMgntInfo->mBrates.Length = 0;
2156 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2157
2158                 ieee80211_disassociate(priv->ieee80211);
2159
2160
2161         }
2162
2163 }
2164
2165 void
2166 MgntDisconnectAP(
2167         struct net_device *dev,
2168         u8                      asRsn
2169 )
2170 {
2171         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2172
2173 //
2174 // Commented out by rcnjko, 2005.01.27:
2175 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2176 //
2177 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2178 //      SecClearAllKeys(Adapter);
2179
2180         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2181 #ifdef TODO
2182         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2183                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2184         {
2185                 SecClearAllKeys(Adapter);
2186                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2187         }
2188 #endif
2189         // 2004.10.11, by rcnjko.
2190         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2191         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2192
2193         priv->ieee80211->state = IEEE80211_NOLINK;
2194 //      pMgntInfo->AsocTimestamp = 0;
2195 }
2196 bool
2197 MgntDisconnect(
2198         struct net_device *dev,
2199         u8                      asRsn
2200 )
2201 {
2202         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2203         //
2204         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2205         //
2206 #ifdef TODO
2207         if(pMgntInfo->mPss != eAwake)
2208         {
2209                 //
2210                 // Using AwkaeTimer to prevent mismatch ps state.
2211                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2212                 //
2213                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2214                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2215         }
2216 #endif
2217
2218         // Indication of disassociation event.
2219         //DrvIFIndicateDisassociation(Adapter, asRsn);
2220         if(IS_DOT11D_ENABLE(priv->ieee80211))
2221                 Dot11d_Reset(priv->ieee80211);
2222         // In adhoc mode, update beacon frame.
2223         if( priv->ieee80211->state == IEEE80211_LINKED )
2224         {
2225                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2226                 {
2227 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2228                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2229                         MgntDisconnectIBSS(dev);
2230                 }
2231                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2232                 {
2233                         // We clear key here instead of MgntDisconnectAP() because that
2234                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2235                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2236                         // used to handle disassociation related things to AP, e.g. send Disassoc
2237                         // frame to AP.  2005.01.27, by rcnjko.
2238 //                      SecClearAllKeys(Adapter);
2239
2240 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2241                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2242                         MgntDisconnectAP(dev, asRsn);
2243                 }
2244
2245                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2246 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2247         }
2248
2249         return true;
2250 }
2251 //
2252 //      Description:
2253 //              Chang RF Power State.
2254 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2255 //
2256 //      Assumption:
2257 //              PASSIVE LEVEL.
2258 //
2259 bool
2260 SetRFPowerState(
2261         struct net_device *dev,
2262         RT_RF_POWER_STATE       eRFPowerState
2263         )
2264 {
2265         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2266         bool                    bResult = false;
2267
2268 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2269         if(eRFPowerState == priv->eRFPowerState)
2270         {
2271 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2272                 return bResult;
2273         }
2274
2275         switch(priv->rf_chip)
2276         {
2277                 case RF_ZEBRA2:
2278                 case RF_ZEBRA4:
2279                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2280                         break;
2281
2282                 default:
2283                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2284                         break;;
2285 }
2286 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2287
2288         return bResult;
2289 }
2290 void
2291 HalEnableRx8185Dummy(
2292         struct net_device *dev
2293         )
2294 {
2295 }
2296 void
2297 HalDisableRx8185Dummy(
2298         struct net_device *dev
2299         )
2300 {
2301 }
2302
2303 bool
2304 MgntActSet_RF_State(
2305         struct net_device *dev,
2306         RT_RF_POWER_STATE       StateToSet,
2307         u32     ChangeSource
2308         )
2309 {
2310         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2311         bool                            bActionAllowed = false;
2312         bool                            bConnectBySSID = false;
2313         RT_RF_POWER_STATE       rtState;
2314         u16                             RFWaitCounter = 0;
2315         unsigned long flag;
2316 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2317         //
2318         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2319         // Only one thread can change the RF state at one time, and others should wait to be executed.
2320         //
2321 #if 1
2322         while(true)
2323         {
2324 //              down(&priv->rf_state);
2325                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2326                 if(priv->RFChangeInProgress)
2327                 {
2328 //                      printk("====================>haha111111111\n");
2329 //                      up(&priv->rf_state);
2330 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2331                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2332                         // Set RF after the previous action is done.
2333                         while(priv->RFChangeInProgress)
2334                         {
2335                                 RFWaitCounter ++;
2336 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2337                                 udelay(1000); // 1 ms
2338
2339                                 // Wait too long, return FALSE to avoid to be stuck here.
2340                                 if(RFWaitCounter > 1000) // 1sec
2341                                 {
2342 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2343                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2344                                         // TODO: Reset RF state?
2345                                         return false;
2346                                 }
2347                         }
2348                 }
2349                 else
2350                 {
2351 //                      printk("========================>haha2\n");
2352                         priv->RFChangeInProgress = true;
2353 //                      up(&priv->rf_state);
2354                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2355                         break;
2356                 }
2357         }
2358 #endif
2359         rtState = priv->eRFPowerState;
2360
2361
2362         switch(StateToSet)
2363         {
2364         case eRfOn:
2365                 //
2366                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2367                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2368                 //
2369                 priv->RfOffReason &= (~ChangeSource);
2370
2371                 if(! priv->RfOffReason)
2372                 {
2373                         priv->RfOffReason = 0;
2374                         bActionAllowed = true;
2375
2376                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2377                         {
2378                                 bConnectBySSID = true;
2379                         }
2380                 }
2381                 else
2382 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2383                         ;
2384                 break;
2385
2386         case eRfOff:
2387                  // 070125, rcnjko: we always keep connected in AP mode.
2388
2389                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2390                         {
2391                                 //
2392                                 // 060808, Annie:
2393                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2394                                 //
2395
2396                                 //
2397                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2398                                 // because we do NOT need to set ssid to dummy ones.
2399                                 // Revised by Roger, 2007.12.04.
2400                                 //
2401                                 MgntDisconnect( dev, disas_lv_ss );
2402
2403                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2404                                 // 2007.05.28, by shien chang.
2405 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2406 //                              pMgntInfo->NumBssDesc = 0;
2407 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2408 //                              pMgntInfo->NumBssDesc4Query = 0;
2409                         }
2410
2411
2412
2413                 priv->RfOffReason |= ChangeSource;
2414                 bActionAllowed = true;
2415                 break;
2416
2417         case eRfSleep:
2418                 priv->RfOffReason |= ChangeSource;
2419                 bActionAllowed = true;
2420                 break;
2421
2422         default:
2423                 break;
2424         }
2425
2426         if(bActionAllowed)
2427         {
2428 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2429                 // Config HW to the specified mode.
2430 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2431                 SetRFPowerState(dev, StateToSet);
2432
2433                 // Turn on RF.
2434                 if(StateToSet == eRfOn)
2435                 {
2436                         HalEnableRx8185Dummy(dev);
2437                         if(bConnectBySSID)
2438                         {
2439                         // by amy not supported
2440 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2441                         }
2442                 }
2443                 // Turn off RF.
2444                 else if(StateToSet == eRfOff)
2445                 {
2446                         HalDisableRx8185Dummy(dev);
2447                 }
2448         }
2449         else
2450         {
2451         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2452         }
2453
2454         // Release RF spinlock
2455 //      down(&priv->rf_state);
2456         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2457         priv->RFChangeInProgress = false;
2458 //      up(&priv->rf_state);
2459         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2460 //      printk("<===MgntActSet_RF_State()\n");
2461         return bActionAllowed;
2462 }
2463 void
2464 InactivePowerSave(
2465         struct net_device *dev
2466         )
2467 {
2468         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2469         //u8 index = 0;
2470
2471         //
2472         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2473         // is really scheduled.
2474         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2475         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2476         // blocks the IPS procedure of switching RF.
2477         // By Bruce, 2007-12-25.
2478         //
2479         priv->bSwRfProcessing = true;
2480
2481         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2482
2483         //
2484         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2485         //
2486 #if 0
2487         while( index < 4 )
2488         {
2489                 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2490                         (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2491                 {
2492                         if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2493                         pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2494
2495                 }
2496                 index++;
2497         }
2498 #endif
2499         priv->bSwRfProcessing = false;
2500 }
2501
2502 //
2503 //      Description:
2504 //              Enter the inactive power save mode. RF will be off
2505 //      2007.08.17, by shien chang.
2506 //
2507 void
2508 IPSEnter(
2509         struct net_device *dev
2510         )
2511 {
2512         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2513         RT_RF_POWER_STATE rtState;
2514         //printk("==============================>enter IPS\n");
2515         if (priv->bInactivePs)
2516         {
2517                 rtState = priv->eRFPowerState;
2518
2519                 //
2520                 // Added by Bruce, 2007-12-25.
2521                 // Do not enter IPS in the following conditions:
2522                 // (1) RF is already OFF or Sleep
2523                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2524                 // (3) Connectted (only disconnected can trigger IPS)
2525                 // (4) IBSS (send Beacon)
2526                 // (5) AP mode (send Beacon)
2527                 //
2528                 if (rtState == eRfOn && !priv->bSwRfProcessing
2529                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2530                 {
2531         //              printk("IPSEnter(): Turn off RF.\n");
2532                         priv->eInactivePowerState = eRfOff;
2533                         InactivePowerSave(dev);
2534                 }
2535         }
2536 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2537 }
2538 void
2539 IPSLeave(
2540         struct net_device *dev
2541         )
2542 {
2543         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2544         RT_RF_POWER_STATE rtState;
2545         //printk("===================================>leave IPS\n");
2546         if (priv->bInactivePs)
2547         {
2548                 rtState = priv->eRFPowerState;
2549                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2550                 {
2551 //                      printk("IPSLeave(): Turn on RF.\n");
2552                         priv->eInactivePowerState = eRfOn;
2553                         InactivePowerSave(dev);
2554                 }
2555         }
2556 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2557 }
2558 //by amy for power save
2559 void rtl8185b_adapter_start(struct net_device *dev)
2560 {
2561       struct r8180_priv *priv = ieee80211_priv(dev);
2562         struct ieee80211_device *ieee = priv->ieee80211;
2563
2564         u8 SupportedWirelessMode;
2565         u8                      InitWirelessMode;
2566         u8                      bInvalidWirelessMode = 0;
2567         //int i;
2568         u8 tmpu8;
2569         //u8 u1tmp,u2tmp;
2570         u8 btCR9346;
2571         u8 TmpU1b;
2572         u8 btPSR;
2573
2574         //rtl8180_rtx_disable(dev);
2575 //{by amy 080312
2576         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2577 //by amy 080312}
2578         rtl8180_reset(dev);
2579
2580         priv->dma_poll_mask = 0;
2581         priv->dma_poll_stop_mask = 0;
2582
2583         //rtl8180_beacon_tx_disable(dev);
2584
2585         HwConfigureRTL8185(dev);
2586
2587         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2588         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2589
2590         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2591
2592         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2593
2594         write_nic_word(dev, BcnItv, 100);
2595         write_nic_word(dev, AtimWnd, 2);
2596
2597         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2598         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2599
2600         write_nic_byte(dev, WPA_CONFIG, 0);
2601
2602         MacConfig_85BASIC(dev);
2603
2604         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2605         // BT_DEMO_BOARD type
2606         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2607 //by amy
2608 //#ifdef CONFIG_RTL818X_S
2609                 // for jong required
2610 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2611 //#endif
2612 //by amy
2613         //BT_QA_BOARD
2614         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2615
2616         //-----------------------------------------------------------------------------
2617         // Set up PHY related.
2618         //-----------------------------------------------------------------------------
2619         // Enable Config3.PARAM_En to revise AnaaParm.
2620         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2621 //by amy
2622         tmpu8 = read_nic_byte(dev, CONFIG3);
2623         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2624 //by amy
2625         // Turn on Analog power.
2626         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2627         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2628         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2629 //by amy
2630         write_nic_word(dev, ANAPARAM3, 0x0010);
2631 //by amy
2632
2633         write_nic_byte(dev, CONFIG3, tmpu8);
2634         write_nic_byte(dev, CR9346, 0x00);
2635 //{by amy 080312 for led
2636         // enable EEM0 and EEM1 in 9346CR
2637         btCR9346 = read_nic_byte(dev, CR9346);
2638         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2639
2640         // B cut use LED1 to control HW RF on/off
2641         TmpU1b = read_nic_byte(dev, CONFIG5);
2642         TmpU1b = TmpU1b & ~BIT3;
2643         write_nic_byte(dev,CONFIG5, TmpU1b);
2644
2645         // disable EEM0 and EEM1 in 9346CR
2646         btCR9346 &= ~(0xC0);
2647         write_nic_byte(dev, CR9346, btCR9346);
2648
2649         //Enable Led (suggested by Jong)
2650         // B-cut RF Radio on/off  5e[3]=0
2651         btPSR = read_nic_byte(dev, PSR);
2652         write_nic_byte(dev, PSR, (btPSR | BIT3));
2653 //by amy 080312 for led}
2654         // setup initial timing for RFE.
2655         write_nic_word(dev, RFPinsOutput, 0x0480);
2656         SetOutputEnableOfRfPins(dev);
2657         write_nic_word(dev, RFPinsSelect, 0x2488);
2658
2659         // PHY config.
2660         PhyConfig8185(dev);
2661
2662         // We assume RegWirelessMode has already been initialized before,
2663         // however, we has to validate the wireless mode here and provide a reasonble
2664         // initialized value if necessary. 2005.01.13, by rcnjko.
2665         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2666         if(     (ieee->mode != WIRELESS_MODE_B) &&
2667                 (ieee->mode != WIRELESS_MODE_G) &&
2668                 (ieee->mode != WIRELESS_MODE_A) &&
2669                 (ieee->mode != WIRELESS_MODE_AUTO))
2670         { // It should be one of B, G, A, or AUTO.
2671                 bInvalidWirelessMode = 1;
2672         }
2673         else
2674         { // One of B, G, A, or AUTO.
2675                 // Check if the wireless mode is supported by RF.
2676                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2677                         (ieee->mode & SupportedWirelessMode) == 0 )
2678                 {
2679                         bInvalidWirelessMode = 1;
2680                 }
2681         }
2682
2683         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2684         { // Auto or other invalid value.
2685                 // Assigne a wireless mode to initialize.
2686                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2687                 {
2688                         InitWirelessMode = WIRELESS_MODE_A;
2689                 }
2690                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2691                 {
2692                         InitWirelessMode = WIRELESS_MODE_G;
2693                 }
2694                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2695                 {
2696                         InitWirelessMode = WIRELESS_MODE_B;
2697                 }
2698                 else
2699                 {
2700                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2701                                  SupportedWirelessMode);
2702                         InitWirelessMode = WIRELESS_MODE_B;
2703                 }
2704
2705                 // Initialize RegWirelessMode if it is not a valid one.
2706                 if(bInvalidWirelessMode)
2707                 {
2708                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2709                 }
2710         }
2711         else
2712         { // One of B, G, A.
2713                 InitWirelessMode = ieee->mode;
2714         }
2715 //by amy for power save
2716 #ifdef ENABLE_IPS
2717 //      printk("initialize ENABLE_IPS\n");
2718         priv->eRFPowerState = eRfOff;
2719         priv->RfOffReason = 0;
2720         {
2721         //      u32 tmp2;
2722         //      u32 tmp = jiffies;
2723                 MgntActSet_RF_State(dev, eRfOn, 0);
2724         //      tmp2 = jiffies;
2725         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2726         }
2727 //      DrvIFIndicateCurrentPhyStatus(priv);
2728                 //
2729                 // If inactive power mode is enabled, disable rf while in disconnected state.
2730                 // 2007.07.16, by shien chang.
2731                 //
2732         if (priv->bInactivePs)
2733         {
2734         //      u32 tmp2;
2735         //      u32 tmp = jiffies;
2736                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2737         //      tmp2 = jiffies;
2738         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2739
2740         }
2741 #endif
2742 //      IPSEnter(dev);
2743 //by amy for power save
2744 #ifdef TODO
2745         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2746         // We shall turn off RF after setting CMDR, otherwise,
2747         // RF will be turnned on after we enable MAC Tx/Rx.
2748         if(Adapter->MgntInfo.RegRfOff == TRUE)
2749         {
2750                 SetRFPowerState8185(Adapter, RF_OFF);
2751         }
2752         else
2753         {
2754                 SetRFPowerState8185(Adapter, RF_ON);
2755         }
2756 #endif
2757
2758 /*   //these is equal with above TODO.
2759         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2760         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2761         RF_WriteReg(dev, 0x4, 0x9FF);
2762         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2763         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2764         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2765         write_nic_byte(dev, CR9346, 0x00);
2766 */
2767
2768         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2769
2770         //-----------------------------------------------------------------------------
2771
2772         rtl8185b_irq_enable(dev);
2773
2774         netif_start_queue(dev);
2775
2776  }
2777
2778
2779 void rtl8185b_rx_enable(struct net_device *dev)
2780 {
2781         u8 cmd;
2782         //u32 rxconf;
2783         /* for now we accept data, management & ctl frame*/
2784         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2785 #if 0
2786         rxconf=read_nic_dword(dev,RX_CONF);
2787         rxconf = rxconf &~ MAC_FILTER_MASK;
2788         rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
2789         rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
2790         rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
2791         rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
2792 //      rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2793         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2794
2795         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2796            dev->flags & IFF_PROMISC){
2797                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2798         }else{
2799                 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
2800                 if(priv->card_8185 == 0)
2801                         rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2802         }
2803
2804         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2805                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2806                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2807         }*/
2808
2809         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2810                 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
2811                 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
2812                 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
2813         }
2814
2815         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2816                 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2817
2818         //if(!priv->card_8185){
2819                 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
2820                 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
2821         //}
2822
2823         rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
2824         rxconf = rxconf &~ MAX_RX_DMA_MASK;
2825         rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
2826
2827         //if(!priv->card_8185)
2828                 rxconf = rxconf | RCR_ONLYERLPKT;
2829
2830         rxconf = rxconf &~ RCR_CS_MASK;
2831         if(!priv->card_8185)
2832                 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
2833 //      rxconf &=~ 0xfff00000;
2834 //      rxconf |= 0x90100000;//9014f76f;
2835         write_nic_dword(dev, RX_CONF, rxconf);
2836 #endif
2837
2838         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2839
2840         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2841            dev->flags & IFF_PROMISC){
2842                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2843                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2844         }
2845
2846         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2847                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2848                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2849         }*/
2850
2851         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2852                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2853         }
2854
2855         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2856                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2857
2858         write_nic_dword(dev, RCR, priv->ReceiveConfig);
2859
2860         fix_rx_fifo(dev);
2861
2862 #ifdef DEBUG_RX
2863         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2864 #endif
2865         cmd=read_nic_byte(dev,CMD);
2866         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2867
2868 }
2869
2870 void rtl8185b_tx_enable(struct net_device *dev)
2871 {
2872         u8 cmd;
2873         //u8 tx_agc_ctl;
2874         u8 byte;
2875         //u32 txconf;
2876         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2877
2878 #if 0
2879         txconf= read_nic_dword(dev,TX_CONF);
2880         if(priv->card_8185){
2881
2882
2883                 byte = read_nic_byte(dev,CW_CONF);
2884                 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
2885                 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
2886                 write_nic_byte(dev, CW_CONF, byte);
2887
2888                 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
2889                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
2890                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
2891                 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
2892                 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
2893                 /*
2894                 write_nic_word(dev, 0x5e, 0x01);
2895                 force_pci_posting(dev);
2896                 mdelay(1);
2897                 write_nic_word(dev, 0xfe, 0x10);
2898                 force_pci_posting(dev);
2899                 mdelay(1);
2900                 write_nic_word(dev, 0x5e, 0x00);
2901                 force_pci_posting(dev);
2902                 mdelay(1);
2903                 */
2904                 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
2905         }
2906
2907         if(priv->card_8185){
2908
2909                 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
2910
2911         }else{
2912
2913                 if(hwseqnum)
2914                         txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
2915                 else
2916                         txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
2917         }
2918
2919         txconf = txconf &~ TX_LOOPBACK_MASK;
2920         txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
2921         txconf = txconf &~ TCR_DPRETRY_MASK;
2922         txconf = txconf &~ TCR_RTSRETRY_MASK;
2923         txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
2924         txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
2925         txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
2926
2927         if(priv->card_8185){
2928                 if(priv->hw_plcp_len)
2929                         txconf = txconf &~ TCR_PLCP_LEN;
2930                 else
2931                         txconf = txconf | TCR_PLCP_LEN;
2932         }else{
2933                 txconf = txconf &~ TCR_SAT;
2934         }
2935         txconf = txconf &~ TCR_MXDMA_MASK;
2936         txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
2937         txconf = txconf | TCR_CWMIN;
2938         txconf = txconf | TCR_DISCW;
2939
2940 //      if(priv->ieee80211->hw_wep)
2941 //              txconf=txconf &~ (1<<TX_NOICV_SHIFT);
2942 //      else
2943                 txconf=txconf | (1<<TX_NOICV_SHIFT);
2944
2945         write_nic_dword(dev,TX_CONF,txconf);
2946 #endif
2947
2948         write_nic_dword(dev, TCR, priv->TransmitConfig);
2949         byte = read_nic_byte(dev, MSR);
2950         byte |= MSR_LINK_ENEDCA;
2951         write_nic_byte(dev, MSR, byte);
2952
2953         fix_tx_fifo(dev);
2954
2955 #ifdef DEBUG_TX
2956         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2957 #endif
2958
2959         cmd=read_nic_byte(dev,CMD);
2960         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2961
2962         //write_nic_dword(dev,TX_CONF,txconf);
2963
2964
2965 /*
2966         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2967         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2968         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2969         */
2970 }
2971
2972