SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #include "r8180_pm.h"
  34
  35 #include "ieee80211/dot11d.h"
  36
  37 #ifdef CONFIG_RTL8185B
  38
  39 //#define CONFIG_RTL8180_IO_MAP
  40
  41 #define TC_3W_POLL_MAX_TRY_CNT 5
  42 static u8 MAC_REG_TABLE[][2]={
  43                         //PAGA 0:
  44                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  45                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  46                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  47                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  48                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  49                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  50                         {0x94, 0x0F}, {0x95, 0x32},
  51                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  52                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  53                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  54                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  55                         {0xff, 0x00},
  56
  57                         //PAGE 1:
  58                         // For Flextronics system Logo PCIHCT failure:
  59                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  60                         {0x5e, 0x01},
  61                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  62                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  63                         {0x82, 0xFF}, {0x83, 0x03},
  64                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  65                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  66                         {0xe2, 0x00},
  67
  68
  69                         //PAGE 2:
  70                         {0x5e, 0x02},
  71                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  72                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  73                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  74                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  75                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  76                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  77                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  78
  79                         //PAGA 0:
  80                         {0x5e, 0x00},{0x9f, 0x03}
  81                 };
  82
  83
  84 static u8  ZEBRA_AGC[]={
  85                         0,
  86                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  87                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  88                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  89                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  90                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  91                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  92                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  93                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  94                         };
  95
  96 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  97                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  98                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  99                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
 100                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 101                         0x0183,0x0163,0x0143,0x0123,0x0103
 102         };
 103
 104 static u8 OFDM_CONFIG[]={
 105                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 106                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 107                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 108
 109                         // 0x00
 110                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 111                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 112                         // 0x10
 113                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 114                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 115                         // 0x20
 116                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 117                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 118                         // 0x30
 119                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 120                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 121                 };
 122
 123 /*---------------------------------------------------------------
 124   * Hardware IO
 125   * the code is ported from Windows source code
 126   ----------------------------------------------------------------*/
 127
 128 void
 129 PlatformIOWrite1Byte(
 130         struct net_device *dev,
 131         u32             offset,
 132         u8              data
 133         )
 134 {
 135 #ifndef CONFIG_RTL8180_IO_MAP
 136         write_nic_byte(dev, offset, data);
 137         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 138
 139 #else // Port IO
 140         u32 Page = (offset >> 8);
 141
 142         switch(Page)
 143         {
 144         case 0: // Page 0
 145                 write_nic_byte(dev, offset, data);
 146                 break;
 147
 148         case 1: // Page 1
 149         case 2: // Page 2
 150         case 3: // Page 3
 151                 {
 152                         u8 psr = read_nic_byte(dev, PSR);
 153
 154                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 155                         write_nic_byte(dev, (offset & 0xff), data);
 156                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 157                 }
 158                 break;
 159
 160         default:
 161                 // Illegal page number.
 162                 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 163                 break;
 164         }
 165 #endif
 166 }
 167
 168 void
 169 PlatformIOWrite2Byte(
 170         struct net_device *dev,
 171         u32             offset,
 172         u16             data
 173         )
 174 {
 175 #ifndef CONFIG_RTL8180_IO_MAP
 176         write_nic_word(dev, offset, data);
 177         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 178
 179
 180 #else // Port IO
 181         u32 Page = (offset >> 8);
 182
 183         switch(Page)
 184         {
 185         case 0: // Page 0
 186                 write_nic_word(dev, offset, data);
 187                 break;
 188
 189         case 1: // Page 1
 190         case 2: // Page 2
 191         case 3: // Page 3
 192                 {
 193                         u8 psr = read_nic_byte(dev, PSR);
 194
 195                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 196                         write_nic_word(dev, (offset & 0xff), data);
 197                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 198                 }
 199                 break;
 200
 201         default:
 202                 // Illegal page number.
 203                 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 204                 break;
 205         }
 206 #endif
 207 }
 208 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 209
 210 void
 211 PlatformIOWrite4Byte(
 212         struct net_device *dev,
 213         u32             offset,
 214         u32             data
 215         )
 216 {
 217 #ifndef CONFIG_RTL8180_IO_MAP
 218 //{by amy 080312
 219 if (offset == PhyAddr)
 220         {//For Base Band configuration.
 221                 unsigned char   cmdByte;
 222                 unsigned long   dataBytes;
 223                 unsigned char   idx;
 224                 u8      u1bTmp;
 225
 226                 cmdByte = (u8)(data & 0x000000ff);
 227                 dataBytes = data>>8;
 228
 229                 //
 230                 // 071010, rcnjko:
 231                 // The critical section is only BB read/write race condition.
 232                 // Assumption:
 233                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 234                 // acquiring the spinlock in such context.
 235                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 236                 //
 237 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 238
 239                 for(idx = 0; idx < 30; idx++)
 240                 { // Make sure command bit is clear before access it.
 241                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 242                         if((u1bTmp & BIT7) == 0)
 243                                 break;
 244                         else
 245                                 mdelay(10);
 246                 }
 247
 248                 for(idx=0; idx < 3; idx++)
 249                 {
 250                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 251                 }
 252                 write_nic_byte(dev, offset, cmdByte);
 253
 254 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 255         }
 256 //by amy 080312}
 257         else{
 258                 write_nic_dword(dev, offset, data);
 259                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 260         }
 261 #else // Port IO
 262         u32 Page = (offset >> 8);
 263
 264         switch(Page)
 265         {
 266         case 0: // Page 0
 267                 write_nic_word(dev, offset, data);
 268                 break;
 269
 270         case 1: // Page 1
 271         case 2: // Page 2
 272         case 3: // Page 3
 273                 {
 274                         u8 psr = read_nic_byte(dev, PSR);
 275
 276                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 277                         write_nic_dword(dev, (offset & 0xff), data);
 278                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 279                 }
 280                 break;
 281
 282         default:
 283                 // Illegal page number.
 284                 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
 285                 break;
 286         }
 287 #endif
 288 }
 289
 290 u8
 291 PlatformIORead1Byte(
 292         struct net_device *dev,
 293         u32             offset
 294         )
 295 {
 296         u8      data = 0;
 297
 298 #ifndef CONFIG_RTL8180_IO_MAP
 299         data = read_nic_byte(dev, offset);
 300
 301 #else // Port IO
 302         u32 Page = (offset >> 8);
 303
 304         switch(Page)
 305         {
 306         case 0: // Page 0
 307                 data = read_nic_byte(dev, offset);
 308                 break;
 309
 310         case 1: // Page 1
 311         case 2: // Page 2
 312         case 3: // Page 3
 313                 {
 314                         u8 psr = read_nic_byte(dev, PSR);
 315
 316                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 317                         data = read_nic_byte(dev, (offset & 0xff));
 318                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 319                 }
 320                 break;
 321
 322         default:
 323                 // Illegal page number.
 324                 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 325                 break;
 326         }
 327 #endif
 328
 329         return data;
 330 }
 331
 332 u16
 333 PlatformIORead2Byte(
 334         struct net_device *dev,
 335         u32             offset
 336         )
 337 {
 338         u16     data = 0;
 339
 340 #ifndef CONFIG_RTL8180_IO_MAP
 341         data = read_nic_word(dev, offset);
 342
 343 #else // Port IO
 344         u32 Page = (offset >> 8);
 345
 346         switch(Page)
 347         {
 348         case 0: // Page 0
 349                 data = read_nic_word(dev, offset);
 350                 break;
 351
 352         case 1: // Page 1
 353         case 2: // Page 2
 354         case 3: // Page 3
 355                 {
 356                         u8 psr = read_nic_byte(dev, PSR);
 357
 358                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 359                         data = read_nic_word(dev, (offset & 0xff));
 360                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 361                 }
 362                 break;
 363
 364         default:
 365                 // Illegal page number.
 366                 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 367                 break;
 368         }
 369 #endif
 370
 371         return data;
 372 }
 373
 374 u32
 375 PlatformIORead4Byte(
 376         struct net_device *dev,
 377         u32             offset
 378         )
 379 {
 380         u32     data = 0;
 381
 382 #ifndef CONFIG_RTL8180_IO_MAP
 383         data = read_nic_dword(dev, offset);
 384
 385 #else // Port IO
 386         u32 Page = (offset >> 8);
 387
 388         switch(Page)
 389         {
 390         case 0: // Page 0
 391                 data = read_nic_dword(dev, offset);
 392                 break;
 393
 394         case 1: // Page 1
 395         case 2: // Page 2
 396         case 3: // Page 3
 397                 {
 398                         u8 psr = read_nic_byte(dev, PSR);
 399
 400                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 401                         data = read_nic_dword(dev, (offset & 0xff));
 402                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 403                 }
 404                 break;
 405
 406         default:
 407                 // Illegal page number.
 408                 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
 409                 break;
 410         }
 411 #endif
 412
 413         return data;
 414 }
 415
 416 void
 417 SetOutputEnableOfRfPins(
 418         struct net_device *dev
 419         )
 420 {
 421         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 422
 423         switch(priv->rf_chip)
 424         {
 425         case RFCHIPID_RTL8225:
 426         case RF_ZEBRA2:
 427         case RF_ZEBRA4:
 428                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 429                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 430                 break;
 431         }
 432 }
 433
 434 void
 435 ZEBRA_RFSerialWrite(
 436         struct net_device *dev,
 437         u32                     data2Write,
 438         u8                      totalLength,
 439         u8                      low2high
 440         )
 441 {
 442         ThreeWireReg            twreg;
 443         int                             i;
 444         u16                             oval,oval2,oval3;
 445         u32                             mask;
 446         u16                             UshortBuffer;
 447
 448         u8                      u1bTmp;
 449         // RTL8187S HSSI Read/Write Function
 450         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 451         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 452         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 453         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 454         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 455
 456         oval2 = read_nic_word(dev, RFPinsEnable);
 457         oval3 = read_nic_word(dev, RFPinsSelect);
 458
 459         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 460         oval3 &= 0xfff8;
 461
 462         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 463         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 464         udelay(10);
 465
 466         // Add this to avoid hardware and software 3-wire conflict.
 467         // 2005.03.01, by rcnjko.
 468         twreg.longData = 0;
 469         twreg.struc.enableB = 1;
 470         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 471         udelay(2);
 472         twreg.struc.enableB = 0;
 473         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 474         udelay(10);
 475
 476         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 477
 478         for(i=0; i<totalLength/2; i++)
 479         {
 480                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 481                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 482                 twreg.struc.clk = 1;
 483                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 484                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 485
 486                 mask = (low2high)?(mask<<1):(mask>>1);
 487                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 488                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 489                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 490                 twreg.struc.clk = 0;
 491                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 492                 mask = (low2high)?(mask<<1):(mask>>1);
 493         }
 494
 495         twreg.struc.enableB = 1;
 496         twreg.struc.clk = 0;
 497         twreg.struc.data = 0;
 498         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 499         udelay(10);
 500
 501         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 502         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 503
 504         SetOutputEnableOfRfPins(dev);
 505 }
 506 //by amy
 507
 508
 509 int
 510 HwHSSIThreeWire(
 511         struct net_device *dev,
 512         u8                      *pDataBuf,
 513         u8                      nDataBufBitCnt,
 514         int                     bSI,
 515         int                     bWrite
 516         )
 517 {
 518         int     bResult = 1;
 519         u8      TryCnt;
 520         u8      u1bTmp;
 521
 522         do
 523         {
 524                 // Check if WE and RE are cleared.
 525                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 526                 {
 527                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 528                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 529                         {
 530                                 break;
 531                         }
 532                         udelay(10);
 533                 }
 534                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 535                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 536
 537                 // RTL8187S HSSI Read/Write Function
 538                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 539
 540                 if(bSI)
 541                 {
 542                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 543                 }else
 544                 {
 545                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 546                 }
 547
 548                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 549
 550                 if(bSI)
 551                 {
 552                         // jong: HW SI read must set reg84[3]=0.
 553                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 554                         u1bTmp &= ~BIT3;
 555                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 556                 }
 557                 // Fill up data buffer for write operation.
 558
 559                 if(bWrite)
 560                 {
 561                         if(nDataBufBitCnt == 16)
 562                         {
 563                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 564                         }
 565                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 566                         {
 567                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 568                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 569                         }
 570                         else
 571                         {
 572                                 int idx;
 573                                 int ByteCnt = nDataBufBitCnt / 8;
 574                                 //printk("%d\n",nDataBufBitCnt);
 575                                 if ((nDataBufBitCnt % 8) != 0)
 576                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 577                                 nDataBufBitCnt);
 578
 579                                if (nDataBufBitCnt > 64)
 580                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 581                                 nDataBufBitCnt);
 582
 583                                 for(idx = 0; idx < ByteCnt; idx++)
 584                                 {
 585                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 586                                 }
 587                         }
 588                 }
 589                 else            //read
 590                 {
 591                         if(bSI)
 592                         {
 593                                 // SI - reg274[3:0] : RF register's Address
 594                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 595                         }
 596                         else
 597                         {
 598                                 // PI - reg274[15:12] : RF register's Address
 599                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 600                         }
 601                 }
 602
 603                 // Set up command: WE or RE.
 604                 if(bWrite)
 605                 {
 606                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 607                 }
 608                 else
 609                 {
 610                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 611                 }
 612
 613                 // Check if DONE is set.
 614                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 615                 {
 616                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 617                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 618                         {
 619                                 break;
 620                         }
 621                         udelay(10);
 622                 }
 623
 624                 write_nic_byte(dev, SW_3W_CMD1, 0);
 625
 626                 // Read back data for read operation.
 627                 if(bWrite == 0)
 628                 {
 629                         if(bSI)
 630                         {
 631                                 //Serial Interface : reg363_362[11:0]
 632                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 633                         }
 634                         else
 635                         {
 636                                 //Parallel Interface : reg361_360[11:0]
 637                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 638                         }
 639
 640                         *((u16*)pDataBuf) &= 0x0FFF;
 641                 }
 642
 643         }while(0);
 644
 645         return bResult;
 646 }
 647 //by amy
 648
 649 int
 650 HwThreeWire(
 651         struct net_device *dev,
 652         u8                      *pDataBuf,
 653         u8                      nDataBufBitCnt,
 654         int                     bHold,
 655         int                     bWrite
 656         )
 657 {
 658         int     bResult = 1;
 659         u8      TryCnt;
 660         u8      u1bTmp;
 661
 662         do
 663         {
 664                 // Check if WE and RE are cleared.
 665                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 666                 {
 667                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 668                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 669                         {
 670                                 break;
 671                         }
 672                         udelay(10);
 673                 }
 674                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 675                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 676
 677                 // Fill up data buffer for write operation.
 678                 if(nDataBufBitCnt == 16)
 679                 {
 680                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 681                 }
 682                 else if(nDataBufBitCnt == 64)
 683                 {
 684                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 685                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 686                 }
 687                 else
 688                 {
 689                         int idx;
 690                         int ByteCnt = nDataBufBitCnt / 8;
 691
 692                         if ((nDataBufBitCnt % 8) != 0)
 693                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 694                                 nDataBufBitCnt);
 695
 696                         if (nDataBufBitCnt > 64)
 697                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 698                                 nDataBufBitCnt);
 699
 700                         for(idx = 0; idx < ByteCnt; idx++)
 701                         {
 702                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 703                         }
 704                 }
 705
 706                 // Fill up length field.
 707                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 708                 if(bHold)
 709                         u1bTmp |= SW_3W_CMD0_HOLD;
 710                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 711
 712                 // Set up command: WE or RE.
 713                 if(bWrite)
 714                 {
 715                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 716                 }
 717                 else
 718                 {
 719                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 720                 }
 721
 722                 // Check if WE and RE are cleared and DONE is set.
 723                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 724                 {
 725                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 726                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 727                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 728                         {
 729                                 break;
 730                         }
 731                         udelay(10);
 732                 }
 733                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 734                 {
 735                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 736                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 737                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 738                         write_nic_byte(dev, SW_3W_CMD1, 0);
 739                 }
 740
 741                 // Read back data for read operation.
 742                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 743                 if(bWrite == 0)
 744                 {
 745                         if(nDataBufBitCnt == 16)
 746                         {
 747                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 748                         }
 749                         else if(nDataBufBitCnt == 64)
 750                         {
 751                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 752                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 753                         }
 754                         else
 755                         {
 756                                 int idx;
 757                                 int ByteCnt = nDataBufBitCnt / 8;
 758
 759                                 if ((nDataBufBitCnt % 8) != 0)
 760                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 761                                         nDataBufBitCnt);
 762
 763                                 if (nDataBufBitCnt > 64)
 764                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 765                                         nDataBufBitCnt);
 766
 767                                 for(idx = 0; idx < ByteCnt; idx++)
 768                                 {
 769                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 770                                 }
 771                         }
 772                 }
 773
 774         }while(0);
 775
 776         return bResult;
 777 }
 778
 779
 780 void
 781 RF_WriteReg(
 782         struct net_device *dev,
 783         u8              offset,
 784         u32             data
 785         )
 786 {
 787         //RFReg                 reg;
 788         u32                     data2Write;
 789         u8                      len;
 790         u8                      low2high;
 791         //u32                   RF_Read = 0;
 792         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 793
 794
 795         switch(priv->rf_chip)
 796         {
 797         case RFCHIPID_RTL8225:
 798         case RF_ZEBRA2:         // Annie 2006-05-12.
 799         case RF_ZEBRA4:        //by amy
 800                 switch(priv->RegThreeWireMode)
 801                 {
 802                 case SW_THREE_WIRE:
 803                         { // Perform SW 3-wire programming by driver.
 804                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 805                                 len = 16;
 806                                 low2high = 0;
 807                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 808                         }
 809                         break;
 810
 811                 case HW_THREE_WIRE:
 812                         { // Pure HW 3-wire.
 813                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 814                                 len = 16;
 815                                 HwThreeWire(
 816                                         dev,
 817                                         (u8 *)(&data2Write),    // pDataBuf,
 818                                         len,                            // nDataBufBitCnt,
 819                                         0,                                      // bHold,
 820                                         1);                                     // bWrite
 821                         }
 822                         break;
 823                         case HW_THREE_WIRE_PI: //Parallel Interface
 824                         { // Pure HW 3-wire.
 825                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 826                                 len = 16;
 827                                         HwHSSIThreeWire(
 828                                                 dev,
 829                                                 (u8*)(&data2Write),     // pDataBuf,
 830                                                 len,                                            // nDataBufBitCnt,
 831                                                 0,                                      // bSI
 832                                                 1);                                     // bWrite
 833
 834                                 //printk("33333\n");
 835                         }
 836                         break;
 837
 838                         case HW_THREE_WIRE_SI: //Serial Interface
 839                         { // Pure HW 3-wire.
 840                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 841                                 len = 16;
 842 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 843 //                                low2high = 0;
 844 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 845
 846                                 HwHSSIThreeWire(
 847                                         dev,
 848                                         (u8*)(&data2Write),     // pDataBuf,
 849                                         len,                                            // nDataBufBitCnt,
 850                                         1,                                      // bSI
 851                                         1);                                     // bWrite
 852
 853 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 854                         }
 855                         break;
 856
 857
 858                 default:
 859                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 860                         break;
 861                 }
 862                 break;
 863
 864         default:
 865                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 866                 break;
 867         }
 868 }
 869
 870
 871 void
 872 ZEBRA_RFSerialRead(
 873         struct net_device *dev,
 874         u32             data2Write,
 875         u8              wLength,
 876         u32             *data2Read,
 877         u8              rLength,
 878         u8              low2high
 879         )
 880 {
 881         ThreeWireReg    twreg;
 882         int                             i;
 883         u16                     oval,oval2,oval3,tmp, wReg80;
 884         u32                     mask;
 885         u8                      u1bTmp;
 886         ThreeWireReg    tdata;
 887         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 888         { // RTL8187S HSSI Read/Write Function
 889                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 890                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 891                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 892         }
 893
 894         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 895         oval2 = read_nic_word(dev, RFPinsEnable);
 896         oval3 = read_nic_word(dev, RFPinsSelect);
 897
 898         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 899         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 900
 901         *data2Read = 0;
 902
 903         // We must clear BIT0-3 here, otherwise,
 904         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 905         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 906         oval &= ~0xf;
 907
 908         // Avoid collision with hardware three-wire.
 909         twreg.longData = 0;
 910         twreg.struc.enableB = 1;
 911         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 912
 913         twreg.longData = 0;
 914         twreg.struc.enableB = 0;
 915         twreg.struc.clk = 0;
 916         twreg.struc.read_write = 0;
 917         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 918
 919         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 920         for(i = 0; i < wLength/2; i++)
 921         {
 922                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 923                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 924                 twreg.struc.clk = 1;
 925                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 926                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 927
 928                 mask = (low2high) ? (mask<<1): (mask>>1);
 929
 930                 if(i == 2)
 931                 {
 932                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 933                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 934                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 935
 936                         twreg.struc.read_write=1;
 937                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 938                         twreg.struc.clk = 0;
 939                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 940                         break;
 941                 }
 942                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 943                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 944                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 945
 946                 twreg.struc.clk = 0;
 947                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 948
 949                 mask = (low2high) ? (mask<<1) : (mask>>1);
 950         }
 951
 952         twreg.struc.clk = 0;
 953         twreg.struc.data = 0;
 954         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 955         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 956
 957         //
 958         // 061016, by rcnjko:
 959         // We must set data pin to HW controled, otherwise RF can't driver it and
 960         // value RF register won't be able to read back properly.
 961         //
 962         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 963
 964         for(i = 0; i < rLength; i++)
 965         {
 966                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 967                 twreg.struc.clk = 1;
 968                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 969                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 970                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 971                 tmp = read_nic_word(dev, RFPinsInput);
 972                 tdata.longData = tmp;
 973                 *data2Read |= tdata.struc.clk ? mask : 0;
 974
 975                 twreg.struc.clk = 0;
 976                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 977
 978                 mask = (low2high) ? (mask<<1) : (mask>>1);
 979         }
 980         twreg.struc.enableB = 1;
 981         twreg.struc.clk = 0;
 982         twreg.struc.data = 0;
 983         twreg.struc.read_write = 1;
 984         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 985
 986         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 987         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 988         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 989         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 990         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 991         write_nic_word(dev, RFPinsOutput, 0x3a0);
 992         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 993 }
 994
 995
 996 u32
 997 RF_ReadReg(
 998         struct net_device *dev,
 999         u8              offset
1000         )
1001 {
1002         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1003         u32                     data2Write;
1004         u8                      wlen;
1005         u8                      rlen;
1006         u8                      low2high;
1007         u32                     dataRead;
1008
1009         switch(priv->rf_chip)
1010         {
1011         case RFCHIPID_RTL8225:
1012         case RF_ZEBRA2:
1013         case RF_ZEBRA4:
1014                 switch(priv->RegThreeWireMode)
1015                 {
1016                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
1017                         {
1018                                 data2Write = ((u32)(offset&0x0f));
1019                                 wlen=16;
1020                                 HwHSSIThreeWire(
1021                                         dev,
1022                                         (u8*)(&data2Write),     // pDataBuf,
1023                                         wlen,                                   // nDataBufBitCnt,
1024                                         0,                                      // bSI
1025                                         0);                                     // bWrite
1026                                 dataRead= data2Write;
1027                         }
1028                         break;
1029
1030                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1031                         {
1032                                 data2Write = ((u32)(offset&0x0f)) ;
1033                                 wlen=16;
1034                                 HwHSSIThreeWire(
1035                                         dev,
1036                                         (u8*)(&data2Write),     // pDataBuf,
1037                                         wlen,                                   // nDataBufBitCnt,
1038                                         1,                                      // bSI
1039                                         0                                       // bWrite
1040                                         );
1041                                 dataRead= data2Write;
1042                         }
1043                         break;
1044
1045                         // Perform SW 3-wire programming by driver.
1046                         default:
1047                         {
1048                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1049                                 wlen = 6;
1050                                 rlen = 12;
1051                                 low2high = 0;
1052                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1053                         }
1054                         break;
1055                 }
1056                 break;
1057         default:
1058                 dataRead = 0;
1059                 break;
1060         }
1061
1062         return dataRead;
1063 }
1064
1065
1066 // by Owen on 04/07/14 for writing BB register successfully
1067 void
1068 WriteBBPortUchar(
1069         struct net_device *dev,
1070         u32             Data
1071         )
1072 {
1073         //u8    TimeoutCounter;
1074         u8      RegisterContent;
1075         u8      UCharData;
1076
1077         UCharData = (u8)((Data & 0x0000ff00) >> 8);
1078         PlatformIOWrite4Byte(dev, PhyAddr, Data);
1079         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1080         {
1081                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1082                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1083                 //if(UCharData == RegisterContent)
1084                 //      break;
1085         }
1086 }
1087
1088 u8
1089 ReadBBPortUchar(
1090         struct net_device *dev,
1091         u32             addr
1092         )
1093 {
1094         //u8    TimeoutCounter;
1095         u8      RegisterContent;
1096
1097         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1098         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1099
1100         return RegisterContent;
1101 }
1102 //{by amy 080312
1103 //
1104 //      Description:
1105 //              Perform Antenna settings with antenna diversity on 87SE.
1106 //    Created by Roger, 2008.01.25.
1107 //
1108 bool
1109 SetAntennaConfig87SE(
1110         struct net_device *dev,
1111         u8                      DefaultAnt,             // 0: Main, 1: Aux.
1112         bool            bAntDiversity   // 1:Enable, 0: Disable.
1113 )
1114 {
1115         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1116         bool   bAntennaSwitched = true;
1117
1118         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1119
1120         // Threshold for antenna diversity.
1121         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1122
1123         if( bAntDiversity )  //  Enable Antenna Diversity.
1124         {
1125                 if( DefaultAnt == 1 )  // aux antenna
1126                 {
1127                         // Mac register, aux antenna
1128                         write_nic_byte(dev, ANTSEL, 0x00);
1129
1130                         // Config CCK RX antenna.
1131                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1132                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1133
1134                         // Config OFDM RX antenna.
1135                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1136                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1137                 }
1138                 else //  use main antenna
1139                 {
1140                         // Mac register, main antenna
1141                         write_nic_byte(dev, ANTSEL, 0x03);
1142                         //base band
1143                         // Config CCK RX antenna.
1144                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1145                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1146
1147                         // Config OFDM RX antenna.
1148                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1149                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1150                 }
1151         }
1152         else   // Disable Antenna Diversity.
1153         {
1154                 if( DefaultAnt == 1 ) // aux Antenna
1155                 {
1156                         // Mac register, aux antenna
1157                         write_nic_byte(dev, ANTSEL, 0x00);
1158
1159                         // Config CCK RX antenna.
1160                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1161                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1162
1163                         // Config OFDM RX antenna.
1164                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1165                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1166                 }
1167                 else // main Antenna
1168                 {
1169                         // Mac register, main antenna
1170                         write_nic_byte(dev, ANTSEL, 0x03);
1171
1172                         // Config CCK RX antenna.
1173                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1174                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1175
1176                         // Config OFDM RX antenna.
1177                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1178                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1179                 }
1180         }
1181         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1182         return  bAntennaSwitched;
1183 }
1184 //by amy 080312
1185 /*---------------------------------------------------------------
1186   * Hardware Initialization.
1187   * the code is ported from Windows source code
1188   ----------------------------------------------------------------*/
1189
1190 void
1191 ZEBRA_Config_85BASIC_HardCode(
1192         struct net_device *dev
1193         )
1194 {
1195
1196         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1197         u32                     i;
1198         u32     addr,data;
1199         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1200        u8                       u1b24E;
1201
1202
1203         //=============================================================================
1204         // 87S_PCIE :: RADIOCFG.TXT
1205         //=============================================================================
1206
1207
1208         // Page1 : reg16-reg30
1209         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1210         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1211         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1212
1213         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1214                 priv->card_8185 = VERSION_8187S_D;
1215
1216         // Page0 : reg0-reg15
1217
1218 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1219         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1220
1221         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1222
1223 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1224         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1225
1226 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1227         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1228
1229         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1230         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1231         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1232         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1233         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1234         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1235         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1236         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1237         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1238         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1239         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1240         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1241
1242
1243         // Page1 : reg16-reg30
1244         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1245
1246         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1247
1248         if(priv->card_8185 < VERSION_8187S_C)
1249         {
1250                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1251                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1252                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1253         }
1254         else
1255         {
1256                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1257                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1258                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1259         }
1260
1261
1262         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1263 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1264 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1265 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1266         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1267         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1268
1269         if(priv->card_8185 == VERSION_8187S_D)
1270         {
1271                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1272                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1273                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1274         }
1275         else
1276         {
1277                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1278                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1279                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1280         }
1281
1282         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1283
1284 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1285         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1286
1287         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1288         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1289         for(i=0;i<=36;i++)
1290         {
1291                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1292                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1293                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1294         }
1295
1296         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1297         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1298         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1299
1300         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1301         mdelay(10);     // Deay 10 ms. //0xfd
1302
1303 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1304         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1305         //mdelay(10);   // Deay 10 ms. //0xfd
1306
1307         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1308         mdelay(10);     // Deay 10 ms. //0xfd
1309
1310         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1311         mdelay(10);     // Deay 10 ms. //0xfd
1312
1313         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1314         mdelay(10);     // Deay 10 ms. //0xfd
1315
1316         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1317         mdelay(10);     // Deay 10 ms. //0xfd
1318
1319         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1320         mdelay(200);    // Deay 200 ms. //0xfd
1321         mdelay(10);     // Deay 10 ms. //0xfd
1322         mdelay(10);     // Deay 10 ms. //0xfd
1323
1324         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1325         mdelay(10);     // Deay 10 ms. //0xfd
1326
1327         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1328         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1329         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1330         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1331
1332         // DAC calibration off 20070702
1333         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1334         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1335 //{by amy 080312
1336         // For crystal calibration, added by Roger, 2007.12.11.
1337         if( priv->bXtalCalibration ) // reg 30.
1338         { // enable crystal calibration.
1339                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1340                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1341                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1342                 // So we should minus 4 BITs offset.
1343                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1344                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1345                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1346         }
1347         else
1348         { // using default value. Xin=6, Xout=6.
1349                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1350         }
1351 //by amy 080312
1352 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1353
1354         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1355 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1356         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1357         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1358         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1359         mdelay(10);     // Deay 10 ms. //0xfe
1360         mdelay(10);     // Deay 10 ms. //0xfe
1361         mdelay(10);     // Deay 10 ms. //0xfe
1362         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1363         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1364         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1365
1366 #if 0//-edward
1367         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1);
1368         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1369         RF_WriteReg(dev, 0x00, 0x009F);                 mdelay(1);
1370 #endif
1371         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1372         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1373         //power save parameters.
1374         u1b24E = read_nic_byte(dev, 0x24E);
1375         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1376
1377         //=============================================================================
1378
1379         //=============================================================================
1380         // CCKCONF.TXT
1381         //=============================================================================
1382
1383         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1384                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1385                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1386                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1387                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1388                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1389         */
1390 #if 0
1391         write_nic_dword(dev, PHY_ADR, 0x0100c880);
1392         write_nic_dword(dev, PHY_ADR, 0x01001c86);
1393         write_nic_dword(dev, PHY_ADR, 0x01007890);
1394         write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1395         write_nic_dword(dev, PHY_ADR, 0x010006af);
1396         write_nic_dword(dev, PHY_ADR, 0x01004681);
1397 #endif
1398         write_phy_cck(dev,0x00,0xc8);
1399         write_phy_cck(dev,0x06,0x1c);
1400         write_phy_cck(dev,0x10,0x78);
1401         write_phy_cck(dev,0x2e,0xd0);
1402         write_phy_cck(dev,0x2f,0x06);
1403         write_phy_cck(dev,0x01,0x46);
1404
1405         // power control
1406         write_nic_byte(dev, CCK_TXAGC, 0x10);
1407         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1408         write_nic_byte(dev, ANTSEL, 0x03);
1409
1410
1411
1412         //=============================================================================
1413         // AGC.txt
1414         //=============================================================================
1415
1416 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1417         write_phy_ofdm(dev, 0x00, 0x12);
1418         //WriteBBPortUchar(dev, 0x00001280);
1419
1420         for (i=0; i<128; i++)
1421         {
1422                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1423
1424                 data = ZEBRA_AGC[i+1];
1425                 data = data << 8;
1426                 data = data | 0x0000008F;
1427
1428                 addr = i + 0x80; //enable writing AGC table
1429                 addr = addr << 8;
1430                 addr = addr | 0x0000008E;
1431
1432                 WriteBBPortUchar(dev, data);
1433                 WriteBBPortUchar(dev, addr);
1434                 WriteBBPortUchar(dev, 0x0000008E);
1435         }
1436
1437         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1438         //WriteBBPortUchar(dev, 0x00001080);
1439
1440         //=============================================================================
1441
1442         //=============================================================================
1443         // OFDMCONF.TXT
1444         //=============================================================================
1445
1446         for(i=0; i<60; i++)
1447         {
1448                 u4bRegOffset=i;
1449                 u4bRegValue=OFDM_CONFIG[i];
1450
1451                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1452
1453                 WriteBBPortUchar(dev,
1454                                                 (0x00000080 |
1455                                                 (u4bRegOffset & 0x7f) |
1456                                                 ((u4bRegValue & 0xff) << 8)));
1457         }
1458
1459         //=============================================================================
1460 //by amy for antenna
1461         //=============================================================================
1462 //{by amy 080312
1463         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1464         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1465 //by amy 080312}
1466 #if 0
1467         // Config Sw/Hw  Antenna Diversity
1468         if( priv->bSwAntennaDiverity )  //  Use SW+Hw Antenna Diversity
1469         {
1470                 if( priv->bDefaultAntenna1 == true )  // aux antenna
1471                 {
1472                         // Mac register, aux antenna
1473                         write_nic_byte(dev, ANTSEL, 0x00);
1474                         // Config CCK RX antenna.
1475                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1476                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1477                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1478                         // Config OFDM RX antenna.
1479                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1480                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1481                 }
1482                 else //  main antenna
1483                 {
1484                         // Mac register, main antenna
1485                         write_nic_byte(dev, ANTSEL, 0x03);
1486                         //base band
1487                         // Config CCK RX antenna.
1488                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1489                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1490                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1491                         // Config OFDM RX antenna.
1492                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1493                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1494                 }
1495         }
1496         else   // Disable Antenna Diversity
1497         {
1498                 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1499                 {
1500                         // Mac register, aux antenna
1501                         write_nic_byte(dev, ANTSEL, 0x00);
1502                         // Config CCK RX antenna.
1503                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1504                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1505                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1506                         // Config OFDM RX antenna.
1507                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1508                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1509                 }
1510                 else // main Antenna
1511                 {
1512                         // Mac register, main antenna
1513                         write_nic_byte(dev, ANTSEL, 0x03);
1514                         // Config CCK RX antenna.
1515                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1516                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1517                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1518                         // Config OFDM RX antenna.
1519                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1520                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1521                 }
1522         }
1523 #endif
1524 //by amy for antenna
1525 }
1526
1527
1528 void
1529 UpdateInitialGain(
1530         struct net_device *dev
1531         )
1532 {
1533         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1534         //unsigned char* IGTable;
1535         //u8                    DIG_CurrentInitialGain = 4;
1536         //unsigned char u1Tmp;
1537
1538         //lzm add 080826
1539         if(priv->eRFPowerState != eRfOn)
1540         {
1541                 //Don't access BB/RF under disable PLL situation.
1542                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1543                 // Back to the original state
1544                 priv->InitialGain= priv->InitialGainBackUp;
1545                 return;
1546         }
1547
1548         switch(priv->rf_chip)
1549         {
1550 #if 0
1551         case RF_ZEBRA2:
1552                 // Dynamic set initial gain, by shien chang, 2006.07.14
1553                 switch(priv->InitialGain)
1554                 {
1555                         case 1: //m861dBm
1556                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1557                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1558                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1559                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1560                                 break;
1561
1562                         case 2: //m862dBm
1563                                 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1564                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1565                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1566                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1567                                 break;
1568
1569                         case 3: //m863dBm
1570                                 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1571                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1572                                 write_nic_dword(dev, PhyAddr, 0x96a4);  mdelay(1);
1573                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1574                                 break;
1575
1576                         case 4: //m864dBm
1577                                 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1578                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1579                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1580                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1581                                 break;
1582
1583                         case 5: //m82dBm
1584                                 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1585                                 write_nic_dword(dev, PhyAddr, 0x3697);  mdelay(1);
1586                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1587                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1588                                 break;
1589
1590                         case 6: //m78dBm
1591                                 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1592                                 write_nic_dword(dev, PhyAddr, 0x4697);  mdelay(1);
1593                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1594                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1595                                 break;
1596
1597                         case 7: //m74dBm
1598                                 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1599                                 write_nic_dword(dev, PhyAddr, 0x5697);  mdelay(1);
1600                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1601                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1602                                 break;
1603
1604                         default:        //MP
1605                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1606                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1607                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1608                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1609                                 break;
1610                 }
1611                 break;
1612 #endif
1613         case RF_ZEBRA4:
1614                 // Dynamic set initial gain, follow 87B
1615                 switch(priv->InitialGain)
1616                 {
1617                         case 1: //m861dBm
1618                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1619                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1620                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1621                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1622                                 break;
1623
1624                         case 2: //m862dBm
1625                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1626                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1627                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1628                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1629                                 break;
1630
1631                         case 3: //m863dBm
1632                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1633                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1634                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1635                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1636                                 break;
1637
1638                         case 4: //m864dBm
1639                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1640                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1641                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1642                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1643                                 break;
1644
1645                         case 5: //m82dBm
1646                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1647                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1648                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1649                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1650                                 break;
1651
1652                         case 6: //m78dBm
1653                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1654                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1655                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1656                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1657                                 break;
1658
1659                         case 7: //m74dBm
1660                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1661                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1662                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1663                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1664                                 break;
1665
1666                         case 8:
1667                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1668                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1669                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1670                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1671                                 break;
1672
1673
1674                         default:        //MP
1675                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1676                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1677                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1678                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1679                                 break;
1680                 }
1681                 break;
1682
1683
1684         default:
1685                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1686                 break;
1687         }
1688 }
1689 //
1690 //      Description:
1691 //              Tx Power tracking mechanism routine on 87SE.
1692 //      Created by Roger, 2007.12.11.
1693 //
1694 void
1695 InitTxPwrTracking87SE(
1696         struct net_device *dev
1697 )
1698 {
1699         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1700         u32     u4bRfReg;
1701
1702         u4bRfReg = RF_ReadReg(dev, 0x02);
1703
1704         // Enable Thermal meter indication.
1705         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1706         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1707 }
1708
1709 void
1710 PhyConfig8185(
1711         struct net_device *dev
1712         )
1713 {
1714         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1715        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1716            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1717         // RF config
1718         switch(priv->rf_chip)
1719         {
1720         case RF_ZEBRA2:
1721         case RF_ZEBRA4:
1722                 ZEBRA_Config_85BASIC_HardCode( dev);
1723                 break;
1724         }
1725 //{by amy 080312
1726         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1727         if(priv->bDigMechanism)
1728         {
1729                 if(priv->InitialGain == 0)
1730                         priv->InitialGain = 4;
1731                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1732         }
1733
1734         //
1735         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1736         // We initialize thermal meter here to avoid unsuccessful configuration.
1737         // Added by Roger, 2007.12.11.
1738         //
1739         if(priv->bTxPowerTrack)
1740                 InitTxPwrTracking87SE(dev);
1741
1742 //by amy 080312}
1743         priv->InitialGainBackUp= priv->InitialGain;
1744         UpdateInitialGain(dev);
1745
1746         return;
1747 }
1748
1749
1750
1751
1752 void
1753 HwConfigureRTL8185(
1754                 struct net_device *dev
1755                 )
1756 {
1757         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1758 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1759         u8              bUNIVERSAL_CONTROL_RL = 0;
1760
1761         u8              bUNIVERSAL_CONTROL_AGC = 1;
1762         u8              bUNIVERSAL_CONTROL_ANT = 1;
1763         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1764         u8              val8;
1765         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1766         //struct ieee80211_device *ieee = priv->ieee80211;
1767         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1768 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1769 //      {
1770 //              write_nic_word(dev, BRSR, 0xffff);
1771 //      }
1772 //      else
1773 //      {
1774 //              write_nic_word(dev, BRSR, 0x000f);
1775 //      }
1776 //by amy 080312}
1777         write_nic_word(dev, BRSR, 0x0fff);
1778         // Retry limit
1779         val8 = read_nic_byte(dev, CW_CONF);
1780
1781         if(bUNIVERSAL_CONTROL_RL)
1782                 val8 = val8 & 0xfd;
1783         else
1784                 val8 = val8 | 0x02;
1785
1786         write_nic_byte(dev, CW_CONF, val8);
1787
1788         // Tx AGC
1789         val8 = read_nic_byte(dev, TXAGC_CTL);
1790         if(bUNIVERSAL_CONTROL_AGC)
1791         {
1792                 write_nic_byte(dev, CCK_TXAGC, 128);
1793                 write_nic_byte(dev, OFDM_TXAGC, 128);
1794                 val8 = val8 & 0xfe;
1795         }
1796         else
1797         {
1798                 val8 = val8 | 0x01 ;
1799         }
1800
1801
1802         write_nic_byte(dev, TXAGC_CTL, val8);
1803
1804         // Tx Antenna including Feedback control
1805         val8 = read_nic_byte(dev, TXAGC_CTL );
1806
1807         if(bUNIVERSAL_CONTROL_ANT)
1808         {
1809                 write_nic_byte(dev, ANTSEL, 0x00);
1810                 val8 = val8 & 0xfd;
1811         }
1812         else
1813         {
1814                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1815         }
1816
1817         write_nic_byte(dev, TXAGC_CTL, val8);
1818
1819         // Auto Rate fallback control
1820         val8 = read_nic_byte(dev, RATE_FALLBACK);
1821         val8 &= 0x7c;
1822         if( bAUTO_RATE_FALLBACK_CTL )
1823         {
1824                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1825
1826                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1827                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1828 //by amy
1829 #if 0
1830                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff);        // set 1M ~ 54M
1831 #endif
1832                 // Aadded by Roger, 2007.11.15.
1833                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1834 //by amy
1835         }
1836         else
1837         {
1838         }
1839         write_nic_byte(dev, RATE_FALLBACK, val8);
1840 }
1841
1842
1843
1844 static void
1845 MacConfig_85BASIC_HardCode(
1846         struct net_device *dev)
1847 {
1848         //============================================================================
1849         // MACREG.TXT
1850         //============================================================================
1851         int                     nLinesRead = 0;
1852
1853         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1854         int     i;
1855
1856         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1857
1858         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1859         {
1860                 u4bRegOffset=MAC_REG_TABLE[i][0];
1861                 u4bRegValue=MAC_REG_TABLE[i][1];
1862
1863                 if(u4bRegOffset == 0x5e)
1864                 {
1865                     u4bPageIndex = u4bRegValue;
1866                 }
1867                 else
1868                 {
1869                     u4bRegOffset |= (u4bPageIndex << 8);
1870                 }
1871                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1872                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1873         }
1874         //============================================================================
1875 }
1876
1877
1878
1879 static void
1880 MacConfig_85BASIC(
1881         struct net_device *dev)
1882 {
1883
1884        u8                       u1DA;
1885         MacConfig_85BASIC_HardCode(dev);
1886
1887         //============================================================================
1888
1889         // Follow TID_AC_MAP of WMac.
1890         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1891
1892         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1893         write_nic_word(dev, IntMig, 0x0000);
1894
1895         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1896         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1897         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1898         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1899
1900         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1901         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1902 //by amy
1903 #if 0
1904         write_nic_dword(dev, RFTiming, 0x00004001);
1905 #endif
1906         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1907
1908         //Enable DA10 TX power saving
1909         u1DA = read_nic_byte(dev, PHYPR);
1910         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1911
1912         //POWER:
1913         write_nic_word(dev, 0x360, 0x1000);
1914         write_nic_word(dev, 0x362, 0x1000);
1915
1916         // AFE.
1917         write_nic_word(dev, 0x370, 0x0560);
1918         write_nic_word(dev, 0x372, 0x0560);
1919         write_nic_word(dev, 0x374, 0x0DA4);
1920         write_nic_word(dev, 0x376, 0x0DA4);
1921         write_nic_word(dev, 0x378, 0x0560);
1922         write_nic_word(dev, 0x37A, 0x0560);
1923         write_nic_word(dev, 0x37C, 0x00EC);
1924 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1925         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1926        write_nic_byte(dev, 0x24E,0x01);
1927 //by amy
1928
1929 }
1930
1931
1932
1933
1934 u8
1935 GetSupportedWirelessMode8185(
1936         struct net_device *dev
1937 )
1938 {
1939         u8                      btSupportedWirelessMode = 0;
1940         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1941
1942         switch(priv->rf_chip)
1943         {
1944         case RF_ZEBRA2:
1945         case RF_ZEBRA4:
1946                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1947                 break;
1948         default:
1949                 btSupportedWirelessMode = WIRELESS_MODE_B;
1950                 break;
1951         }
1952
1953         return btSupportedWirelessMode;
1954 }
1955
1956 void
1957 ActUpdateChannelAccessSetting(
1958         struct net_device *dev,
1959         WIRELESS_MODE                   WirelessMode,
1960         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1961         )
1962 {
1963         struct r8180_priv *priv = ieee80211_priv(dev);
1964         struct ieee80211_device *ieee = priv->ieee80211;
1965         AC_CODING       eACI;
1966         AC_PARAM        AcParam;
1967         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1968         u8      bFollowLegacySetting = 0;
1969         u8   u1bAIFS;
1970
1971         //
1972         // <RJ_TODO_8185B>
1973         // TODO: We still don't know how to set up these registers, just follow WMAC to
1974         // verify 8185B FPAG.
1975         //
1976         // <RJ_TODO_8185B>
1977         // Jong said CWmin/CWmax register are not functional in 8185B,
1978         // so we shall fill channel access realted register into AC parameter registers,
1979         // even in nQBss.
1980         //
1981         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1982         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1983         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1984         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1985         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1986         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1987
1988         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1989         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1990         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1991
1992         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1993
1994         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1995         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1996         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1997         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1998
1999         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
2000
2001         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2002
2003 #ifdef TODO
2004         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2005         if( pStaQos->CurrentQosMode > QOS_DISABLE )
2006         { // QoS mode.
2007                 if(pStaQos->QBssWirelessMode == WirelessMode)
2008                 {
2009                         // Follow AC Parameters of the QBSS.
2010                         for(eACI = 0; eACI < AC_MAX; eACI++)
2011                         {
2012                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2013                         }
2014                 }
2015                 else
2016                 {
2017                         // Follow Default WMM AC Parameters.
2018                         bFollowLegacySetting = 1;
2019                 }
2020         }
2021         else
2022 #endif
2023         { // Legacy 802.11.
2024                 bFollowLegacySetting = 1;
2025
2026         }
2027
2028         // this setting is copied from rtl8187B.  xiong-2006-11-13
2029         if(bFollowLegacySetting)
2030         {
2031
2032
2033                 //
2034                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2035                 // 2005.12.01, by rcnjko.
2036                 //
2037                 AcParam.longData = 0;
2038                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2039                 AcParam.f.AciAifsn.f.ACM = 0;
2040                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2041                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2042                 AcParam.f.TXOPLimit = 0;
2043
2044                 //lzm reserved 080826
2045 #if 1
2046                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2047                 if( ieee->current_network.Turbo_Enable == 1 )
2048                         AcParam.f.TXOPLimit = 0x01FF;
2049                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
2050                 if (ieee->iw_mode == IW_MODE_ADHOC)
2051                         AcParam.f.TXOPLimit = 0x0020;
2052 #endif
2053
2054                 for(eACI = 0; eACI < AC_MAX; eACI++)
2055                 {
2056                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2057                         {
2058                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
2059                                 AC_CODING       eACI;
2060                                 u8              u1bAIFS;
2061                                 u32             u4bAcParam;
2062
2063                                 // Retrive paramters to udpate.
2064                                 eACI = pAcParam->f.AciAifsn.f.ACI;
2065                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2066                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
2067                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
2068                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
2069                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2070
2071                                 switch(eACI)
2072                                 {
2073                                         case AC1_BK:
2074                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2075                                                 break;
2076
2077                                         case AC0_BE:
2078                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2079                                                 break;
2080
2081                                         case AC2_VI:
2082                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2083                                                 break;
2084
2085                                         case AC3_VO:
2086                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2087                                                 break;
2088
2089                                         default:
2090                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2091                                                 break;
2092                                 }
2093
2094                                 // Cehck ACM bit.
2095                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2096                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2097                                 {
2098                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2099                                         AC_CODING       eACI = pAciAifsn->f.ACI;
2100
2101                                         //modified Joseph
2102                                         //for 8187B AsynIORead issue
2103 #ifdef TODO
2104                                         u8      AcmCtrl = pHalData->AcmControl;
2105 #else
2106                                         u8      AcmCtrl = 0;
2107 #endif
2108                                         if( pAciAifsn->f.ACM )
2109                                         { // ACM bit is 1.
2110                                                 switch(eACI)
2111                                                 {
2112                                                         case AC0_BE:
2113                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
2114                                                                 break;
2115
2116                                                         case AC2_VI:
2117                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
2118                                                                 break;
2119
2120                                                         case AC3_VO:
2121                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
2122                                                                 break;
2123
2124                                                         default:
2125                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2126                                                                 break;
2127                                                 }
2128                                         }
2129                                         else
2130                                         { // ACM bit is 0.
2131                                                 switch(eACI)
2132                                                 {
2133                                                         case AC0_BE:
2134                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
2135                                                                 break;
2136
2137                                                         case AC2_VI:
2138                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
2139                                                                 break;
2140
2141                                                         case AC3_VO:
2142                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
2143                                                                 break;
2144
2145                                                         default:
2146                                                                 break;
2147                                                 }
2148                                         }
2149
2150                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2151
2152 #ifdef TO_DO
2153                                         pHalData->AcmControl = AcmCtrl;
2154 #endif
2155                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2156                                         write_nic_byte(dev, ACM_CONTROL, 0);
2157                                 }
2158                         }
2159                 }
2160
2161
2162         }
2163 }
2164
2165 void
2166 ActSetWirelessMode8185(
2167         struct net_device *dev,
2168         u8                              btWirelessMode
2169         )
2170 {
2171         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2172         struct ieee80211_device *ieee = priv->ieee80211;
2173         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
2174         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2175
2176         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2177         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2178                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2179                         btWirelessMode, btSupportedWirelessMode);
2180                 return;
2181         }
2182
2183         // 1. Assign wireless mode to swtich if necessary.
2184         if (btWirelessMode == WIRELESS_MODE_AUTO)
2185         {
2186                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2187                 {
2188                         btWirelessMode = WIRELESS_MODE_A;
2189                 }
2190                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2191                 {
2192                         btWirelessMode = WIRELESS_MODE_G;
2193                 }
2194                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2195                 {
2196                         btWirelessMode = WIRELESS_MODE_B;
2197                 }
2198                 else
2199                 {
2200                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2201                                          btSupportedWirelessMode);
2202                         btWirelessMode = WIRELESS_MODE_B;
2203                 }
2204         }
2205
2206
2207         // 2. Swtich band: RF or BB specific actions,
2208         // for example, refresh tables in omc8255, or change initial gain if necessary.
2209         switch(priv->rf_chip)
2210         {
2211         case RF_ZEBRA2:
2212         case RF_ZEBRA4:
2213                 {
2214                         // Nothing to do for Zebra to switch band.
2215                         // Update current wireless mode if we swtich to specified band successfully.
2216                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
2217                 }
2218                 break;
2219
2220         default:
2221                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2222                 break;
2223         }
2224
2225         // 3. Change related setting.
2226         if( ieee->mode == WIRELESS_MODE_A ){
2227                 DMESG("WIRELESS_MODE_A\n");
2228         }
2229         else if( ieee->mode == WIRELESS_MODE_B ){
2230                 DMESG("WIRELESS_MODE_B\n");
2231         }
2232         else if( ieee->mode == WIRELESS_MODE_G ){
2233                 DMESG("WIRELESS_MODE_G\n");
2234         }
2235
2236         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2237 }
2238
2239 void rtl8185b_irq_enable(struct net_device *dev)
2240 {
2241         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2242
2243         priv->irq_enabled = 1;
2244         write_nic_dword(dev, IMR, priv->IntrMask);
2245 }
2246 //by amy for power save
2247 void
2248 DrvIFIndicateDisassociation(
2249         struct net_device *dev,
2250         u16                     reason
2251         )
2252 {
2253         //printk("==> DrvIFIndicateDisassociation()\n");
2254
2255         // nothing is needed after disassociation request.
2256
2257         //printk("<== DrvIFIndicateDisassociation()\n");
2258 }
2259 void
2260 MgntDisconnectIBSS(
2261         struct net_device *dev
2262 )
2263 {
2264         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2265         u8                      i;
2266
2267         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2268
2269         DrvIFIndicateDisassociation(dev, unspec_reason);
2270
2271 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2272         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
2273
2274         priv->ieee80211->state = IEEE80211_NOLINK;
2275
2276         //Stop Beacon.
2277
2278         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2279         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2280         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2281
2282         // Disable Beacon Queue Own bit, suggested by jong
2283 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2284         ieee80211_stop_send_beacons(priv->ieee80211);
2285
2286         priv->ieee80211->link_change(dev);
2287         notify_wx_assoc_event(priv->ieee80211);
2288
2289         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2290 #if 0
2291         if(pMgntInfo->bEnableSwBeaconTimer)
2292         {
2293                 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2294 // comment out by haich, 2007.10.01
2295 //#if DEV_BUS_TYPE==USB_INTERFACE
2296                 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2297 //#endif
2298         }
2299 #endif
2300
2301 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2302
2303 }
2304 void
2305 MlmeDisassociateRequest(
2306         struct net_device *dev,
2307         u8*                     asSta,
2308         u8                      asRsn
2309         )
2310 {
2311         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2312         u8 i;
2313
2314         SendDisassociation(priv->ieee80211, asSta, asRsn );
2315
2316         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2317                 //ShuChen TODO: change media status.
2318                 //ShuChen TODO: What to do when disassociate.
2319                 DrvIFIndicateDisassociation(dev, unspec_reason);
2320
2321
2322         //      pMgntInfo->AsocTimestamp = 0;
2323                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2324 //              pMgntInfo->mBrates.Length = 0;
2325 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2326
2327                 ieee80211_disassociate(priv->ieee80211);
2328
2329
2330         }
2331
2332 }
2333
2334 void
2335 MgntDisconnectAP(
2336         struct net_device *dev,
2337         u8                      asRsn
2338 )
2339 {
2340         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2341
2342 //
2343 // Commented out by rcnjko, 2005.01.27:
2344 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2345 //
2346 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2347 //      SecClearAllKeys(Adapter);
2348
2349         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2350 #ifdef TODO
2351         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2352                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2353         {
2354                 SecClearAllKeys(Adapter);
2355                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2356         }
2357 #endif
2358         // 2004.10.11, by rcnjko.
2359         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2360         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2361
2362         priv->ieee80211->state = IEEE80211_NOLINK;
2363 //      pMgntInfo->AsocTimestamp = 0;
2364 }
2365 bool
2366 MgntDisconnect(
2367         struct net_device *dev,
2368         u8                      asRsn
2369 )
2370 {
2371         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2372         //
2373         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2374         //
2375 #ifdef TODO
2376         if(pMgntInfo->mPss != eAwake)
2377         {
2378                 //
2379                 // Using AwkaeTimer to prevent mismatch ps state.
2380                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2381                 //
2382                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2383                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2384         }
2385 #endif
2386
2387         // Indication of disassociation event.
2388         //DrvIFIndicateDisassociation(Adapter, asRsn);
2389         if(IS_DOT11D_ENABLE(priv->ieee80211))
2390                 Dot11d_Reset(priv->ieee80211);
2391         // In adhoc mode, update beacon frame.
2392         if( priv->ieee80211->state == IEEE80211_LINKED )
2393         {
2394                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2395                 {
2396 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2397                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2398                         MgntDisconnectIBSS(dev);
2399                 }
2400                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2401                 {
2402                         // We clear key here instead of MgntDisconnectAP() because that
2403                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2404                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2405                         // used to handle disassociation related things to AP, e.g. send Disassoc
2406                         // frame to AP.  2005.01.27, by rcnjko.
2407 //                      SecClearAllKeys(Adapter);
2408
2409 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2410                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2411                         MgntDisconnectAP(dev, asRsn);
2412                 }
2413
2414                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2415 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2416         }
2417
2418         return true;
2419 }
2420 //
2421 //      Description:
2422 //              Chang RF Power State.
2423 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2424 //
2425 //      Assumption:
2426 //              PASSIVE LEVEL.
2427 //
2428 bool
2429 SetRFPowerState(
2430         struct net_device *dev,
2431         RT_RF_POWER_STATE       eRFPowerState
2432         )
2433 {
2434         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2435         bool                    bResult = false;
2436
2437 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2438         if(eRFPowerState == priv->eRFPowerState)
2439         {
2440 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2441                 return bResult;
2442         }
2443
2444         switch(priv->rf_chip)
2445         {
2446                 case RF_ZEBRA2:
2447                 case RF_ZEBRA4:
2448                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2449                         break;
2450
2451                 default:
2452                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2453                         break;;
2454 }
2455 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2456
2457         return bResult;
2458 }
2459 void
2460 HalEnableRx8185Dummy(
2461         struct net_device *dev
2462         )
2463 {
2464 }
2465 void
2466 HalDisableRx8185Dummy(
2467         struct net_device *dev
2468         )
2469 {
2470 }
2471
2472 bool
2473 MgntActSet_RF_State(
2474         struct net_device *dev,
2475         RT_RF_POWER_STATE       StateToSet,
2476         u32     ChangeSource
2477         )
2478 {
2479         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2480         bool                            bActionAllowed = false;
2481         bool                            bConnectBySSID = false;
2482         RT_RF_POWER_STATE       rtState;
2483         u16                             RFWaitCounter = 0;
2484         unsigned long flag;
2485 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2486         //
2487         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2488         // Only one thread can change the RF state at one time, and others should wait to be executed.
2489         //
2490 #if 1
2491         while(true)
2492         {
2493 //              down(&priv->rf_state);
2494                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2495                 if(priv->RFChangeInProgress)
2496                 {
2497 //                      printk("====================>haha111111111\n");
2498 //                      up(&priv->rf_state);
2499 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2500                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2501                         // Set RF after the previous action is done.
2502                         while(priv->RFChangeInProgress)
2503                         {
2504                                 RFWaitCounter ++;
2505 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2506                                 udelay(1000); // 1 ms
2507
2508                                 // Wait too long, return FALSE to avoid to be stuck here.
2509                                 if(RFWaitCounter > 1000) // 1sec
2510                                 {
2511 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2512                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2513                                         // TODO: Reset RF state?
2514                                         return false;
2515                                 }
2516                         }
2517                 }
2518                 else
2519                 {
2520 //                      printk("========================>haha2\n");
2521                         priv->RFChangeInProgress = true;
2522 //                      up(&priv->rf_state);
2523                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2524                         break;
2525                 }
2526         }
2527 #endif
2528         rtState = priv->eRFPowerState;
2529
2530
2531         switch(StateToSet)
2532         {
2533         case eRfOn:
2534                 //
2535                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2536                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2537                 //
2538                 priv->RfOffReason &= (~ChangeSource);
2539
2540                 if(! priv->RfOffReason)
2541                 {
2542                         priv->RfOffReason = 0;
2543                         bActionAllowed = true;
2544
2545                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2546                         {
2547                                 bConnectBySSID = true;
2548                         }
2549                 }
2550                 else
2551 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2552                         ;
2553                 break;
2554
2555         case eRfOff:
2556                  // 070125, rcnjko: we always keep connected in AP mode.
2557
2558                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2559                         {
2560                                 //
2561                                 // 060808, Annie:
2562                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2563                                 //
2564
2565                                 //
2566                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2567                                 // because we do NOT need to set ssid to dummy ones.
2568                                 // Revised by Roger, 2007.12.04.
2569                                 //
2570                                 MgntDisconnect( dev, disas_lv_ss );
2571
2572                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2573                                 // 2007.05.28, by shien chang.
2574 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2575 //                              pMgntInfo->NumBssDesc = 0;
2576 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2577 //                              pMgntInfo->NumBssDesc4Query = 0;
2578                         }
2579
2580
2581
2582                 priv->RfOffReason |= ChangeSource;
2583                 bActionAllowed = true;
2584                 break;
2585
2586         case eRfSleep:
2587                 priv->RfOffReason |= ChangeSource;
2588                 bActionAllowed = true;
2589                 break;
2590
2591         default:
2592                 break;
2593         }
2594
2595         if(bActionAllowed)
2596         {
2597 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2598                 // Config HW to the specified mode.
2599 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2600                 SetRFPowerState(dev, StateToSet);
2601
2602                 // Turn on RF.
2603                 if(StateToSet == eRfOn)
2604                 {
2605                         HalEnableRx8185Dummy(dev);
2606                         if(bConnectBySSID)
2607                         {
2608                         // by amy not supported
2609 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2610                         }
2611                 }
2612                 // Turn off RF.
2613                 else if(StateToSet == eRfOff)
2614                 {
2615                         HalDisableRx8185Dummy(dev);
2616                 }
2617         }
2618         else
2619         {
2620         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2621         }
2622
2623         // Release RF spinlock
2624 //      down(&priv->rf_state);
2625         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2626         priv->RFChangeInProgress = false;
2627 //      up(&priv->rf_state);
2628         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2629 //      printk("<===MgntActSet_RF_State()\n");
2630         return bActionAllowed;
2631 }
2632 void
2633 InactivePowerSave(
2634         struct net_device *dev
2635         )
2636 {
2637         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2638         //u8 index = 0;
2639
2640         //
2641         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2642         // is really scheduled.
2643         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2644         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2645         // blocks the IPS procedure of switching RF.
2646         // By Bruce, 2007-12-25.
2647         //
2648         priv->bSwRfProcessing = true;
2649
2650         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2651
2652         //
2653         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2654         //
2655 #if 0
2656         while( index < 4 )
2657         {
2658                 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2659                         (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2660                 {
2661                         if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2662                         pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2663
2664                 }
2665                 index++;
2666         }
2667 #endif
2668         priv->bSwRfProcessing = false;
2669 }
2670
2671 //
2672 //      Description:
2673 //              Enter the inactive power save mode. RF will be off
2674 //      2007.08.17, by shien chang.
2675 //
2676 void
2677 IPSEnter(
2678         struct net_device *dev
2679         )
2680 {
2681         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2682         RT_RF_POWER_STATE rtState;
2683         //printk("==============================>enter IPS\n");
2684         if (priv->bInactivePs)
2685         {
2686                 rtState = priv->eRFPowerState;
2687
2688                 //
2689                 // Added by Bruce, 2007-12-25.
2690                 // Do not enter IPS in the following conditions:
2691                 // (1) RF is already OFF or Sleep
2692                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2693                 // (3) Connectted (only disconnected can trigger IPS)
2694                 // (4) IBSS (send Beacon)
2695                 // (5) AP mode (send Beacon)
2696                 //
2697                 if (rtState == eRfOn && !priv->bSwRfProcessing
2698                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2699                 {
2700         //              printk("IPSEnter(): Turn off RF.\n");
2701                         priv->eInactivePowerState = eRfOff;
2702                         InactivePowerSave(dev);
2703                 }
2704         }
2705 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2706 }
2707 void
2708 IPSLeave(
2709         struct net_device *dev
2710         )
2711 {
2712         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2713         RT_RF_POWER_STATE rtState;
2714         //printk("===================================>leave IPS\n");
2715         if (priv->bInactivePs)
2716         {
2717                 rtState = priv->eRFPowerState;
2718                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2719                 {
2720 //                      printk("IPSLeave(): Turn on RF.\n");
2721                         priv->eInactivePowerState = eRfOn;
2722                         InactivePowerSave(dev);
2723                 }
2724         }
2725 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2726 }
2727 //by amy for power save
2728 void rtl8185b_adapter_start(struct net_device *dev)
2729 {
2730       struct r8180_priv *priv = ieee80211_priv(dev);
2731         struct ieee80211_device *ieee = priv->ieee80211;
2732
2733         u8 SupportedWirelessMode;
2734         u8                      InitWirelessMode;
2735         u8                      bInvalidWirelessMode = 0;
2736         //int i;
2737         u8 tmpu8;
2738         //u8 u1tmp,u2tmp;
2739         u8 btCR9346;
2740         u8 TmpU1b;
2741         u8 btPSR;
2742
2743         //rtl8180_rtx_disable(dev);
2744 //{by amy 080312
2745         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2746 //by amy 080312}
2747         rtl8180_reset(dev);
2748
2749         priv->dma_poll_mask = 0;
2750         priv->dma_poll_stop_mask = 0;
2751
2752         //rtl8180_beacon_tx_disable(dev);
2753
2754         HwConfigureRTL8185(dev);
2755
2756         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2757         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2758
2759         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2760
2761         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2762
2763         write_nic_word(dev, BcnItv, 100);
2764         write_nic_word(dev, AtimWnd, 2);
2765
2766         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2767         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2768
2769         write_nic_byte(dev, WPA_CONFIG, 0);
2770
2771         MacConfig_85BASIC(dev);
2772
2773         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2774         // BT_DEMO_BOARD type
2775         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2776 //by amy
2777 //#ifdef CONFIG_RTL818X_S
2778                 // for jong required
2779 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2780 //#endif
2781 //by amy
2782         //BT_QA_BOARD
2783         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2784
2785         //-----------------------------------------------------------------------------
2786         // Set up PHY related.
2787         //-----------------------------------------------------------------------------
2788         // Enable Config3.PARAM_En to revise AnaaParm.
2789         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2790 //by amy
2791         tmpu8 = read_nic_byte(dev, CONFIG3);
2792         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2793 //by amy
2794         // Turn on Analog power.
2795         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2796         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2797         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2798 //by amy
2799         write_nic_word(dev, ANAPARAM3, 0x0010);
2800 //by amy
2801
2802         write_nic_byte(dev, CONFIG3, tmpu8);
2803         write_nic_byte(dev, CR9346, 0x00);
2804 //{by amy 080312 for led
2805         // enable EEM0 and EEM1 in 9346CR
2806         btCR9346 = read_nic_byte(dev, CR9346);
2807         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2808
2809         // B cut use LED1 to control HW RF on/off
2810         TmpU1b = read_nic_byte(dev, CONFIG5);
2811         TmpU1b = TmpU1b & ~BIT3;
2812         write_nic_byte(dev,CONFIG5, TmpU1b);
2813
2814         // disable EEM0 and EEM1 in 9346CR
2815         btCR9346 &= ~(0xC0);
2816         write_nic_byte(dev, CR9346, btCR9346);
2817
2818         //Enable Led (suggested by Jong)
2819         // B-cut RF Radio on/off  5e[3]=0
2820         btPSR = read_nic_byte(dev, PSR);
2821         write_nic_byte(dev, PSR, (btPSR | BIT3));
2822 //by amy 080312 for led}
2823         // setup initial timing for RFE.
2824         write_nic_word(dev, RFPinsOutput, 0x0480);
2825         SetOutputEnableOfRfPins(dev);
2826         write_nic_word(dev, RFPinsSelect, 0x2488);
2827
2828         // PHY config.
2829         PhyConfig8185(dev);
2830
2831         // We assume RegWirelessMode has already been initialized before,
2832         // however, we has to validate the wireless mode here and provide a reasonble
2833         // initialized value if necessary. 2005.01.13, by rcnjko.
2834         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2835         if(     (ieee->mode != WIRELESS_MODE_B) &&
2836                 (ieee->mode != WIRELESS_MODE_G) &&
2837                 (ieee->mode != WIRELESS_MODE_A) &&
2838                 (ieee->mode != WIRELESS_MODE_AUTO))
2839         { // It should be one of B, G, A, or AUTO.
2840                 bInvalidWirelessMode = 1;
2841         }
2842         else
2843         { // One of B, G, A, or AUTO.
2844                 // Check if the wireless mode is supported by RF.
2845                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2846                         (ieee->mode & SupportedWirelessMode) == 0 )
2847                 {
2848                         bInvalidWirelessMode = 1;
2849                 }
2850         }
2851
2852         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2853         { // Auto or other invalid value.
2854                 // Assigne a wireless mode to initialize.
2855                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2856                 {
2857                         InitWirelessMode = WIRELESS_MODE_A;
2858                 }
2859                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2860                 {
2861                         InitWirelessMode = WIRELESS_MODE_G;
2862                 }
2863                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2864                 {
2865                         InitWirelessMode = WIRELESS_MODE_B;
2866                 }
2867                 else
2868                 {
2869                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2870                                  SupportedWirelessMode);
2871                         InitWirelessMode = WIRELESS_MODE_B;
2872                 }
2873
2874                 // Initialize RegWirelessMode if it is not a valid one.
2875                 if(bInvalidWirelessMode)
2876                 {
2877                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2878                 }
2879         }
2880         else
2881         { // One of B, G, A.
2882                 InitWirelessMode = ieee->mode;
2883         }
2884 //by amy for power save
2885 #ifdef ENABLE_IPS
2886 //      printk("initialize ENABLE_IPS\n");
2887         priv->eRFPowerState = eRfOff;
2888         priv->RfOffReason = 0;
2889         {
2890         //      u32 tmp2;
2891         //      u32 tmp = jiffies;
2892                 MgntActSet_RF_State(dev, eRfOn, 0);
2893         //      tmp2 = jiffies;
2894         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2895         }
2896 //      DrvIFIndicateCurrentPhyStatus(priv);
2897                 //
2898                 // If inactive power mode is enabled, disable rf while in disconnected state.
2899                 // 2007.07.16, by shien chang.
2900                 //
2901         if (priv->bInactivePs)
2902         {
2903         //      u32 tmp2;
2904         //      u32 tmp = jiffies;
2905                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2906         //      tmp2 = jiffies;
2907         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2908
2909         }
2910 #endif
2911 //      IPSEnter(dev);
2912 //by amy for power save
2913 #ifdef TODO
2914         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2915         // We shall turn off RF after setting CMDR, otherwise,
2916         // RF will be turnned on after we enable MAC Tx/Rx.
2917         if(Adapter->MgntInfo.RegRfOff == TRUE)
2918         {
2919                 SetRFPowerState8185(Adapter, RF_OFF);
2920         }
2921         else
2922         {
2923                 SetRFPowerState8185(Adapter, RF_ON);
2924         }
2925 #endif
2926
2927 /*   //these is equal with above TODO.
2928         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2929         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2930         RF_WriteReg(dev, 0x4, 0x9FF);
2931         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2932         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2933         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2934         write_nic_byte(dev, CR9346, 0x00);
2935 */
2936
2937         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2938
2939         //-----------------------------------------------------------------------------
2940
2941         rtl8185b_irq_enable(dev);
2942
2943         netif_start_queue(dev);
2944
2945  }
2946
2947
2948 void rtl8185b_rx_enable(struct net_device *dev)
2949 {
2950         u8 cmd;
2951         //u32 rxconf;
2952         /* for now we accept data, management & ctl frame*/
2953         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2954 #if 0
2955         rxconf=read_nic_dword(dev,RX_CONF);
2956         rxconf = rxconf &~ MAC_FILTER_MASK;
2957         rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
2958         rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
2959         rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
2960         rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
2961 //      rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2962         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2963
2964         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2965            dev->flags & IFF_PROMISC){
2966                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2967         }else{
2968                 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
2969                 if(priv->card_8185 == 0)
2970                         rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2971         }
2972
2973         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2974                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2975                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2976         }*/
2977
2978         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2979                 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
2980                 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
2981                 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
2982         }
2983
2984         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2985                 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
2986
2987         //if(!priv->card_8185){
2988                 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
2989                 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
2990         //}
2991
2992         rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
2993         rxconf = rxconf &~ MAX_RX_DMA_MASK;
2994         rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
2995
2996         //if(!priv->card_8185)
2997                 rxconf = rxconf | RCR_ONLYERLPKT;
2998
2999         rxconf = rxconf &~ RCR_CS_MASK;
3000         if(!priv->card_8185)
3001                 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3002 //      rxconf &=~ 0xfff00000;
3003 //      rxconf |= 0x90100000;//9014f76f;
3004         write_nic_dword(dev, RX_CONF, rxconf);
3005 #endif
3006
3007         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3008
3009         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3010            dev->flags & IFF_PROMISC){
3011                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3012                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3013         }
3014
3015         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3016                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3017                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3018         }*/
3019
3020         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3021                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3022         }
3023
3024         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3025                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3026
3027         write_nic_dword(dev, RCR, priv->ReceiveConfig);
3028
3029         fix_rx_fifo(dev);
3030
3031 #ifdef DEBUG_RX
3032         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3033 #endif
3034         cmd=read_nic_byte(dev,CMD);
3035         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3036
3037 }
3038
3039 void rtl8185b_tx_enable(struct net_device *dev)
3040 {
3041         u8 cmd;
3042         //u8 tx_agc_ctl;
3043         u8 byte;
3044         //u32 txconf;
3045         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3046
3047 #if 0
3048         txconf= read_nic_dword(dev,TX_CONF);
3049         if(priv->card_8185){
3050
3051
3052                 byte = read_nic_byte(dev,CW_CONF);
3053                 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3054                 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3055                 write_nic_byte(dev, CW_CONF, byte);
3056
3057                 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3058                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3059                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3060                 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3061                 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3062                 /*
3063                 write_nic_word(dev, 0x5e, 0x01);
3064                 force_pci_posting(dev);
3065                 mdelay(1);
3066                 write_nic_word(dev, 0xfe, 0x10);
3067                 force_pci_posting(dev);
3068                 mdelay(1);
3069                 write_nic_word(dev, 0x5e, 0x00);
3070                 force_pci_posting(dev);
3071                 mdelay(1);
3072                 */
3073                 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3074         }
3075
3076         if(priv->card_8185){
3077
3078                 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3079
3080         }else{
3081
3082                 if(hwseqnum)
3083                         txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3084                 else
3085                         txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3086         }
3087
3088         txconf = txconf &~ TX_LOOPBACK_MASK;
3089         txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3090         txconf = txconf &~ TCR_DPRETRY_MASK;
3091         txconf = txconf &~ TCR_RTSRETRY_MASK;
3092         txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3093         txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3094         txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3095
3096         if(priv->card_8185){
3097                 if(priv->hw_plcp_len)
3098                         txconf = txconf &~ TCR_PLCP_LEN;
3099                 else
3100                         txconf = txconf | TCR_PLCP_LEN;
3101         }else{
3102                 txconf = txconf &~ TCR_SAT;
3103         }
3104         txconf = txconf &~ TCR_MXDMA_MASK;
3105         txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3106         txconf = txconf | TCR_CWMIN;
3107         txconf = txconf | TCR_DISCW;
3108
3109 //      if(priv->ieee80211->hw_wep)
3110 //              txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3111 //      else
3112                 txconf=txconf | (1<<TX_NOICV_SHIFT);
3113
3114         write_nic_dword(dev,TX_CONF,txconf);
3115 #endif
3116
3117         write_nic_dword(dev, TCR, priv->TransmitConfig);
3118         byte = read_nic_byte(dev, MSR);
3119         byte |= MSR_LINK_ENEDCA;
3120         write_nic_byte(dev, MSR, byte);
3121
3122         fix_tx_fifo(dev);
3123
3124 #ifdef DEBUG_TX
3125         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3126 #endif
3127
3128         cmd=read_nic_byte(dev,CMD);
3129         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3130
3131         //write_nic_dword(dev,TX_CONF,txconf);
3132
3133
3134 /*
3135         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3136         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3137         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3138         */
3139 }
3140
3141
3142 #endif