SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #ifdef CONFIG_RTL8180_PM
  34 #include "r8180_pm.h"
  35 #endif
  36
  37 #include "ieee80211/dot11d.h"
  38
  39 #ifdef CONFIG_RTL8185B
  40
  41 //#define CONFIG_RTL8180_IO_MAP
  42
  43 #define TC_3W_POLL_MAX_TRY_CNT 5
  44 #ifdef CONFIG_RTL818X_S
  45 static u8 MAC_REG_TABLE[][2]={
  46                         //PAGA 0:
  47                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  48                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  49                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  50                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  51                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  52                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  53                         {0x94, 0x0F}, {0x95, 0x32},
  54                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  55                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  56                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  57                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  58                         {0xff, 0x00},
  59
  60                         //PAGE 1:
  61                         // For Flextronics system Logo PCIHCT failure:
  62                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  63                         {0x5e, 0x01},
  64                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  65                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  66                         {0x82, 0xFF}, {0x83, 0x03},
  67                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  68                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  69                         {0xe2, 0x00},
  70
  71
  72                         //PAGE 2:
  73                         {0x5e, 0x02},
  74                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  75                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  76                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  77                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  78                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  79                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  80                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  81
  82                         //PAGA 0:
  83                         {0x5e, 0x00},{0x9f, 0x03}
  84                 };
  85
  86
  87 static u8  ZEBRA_AGC[]={
  88                         0,
  89                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  90                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  91                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  92                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  93                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  94                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  95                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  96                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  97                         };
  98
  99 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
 100                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
 101                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
 102                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
 103                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 104                         0x0183,0x0163,0x0143,0x0123,0x0103
 105         };
 106
 107 static u8 OFDM_CONFIG[]={
 108                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 109                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 110                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 111
 112                         // 0x00
 113                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 114                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 115                         // 0x10
 116                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 117                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 118                         // 0x20
 119                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 120                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 121                         // 0x30
 122                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 123                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 124                 };
 125 #else
 126  static u8 MAC_REG_TABLE[][2]={
 127                         //PAGA 0:
 128                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
 129                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
 130                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
 131                         {0xff, 0x00},
 132
 133                         //PAGE 1:
 134                         {0x5e, 0x01},
 135                         {0x58, 0x4b}, {0x59, 0x00}, {0x5a, 0x4b}, {0x5b, 0x00}, {0x60, 0x4b},
 136                         {0x61, 0x09}, {0x62, 0x4b}, {0x63, 0x09}, {0xce, 0x0f}, {0xcf, 0x00},
 137                         {0xe0, 0xff}, {0xe1, 0x0f}, {0xe2, 0x00}, {0xf0, 0x4e}, {0xf1, 0x01},
 138                         {0xf2, 0x02}, {0xf3, 0x03}, {0xf4, 0x04}, {0xf5, 0x05}, {0xf6, 0x06},
 139                         {0xf7, 0x07}, {0xf8, 0x08},
 140
 141
 142                         //PAGE 2:
 143                         {0x5e, 0x02},
 144                         {0x0c, 0x04}, {0x21, 0x61}, {0x22, 0x68}, {0x23, 0x6f}, {0x24, 0x76},
 145                         {0x25, 0x7d}, {0x26, 0x84}, {0x27, 0x8d}, {0x4d, 0x08}, {0x4e, 0x00},
 146                         {0x50, 0x05}, {0x51, 0xf5}, {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0x1f},
 147                         {0x55, 0x23}, {0x56, 0x45}, {0x57, 0x67}, {0x58, 0x08}, {0x59, 0x08},
 148                         {0x5a, 0x08}, {0x5b, 0x08}, {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08},
 149                         {0x63, 0x08}, {0x64, 0xcf}, {0x72, 0x56}, {0x73, 0x9a},
 150
 151                         //PAGA 0:
 152                         {0x5e, 0x00},
 153                         {0x34, 0xff}, {0x35, 0x0f}, {0x5b, 0x40}, {0x84, 0x88}, {0x85, 0x24},
 154                         {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x07}, {0x8d, 0x00}, {0x94, 0x1b},
 155                         {0x95, 0x12}, {0x96, 0x00}, {0x97, 0x06}, {0x9d, 0x1a}, {0x9f, 0x10},
 156                         {0xb4, 0x22}, {0xbe, 0x80}, {0xdb, 0x00}, {0xee, 0x00}, {0x5b, 0x42},
 157                         {0x91, 0x03},
 158
 159                         //PAGE 2:
 160                         {0x5e, 0x02},
 161                         {0x4c, 0x03},
 162
 163                         //PAGE 0:
 164                         {0x5e, 0x00},
 165
 166                         //PAGE 3:
 167                         {0x5e, 0x03},
 168                         {0x9f, 0x00},
 169
 170                         //PAGE 0:
 171                         {0x5e, 0x00},
 172                         {0x8c, 0x01}, {0x8d, 0x10},{0x8e, 0x08}, {0x8f, 0x00}
 173                 };
 174
 175
 176 static u8  ZEBRA_AGC[]={
 177         0,
 178         0x5e,0x5e,0x5e,0x5e,0x5d,0x5b,0x59,0x57,0x55,0x53,0x51,0x4f,0x4d,0x4b,0x49,0x47,
 179         0x45,0x43,0x41,0x3f,0x3d,0x3b,0x39,0x37,0x35,0x33,0x31,0x2f,0x2d,0x2b,0x29,0x27,
 180         0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x11,0x0f,0x0d,0x0b,0x09,0x07,
 181         0x05,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
 182         0x19,0x19,0x19,0x019,0x19,0x19,0x19,0x19,0x19,0x19,0x1e,0x1f,0x20,0x21,0x21,0x22,
 183         0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,0x28,0x29,0x2a,0x2a,0x2b,
 184         0x2b,0x2b,0x2c,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,0x30,0x31,0x31,0x31,0x31,
 185         0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31
 186         };
 187
 188 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
 189         0,
 190         0x0400,0x0401,0x0402,0x0403,0x0404,0x0405,0x0408,0x0409,
 191         0x040a,0x040b,0x0502,0x0503,0x0504,0x0505,0x0540,0x0541,
 192         0x0542,0x0543,0x0544,0x0545,0x0580,0x0581,0x0582,0x0583,
 193         0x0584,0x0585,0x0588,0x0589,0x058a,0x058b,0x0643,0x0644,
 194         0x0645,0x0680,0x0681,0x0682,0x0683,0x0684,0x0685,0x0688,
 195         0x0689,0x068a,0x068b,0x068c,0x0742,0x0743,0x0744,0x0745,
 196         0x0780,0x0781,0x0782,0x0783,0x0784,0x0785,0x0788,0x0789,
 197         0x078a,0x078b,0x078c,0x078d,0x0790,0x0791,0x0792,0x0793,
 198         0x0794,0x0795,0x0798,0x0799,0x079a,0x079b,0x079c,0x079d,
 199         0x07a0,0x07a1,0x07a2,0x07a3,0x07a4,0x07a5,0x07a8,0x07a9,
 200         0x03aa,0x03ab,0x03ac,0x03ad,0x03b0,0x03b1,0x03b2,0x03b3,
 201         0x03b4,0x03b5,0x03b8,0x03b9,0x03ba,0x03bb,0x03bb
 202 };
 203
 204 // 2006.07.13, SD3 szuyitasi:
 205 //      OFDM.0x03=0x0C (original is 0x0F)
 206 // Use the new SD3 given param, by shien chang, 2006.07.14
 207 static u8 OFDM_CONFIG[]={
 208         0x10, 0x0d, 0x01, 0x0C, 0x14, 0xfb, 0x0f, 0x60, 0x00, 0x60,
 209         0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,
 210         0x00, 0x00, 0xa8, 0x46, 0xb2, 0x33, 0x07, 0xa5, 0x6f, 0x55,
 211         0xc8, 0xb3, 0x0a, 0xe1, 0x1c, 0x8a, 0xb6, 0x83, 0x34, 0x0f,
 212         0x4f, 0x23, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 0xc0, 0xc1,
 213         0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 0x6d, 0x3c, 0xff, 0x07
 214 };
 215 #endif
 216
 217 /*---------------------------------------------------------------
 218   * Hardware IO
 219   * the code is ported from Windows source code
 220   ----------------------------------------------------------------*/
 221
 222 void
 223 PlatformIOWrite1Byte(
 224         struct net_device *dev,
 225         u32             offset,
 226         u8              data
 227         )
 228 {
 229 #ifndef CONFIG_RTL8180_IO_MAP
 230         write_nic_byte(dev, offset, data);
 231         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 232
 233 #else // Port IO
 234         u32 Page = (offset >> 8);
 235
 236         switch(Page)
 237         {
 238         case 0: // Page 0
 239                 write_nic_byte(dev, offset, data);
 240                 break;
 241
 242         case 1: // Page 1
 243         case 2: // Page 2
 244         case 3: // Page 3
 245                 {
 246                         u8 psr = read_nic_byte(dev, PSR);
 247
 248                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 249                         write_nic_byte(dev, (offset & 0xff), data);
 250                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 251                 }
 252                 break;
 253
 254         default:
 255                 // Illegal page number.
 256                 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 257                 break;
 258         }
 259 #endif
 260 }
 261
 262 void
 263 PlatformIOWrite2Byte(
 264         struct net_device *dev,
 265         u32             offset,
 266         u16             data
 267         )
 268 {
 269 #ifndef CONFIG_RTL8180_IO_MAP
 270         write_nic_word(dev, offset, data);
 271         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 272
 273
 274 #else // Port IO
 275         u32 Page = (offset >> 8);
 276
 277         switch(Page)
 278         {
 279         case 0: // Page 0
 280                 write_nic_word(dev, offset, data);
 281                 break;
 282
 283         case 1: // Page 1
 284         case 2: // Page 2
 285         case 3: // Page 3
 286                 {
 287                         u8 psr = read_nic_byte(dev, PSR);
 288
 289                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 290                         write_nic_word(dev, (offset & 0xff), data);
 291                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 292                 }
 293                 break;
 294
 295         default:
 296                 // Illegal page number.
 297                 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 298                 break;
 299         }
 300 #endif
 301 }
 302 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 303
 304 void
 305 PlatformIOWrite4Byte(
 306         struct net_device *dev,
 307         u32             offset,
 308         u32             data
 309         )
 310 {
 311 #ifndef CONFIG_RTL8180_IO_MAP
 312 //{by amy 080312
 313 if (offset == PhyAddr)
 314         {//For Base Band configuration.
 315                 unsigned char   cmdByte;
 316                 unsigned long   dataBytes;
 317                 unsigned char   idx;
 318                 u8      u1bTmp;
 319
 320                 cmdByte = (u8)(data & 0x000000ff);
 321                 dataBytes = data>>8;
 322
 323                 //
 324                 // 071010, rcnjko:
 325                 // The critical section is only BB read/write race condition.
 326                 // Assumption:
 327                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 328                 // acquiring the spinlock in such context.
 329                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 330                 //
 331 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 332
 333                 for(idx = 0; idx < 30; idx++)
 334                 { // Make sure command bit is clear before access it.
 335                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 336                         if((u1bTmp & BIT7) == 0)
 337                                 break;
 338                         else
 339                                 mdelay(10);
 340                 }
 341
 342                 for(idx=0; idx < 3; idx++)
 343                 {
 344                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 345                 }
 346                 write_nic_byte(dev, offset, cmdByte);
 347
 348 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 349         }
 350 //by amy 080312}
 351         else{
 352                 write_nic_dword(dev, offset, data);
 353                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 354         }
 355 #else // Port IO
 356         u32 Page = (offset >> 8);
 357
 358         switch(Page)
 359         {
 360         case 0: // Page 0
 361                 write_nic_word(dev, offset, data);
 362                 break;
 363
 364         case 1: // Page 1
 365         case 2: // Page 2
 366         case 3: // Page 3
 367                 {
 368                         u8 psr = read_nic_byte(dev, PSR);
 369
 370                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 371                         write_nic_dword(dev, (offset & 0xff), data);
 372                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 373                 }
 374                 break;
 375
 376         default:
 377                 // Illegal page number.
 378                 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
 379                 break;
 380         }
 381 #endif
 382 }
 383
 384 u8
 385 PlatformIORead1Byte(
 386         struct net_device *dev,
 387         u32             offset
 388         )
 389 {
 390         u8      data = 0;
 391
 392 #ifndef CONFIG_RTL8180_IO_MAP
 393         data = read_nic_byte(dev, offset);
 394
 395 #else // Port IO
 396         u32 Page = (offset >> 8);
 397
 398         switch(Page)
 399         {
 400         case 0: // Page 0
 401                 data = read_nic_byte(dev, offset);
 402                 break;
 403
 404         case 1: // Page 1
 405         case 2: // Page 2
 406         case 3: // Page 3
 407                 {
 408                         u8 psr = read_nic_byte(dev, PSR);
 409
 410                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 411                         data = read_nic_byte(dev, (offset & 0xff));
 412                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 413                 }
 414                 break;
 415
 416         default:
 417                 // Illegal page number.
 418                 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 419                 break;
 420         }
 421 #endif
 422
 423         return data;
 424 }
 425
 426 u16
 427 PlatformIORead2Byte(
 428         struct net_device *dev,
 429         u32             offset
 430         )
 431 {
 432         u16     data = 0;
 433
 434 #ifndef CONFIG_RTL8180_IO_MAP
 435         data = read_nic_word(dev, offset);
 436
 437 #else // Port IO
 438         u32 Page = (offset >> 8);
 439
 440         switch(Page)
 441         {
 442         case 0: // Page 0
 443                 data = read_nic_word(dev, offset);
 444                 break;
 445
 446         case 1: // Page 1
 447         case 2: // Page 2
 448         case 3: // Page 3
 449                 {
 450                         u8 psr = read_nic_byte(dev, PSR);
 451
 452                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 453                         data = read_nic_word(dev, (offset & 0xff));
 454                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 455                 }
 456                 break;
 457
 458         default:
 459                 // Illegal page number.
 460                 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 461                 break;
 462         }
 463 #endif
 464
 465         return data;
 466 }
 467
 468 u32
 469 PlatformIORead4Byte(
 470         struct net_device *dev,
 471         u32             offset
 472         )
 473 {
 474         u32     data = 0;
 475
 476 #ifndef CONFIG_RTL8180_IO_MAP
 477         data = read_nic_dword(dev, offset);
 478
 479 #else // Port IO
 480         u32 Page = (offset >> 8);
 481
 482         switch(Page)
 483         {
 484         case 0: // Page 0
 485                 data = read_nic_dword(dev, offset);
 486                 break;
 487
 488         case 1: // Page 1
 489         case 2: // Page 2
 490         case 3: // Page 3
 491                 {
 492                         u8 psr = read_nic_byte(dev, PSR);
 493
 494                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 495                         data = read_nic_dword(dev, (offset & 0xff));
 496                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 497                 }
 498                 break;
 499
 500         default:
 501                 // Illegal page number.
 502                 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
 503                 break;
 504         }
 505 #endif
 506
 507         return data;
 508 }
 509
 510 void
 511 SetOutputEnableOfRfPins(
 512         struct net_device *dev
 513         )
 514 {
 515         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 516
 517         switch(priv->rf_chip)
 518         {
 519         case RFCHIPID_RTL8225:
 520         case RF_ZEBRA2:
 521         case RF_ZEBRA4:
 522                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 523                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 524                 break;
 525         }
 526 }
 527
 528 void
 529 ZEBRA_RFSerialWrite(
 530         struct net_device *dev,
 531         u32                     data2Write,
 532         u8                      totalLength,
 533         u8                      low2high
 534         )
 535 {
 536         ThreeWireReg            twreg;
 537         int                             i;
 538         u16                             oval,oval2,oval3;
 539         u32                             mask;
 540         u16                             UshortBuffer;
 541
 542         u8                      u1bTmp;
 543 #ifdef CONFIG_RTL818X_S
 544         // RTL8187S HSSI Read/Write Function
 545         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 546         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 547         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 548 #endif
 549         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 550         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 551
 552         oval2 = read_nic_word(dev, RFPinsEnable);
 553         oval3 = read_nic_word(dev, RFPinsSelect);
 554
 555         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 556         oval3 &= 0xfff8;
 557
 558         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 559         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 560         udelay(10);
 561
 562         // Add this to avoid hardware and software 3-wire conflict.
 563         // 2005.03.01, by rcnjko.
 564         twreg.longData = 0;
 565         twreg.struc.enableB = 1;
 566         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 567         udelay(2);
 568         twreg.struc.enableB = 0;
 569         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 570         udelay(10);
 571
 572         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 573
 574         for(i=0; i<totalLength/2; i++)
 575         {
 576                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 577                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 578                 twreg.struc.clk = 1;
 579                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 580                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 581
 582                 mask = (low2high)?(mask<<1):(mask>>1);
 583                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 584                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 585                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 586                 twreg.struc.clk = 0;
 587                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 588                 mask = (low2high)?(mask<<1):(mask>>1);
 589         }
 590
 591         twreg.struc.enableB = 1;
 592         twreg.struc.clk = 0;
 593         twreg.struc.data = 0;
 594         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 595         udelay(10);
 596
 597         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 598         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 599
 600         SetOutputEnableOfRfPins(dev);
 601 }
 602 //by amy
 603
 604
 605 int
 606 HwHSSIThreeWire(
 607         struct net_device *dev,
 608         u8                      *pDataBuf,
 609         u8                      nDataBufBitCnt,
 610         int                     bSI,
 611         int                     bWrite
 612         )
 613 {
 614         int     bResult = 1;
 615         u8      TryCnt;
 616         u8      u1bTmp;
 617
 618         do
 619         {
 620                 // Check if WE and RE are cleared.
 621                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 622                 {
 623                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 624                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 625                         {
 626                                 break;
 627                         }
 628                         udelay(10);
 629                 }
 630                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 631                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 632
 633                 // RTL8187S HSSI Read/Write Function
 634                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 635
 636                 if(bSI)
 637                 {
 638                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 639                 }else
 640                 {
 641                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 642                 }
 643
 644                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 645
 646                 if(bSI)
 647                 {
 648                         // jong: HW SI read must set reg84[3]=0.
 649                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 650                         u1bTmp &= ~BIT3;
 651                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 652                 }
 653                 // Fill up data buffer for write operation.
 654
 655                 if(bWrite)
 656                 {
 657                         if(nDataBufBitCnt == 16)
 658                         {
 659                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 660                         }
 661                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 662                         {
 663                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 664                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 665                         }
 666                         else
 667                         {
 668                                 int idx;
 669                                 int ByteCnt = nDataBufBitCnt / 8;
 670                                 //printk("%d\n",nDataBufBitCnt);
 671                                 if ((nDataBufBitCnt % 8) != 0)
 672                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 673                                 nDataBufBitCnt);
 674
 675                                if (nDataBufBitCnt > 64)
 676                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 677                                 nDataBufBitCnt);
 678
 679                                 for(idx = 0; idx < ByteCnt; idx++)
 680                                 {
 681                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 682                                 }
 683                         }
 684                 }
 685                 else            //read
 686                 {
 687                         if(bSI)
 688                         {
 689                                 // SI - reg274[3:0] : RF register's Address
 690                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 691                         }
 692                         else
 693                         {
 694                                 // PI - reg274[15:12] : RF register's Address
 695                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 696                         }
 697                 }
 698
 699                 // Set up command: WE or RE.
 700                 if(bWrite)
 701                 {
 702                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 703                 }
 704                 else
 705                 {
 706                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 707                 }
 708
 709                 // Check if DONE is set.
 710                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 711                 {
 712                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 713                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 714                         {
 715                                 break;
 716                         }
 717                         udelay(10);
 718                 }
 719
 720                 write_nic_byte(dev, SW_3W_CMD1, 0);
 721
 722                 // Read back data for read operation.
 723                 if(bWrite == 0)
 724                 {
 725                         if(bSI)
 726                         {
 727                                 //Serial Interface : reg363_362[11:0]
 728                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 729                         }
 730                         else
 731                         {
 732                                 //Parallel Interface : reg361_360[11:0]
 733                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 734                         }
 735
 736                         *((u16*)pDataBuf) &= 0x0FFF;
 737                 }
 738
 739         }while(0);
 740
 741         return bResult;
 742 }
 743 //by amy
 744
 745 int
 746 HwThreeWire(
 747         struct net_device *dev,
 748         u8                      *pDataBuf,
 749         u8                      nDataBufBitCnt,
 750         int                     bHold,
 751         int                     bWrite
 752         )
 753 {
 754         int     bResult = 1;
 755         u8      TryCnt;
 756         u8      u1bTmp;
 757
 758         do
 759         {
 760                 // Check if WE and RE are cleared.
 761                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 762                 {
 763                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 764                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 765                         {
 766                                 break;
 767                         }
 768                         udelay(10);
 769                 }
 770                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 771                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 772
 773                 // Fill up data buffer for write operation.
 774                 if(nDataBufBitCnt == 16)
 775                 {
 776                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 777                 }
 778                 else if(nDataBufBitCnt == 64)
 779                 {
 780                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 781                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 782                 }
 783                 else
 784                 {
 785                         int idx;
 786                         int ByteCnt = nDataBufBitCnt / 8;
 787
 788                         if ((nDataBufBitCnt % 8) != 0)
 789                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 790                                 nDataBufBitCnt);
 791
 792                         if (nDataBufBitCnt > 64)
 793                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 794                                 nDataBufBitCnt);
 795
 796                         for(idx = 0; idx < ByteCnt; idx++)
 797                         {
 798                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 799                         }
 800                 }
 801
 802                 // Fill up length field.
 803                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 804                 if(bHold)
 805                         u1bTmp |= SW_3W_CMD0_HOLD;
 806                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 807
 808                 // Set up command: WE or RE.
 809                 if(bWrite)
 810                 {
 811                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 812                 }
 813                 else
 814                 {
 815                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 816                 }
 817
 818                 // Check if WE and RE are cleared and DONE is set.
 819                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 820                 {
 821                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 822                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 823                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 824                         {
 825                                 break;
 826                         }
 827                         udelay(10);
 828                 }
 829                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 830                 {
 831                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 832                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 833                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 834                         write_nic_byte(dev, SW_3W_CMD1, 0);
 835                 }
 836
 837                 // Read back data for read operation.
 838                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 839                 if(bWrite == 0)
 840                 {
 841                         if(nDataBufBitCnt == 16)
 842                         {
 843                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 844                         }
 845                         else if(nDataBufBitCnt == 64)
 846                         {
 847                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 848                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 849                         }
 850                         else
 851                         {
 852                                 int idx;
 853                                 int ByteCnt = nDataBufBitCnt / 8;
 854
 855                                 if ((nDataBufBitCnt % 8) != 0)
 856                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 857                                         nDataBufBitCnt);
 858
 859                                 if (nDataBufBitCnt > 64)
 860                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 861                                         nDataBufBitCnt);
 862
 863                                 for(idx = 0; idx < ByteCnt; idx++)
 864                                 {
 865                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 866                                 }
 867                         }
 868                 }
 869
 870         }while(0);
 871
 872         return bResult;
 873 }
 874
 875
 876 void
 877 RF_WriteReg(
 878         struct net_device *dev,
 879         u8              offset,
 880         u32             data
 881         )
 882 {
 883         //RFReg                 reg;
 884         u32                     data2Write;
 885         u8                      len;
 886         u8                      low2high;
 887         //u32                   RF_Read = 0;
 888         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 889
 890
 891         switch(priv->rf_chip)
 892         {
 893         case RFCHIPID_RTL8225:
 894         case RF_ZEBRA2:         // Annie 2006-05-12.
 895         case RF_ZEBRA4:        //by amy
 896                 switch(priv->RegThreeWireMode)
 897                 {
 898                 case SW_THREE_WIRE:
 899                         { // Perform SW 3-wire programming by driver.
 900                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 901                                 len = 16;
 902                                 low2high = 0;
 903                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 904                         }
 905                         break;
 906
 907                 case HW_THREE_WIRE:
 908                         { // Pure HW 3-wire.
 909                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 910                                 len = 16;
 911                                 HwThreeWire(
 912                                         dev,
 913                                         (u8 *)(&data2Write),    // pDataBuf,
 914                                         len,                            // nDataBufBitCnt,
 915                                         0,                                      // bHold,
 916                                         1);                                     // bWrite
 917                         }
 918                         break;
 919   #ifdef CONFIG_RTL818X_S
 920                         case HW_THREE_WIRE_PI: //Parallel Interface
 921                         { // Pure HW 3-wire.
 922                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 923                                 len = 16;
 924                                         HwHSSIThreeWire(
 925                                                 dev,
 926                                                 (u8*)(&data2Write),     // pDataBuf,
 927                                                 len,                                            // nDataBufBitCnt,
 928                                                 0,                                      // bSI
 929                                                 1);                                     // bWrite
 930
 931                                 //printk("33333\n");
 932                         }
 933                         break;
 934
 935                         case HW_THREE_WIRE_SI: //Serial Interface
 936                         { // Pure HW 3-wire.
 937                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 938                                 len = 16;
 939 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 940 //                                low2high = 0;
 941 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 942
 943                                 HwHSSIThreeWire(
 944                                         dev,
 945                                         (u8*)(&data2Write),     // pDataBuf,
 946                                         len,                                            // nDataBufBitCnt,
 947                                         1,                                      // bSI
 948                                         1);                                     // bWrite
 949
 950 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 951                         }
 952                         break;
 953   #endif
 954
 955
 956                 default:
 957                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 958                         break;
 959                 }
 960                 break;
 961
 962         default:
 963                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 964                 break;
 965         }
 966 }
 967
 968
 969 void
 970 ZEBRA_RFSerialRead(
 971         struct net_device *dev,
 972         u32             data2Write,
 973         u8              wLength,
 974         u32             *data2Read,
 975         u8              rLength,
 976         u8              low2high
 977         )
 978 {
 979         ThreeWireReg    twreg;
 980         int                             i;
 981         u16                     oval,oval2,oval3,tmp, wReg80;
 982         u32                     mask;
 983         u8                      u1bTmp;
 984         ThreeWireReg    tdata;
 985         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 986 #ifdef CONFIG_RTL818X_S
 987         { // RTL8187S HSSI Read/Write Function
 988                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 989                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 990                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 991         }
 992 #endif
 993
 994         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 995         oval2 = read_nic_word(dev, RFPinsEnable);
 996         oval3 = read_nic_word(dev, RFPinsSelect);
 997
 998         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 999         write_nic_word(dev, RFPinsSelect, oval3|0xf);
1000
1001         *data2Read = 0;
1002
1003         // We must clear BIT0-3 here, otherwise,
1004         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
1005         // which will cause the value read become 0. 2005.04.11, by rcnjko.
1006         oval &= ~0xf;
1007
1008         // Avoid collision with hardware three-wire.
1009         twreg.longData = 0;
1010         twreg.struc.enableB = 1;
1011         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
1012
1013         twreg.longData = 0;
1014         twreg.struc.enableB = 0;
1015         twreg.struc.clk = 0;
1016         twreg.struc.read_write = 0;
1017         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
1018
1019         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
1020         for(i = 0; i < wLength/2; i++)
1021         {
1022                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
1023                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1024                 twreg.struc.clk = 1;
1025                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1026                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1027
1028                 mask = (low2high) ? (mask<<1): (mask>>1);
1029
1030                 if(i == 2)
1031                 {
1032                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
1033                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
1034                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
1035
1036                         twreg.struc.read_write=1;
1037                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1038                         twreg.struc.clk = 0;
1039                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1040                         break;
1041                 }
1042                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
1043                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1044                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1045
1046                 twreg.struc.clk = 0;
1047                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1048
1049                 mask = (low2high) ? (mask<<1) : (mask>>1);
1050         }
1051
1052         twreg.struc.clk = 0;
1053         twreg.struc.data = 0;
1054         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1055         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
1056
1057         //
1058         // 061016, by rcnjko:
1059         // We must set data pin to HW controled, otherwise RF can't driver it and
1060         // value RF register won't be able to read back properly.
1061         //
1062         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
1063
1064         for(i = 0; i < rLength; i++)
1065         {
1066                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1067                 twreg.struc.clk = 1;
1068                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1069                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1070                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1071                 tmp = read_nic_word(dev, RFPinsInput);
1072                 tdata.longData = tmp;
1073                 *data2Read |= tdata.struc.clk ? mask : 0;
1074
1075                 twreg.struc.clk = 0;
1076                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1077
1078                 mask = (low2high) ? (mask<<1) : (mask>>1);
1079         }
1080         twreg.struc.enableB = 1;
1081         twreg.struc.clk = 0;
1082         twreg.struc.data = 0;
1083         twreg.struc.read_write = 1;
1084         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1085
1086         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
1087         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
1088         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
1089         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
1090         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
1091         write_nic_word(dev, RFPinsOutput, 0x3a0);
1092         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
1093 }
1094
1095
1096 u32
1097 RF_ReadReg(
1098         struct net_device *dev,
1099         u8              offset
1100         )
1101 {
1102         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1103         u32                     data2Write;
1104         u8                      wlen;
1105         u8                      rlen;
1106         u8                      low2high;
1107         u32                     dataRead;
1108
1109         switch(priv->rf_chip)
1110         {
1111         case RFCHIPID_RTL8225:
1112         case RF_ZEBRA2:
1113         case RF_ZEBRA4:
1114                 switch(priv->RegThreeWireMode)
1115                 {
1116 #ifdef CONFIG_RTL818X_S
1117                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
1118                         {
1119                                 data2Write = ((u32)(offset&0x0f));
1120                                 wlen=16;
1121                                 HwHSSIThreeWire(
1122                                         dev,
1123                                         (u8*)(&data2Write),     // pDataBuf,
1124                                         wlen,                                   // nDataBufBitCnt,
1125                                         0,                                      // bSI
1126                                         0);                                     // bWrite
1127                                 dataRead= data2Write;
1128                         }
1129                         break;
1130
1131                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1132                         {
1133                                 data2Write = ((u32)(offset&0x0f)) ;
1134                                 wlen=16;
1135                                 HwHSSIThreeWire(
1136                                         dev,
1137                                         (u8*)(&data2Write),     // pDataBuf,
1138                                         wlen,                                   // nDataBufBitCnt,
1139                                         1,                                      // bSI
1140                                         0                                       // bWrite
1141                                         );
1142                                 dataRead= data2Write;
1143                         }
1144                         break;
1145
1146 #endif
1147                         // Perform SW 3-wire programming by driver.
1148                         default:
1149                         {
1150                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1151                                 wlen = 6;
1152                                 rlen = 12;
1153                                 low2high = 0;
1154                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1155                         }
1156                         break;
1157                 }
1158                 break;
1159         default:
1160                 dataRead = 0;
1161                 break;
1162         }
1163
1164         return dataRead;
1165 }
1166
1167
1168 // by Owen on 04/07/14 for writing BB register successfully
1169 void
1170 WriteBBPortUchar(
1171         struct net_device *dev,
1172         u32             Data
1173         )
1174 {
1175         //u8    TimeoutCounter;
1176         u8      RegisterContent;
1177         u8      UCharData;
1178
1179         UCharData = (u8)((Data & 0x0000ff00) >> 8);
1180         PlatformIOWrite4Byte(dev, PhyAddr, Data);
1181         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1182         {
1183                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1184                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1185                 //if(UCharData == RegisterContent)
1186                 //      break;
1187         }
1188 }
1189
1190 u8
1191 ReadBBPortUchar(
1192         struct net_device *dev,
1193         u32             addr
1194         )
1195 {
1196         //u8    TimeoutCounter;
1197         u8      RegisterContent;
1198
1199         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1200         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1201
1202         return RegisterContent;
1203 }
1204 //{by amy 080312
1205 #ifdef CONFIG_RTL818X_S
1206 //
1207 //      Description:
1208 //              Perform Antenna settings with antenna diversity on 87SE.
1209 //    Created by Roger, 2008.01.25.
1210 //
1211 bool
1212 SetAntennaConfig87SE(
1213         struct net_device *dev,
1214         u8                      DefaultAnt,             // 0: Main, 1: Aux.
1215         bool            bAntDiversity   // 1:Enable, 0: Disable.
1216 )
1217 {
1218         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1219         bool   bAntennaSwitched = true;
1220
1221         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1222
1223         // Threshold for antenna diversity.
1224         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1225
1226         if( bAntDiversity )  //  Enable Antenna Diversity.
1227         {
1228                 if( DefaultAnt == 1 )  // aux antenna
1229                 {
1230                         // Mac register, aux antenna
1231                         write_nic_byte(dev, ANTSEL, 0x00);
1232
1233                         // Config CCK RX antenna.
1234                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1235                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1236
1237                         // Config OFDM RX antenna.
1238                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1239                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1240                 }
1241                 else //  use main antenna
1242                 {
1243                         // Mac register, main antenna
1244                         write_nic_byte(dev, ANTSEL, 0x03);
1245                         //base band
1246                         // Config CCK RX antenna.
1247                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1248                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1249
1250                         // Config OFDM RX antenna.
1251                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1252                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1253                 }
1254         }
1255         else   // Disable Antenna Diversity.
1256         {
1257                 if( DefaultAnt == 1 ) // aux Antenna
1258                 {
1259                         // Mac register, aux antenna
1260                         write_nic_byte(dev, ANTSEL, 0x00);
1261
1262                         // Config CCK RX antenna.
1263                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1264                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1265
1266                         // Config OFDM RX antenna.
1267                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1268                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1269                 }
1270                 else // main Antenna
1271                 {
1272                         // Mac register, main antenna
1273                         write_nic_byte(dev, ANTSEL, 0x03);
1274
1275                         // Config CCK RX antenna.
1276                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1277                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1278
1279                         // Config OFDM RX antenna.
1280                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1281                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1282                 }
1283         }
1284         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1285         return  bAntennaSwitched;
1286 }
1287 #endif
1288 //by amy 080312
1289 /*---------------------------------------------------------------
1290   * Hardware Initialization.
1291   * the code is ported from Windows source code
1292   ----------------------------------------------------------------*/
1293
1294 void
1295 ZEBRA_Config_85BASIC_HardCode(
1296         struct net_device *dev
1297         )
1298 {
1299
1300         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1301         u32                     i;
1302         u32     addr,data;
1303         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1304        u8                       u1b24E;
1305
1306 #ifdef CONFIG_RTL818X_S
1307
1308         //=============================================================================
1309         // 87S_PCIE :: RADIOCFG.TXT
1310         //=============================================================================
1311
1312
1313         // Page1 : reg16-reg30
1314         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1315         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1316         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1317
1318         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1319                 priv->card_8185 = VERSION_8187S_D;
1320
1321         // Page0 : reg0-reg15
1322
1323 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1324         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1325
1326         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1327
1328 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1329         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1330
1331 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1332         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1333
1334         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1335         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1336         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1337         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1338         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1339         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1340         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1341         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1342         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1343         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1344         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1345         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1346
1347
1348         // Page1 : reg16-reg30
1349         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1350
1351         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1352
1353         if(priv->card_8185 < VERSION_8187S_C)
1354         {
1355                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1356                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1357                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1358         }
1359         else
1360         {
1361                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1362                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1363                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1364         }
1365
1366
1367         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1368 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1369 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1370 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1371         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1372         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1373
1374         if(priv->card_8185 == VERSION_8187S_D)
1375         {
1376                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1377                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1378                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1379         }
1380         else
1381         {
1382                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1383                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1384                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1385         }
1386
1387         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1388
1389 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1390         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1391
1392         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1393         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1394         for(i=0;i<=36;i++)
1395         {
1396                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1397                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1398                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1399         }
1400
1401         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1402         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1403         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1404
1405         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1406         mdelay(10);     // Deay 10 ms. //0xfd
1407
1408 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1409         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1410         //mdelay(10);   // Deay 10 ms. //0xfd
1411
1412         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1413         mdelay(10);     // Deay 10 ms. //0xfd
1414
1415         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1416         mdelay(10);     // Deay 10 ms. //0xfd
1417
1418         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1419         mdelay(10);     // Deay 10 ms. //0xfd
1420
1421         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1422         mdelay(10);     // Deay 10 ms. //0xfd
1423
1424         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1425         mdelay(200);    // Deay 200 ms. //0xfd
1426         mdelay(10);     // Deay 10 ms. //0xfd
1427         mdelay(10);     // Deay 10 ms. //0xfd
1428
1429         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1430         mdelay(10);     // Deay 10 ms. //0xfd
1431
1432         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1433         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1434         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1435         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1436
1437         // DAC calibration off 20070702
1438         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1439         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1440 //{by amy 080312
1441         // For crystal calibration, added by Roger, 2007.12.11.
1442         if( priv->bXtalCalibration ) // reg 30.
1443         { // enable crystal calibration.
1444                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1445                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1446                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1447                 // So we should minus 4 BITs offset.
1448                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1449                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1450                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1451         }
1452         else
1453         { // using default value. Xin=6, Xout=6.
1454                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1455         }
1456 //by amy 080312
1457 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1458
1459         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1460 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1461         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1462         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1463         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1464         mdelay(10);     // Deay 10 ms. //0xfe
1465         mdelay(10);     // Deay 10 ms. //0xfe
1466         mdelay(10);     // Deay 10 ms. //0xfe
1467         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1468         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1469         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1470
1471 #if 0//-edward
1472         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1);
1473         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1474         RF_WriteReg(dev, 0x00, 0x009F);                 mdelay(1);
1475 #endif
1476         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1477         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1478         //power save parameters.
1479         u1b24E = read_nic_byte(dev, 0x24E);
1480         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1481
1482         //=============================================================================
1483
1484         //=============================================================================
1485         // CCKCONF.TXT
1486         //=============================================================================
1487
1488         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1489                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1490                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1491                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1492                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1493                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1494         */
1495 #if 0
1496         write_nic_dword(dev, PHY_ADR, 0x0100c880);
1497         write_nic_dword(dev, PHY_ADR, 0x01001c86);
1498         write_nic_dword(dev, PHY_ADR, 0x01007890);
1499         write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1500         write_nic_dword(dev, PHY_ADR, 0x010006af);
1501         write_nic_dword(dev, PHY_ADR, 0x01004681);
1502 #endif
1503         write_phy_cck(dev,0x00,0xc8);
1504         write_phy_cck(dev,0x06,0x1c);
1505         write_phy_cck(dev,0x10,0x78);
1506         write_phy_cck(dev,0x2e,0xd0);
1507         write_phy_cck(dev,0x2f,0x06);
1508         write_phy_cck(dev,0x01,0x46);
1509
1510         // power control
1511         write_nic_byte(dev, CCK_TXAGC, 0x10);
1512         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1513         write_nic_byte(dev, ANTSEL, 0x03);
1514 #else
1515         //=============================================================================
1516         // RADIOCFG.TXT
1517         //=============================================================================
1518
1519         RF_WriteReg(dev, 0x00, 0x00b7);                 mdelay(1);
1520         RF_WriteReg(dev, 0x01, 0x0ee0);                 mdelay(1);
1521         RF_WriteReg(dev, 0x02, 0x044d);                 mdelay(1);
1522         RF_WriteReg(dev, 0x03, 0x0441);                 mdelay(1);
1523         RF_WriteReg(dev, 0x04, 0x08c3);                 mdelay(1);
1524         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1525         RF_WriteReg(dev, 0x06, 0x00e6);                 mdelay(1);
1526         RF_WriteReg(dev, 0x07, 0x082a);                 mdelay(1);
1527         RF_WriteReg(dev, 0x08, 0x003f);                 mdelay(1);
1528         RF_WriteReg(dev, 0x09, 0x0335);                 mdelay(1);
1529         RF_WriteReg(dev, 0x0a, 0x09d4);                 mdelay(1);
1530         RF_WriteReg(dev, 0x0b, 0x07bb);                 mdelay(1);
1531         RF_WriteReg(dev, 0x0c, 0x0850);                 mdelay(1);
1532         RF_WriteReg(dev, 0x0d, 0x0cdf);                 mdelay(1);
1533         RF_WriteReg(dev, 0x0e, 0x002b);                 mdelay(1);
1534         RF_WriteReg(dev, 0x0f, 0x0114);                 mdelay(1);
1535
1536         RF_WriteReg(dev, 0x00, 0x01b7);                 mdelay(1);
1537
1538
1539         for(i=1;i<=95;i++)
1540         {
1541                 RF_WriteReg(dev, 0x01, i);      mdelay(1);
1542                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1543                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1544         }
1545
1546         RF_WriteReg(dev, 0x03, 0x0080);                 mdelay(1);      // write reg 18
1547         RF_WriteReg(dev, 0x05, 0x0004);                 mdelay(1);      // write reg 20
1548         RF_WriteReg(dev, 0x00, 0x00b7);                 mdelay(1);      // switch to reg0-reg15
1549         //0xfd
1550         //0xfd
1551         //0xfd
1552         RF_WriteReg(dev, 0x02, 0x0c4d);                 mdelay(1);
1553         mdelay(100);    // Deay 100 ms. //0xfe
1554         mdelay(100);    // Deay 100 ms. //0xfe
1555         RF_WriteReg(dev, 0x02, 0x044d);                 mdelay(1);
1556         RF_WriteReg(dev, 0x00, 0x02bf);                 mdelay(1);      //0x002f disable 6us corner change,  06f--> enable
1557
1558         //=============================================================================
1559
1560         //=============================================================================
1561         // CCKCONF.TXT
1562         //=============================================================================
1563
1564         //=============================================================================
1565
1566         //=============================================================================
1567         // Follow WMAC RTL8225_Config()
1568         //=============================================================================
1569
1570         // power control
1571         write_nic_byte(dev, CCK_TXAGC, 0x03);
1572         write_nic_byte(dev, OFDM_TXAGC, 0x07);
1573         write_nic_byte(dev, ANTSEL, 0x03);
1574
1575         //=============================================================================
1576
1577         // OFDM BBP setup
1578 //      SetOutputEnableOfRfPins(dev);//by amy
1579 #endif
1580
1581
1582
1583         //=============================================================================
1584         // AGC.txt
1585         //=============================================================================
1586
1587 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1588         write_phy_ofdm(dev, 0x00, 0x12);
1589         //WriteBBPortUchar(dev, 0x00001280);
1590
1591         for (i=0; i<128; i++)
1592         {
1593                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1594
1595                 data = ZEBRA_AGC[i+1];
1596                 data = data << 8;
1597                 data = data | 0x0000008F;
1598
1599                 addr = i + 0x80; //enable writing AGC table
1600                 addr = addr << 8;
1601                 addr = addr | 0x0000008E;
1602
1603                 WriteBBPortUchar(dev, data);
1604                 WriteBBPortUchar(dev, addr);
1605                 WriteBBPortUchar(dev, 0x0000008E);
1606         }
1607
1608         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1609         //WriteBBPortUchar(dev, 0x00001080);
1610
1611         //=============================================================================
1612
1613         //=============================================================================
1614         // OFDMCONF.TXT
1615         //=============================================================================
1616
1617         for(i=0; i<60; i++)
1618         {
1619                 u4bRegOffset=i;
1620                 u4bRegValue=OFDM_CONFIG[i];
1621
1622                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1623
1624                 WriteBBPortUchar(dev,
1625                                                 (0x00000080 |
1626                                                 (u4bRegOffset & 0x7f) |
1627                                                 ((u4bRegValue & 0xff) << 8)));
1628         }
1629
1630         //=============================================================================
1631 //by amy for antenna
1632         //=============================================================================
1633 //{by amy 080312
1634 #ifdef CONFIG_RTL818X_S
1635         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1636         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1637 #endif
1638 //by amy 080312}
1639 #if 0
1640         // Config Sw/Hw  Antenna Diversity
1641         if( priv->bSwAntennaDiverity )  //  Use SW+Hw Antenna Diversity
1642         {
1643                 if( priv->bDefaultAntenna1 == true )  // aux antenna
1644                 {
1645                         // Mac register, aux antenna
1646                         write_nic_byte(dev, ANTSEL, 0x00);
1647                         // Config CCK RX antenna.
1648                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1649                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1650                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1651                         // Config OFDM RX antenna.
1652                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1653                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1654                 }
1655                 else //  main antenna
1656                 {
1657                         // Mac register, main antenna
1658                         write_nic_byte(dev, ANTSEL, 0x03);
1659                         //base band
1660                         // Config CCK RX antenna.
1661                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1662                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1663                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1664                         // Config OFDM RX antenna.
1665                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1666                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1667                 }
1668         }
1669         else   // Disable Antenna Diversity
1670         {
1671                 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1672                 {
1673                         // Mac register, aux antenna
1674                         write_nic_byte(dev, ANTSEL, 0x00);
1675                         // Config CCK RX antenna.
1676                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1677                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1678                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1679                         // Config OFDM RX antenna.
1680                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1681                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1682                 }
1683                 else // main Antenna
1684                 {
1685                         // Mac register, main antenna
1686                         write_nic_byte(dev, ANTSEL, 0x03);
1687                         // Config CCK RX antenna.
1688                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1689                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1690                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1691                         // Config OFDM RX antenna.
1692                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1693                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1694                 }
1695         }
1696 #endif
1697 //by amy for antenna
1698 }
1699
1700
1701 void
1702 UpdateInitialGain(
1703         struct net_device *dev
1704         )
1705 {
1706         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1707         //unsigned char* IGTable;
1708         //u8                    DIG_CurrentInitialGain = 4;
1709         //unsigned char u1Tmp;
1710
1711         //lzm add 080826
1712         if(priv->eRFPowerState != eRfOn)
1713         {
1714                 //Don't access BB/RF under disable PLL situation.
1715                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1716                 // Back to the original state
1717                 priv->InitialGain= priv->InitialGainBackUp;
1718                 return;
1719         }
1720
1721         switch(priv->rf_chip)
1722         {
1723 #if 0
1724         case RF_ZEBRA2:
1725                 // Dynamic set initial gain, by shien chang, 2006.07.14
1726                 switch(priv->InitialGain)
1727                 {
1728                         case 1: //m861dBm
1729                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1730                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1731                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1732                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1733                                 break;
1734
1735                         case 2: //m862dBm
1736                                 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1737                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1738                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1739                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1740                                 break;
1741
1742                         case 3: //m863dBm
1743                                 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1744                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1745                                 write_nic_dword(dev, PhyAddr, 0x96a4);  mdelay(1);
1746                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1747                                 break;
1748
1749                         case 4: //m864dBm
1750                                 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1751                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1752                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1753                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1754                                 break;
1755
1756                         case 5: //m82dBm
1757                                 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1758                                 write_nic_dword(dev, PhyAddr, 0x3697);  mdelay(1);
1759                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1760                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1761                                 break;
1762
1763                         case 6: //m78dBm
1764                                 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1765                                 write_nic_dword(dev, PhyAddr, 0x4697);  mdelay(1);
1766                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1767                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1768                                 break;
1769
1770                         case 7: //m74dBm
1771                                 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1772                                 write_nic_dword(dev, PhyAddr, 0x5697);  mdelay(1);
1773                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1774                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1775                                 break;
1776
1777                         default:        //MP
1778                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1779                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1780                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1781                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1782                                 break;
1783                 }
1784                 break;
1785 #endif
1786         case RF_ZEBRA4:
1787                 // Dynamic set initial gain, follow 87B
1788                 switch(priv->InitialGain)
1789                 {
1790                         case 1: //m861dBm
1791                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1792                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1793                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1794                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1795                                 break;
1796
1797                         case 2: //m862dBm
1798                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1799                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1800                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1801                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1802                                 break;
1803
1804                         case 3: //m863dBm
1805                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1806                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1807                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1808                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1809                                 break;
1810
1811                         case 4: //m864dBm
1812                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1813                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1814                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1815                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1816                                 break;
1817
1818                         case 5: //m82dBm
1819                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1820                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1821                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1822                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1823                                 break;
1824
1825                         case 6: //m78dBm
1826                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1827                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1828                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1829                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1830                                 break;
1831
1832                         case 7: //m74dBm
1833                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1834                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1835                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1836                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1837                                 break;
1838
1839                         case 8:
1840                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1841                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1842                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1843                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1844                                 break;
1845
1846
1847                         default:        //MP
1848                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1849                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1850                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1851                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1852                                 break;
1853                 }
1854                 break;
1855
1856
1857         default:
1858                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1859                 break;
1860         }
1861 }
1862 #ifdef CONFIG_RTL818X_S
1863 //
1864 //      Description:
1865 //              Tx Power tracking mechanism routine on 87SE.
1866 //      Created by Roger, 2007.12.11.
1867 //
1868 void
1869 InitTxPwrTracking87SE(
1870         struct net_device *dev
1871 )
1872 {
1873         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1874         u32     u4bRfReg;
1875
1876         u4bRfReg = RF_ReadReg(dev, 0x02);
1877
1878         // Enable Thermal meter indication.
1879         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1880         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1881 }
1882
1883 #endif
1884 void
1885 PhyConfig8185(
1886         struct net_device *dev
1887         )
1888 {
1889         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1890        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1891            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1892         // RF config
1893         switch(priv->rf_chip)
1894         {
1895         case RF_ZEBRA2:
1896         case RF_ZEBRA4:
1897                 ZEBRA_Config_85BASIC_HardCode( dev);
1898                 break;
1899         }
1900 //{by amy 080312
1901 #ifdef CONFIG_RTL818X_S
1902         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1903         if(priv->bDigMechanism)
1904         {
1905                 if(priv->InitialGain == 0)
1906                         priv->InitialGain = 4;
1907                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1908         }
1909
1910         //
1911         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1912         // We initialize thermal meter here to avoid unsuccessful configuration.
1913         // Added by Roger, 2007.12.11.
1914         //
1915         if(priv->bTxPowerTrack)
1916                 InitTxPwrTracking87SE(dev);
1917
1918 #endif
1919 //by amy 080312}
1920         priv->InitialGainBackUp= priv->InitialGain;
1921         UpdateInitialGain(dev);
1922
1923         return;
1924 }
1925
1926
1927
1928
1929 void
1930 HwConfigureRTL8185(
1931                 struct net_device *dev
1932                 )
1933 {
1934         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1935 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1936         u8              bUNIVERSAL_CONTROL_RL = 0;
1937
1938         u8              bUNIVERSAL_CONTROL_AGC = 1;
1939         u8              bUNIVERSAL_CONTROL_ANT = 1;
1940         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1941         u8              val8;
1942         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1943         //struct ieee80211_device *ieee = priv->ieee80211;
1944         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1945 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1946 //      {
1947 //              write_nic_word(dev, BRSR, 0xffff);
1948 //      }
1949 //      else
1950 //      {
1951 //              write_nic_word(dev, BRSR, 0x000f);
1952 //      }
1953 //by amy 080312}
1954         write_nic_word(dev, BRSR, 0x0fff);
1955         // Retry limit
1956         val8 = read_nic_byte(dev, CW_CONF);
1957
1958         if(bUNIVERSAL_CONTROL_RL)
1959                 val8 = val8 & 0xfd;
1960         else
1961                 val8 = val8 | 0x02;
1962
1963         write_nic_byte(dev, CW_CONF, val8);
1964
1965         // Tx AGC
1966         val8 = read_nic_byte(dev, TXAGC_CTL);
1967         if(bUNIVERSAL_CONTROL_AGC)
1968         {
1969                 write_nic_byte(dev, CCK_TXAGC, 128);
1970                 write_nic_byte(dev, OFDM_TXAGC, 128);
1971                 val8 = val8 & 0xfe;
1972         }
1973         else
1974         {
1975                 val8 = val8 | 0x01 ;
1976         }
1977
1978
1979         write_nic_byte(dev, TXAGC_CTL, val8);
1980
1981         // Tx Antenna including Feedback control
1982         val8 = read_nic_byte(dev, TXAGC_CTL );
1983
1984         if(bUNIVERSAL_CONTROL_ANT)
1985         {
1986                 write_nic_byte(dev, ANTSEL, 0x00);
1987                 val8 = val8 & 0xfd;
1988         }
1989         else
1990         {
1991                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1992         }
1993
1994         write_nic_byte(dev, TXAGC_CTL, val8);
1995
1996         // Auto Rate fallback control
1997         val8 = read_nic_byte(dev, RATE_FALLBACK);
1998         val8 &= 0x7c;
1999         if( bAUTO_RATE_FALLBACK_CTL )
2000         {
2001                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
2002
2003                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
2004                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
2005 //by amy
2006 #if 0
2007                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff);        // set 1M ~ 54M
2008 #endif
2009 #ifdef CONFIG_RTL818X_S
2010                 // Aadded by Roger, 2007.11.15.
2011                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
2012 #else
2013                 PlatformIOWrite2Byte(dev, ARFR, 0x0c00); //set 48Mbps, 54Mbps.
2014                 // By SD3 szuyi's request. by Roger, 2007.03.26.
2015 #endif
2016 //by amy
2017         }
2018         else
2019         {
2020         }
2021         write_nic_byte(dev, RATE_FALLBACK, val8);
2022 }
2023
2024
2025
2026 static void
2027 MacConfig_85BASIC_HardCode(
2028         struct net_device *dev)
2029 {
2030         //============================================================================
2031         // MACREG.TXT
2032         //============================================================================
2033         int                     nLinesRead = 0;
2034
2035         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
2036         int     i;
2037
2038         nLinesRead=sizeof(MAC_REG_TABLE)/2;
2039
2040         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
2041         {
2042                 u4bRegOffset=MAC_REG_TABLE[i][0];
2043                 u4bRegValue=MAC_REG_TABLE[i][1];
2044
2045                 if(u4bRegOffset == 0x5e)
2046                 {
2047                     u4bPageIndex = u4bRegValue;
2048                 }
2049                 else
2050                 {
2051                     u4bRegOffset |= (u4bPageIndex << 8);
2052                 }
2053                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
2054                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
2055         }
2056         //============================================================================
2057 }
2058
2059
2060
2061 static void
2062 MacConfig_85BASIC(
2063         struct net_device *dev)
2064 {
2065
2066        u8                       u1DA;
2067         MacConfig_85BASIC_HardCode(dev);
2068
2069         //============================================================================
2070
2071         // Follow TID_AC_MAP of WMac.
2072         write_nic_word(dev, TID_AC_MAP, 0xfa50);
2073
2074         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
2075         write_nic_word(dev, IntMig, 0x0000);
2076
2077         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
2078         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
2079         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
2080         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
2081
2082         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
2083         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
2084 //by amy
2085 #if 0
2086         write_nic_dword(dev, RFTiming, 0x00004001);
2087 #endif
2088 #ifdef CONFIG_RTL818X_S
2089         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
2090
2091         //Enable DA10 TX power saving
2092         u1DA = read_nic_byte(dev, PHYPR);
2093         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
2094
2095         //POWER:
2096         write_nic_word(dev, 0x360, 0x1000);
2097         write_nic_word(dev, 0x362, 0x1000);
2098
2099         // AFE.
2100         write_nic_word(dev, 0x370, 0x0560);
2101         write_nic_word(dev, 0x372, 0x0560);
2102         write_nic_word(dev, 0x374, 0x0DA4);
2103         write_nic_word(dev, 0x376, 0x0DA4);
2104         write_nic_word(dev, 0x378, 0x0560);
2105         write_nic_word(dev, 0x37A, 0x0560);
2106         write_nic_word(dev, 0x37C, 0x00EC);
2107 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
2108         write_nic_word(dev, 0x37E, 0x00EC);//+edward
2109 #else
2110        write_nic_dword(dev, RFTiming, 0x00004003);
2111 #endif
2112        write_nic_byte(dev, 0x24E,0x01);
2113 //by amy
2114
2115 }
2116
2117
2118
2119
2120 u8
2121 GetSupportedWirelessMode8185(
2122         struct net_device *dev
2123 )
2124 {
2125         u8                      btSupportedWirelessMode = 0;
2126         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2127
2128         switch(priv->rf_chip)
2129         {
2130         case RF_ZEBRA2:
2131         case RF_ZEBRA4:
2132                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
2133                 break;
2134         default:
2135                 btSupportedWirelessMode = WIRELESS_MODE_B;
2136                 break;
2137         }
2138
2139         return btSupportedWirelessMode;
2140 }
2141
2142 void
2143 ActUpdateChannelAccessSetting(
2144         struct net_device *dev,
2145         WIRELESS_MODE                   WirelessMode,
2146         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
2147         )
2148 {
2149         struct r8180_priv *priv = ieee80211_priv(dev);
2150         struct ieee80211_device *ieee = priv->ieee80211;
2151         AC_CODING       eACI;
2152         AC_PARAM        AcParam;
2153         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
2154         u8      bFollowLegacySetting = 0;
2155         u8   u1bAIFS;
2156
2157         //
2158         // <RJ_TODO_8185B>
2159         // TODO: We still don't know how to set up these registers, just follow WMAC to
2160         // verify 8185B FPAG.
2161         //
2162         // <RJ_TODO_8185B>
2163         // Jong said CWmin/CWmax register are not functional in 8185B,
2164         // so we shall fill channel access realted register into AC parameter registers,
2165         // even in nQBss.
2166         //
2167         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
2168         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
2169         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
2170         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2171         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
2172         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
2173
2174         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
2175         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2176         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2177
2178         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
2179
2180         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
2181         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
2182         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
2183         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
2184
2185         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
2186
2187         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2188
2189 #ifdef TODO
2190         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2191         if( pStaQos->CurrentQosMode > QOS_DISABLE )
2192         { // QoS mode.
2193                 if(pStaQos->QBssWirelessMode == WirelessMode)
2194                 {
2195                         // Follow AC Parameters of the QBSS.
2196                         for(eACI = 0; eACI < AC_MAX; eACI++)
2197                         {
2198                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2199                         }
2200                 }
2201                 else
2202                 {
2203                         // Follow Default WMM AC Parameters.
2204                         bFollowLegacySetting = 1;
2205                 }
2206         }
2207         else
2208 #endif
2209         { // Legacy 802.11.
2210                 bFollowLegacySetting = 1;
2211
2212         }
2213
2214         // this setting is copied from rtl8187B.  xiong-2006-11-13
2215         if(bFollowLegacySetting)
2216         {
2217
2218
2219                 //
2220                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2221                 // 2005.12.01, by rcnjko.
2222                 //
2223                 AcParam.longData = 0;
2224                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2225                 AcParam.f.AciAifsn.f.ACM = 0;
2226                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2227                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2228                 AcParam.f.TXOPLimit = 0;
2229
2230                 //lzm reserved 080826
2231 #if 1
2232 #ifdef THOMAS_TURBO
2233                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2234                 if( ieee->current_network.Turbo_Enable == 1 )
2235                         AcParam.f.TXOPLimit = 0x01FF;
2236 #endif
2237                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
2238                 if (ieee->iw_mode == IW_MODE_ADHOC)
2239                         AcParam.f.TXOPLimit = 0x0020;
2240 #endif
2241
2242                 for(eACI = 0; eACI < AC_MAX; eACI++)
2243                 {
2244                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2245                         {
2246                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
2247                                 AC_CODING       eACI;
2248                                 u8              u1bAIFS;
2249                                 u32             u4bAcParam;
2250
2251                                 // Retrive paramters to udpate.
2252                                 eACI = pAcParam->f.AciAifsn.f.ACI;
2253                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2254                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
2255                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
2256                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
2257                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2258
2259                                 switch(eACI)
2260                                 {
2261                                         case AC1_BK:
2262                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2263                                                 break;
2264
2265                                         case AC0_BE:
2266                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2267                                                 break;
2268
2269                                         case AC2_VI:
2270                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2271                                                 break;
2272
2273                                         case AC3_VO:
2274                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2275                                                 break;
2276
2277                                         default:
2278                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2279                                                 break;
2280                                 }
2281
2282                                 // Cehck ACM bit.
2283                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2284                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2285                                 {
2286                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2287                                         AC_CODING       eACI = pAciAifsn->f.ACI;
2288
2289                                         //modified Joseph
2290                                         //for 8187B AsynIORead issue
2291 #ifdef TODO
2292                                         u8      AcmCtrl = pHalData->AcmControl;
2293 #else
2294                                         u8      AcmCtrl = 0;
2295 #endif
2296                                         if( pAciAifsn->f.ACM )
2297                                         { // ACM bit is 1.
2298                                                 switch(eACI)
2299                                                 {
2300                                                         case AC0_BE:
2301                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
2302                                                                 break;
2303
2304                                                         case AC2_VI:
2305                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
2306                                                                 break;
2307
2308                                                         case AC3_VO:
2309                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
2310                                                                 break;
2311
2312                                                         default:
2313                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2314                                                                 break;
2315                                                 }
2316                                         }
2317                                         else
2318                                         { // ACM bit is 0.
2319                                                 switch(eACI)
2320                                                 {
2321                                                         case AC0_BE:
2322                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
2323                                                                 break;
2324
2325                                                         case AC2_VI:
2326                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
2327                                                                 break;
2328
2329                                                         case AC3_VO:
2330                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
2331                                                                 break;
2332
2333                                                         default:
2334                                                                 break;
2335                                                 }
2336                                         }
2337
2338                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2339
2340 #ifdef TO_DO
2341                                         pHalData->AcmControl = AcmCtrl;
2342 #endif
2343                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2344                                         write_nic_byte(dev, ACM_CONTROL, 0);
2345                                 }
2346                         }
2347                 }
2348
2349
2350         }
2351 }
2352
2353 void
2354 ActSetWirelessMode8185(
2355         struct net_device *dev,
2356         u8                              btWirelessMode
2357         )
2358 {
2359         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2360         struct ieee80211_device *ieee = priv->ieee80211;
2361         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
2362         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2363
2364         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2365         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2366                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2367                         btWirelessMode, btSupportedWirelessMode);
2368                 return;
2369         }
2370
2371         // 1. Assign wireless mode to swtich if necessary.
2372         if (btWirelessMode == WIRELESS_MODE_AUTO)
2373         {
2374                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2375                 {
2376                         btWirelessMode = WIRELESS_MODE_A;
2377                 }
2378                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2379                 {
2380                         btWirelessMode = WIRELESS_MODE_G;
2381                 }
2382                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2383                 {
2384                         btWirelessMode = WIRELESS_MODE_B;
2385                 }
2386                 else
2387                 {
2388                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2389                                          btSupportedWirelessMode);
2390                         btWirelessMode = WIRELESS_MODE_B;
2391                 }
2392         }
2393
2394
2395         // 2. Swtich band: RF or BB specific actions,
2396         // for example, refresh tables in omc8255, or change initial gain if necessary.
2397         switch(priv->rf_chip)
2398         {
2399         case RF_ZEBRA2:
2400         case RF_ZEBRA4:
2401                 {
2402                         // Nothing to do for Zebra to switch band.
2403                         // Update current wireless mode if we swtich to specified band successfully.
2404                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
2405                 }
2406                 break;
2407
2408         default:
2409                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2410                 break;
2411         }
2412
2413         // 3. Change related setting.
2414         if( ieee->mode == WIRELESS_MODE_A ){
2415                 DMESG("WIRELESS_MODE_A\n");
2416         }
2417         else if( ieee->mode == WIRELESS_MODE_B ){
2418                 DMESG("WIRELESS_MODE_B\n");
2419         }
2420         else if( ieee->mode == WIRELESS_MODE_G ){
2421                 DMESG("WIRELESS_MODE_G\n");
2422         }
2423
2424         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2425 }
2426
2427 void rtl8185b_irq_enable(struct net_device *dev)
2428 {
2429         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2430
2431         priv->irq_enabled = 1;
2432         write_nic_dword(dev, IMR, priv->IntrMask);
2433 }
2434 //by amy for power save
2435 void
2436 DrvIFIndicateDisassociation(
2437         struct net_device *dev,
2438         u16                     reason
2439         )
2440 {
2441         //printk("==> DrvIFIndicateDisassociation()\n");
2442
2443         // nothing is needed after disassociation request.
2444
2445         //printk("<== DrvIFIndicateDisassociation()\n");
2446 }
2447 void
2448 MgntDisconnectIBSS(
2449         struct net_device *dev
2450 )
2451 {
2452         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2453         u8                      i;
2454
2455         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2456
2457         DrvIFIndicateDisassociation(dev, unspec_reason);
2458
2459 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2460         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
2461
2462         priv->ieee80211->state = IEEE80211_NOLINK;
2463
2464         //Stop Beacon.
2465
2466         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2467         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2468         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2469
2470         // Disable Beacon Queue Own bit, suggested by jong
2471 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2472         ieee80211_stop_send_beacons(priv->ieee80211);
2473
2474         priv->ieee80211->link_change(dev);
2475         notify_wx_assoc_event(priv->ieee80211);
2476
2477         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2478 #if 0
2479         if(pMgntInfo->bEnableSwBeaconTimer)
2480         {
2481                 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2482 // comment out by haich, 2007.10.01
2483 //#if DEV_BUS_TYPE==USB_INTERFACE
2484                 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2485 //#endif
2486         }
2487 #endif
2488
2489 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2490
2491 }
2492 void
2493 MlmeDisassociateRequest(
2494         struct net_device *dev,
2495         u8*                     asSta,
2496         u8                      asRsn
2497         )
2498 {
2499         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2500         u8 i;
2501
2502         SendDisassociation(priv->ieee80211, asSta, asRsn );
2503
2504         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2505                 //ShuChen TODO: change media status.
2506                 //ShuChen TODO: What to do when disassociate.
2507                 DrvIFIndicateDisassociation(dev, unspec_reason);
2508
2509
2510         //      pMgntInfo->AsocTimestamp = 0;
2511                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2512 //              pMgntInfo->mBrates.Length = 0;
2513 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2514
2515                 ieee80211_disassociate(priv->ieee80211);
2516
2517
2518         }
2519
2520 }
2521
2522 void
2523 MgntDisconnectAP(
2524         struct net_device *dev,
2525         u8                      asRsn
2526 )
2527 {
2528         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2529
2530 //
2531 // Commented out by rcnjko, 2005.01.27:
2532 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2533 //
2534 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2535 //      SecClearAllKeys(Adapter);
2536
2537         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2538 #ifdef TODO
2539         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2540                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2541         {
2542                 SecClearAllKeys(Adapter);
2543                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2544         }
2545 #endif
2546         // 2004.10.11, by rcnjko.
2547         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2548         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2549
2550         priv->ieee80211->state = IEEE80211_NOLINK;
2551 //      pMgntInfo->AsocTimestamp = 0;
2552 }
2553 bool
2554 MgntDisconnect(
2555         struct net_device *dev,
2556         u8                      asRsn
2557 )
2558 {
2559         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2560         //
2561         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2562         //
2563 #ifdef TODO
2564         if(pMgntInfo->mPss != eAwake)
2565         {
2566                 //
2567                 // Using AwkaeTimer to prevent mismatch ps state.
2568                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2569                 //
2570                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2571                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2572         }
2573 #endif
2574
2575         // Indication of disassociation event.
2576         //DrvIFIndicateDisassociation(Adapter, asRsn);
2577         if(IS_DOT11D_ENABLE(priv->ieee80211))
2578                 Dot11d_Reset(priv->ieee80211);
2579         // In adhoc mode, update beacon frame.
2580         if( priv->ieee80211->state == IEEE80211_LINKED )
2581         {
2582                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2583                 {
2584 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2585                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2586                         MgntDisconnectIBSS(dev);
2587                 }
2588                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2589                 {
2590                         // We clear key here instead of MgntDisconnectAP() because that
2591                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2592                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2593                         // used to handle disassociation related things to AP, e.g. send Disassoc
2594                         // frame to AP.  2005.01.27, by rcnjko.
2595 //                      SecClearAllKeys(Adapter);
2596
2597 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2598                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2599                         MgntDisconnectAP(dev, asRsn);
2600                 }
2601
2602                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2603 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2604         }
2605
2606         return true;
2607 }
2608 //
2609 //      Description:
2610 //              Chang RF Power State.
2611 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2612 //
2613 //      Assumption:
2614 //              PASSIVE LEVEL.
2615 //
2616 bool
2617 SetRFPowerState(
2618         struct net_device *dev,
2619         RT_RF_POWER_STATE       eRFPowerState
2620         )
2621 {
2622         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2623         bool                    bResult = false;
2624
2625 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2626         if(eRFPowerState == priv->eRFPowerState)
2627         {
2628 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2629                 return bResult;
2630         }
2631
2632         switch(priv->rf_chip)
2633         {
2634                 case RF_ZEBRA2:
2635                 case RF_ZEBRA4:
2636                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2637                         break;
2638
2639                 default:
2640                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2641                         break;;
2642 }
2643 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2644
2645         return bResult;
2646 }
2647 void
2648 HalEnableRx8185Dummy(
2649         struct net_device *dev
2650         )
2651 {
2652 }
2653 void
2654 HalDisableRx8185Dummy(
2655         struct net_device *dev
2656         )
2657 {
2658 }
2659
2660 bool
2661 MgntActSet_RF_State(
2662         struct net_device *dev,
2663         RT_RF_POWER_STATE       StateToSet,
2664         u32     ChangeSource
2665         )
2666 {
2667         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2668         bool                            bActionAllowed = false;
2669         bool                            bConnectBySSID = false;
2670         RT_RF_POWER_STATE       rtState;
2671         u16                             RFWaitCounter = 0;
2672         unsigned long flag;
2673 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2674         //
2675         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2676         // Only one thread can change the RF state at one time, and others should wait to be executed.
2677         //
2678 #if 1
2679         while(true)
2680         {
2681 //              down(&priv->rf_state);
2682                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2683                 if(priv->RFChangeInProgress)
2684                 {
2685 //                      printk("====================>haha111111111\n");
2686 //                      up(&priv->rf_state);
2687 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2688                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2689                         // Set RF after the previous action is done.
2690                         while(priv->RFChangeInProgress)
2691                         {
2692                                 RFWaitCounter ++;
2693 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2694                                 udelay(1000); // 1 ms
2695
2696                                 // Wait too long, return FALSE to avoid to be stuck here.
2697                                 if(RFWaitCounter > 1000) // 1sec
2698                                 {
2699 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2700                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2701                                         // TODO: Reset RF state?
2702                                         return false;
2703                                 }
2704                         }
2705                 }
2706                 else
2707                 {
2708 //                      printk("========================>haha2\n");
2709                         priv->RFChangeInProgress = true;
2710 //                      up(&priv->rf_state);
2711                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2712                         break;
2713                 }
2714         }
2715 #endif
2716         rtState = priv->eRFPowerState;
2717
2718
2719         switch(StateToSet)
2720         {
2721         case eRfOn:
2722                 //
2723                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2724                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2725                 //
2726                 priv->RfOffReason &= (~ChangeSource);
2727
2728                 if(! priv->RfOffReason)
2729                 {
2730                         priv->RfOffReason = 0;
2731                         bActionAllowed = true;
2732
2733                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2734                         {
2735                                 bConnectBySSID = true;
2736                         }
2737                 }
2738                 else
2739 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2740                         ;
2741                 break;
2742
2743         case eRfOff:
2744                  // 070125, rcnjko: we always keep connected in AP mode.
2745
2746                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2747                         {
2748                                 //
2749                                 // 060808, Annie:
2750                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2751                                 //
2752
2753                                 //
2754                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2755                                 // because we do NOT need to set ssid to dummy ones.
2756                                 // Revised by Roger, 2007.12.04.
2757                                 //
2758                                 MgntDisconnect( dev, disas_lv_ss );
2759
2760                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2761                                 // 2007.05.28, by shien chang.
2762 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2763 //                              pMgntInfo->NumBssDesc = 0;
2764 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2765 //                              pMgntInfo->NumBssDesc4Query = 0;
2766                         }
2767
2768
2769
2770                 priv->RfOffReason |= ChangeSource;
2771                 bActionAllowed = true;
2772                 break;
2773
2774         case eRfSleep:
2775                 priv->RfOffReason |= ChangeSource;
2776                 bActionAllowed = true;
2777                 break;
2778
2779         default:
2780                 break;
2781         }
2782
2783         if(bActionAllowed)
2784         {
2785 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2786                 // Config HW to the specified mode.
2787 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2788                 SetRFPowerState(dev, StateToSet);
2789
2790                 // Turn on RF.
2791                 if(StateToSet == eRfOn)
2792                 {
2793                         HalEnableRx8185Dummy(dev);
2794                         if(bConnectBySSID)
2795                         {
2796                         // by amy not supported
2797 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2798                         }
2799                 }
2800                 // Turn off RF.
2801                 else if(StateToSet == eRfOff)
2802                 {
2803                         HalDisableRx8185Dummy(dev);
2804                 }
2805         }
2806         else
2807         {
2808         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2809         }
2810
2811         // Release RF spinlock
2812 //      down(&priv->rf_state);
2813         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2814         priv->RFChangeInProgress = false;
2815 //      up(&priv->rf_state);
2816         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2817 //      printk("<===MgntActSet_RF_State()\n");
2818         return bActionAllowed;
2819 }
2820 void
2821 InactivePowerSave(
2822         struct net_device *dev
2823         )
2824 {
2825         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2826         //u8 index = 0;
2827
2828         //
2829         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2830         // is really scheduled.
2831         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2832         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2833         // blocks the IPS procedure of switching RF.
2834         // By Bruce, 2007-12-25.
2835         //
2836         priv->bSwRfProcessing = true;
2837
2838         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2839
2840         //
2841         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2842         //
2843 #if 0
2844         while( index < 4 )
2845         {
2846                 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2847                         (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2848                 {
2849                         if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2850                         pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2851
2852                 }
2853                 index++;
2854         }
2855 #endif
2856         priv->bSwRfProcessing = false;
2857 }
2858
2859 //
2860 //      Description:
2861 //              Enter the inactive power save mode. RF will be off
2862 //      2007.08.17, by shien chang.
2863 //
2864 void
2865 IPSEnter(
2866         struct net_device *dev
2867         )
2868 {
2869         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2870         RT_RF_POWER_STATE rtState;
2871         //printk("==============================>enter IPS\n");
2872         if (priv->bInactivePs)
2873         {
2874                 rtState = priv->eRFPowerState;
2875
2876                 //
2877                 // Added by Bruce, 2007-12-25.
2878                 // Do not enter IPS in the following conditions:
2879                 // (1) RF is already OFF or Sleep
2880                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2881                 // (3) Connectted (only disconnected can trigger IPS)
2882                 // (4) IBSS (send Beacon)
2883                 // (5) AP mode (send Beacon)
2884                 //
2885                 if (rtState == eRfOn && !priv->bSwRfProcessing
2886                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2887                 {
2888         //              printk("IPSEnter(): Turn off RF.\n");
2889                         priv->eInactivePowerState = eRfOff;
2890                         InactivePowerSave(dev);
2891                 }
2892         }
2893 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2894 }
2895 void
2896 IPSLeave(
2897         struct net_device *dev
2898         )
2899 {
2900         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2901         RT_RF_POWER_STATE rtState;
2902         //printk("===================================>leave IPS\n");
2903         if (priv->bInactivePs)
2904         {
2905                 rtState = priv->eRFPowerState;
2906                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2907                 {
2908 //                      printk("IPSLeave(): Turn on RF.\n");
2909                         priv->eInactivePowerState = eRfOn;
2910                         InactivePowerSave(dev);
2911                 }
2912         }
2913 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2914 }
2915 //by amy for power save
2916 void rtl8185b_adapter_start(struct net_device *dev)
2917 {
2918       struct r8180_priv *priv = ieee80211_priv(dev);
2919         struct ieee80211_device *ieee = priv->ieee80211;
2920
2921         u8 SupportedWirelessMode;
2922         u8                      InitWirelessMode;
2923         u8                      bInvalidWirelessMode = 0;
2924         //int i;
2925         u8 tmpu8;
2926         //u8 u1tmp,u2tmp;
2927         u8 btCR9346;
2928         u8 TmpU1b;
2929         u8 btPSR;
2930
2931         //rtl8180_rtx_disable(dev);
2932 //{by amy 080312
2933         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2934 //by amy 080312}
2935         rtl8180_reset(dev);
2936
2937         priv->dma_poll_mask = 0;
2938         priv->dma_poll_stop_mask = 0;
2939
2940         //rtl8180_beacon_tx_disable(dev);
2941
2942         HwConfigureRTL8185(dev);
2943
2944         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2945         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2946
2947         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2948
2949         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2950
2951         write_nic_word(dev, BcnItv, 100);
2952         write_nic_word(dev, AtimWnd, 2);
2953
2954         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2955         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2956
2957         write_nic_byte(dev, WPA_CONFIG, 0);
2958
2959         MacConfig_85BASIC(dev);
2960
2961         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2962         // BT_DEMO_BOARD type
2963         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2964 //by amy
2965 //#ifdef CONFIG_RTL818X_S
2966                 // for jong required
2967 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2968 //#endif
2969 //by amy
2970         //BT_QA_BOARD
2971         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2972
2973         //-----------------------------------------------------------------------------
2974         // Set up PHY related.
2975         //-----------------------------------------------------------------------------
2976         // Enable Config3.PARAM_En to revise AnaaParm.
2977         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2978 //by amy
2979         tmpu8 = read_nic_byte(dev, CONFIG3);
2980 #ifdef CONFIG_RTL818X_S
2981         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2982 #else
2983         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En | CONFIG3_CLKRUN_En) );
2984 #endif
2985 //by amy
2986         // Turn on Analog power.
2987         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2988         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2989         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2990 //by amy
2991 #ifdef CONFIG_RTL818X_S
2992         write_nic_word(dev, ANAPARAM3, 0x0010);
2993 #else
2994       write_nic_byte(dev, ANAPARAM3, 0x00);
2995 #endif
2996 //by amy
2997
2998         write_nic_byte(dev, CONFIG3, tmpu8);
2999         write_nic_byte(dev, CR9346, 0x00);
3000 //{by amy 080312 for led
3001         // enable EEM0 and EEM1 in 9346CR
3002         btCR9346 = read_nic_byte(dev, CR9346);
3003         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
3004
3005         // B cut use LED1 to control HW RF on/off
3006         TmpU1b = read_nic_byte(dev, CONFIG5);
3007         TmpU1b = TmpU1b & ~BIT3;
3008         write_nic_byte(dev,CONFIG5, TmpU1b);
3009
3010         // disable EEM0 and EEM1 in 9346CR
3011         btCR9346 &= ~(0xC0);
3012         write_nic_byte(dev, CR9346, btCR9346);
3013
3014         //Enable Led (suggested by Jong)
3015         // B-cut RF Radio on/off  5e[3]=0
3016         btPSR = read_nic_byte(dev, PSR);
3017         write_nic_byte(dev, PSR, (btPSR | BIT3));
3018 //by amy 080312 for led}
3019         // setup initial timing for RFE.
3020         write_nic_word(dev, RFPinsOutput, 0x0480);
3021         SetOutputEnableOfRfPins(dev);
3022         write_nic_word(dev, RFPinsSelect, 0x2488);
3023
3024         // PHY config.
3025         PhyConfig8185(dev);
3026
3027         // We assume RegWirelessMode has already been initialized before,
3028         // however, we has to validate the wireless mode here and provide a reasonble
3029         // initialized value if necessary. 2005.01.13, by rcnjko.
3030         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
3031         if(     (ieee->mode != WIRELESS_MODE_B) &&
3032                 (ieee->mode != WIRELESS_MODE_G) &&
3033                 (ieee->mode != WIRELESS_MODE_A) &&
3034                 (ieee->mode != WIRELESS_MODE_AUTO))
3035         { // It should be one of B, G, A, or AUTO.
3036                 bInvalidWirelessMode = 1;
3037         }
3038         else
3039         { // One of B, G, A, or AUTO.
3040                 // Check if the wireless mode is supported by RF.
3041                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
3042                         (ieee->mode & SupportedWirelessMode) == 0 )
3043                 {
3044                         bInvalidWirelessMode = 1;
3045                 }
3046         }
3047
3048         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
3049         { // Auto or other invalid value.
3050                 // Assigne a wireless mode to initialize.
3051                 if((SupportedWirelessMode & WIRELESS_MODE_A))
3052                 {
3053                         InitWirelessMode = WIRELESS_MODE_A;
3054                 }
3055                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
3056                 {
3057                         InitWirelessMode = WIRELESS_MODE_G;
3058                 }
3059                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
3060                 {
3061                         InitWirelessMode = WIRELESS_MODE_B;
3062                 }
3063                 else
3064                 {
3065                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
3066                                  SupportedWirelessMode);
3067                         InitWirelessMode = WIRELESS_MODE_B;
3068                 }
3069
3070                 // Initialize RegWirelessMode if it is not a valid one.
3071                 if(bInvalidWirelessMode)
3072                 {
3073                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
3074                 }
3075         }
3076         else
3077         { // One of B, G, A.
3078                 InitWirelessMode = ieee->mode;
3079         }
3080 //by amy for power save
3081 #ifdef ENABLE_IPS
3082 //      printk("initialize ENABLE_IPS\n");
3083         priv->eRFPowerState = eRfOff;
3084         priv->RfOffReason = 0;
3085         {
3086         //      u32 tmp2;
3087         //      u32 tmp = jiffies;
3088                 MgntActSet_RF_State(dev, eRfOn, 0);
3089         //      tmp2 = jiffies;
3090         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3091         }
3092 //      DrvIFIndicateCurrentPhyStatus(priv);
3093                 //
3094                 // If inactive power mode is enabled, disable rf while in disconnected state.
3095                 // 2007.07.16, by shien chang.
3096                 //
3097         if (priv->bInactivePs)
3098         {
3099         //      u32 tmp2;
3100         //      u32 tmp = jiffies;
3101                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
3102         //      tmp2 = jiffies;
3103         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3104
3105         }
3106 #endif
3107 //      IPSEnter(dev);
3108 //by amy for power save
3109 #ifdef TODO
3110         // Turn off RF if necessary. 2005.08.23, by rcnjko.
3111         // We shall turn off RF after setting CMDR, otherwise,
3112         // RF will be turnned on after we enable MAC Tx/Rx.
3113         if(Adapter->MgntInfo.RegRfOff == TRUE)
3114         {
3115                 SetRFPowerState8185(Adapter, RF_OFF);
3116         }
3117         else
3118         {
3119                 SetRFPowerState8185(Adapter, RF_ON);
3120         }
3121 #endif
3122
3123 /*   //these is equal with above TODO.
3124         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
3125         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
3126         RF_WriteReg(dev, 0x4, 0x9FF);
3127         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
3128         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
3129         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
3130         write_nic_byte(dev, CR9346, 0x00);
3131 */
3132
3133         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
3134
3135         //-----------------------------------------------------------------------------
3136
3137         rtl8185b_irq_enable(dev);
3138
3139         netif_start_queue(dev);
3140
3141  }
3142
3143
3144 void rtl8185b_rx_enable(struct net_device *dev)
3145 {
3146         u8 cmd;
3147         //u32 rxconf;
3148         /* for now we accept data, management & ctl frame*/
3149         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3150 #if 0
3151         rxconf=read_nic_dword(dev,RX_CONF);
3152         rxconf = rxconf &~ MAC_FILTER_MASK;
3153         rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
3154         rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
3155         rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
3156         rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
3157 //      rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3158         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3159
3160         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3161            dev->flags & IFF_PROMISC){
3162                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3163         }else{
3164                 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
3165                 if(priv->card_8185 == 0)
3166                         rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3167         }
3168
3169         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3170                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3171                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3172         }*/
3173
3174         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3175                 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
3176                 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
3177                 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
3178         }
3179
3180         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3181                 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3182
3183         //if(!priv->card_8185){
3184                 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
3185                 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
3186         //}
3187
3188         rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
3189         rxconf = rxconf &~ MAX_RX_DMA_MASK;
3190         rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
3191
3192         //if(!priv->card_8185)
3193                 rxconf = rxconf | RCR_ONLYERLPKT;
3194
3195         rxconf = rxconf &~ RCR_CS_MASK;
3196         if(!priv->card_8185)
3197                 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3198 //      rxconf &=~ 0xfff00000;
3199 //      rxconf |= 0x90100000;//9014f76f;
3200         write_nic_dword(dev, RX_CONF, rxconf);
3201 #endif
3202
3203         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3204
3205         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3206            dev->flags & IFF_PROMISC){
3207                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3208                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3209         }
3210
3211         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3212                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3213                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3214         }*/
3215
3216         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3217                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3218         }
3219
3220         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3221                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3222
3223         write_nic_dword(dev, RCR, priv->ReceiveConfig);
3224
3225         fix_rx_fifo(dev);
3226
3227 #ifdef DEBUG_RX
3228         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3229 #endif
3230         cmd=read_nic_byte(dev,CMD);
3231         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3232
3233 }
3234
3235 void rtl8185b_tx_enable(struct net_device *dev)
3236 {
3237         u8 cmd;
3238         //u8 tx_agc_ctl;
3239         u8 byte;
3240         //u32 txconf;
3241         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3242
3243 #if 0
3244         txconf= read_nic_dword(dev,TX_CONF);
3245         if(priv->card_8185){
3246
3247
3248                 byte = read_nic_byte(dev,CW_CONF);
3249                 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3250                 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3251                 write_nic_byte(dev, CW_CONF, byte);
3252
3253                 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3254                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3255                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3256                 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3257                 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3258                 /*
3259                 write_nic_word(dev, 0x5e, 0x01);
3260                 force_pci_posting(dev);
3261                 mdelay(1);
3262                 write_nic_word(dev, 0xfe, 0x10);
3263                 force_pci_posting(dev);
3264                 mdelay(1);
3265                 write_nic_word(dev, 0x5e, 0x00);
3266                 force_pci_posting(dev);
3267                 mdelay(1);
3268                 */
3269                 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3270         }
3271
3272         if(priv->card_8185){
3273
3274                 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3275
3276         }else{
3277
3278                 if(hwseqnum)
3279                         txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3280                 else
3281                         txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3282         }
3283
3284         txconf = txconf &~ TX_LOOPBACK_MASK;
3285         txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3286         txconf = txconf &~ TCR_DPRETRY_MASK;
3287         txconf = txconf &~ TCR_RTSRETRY_MASK;
3288         txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3289         txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3290         txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3291
3292         if(priv->card_8185){
3293                 if(priv->hw_plcp_len)
3294                         txconf = txconf &~ TCR_PLCP_LEN;
3295                 else
3296                         txconf = txconf | TCR_PLCP_LEN;
3297         }else{
3298                 txconf = txconf &~ TCR_SAT;
3299         }
3300         txconf = txconf &~ TCR_MXDMA_MASK;
3301         txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3302         txconf = txconf | TCR_CWMIN;
3303         txconf = txconf | TCR_DISCW;
3304
3305 //      if(priv->ieee80211->hw_wep)
3306 //              txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3307 //      else
3308                 txconf=txconf | (1<<TX_NOICV_SHIFT);
3309
3310         write_nic_dword(dev,TX_CONF,txconf);
3311 #endif
3312
3313         write_nic_dword(dev, TCR, priv->TransmitConfig);
3314         byte = read_nic_byte(dev, MSR);
3315         byte |= MSR_LINK_ENEDCA;
3316         write_nic_byte(dev, MSR, byte);
3317
3318         fix_tx_fifo(dev);
3319
3320 #ifdef DEBUG_TX
3321         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3322 #endif
3323
3324         cmd=read_nic_byte(dev,CMD);
3325         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3326
3327         //write_nic_dword(dev,TX_CONF,txconf);
3328
3329
3330 /*
3331         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3332         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3333         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3334         */
3335 }
3336
3337
3338 #endif