SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_sa2400.h"  /* PHILIPS Radio frontend */
  26 #include "r8180_max2820.h" /* MAXIM Radio frontend */
  27 #include "r8180_gct.h"     /* GCT Radio frontend */
  28 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  29 #include "r8180_rtl8255.h" /* RTL8255 Radio frontend */
  30 #include "r8180_93cx6.h"   /* Card EEPROM */
  31 #include "r8180_wx.h"
  32
  33 #include "r8180_pm.h"
  34
  35 #include "ieee80211/dot11d.h"
  36
  37 #ifdef CONFIG_RTL8185B
  38
  39 //#define CONFIG_RTL8180_IO_MAP
  40
  41 #define TC_3W_POLL_MAX_TRY_CNT 5
  42 #ifdef CONFIG_RTL818X_S
  43 static u8 MAC_REG_TABLE[][2]={
  44                         //PAGA 0:
  45                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  46                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  47                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  48                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  49                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  50                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  51                         {0x94, 0x0F}, {0x95, 0x32},
  52                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  53                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  54                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  55                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  56                         {0xff, 0x00},
  57
  58                         //PAGE 1:
  59                         // For Flextronics system Logo PCIHCT failure:
  60                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  61                         {0x5e, 0x01},
  62                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  63                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  64                         {0x82, 0xFF}, {0x83, 0x03},
  65                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  66                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  67                         {0xe2, 0x00},
  68
  69
  70                         //PAGE 2:
  71                         {0x5e, 0x02},
  72                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  73                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  74                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  75                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  76                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  77                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  78                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  79
  80                         //PAGA 0:
  81                         {0x5e, 0x00},{0x9f, 0x03}
  82                 };
  83
  84
  85 static u8  ZEBRA_AGC[]={
  86                         0,
  87                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  88                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  89                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  90                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  91                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  92                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  93                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  94                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  95                         };
  96
  97 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  98                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  99                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
 100                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
 101                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
 102                         0x0183,0x0163,0x0143,0x0123,0x0103
 103         };
 104
 105 static u8 OFDM_CONFIG[]={
 106                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
 107                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 108                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 109
 110                         // 0x00
 111                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 112                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 113                         // 0x10
 114                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 115                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 116                         // 0x20
 117                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 118                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 119                         // 0x30
 120                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 121                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 122                 };
 123 #else
 124  static u8 MAC_REG_TABLE[][2]={
 125                         //PAGA 0:
 126                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
 127                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
 128                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
 129                         {0xff, 0x00},
 130
 131                         //PAGE 1:
 132                         {0x5e, 0x01},
 133                         {0x58, 0x4b}, {0x59, 0x00}, {0x5a, 0x4b}, {0x5b, 0x00}, {0x60, 0x4b},
 134                         {0x61, 0x09}, {0x62, 0x4b}, {0x63, 0x09}, {0xce, 0x0f}, {0xcf, 0x00},
 135                         {0xe0, 0xff}, {0xe1, 0x0f}, {0xe2, 0x00}, {0xf0, 0x4e}, {0xf1, 0x01},
 136                         {0xf2, 0x02}, {0xf3, 0x03}, {0xf4, 0x04}, {0xf5, 0x05}, {0xf6, 0x06},
 137                         {0xf7, 0x07}, {0xf8, 0x08},
 138
 139
 140                         //PAGE 2:
 141                         {0x5e, 0x02},
 142                         {0x0c, 0x04}, {0x21, 0x61}, {0x22, 0x68}, {0x23, 0x6f}, {0x24, 0x76},
 143                         {0x25, 0x7d}, {0x26, 0x84}, {0x27, 0x8d}, {0x4d, 0x08}, {0x4e, 0x00},
 144                         {0x50, 0x05}, {0x51, 0xf5}, {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0x1f},
 145                         {0x55, 0x23}, {0x56, 0x45}, {0x57, 0x67}, {0x58, 0x08}, {0x59, 0x08},
 146                         {0x5a, 0x08}, {0x5b, 0x08}, {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08},
 147                         {0x63, 0x08}, {0x64, 0xcf}, {0x72, 0x56}, {0x73, 0x9a},
 148
 149                         //PAGA 0:
 150                         {0x5e, 0x00},
 151                         {0x34, 0xff}, {0x35, 0x0f}, {0x5b, 0x40}, {0x84, 0x88}, {0x85, 0x24},
 152                         {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x07}, {0x8d, 0x00}, {0x94, 0x1b},
 153                         {0x95, 0x12}, {0x96, 0x00}, {0x97, 0x06}, {0x9d, 0x1a}, {0x9f, 0x10},
 154                         {0xb4, 0x22}, {0xbe, 0x80}, {0xdb, 0x00}, {0xee, 0x00}, {0x5b, 0x42},
 155                         {0x91, 0x03},
 156
 157                         //PAGE 2:
 158                         {0x5e, 0x02},
 159                         {0x4c, 0x03},
 160
 161                         //PAGE 0:
 162                         {0x5e, 0x00},
 163
 164                         //PAGE 3:
 165                         {0x5e, 0x03},
 166                         {0x9f, 0x00},
 167
 168                         //PAGE 0:
 169                         {0x5e, 0x00},
 170                         {0x8c, 0x01}, {0x8d, 0x10},{0x8e, 0x08}, {0x8f, 0x00}
 171                 };
 172
 173
 174 static u8  ZEBRA_AGC[]={
 175         0,
 176         0x5e,0x5e,0x5e,0x5e,0x5d,0x5b,0x59,0x57,0x55,0x53,0x51,0x4f,0x4d,0x4b,0x49,0x47,
 177         0x45,0x43,0x41,0x3f,0x3d,0x3b,0x39,0x37,0x35,0x33,0x31,0x2f,0x2d,0x2b,0x29,0x27,
 178         0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x11,0x0f,0x0d,0x0b,0x09,0x07,
 179         0x05,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
 180         0x19,0x19,0x19,0x019,0x19,0x19,0x19,0x19,0x19,0x19,0x1e,0x1f,0x20,0x21,0x21,0x22,
 181         0x23,0x24,0x24,0x25,0x25,0x26,0x26,0x27,0x27,0x28,0x28,0x28,0x29,0x2a,0x2a,0x2b,
 182         0x2b,0x2b,0x2c,0x2c,0x2c,0x2d,0x2d,0x2d,0x2e,0x2e,0x2f,0x30,0x31,0x31,0x31,0x31,
 183         0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31
 184         };
 185
 186 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
 187         0,
 188         0x0400,0x0401,0x0402,0x0403,0x0404,0x0405,0x0408,0x0409,
 189         0x040a,0x040b,0x0502,0x0503,0x0504,0x0505,0x0540,0x0541,
 190         0x0542,0x0543,0x0544,0x0545,0x0580,0x0581,0x0582,0x0583,
 191         0x0584,0x0585,0x0588,0x0589,0x058a,0x058b,0x0643,0x0644,
 192         0x0645,0x0680,0x0681,0x0682,0x0683,0x0684,0x0685,0x0688,
 193         0x0689,0x068a,0x068b,0x068c,0x0742,0x0743,0x0744,0x0745,
 194         0x0780,0x0781,0x0782,0x0783,0x0784,0x0785,0x0788,0x0789,
 195         0x078a,0x078b,0x078c,0x078d,0x0790,0x0791,0x0792,0x0793,
 196         0x0794,0x0795,0x0798,0x0799,0x079a,0x079b,0x079c,0x079d,
 197         0x07a0,0x07a1,0x07a2,0x07a3,0x07a4,0x07a5,0x07a8,0x07a9,
 198         0x03aa,0x03ab,0x03ac,0x03ad,0x03b0,0x03b1,0x03b2,0x03b3,
 199         0x03b4,0x03b5,0x03b8,0x03b9,0x03ba,0x03bb,0x03bb
 200 };
 201
 202 // 2006.07.13, SD3 szuyitasi:
 203 //      OFDM.0x03=0x0C (original is 0x0F)
 204 // Use the new SD3 given param, by shien chang, 2006.07.14
 205 static u8 OFDM_CONFIG[]={
 206         0x10, 0x0d, 0x01, 0x0C, 0x14, 0xfb, 0x0f, 0x60, 0x00, 0x60,
 207         0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00,
 208         0x00, 0x00, 0xa8, 0x46, 0xb2, 0x33, 0x07, 0xa5, 0x6f, 0x55,
 209         0xc8, 0xb3, 0x0a, 0xe1, 0x1c, 0x8a, 0xb6, 0x83, 0x34, 0x0f,
 210         0x4f, 0x23, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 0xc0, 0xc1,
 211         0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 0x6d, 0x3c, 0xff, 0x07
 212 };
 213 #endif
 214
 215 /*---------------------------------------------------------------
 216   * Hardware IO
 217   * the code is ported from Windows source code
 218   ----------------------------------------------------------------*/
 219
 220 void
 221 PlatformIOWrite1Byte(
 222         struct net_device *dev,
 223         u32             offset,
 224         u8              data
 225         )
 226 {
 227 #ifndef CONFIG_RTL8180_IO_MAP
 228         write_nic_byte(dev, offset, data);
 229         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 230
 231 #else // Port IO
 232         u32 Page = (offset >> 8);
 233
 234         switch(Page)
 235         {
 236         case 0: // Page 0
 237                 write_nic_byte(dev, offset, data);
 238                 break;
 239
 240         case 1: // Page 1
 241         case 2: // Page 2
 242         case 3: // Page 3
 243                 {
 244                         u8 psr = read_nic_byte(dev, PSR);
 245
 246                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 247                         write_nic_byte(dev, (offset & 0xff), data);
 248                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 249                 }
 250                 break;
 251
 252         default:
 253                 // Illegal page number.
 254                 DMESGE("PlatformIOWrite1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 255                 break;
 256         }
 257 #endif
 258 }
 259
 260 void
 261 PlatformIOWrite2Byte(
 262         struct net_device *dev,
 263         u32             offset,
 264         u16             data
 265         )
 266 {
 267 #ifndef CONFIG_RTL8180_IO_MAP
 268         write_nic_word(dev, offset, data);
 269         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 270
 271
 272 #else // Port IO
 273         u32 Page = (offset >> 8);
 274
 275         switch(Page)
 276         {
 277         case 0: // Page 0
 278                 write_nic_word(dev, offset, data);
 279                 break;
 280
 281         case 1: // Page 1
 282         case 2: // Page 2
 283         case 3: // Page 3
 284                 {
 285                         u8 psr = read_nic_byte(dev, PSR);
 286
 287                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 288                         write_nic_word(dev, (offset & 0xff), data);
 289                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 290                 }
 291                 break;
 292
 293         default:
 294                 // Illegal page number.
 295                 DMESGE("PlatformIOWrite2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 296                 break;
 297         }
 298 #endif
 299 }
 300 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 301
 302 void
 303 PlatformIOWrite4Byte(
 304         struct net_device *dev,
 305         u32             offset,
 306         u32             data
 307         )
 308 {
 309 #ifndef CONFIG_RTL8180_IO_MAP
 310 //{by amy 080312
 311 if (offset == PhyAddr)
 312         {//For Base Band configuration.
 313                 unsigned char   cmdByte;
 314                 unsigned long   dataBytes;
 315                 unsigned char   idx;
 316                 u8      u1bTmp;
 317
 318                 cmdByte = (u8)(data & 0x000000ff);
 319                 dataBytes = data>>8;
 320
 321                 //
 322                 // 071010, rcnjko:
 323                 // The critical section is only BB read/write race condition.
 324                 // Assumption:
 325                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 326                 // acquiring the spinlock in such context.
 327                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 328                 //
 329 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 330
 331                 for(idx = 0; idx < 30; idx++)
 332                 { // Make sure command bit is clear before access it.
 333                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 334                         if((u1bTmp & BIT7) == 0)
 335                                 break;
 336                         else
 337                                 mdelay(10);
 338                 }
 339
 340                 for(idx=0; idx < 3; idx++)
 341                 {
 342                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 343                 }
 344                 write_nic_byte(dev, offset, cmdByte);
 345
 346 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 347         }
 348 //by amy 080312}
 349         else{
 350                 write_nic_dword(dev, offset, data);
 351                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 352         }
 353 #else // Port IO
 354         u32 Page = (offset >> 8);
 355
 356         switch(Page)
 357         {
 358         case 0: // Page 0
 359                 write_nic_word(dev, offset, data);
 360                 break;
 361
 362         case 1: // Page 1
 363         case 2: // Page 2
 364         case 3: // Page 3
 365                 {
 366                         u8 psr = read_nic_byte(dev, PSR);
 367
 368                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 369                         write_nic_dword(dev, (offset & 0xff), data);
 370                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 371                 }
 372                 break;
 373
 374         default:
 375                 // Illegal page number.
 376                 DMESGE("PlatformIOWrite4Byte(): illegal page number: %d, offset: %#X", Page, offset);
 377                 break;
 378         }
 379 #endif
 380 }
 381
 382 u8
 383 PlatformIORead1Byte(
 384         struct net_device *dev,
 385         u32             offset
 386         )
 387 {
 388         u8      data = 0;
 389
 390 #ifndef CONFIG_RTL8180_IO_MAP
 391         data = read_nic_byte(dev, offset);
 392
 393 #else // Port IO
 394         u32 Page = (offset >> 8);
 395
 396         switch(Page)
 397         {
 398         case 0: // Page 0
 399                 data = read_nic_byte(dev, offset);
 400                 break;
 401
 402         case 1: // Page 1
 403         case 2: // Page 2
 404         case 3: // Page 3
 405                 {
 406                         u8 psr = read_nic_byte(dev, PSR);
 407
 408                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 409                         data = read_nic_byte(dev, (offset & 0xff));
 410                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 411                 }
 412                 break;
 413
 414         default:
 415                 // Illegal page number.
 416                 DMESGE("PlatformIORead1Byte(): illegal page number: %d, offset: %#X", Page, offset);
 417                 break;
 418         }
 419 #endif
 420
 421         return data;
 422 }
 423
 424 u16
 425 PlatformIORead2Byte(
 426         struct net_device *dev,
 427         u32             offset
 428         )
 429 {
 430         u16     data = 0;
 431
 432 #ifndef CONFIG_RTL8180_IO_MAP
 433         data = read_nic_word(dev, offset);
 434
 435 #else // Port IO
 436         u32 Page = (offset >> 8);
 437
 438         switch(Page)
 439         {
 440         case 0: // Page 0
 441                 data = read_nic_word(dev, offset);
 442                 break;
 443
 444         case 1: // Page 1
 445         case 2: // Page 2
 446         case 3: // Page 3
 447                 {
 448                         u8 psr = read_nic_byte(dev, PSR);
 449
 450                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 451                         data = read_nic_word(dev, (offset & 0xff));
 452                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 453                 }
 454                 break;
 455
 456         default:
 457                 // Illegal page number.
 458                 DMESGE("PlatformIORead2Byte(): illegal page number: %d, offset: %#X", Page, offset);
 459                 break;
 460         }
 461 #endif
 462
 463         return data;
 464 }
 465
 466 u32
 467 PlatformIORead4Byte(
 468         struct net_device *dev,
 469         u32             offset
 470         )
 471 {
 472         u32     data = 0;
 473
 474 #ifndef CONFIG_RTL8180_IO_MAP
 475         data = read_nic_dword(dev, offset);
 476
 477 #else // Port IO
 478         u32 Page = (offset >> 8);
 479
 480         switch(Page)
 481         {
 482         case 0: // Page 0
 483                 data = read_nic_dword(dev, offset);
 484                 break;
 485
 486         case 1: // Page 1
 487         case 2: // Page 2
 488         case 3: // Page 3
 489                 {
 490                         u8 psr = read_nic_byte(dev, PSR);
 491
 492                         write_nic_byte(dev, PSR, ((psr & 0xfc) | (u8)Page)); // Switch to page N.
 493                         data = read_nic_dword(dev, (offset & 0xff));
 494                         write_nic_byte(dev, PSR, (psr & 0xfc)); // Switch to page 0.
 495                 }
 496                 break;
 497
 498         default:
 499                 // Illegal page number.
 500                 DMESGE("PlatformIORead4Byte(): illegal page number: %d, offset: %#X\n", Page, offset);
 501                 break;
 502         }
 503 #endif
 504
 505         return data;
 506 }
 507
 508 void
 509 SetOutputEnableOfRfPins(
 510         struct net_device *dev
 511         )
 512 {
 513         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 514
 515         switch(priv->rf_chip)
 516         {
 517         case RFCHIPID_RTL8225:
 518         case RF_ZEBRA2:
 519         case RF_ZEBRA4:
 520                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 521                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 522                 break;
 523         }
 524 }
 525
 526 void
 527 ZEBRA_RFSerialWrite(
 528         struct net_device *dev,
 529         u32                     data2Write,
 530         u8                      totalLength,
 531         u8                      low2high
 532         )
 533 {
 534         ThreeWireReg            twreg;
 535         int                             i;
 536         u16                             oval,oval2,oval3;
 537         u32                             mask;
 538         u16                             UshortBuffer;
 539
 540         u8                      u1bTmp;
 541 #ifdef CONFIG_RTL818X_S
 542         // RTL8187S HSSI Read/Write Function
 543         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 544         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 545         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 546 #endif
 547         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 548         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 549
 550         oval2 = read_nic_word(dev, RFPinsEnable);
 551         oval3 = read_nic_word(dev, RFPinsSelect);
 552
 553         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 554         oval3 &= 0xfff8;
 555
 556         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 557         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 558         udelay(10);
 559
 560         // Add this to avoid hardware and software 3-wire conflict.
 561         // 2005.03.01, by rcnjko.
 562         twreg.longData = 0;
 563         twreg.struc.enableB = 1;
 564         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 565         udelay(2);
 566         twreg.struc.enableB = 0;
 567         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 568         udelay(10);
 569
 570         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 571
 572         for(i=0; i<totalLength/2; i++)
 573         {
 574                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 575                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 576                 twreg.struc.clk = 1;
 577                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 578                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 579
 580                 mask = (low2high)?(mask<<1):(mask>>1);
 581                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 582                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 583                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 584                 twreg.struc.clk = 0;
 585                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 586                 mask = (low2high)?(mask<<1):(mask>>1);
 587         }
 588
 589         twreg.struc.enableB = 1;
 590         twreg.struc.clk = 0;
 591         twreg.struc.data = 0;
 592         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 593         udelay(10);
 594
 595         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 596         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 597
 598         SetOutputEnableOfRfPins(dev);
 599 }
 600 //by amy
 601
 602
 603 int
 604 HwHSSIThreeWire(
 605         struct net_device *dev,
 606         u8                      *pDataBuf,
 607         u8                      nDataBufBitCnt,
 608         int                     bSI,
 609         int                     bWrite
 610         )
 611 {
 612         int     bResult = 1;
 613         u8      TryCnt;
 614         u8      u1bTmp;
 615
 616         do
 617         {
 618                 // Check if WE and RE are cleared.
 619                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 620                 {
 621                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 622                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 623                         {
 624                                 break;
 625                         }
 626                         udelay(10);
 627                 }
 628                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 629                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 630
 631                 // RTL8187S HSSI Read/Write Function
 632                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 633
 634                 if(bSI)
 635                 {
 636                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 637                 }else
 638                 {
 639                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 640                 }
 641
 642                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 643
 644                 if(bSI)
 645                 {
 646                         // jong: HW SI read must set reg84[3]=0.
 647                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 648                         u1bTmp &= ~BIT3;
 649                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 650                 }
 651                 // Fill up data buffer for write operation.
 652
 653                 if(bWrite)
 654                 {
 655                         if(nDataBufBitCnt == 16)
 656                         {
 657                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 658                         }
 659                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 660                         {
 661                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 662                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 663                         }
 664                         else
 665                         {
 666                                 int idx;
 667                                 int ByteCnt = nDataBufBitCnt / 8;
 668                                 //printk("%d\n",nDataBufBitCnt);
 669                                 if ((nDataBufBitCnt % 8) != 0)
 670                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 671                                 nDataBufBitCnt);
 672
 673                                if (nDataBufBitCnt > 64)
 674                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 675                                 nDataBufBitCnt);
 676
 677                                 for(idx = 0; idx < ByteCnt; idx++)
 678                                 {
 679                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 680                                 }
 681                         }
 682                 }
 683                 else            //read
 684                 {
 685                         if(bSI)
 686                         {
 687                                 // SI - reg274[3:0] : RF register's Address
 688                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 689                         }
 690                         else
 691                         {
 692                                 // PI - reg274[15:12] : RF register's Address
 693                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 694                         }
 695                 }
 696
 697                 // Set up command: WE or RE.
 698                 if(bWrite)
 699                 {
 700                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 701                 }
 702                 else
 703                 {
 704                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 705                 }
 706
 707                 // Check if DONE is set.
 708                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 709                 {
 710                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 711                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 712                         {
 713                                 break;
 714                         }
 715                         udelay(10);
 716                 }
 717
 718                 write_nic_byte(dev, SW_3W_CMD1, 0);
 719
 720                 // Read back data for read operation.
 721                 if(bWrite == 0)
 722                 {
 723                         if(bSI)
 724                         {
 725                                 //Serial Interface : reg363_362[11:0]
 726                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 727                         }
 728                         else
 729                         {
 730                                 //Parallel Interface : reg361_360[11:0]
 731                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 732                         }
 733
 734                         *((u16*)pDataBuf) &= 0x0FFF;
 735                 }
 736
 737         }while(0);
 738
 739         return bResult;
 740 }
 741 //by amy
 742
 743 int
 744 HwThreeWire(
 745         struct net_device *dev,
 746         u8                      *pDataBuf,
 747         u8                      nDataBufBitCnt,
 748         int                     bHold,
 749         int                     bWrite
 750         )
 751 {
 752         int     bResult = 1;
 753         u8      TryCnt;
 754         u8      u1bTmp;
 755
 756         do
 757         {
 758                 // Check if WE and RE are cleared.
 759                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 760                 {
 761                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 762                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 763                         {
 764                                 break;
 765                         }
 766                         udelay(10);
 767                 }
 768                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 769                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 770
 771                 // Fill up data buffer for write operation.
 772                 if(nDataBufBitCnt == 16)
 773                 {
 774                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 775                 }
 776                 else if(nDataBufBitCnt == 64)
 777                 {
 778                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 779                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 780                 }
 781                 else
 782                 {
 783                         int idx;
 784                         int ByteCnt = nDataBufBitCnt / 8;
 785
 786                         if ((nDataBufBitCnt % 8) != 0)
 787                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 788                                 nDataBufBitCnt);
 789
 790                         if (nDataBufBitCnt > 64)
 791                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 792                                 nDataBufBitCnt);
 793
 794                         for(idx = 0; idx < ByteCnt; idx++)
 795                         {
 796                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 797                         }
 798                 }
 799
 800                 // Fill up length field.
 801                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 802                 if(bHold)
 803                         u1bTmp |= SW_3W_CMD0_HOLD;
 804                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 805
 806                 // Set up command: WE or RE.
 807                 if(bWrite)
 808                 {
 809                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 810                 }
 811                 else
 812                 {
 813                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 814                 }
 815
 816                 // Check if WE and RE are cleared and DONE is set.
 817                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 818                 {
 819                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 820                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 821                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 822                         {
 823                                 break;
 824                         }
 825                         udelay(10);
 826                 }
 827                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 828                 {
 829                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 830                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 831                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 832                         write_nic_byte(dev, SW_3W_CMD1, 0);
 833                 }
 834
 835                 // Read back data for read operation.
 836                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 837                 if(bWrite == 0)
 838                 {
 839                         if(nDataBufBitCnt == 16)
 840                         {
 841                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 842                         }
 843                         else if(nDataBufBitCnt == 64)
 844                         {
 845                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 846                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 847                         }
 848                         else
 849                         {
 850                                 int idx;
 851                                 int ByteCnt = nDataBufBitCnt / 8;
 852
 853                                 if ((nDataBufBitCnt % 8) != 0)
 854                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 855                                         nDataBufBitCnt);
 856
 857                                 if (nDataBufBitCnt > 64)
 858                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 859                                         nDataBufBitCnt);
 860
 861                                 for(idx = 0; idx < ByteCnt; idx++)
 862                                 {
 863                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 864                                 }
 865                         }
 866                 }
 867
 868         }while(0);
 869
 870         return bResult;
 871 }
 872
 873
 874 void
 875 RF_WriteReg(
 876         struct net_device *dev,
 877         u8              offset,
 878         u32             data
 879         )
 880 {
 881         //RFReg                 reg;
 882         u32                     data2Write;
 883         u8                      len;
 884         u8                      low2high;
 885         //u32                   RF_Read = 0;
 886         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 887
 888
 889         switch(priv->rf_chip)
 890         {
 891         case RFCHIPID_RTL8225:
 892         case RF_ZEBRA2:         // Annie 2006-05-12.
 893         case RF_ZEBRA4:        //by amy
 894                 switch(priv->RegThreeWireMode)
 895                 {
 896                 case SW_THREE_WIRE:
 897                         { // Perform SW 3-wire programming by driver.
 898                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 899                                 len = 16;
 900                                 low2high = 0;
 901                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 902                         }
 903                         break;
 904
 905                 case HW_THREE_WIRE:
 906                         { // Pure HW 3-wire.
 907                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 908                                 len = 16;
 909                                 HwThreeWire(
 910                                         dev,
 911                                         (u8 *)(&data2Write),    // pDataBuf,
 912                                         len,                            // nDataBufBitCnt,
 913                                         0,                                      // bHold,
 914                                         1);                                     // bWrite
 915                         }
 916                         break;
 917   #ifdef CONFIG_RTL818X_S
 918                         case HW_THREE_WIRE_PI: //Parallel Interface
 919                         { // Pure HW 3-wire.
 920                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 921                                 len = 16;
 922                                         HwHSSIThreeWire(
 923                                                 dev,
 924                                                 (u8*)(&data2Write),     // pDataBuf,
 925                                                 len,                                            // nDataBufBitCnt,
 926                                                 0,                                      // bSI
 927                                                 1);                                     // bWrite
 928
 929                                 //printk("33333\n");
 930                         }
 931                         break;
 932
 933                         case HW_THREE_WIRE_SI: //Serial Interface
 934                         { // Pure HW 3-wire.
 935                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 936                                 len = 16;
 937 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 938 //                                low2high = 0;
 939 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 940
 941                                 HwHSSIThreeWire(
 942                                         dev,
 943                                         (u8*)(&data2Write),     // pDataBuf,
 944                                         len,                                            // nDataBufBitCnt,
 945                                         1,                                      // bSI
 946                                         1);                                     // bWrite
 947
 948 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 949                         }
 950                         break;
 951   #endif
 952
 953
 954                 default:
 955                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 956                         break;
 957                 }
 958                 break;
 959
 960         default:
 961                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 962                 break;
 963         }
 964 }
 965
 966
 967 void
 968 ZEBRA_RFSerialRead(
 969         struct net_device *dev,
 970         u32             data2Write,
 971         u8              wLength,
 972         u32             *data2Read,
 973         u8              rLength,
 974         u8              low2high
 975         )
 976 {
 977         ThreeWireReg    twreg;
 978         int                             i;
 979         u16                     oval,oval2,oval3,tmp, wReg80;
 980         u32                     mask;
 981         u8                      u1bTmp;
 982         ThreeWireReg    tdata;
 983         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 984 #ifdef CONFIG_RTL818X_S
 985         { // RTL8187S HSSI Read/Write Function
 986                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 987                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 988                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 989         }
 990 #endif
 991
 992         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 993         oval2 = read_nic_word(dev, RFPinsEnable);
 994         oval3 = read_nic_word(dev, RFPinsSelect);
 995
 996         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 997         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 998
 999         *data2Read = 0;
1000
1001         // We must clear BIT0-3 here, otherwise,
1002         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
1003         // which will cause the value read become 0. 2005.04.11, by rcnjko.
1004         oval &= ~0xf;
1005
1006         // Avoid collision with hardware three-wire.
1007         twreg.longData = 0;
1008         twreg.struc.enableB = 1;
1009         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
1010
1011         twreg.longData = 0;
1012         twreg.struc.enableB = 0;
1013         twreg.struc.clk = 0;
1014         twreg.struc.read_write = 0;
1015         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
1016
1017         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
1018         for(i = 0; i < wLength/2; i++)
1019         {
1020                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
1021                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1022                 twreg.struc.clk = 1;
1023                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1024                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1025
1026                 mask = (low2high) ? (mask<<1): (mask>>1);
1027
1028                 if(i == 2)
1029                 {
1030                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
1031                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
1032                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
1033
1034                         twreg.struc.read_write=1;
1035                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1036                         twreg.struc.clk = 0;
1037                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1038                         break;
1039                 }
1040                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
1041                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1042                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1043
1044                 twreg.struc.clk = 0;
1045                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1046
1047                 mask = (low2high) ? (mask<<1) : (mask>>1);
1048         }
1049
1050         twreg.struc.clk = 0;
1051         twreg.struc.data = 0;
1052         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1053         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
1054
1055         //
1056         // 061016, by rcnjko:
1057         // We must set data pin to HW controled, otherwise RF can't driver it and
1058         // value RF register won't be able to read back properly.
1059         //
1060         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
1061
1062         for(i = 0; i < rLength; i++)
1063         {
1064                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
1065                 twreg.struc.clk = 1;
1066                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1067                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1068                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1069                 tmp = read_nic_word(dev, RFPinsInput);
1070                 tdata.longData = tmp;
1071                 *data2Read |= tdata.struc.clk ? mask : 0;
1072
1073                 twreg.struc.clk = 0;
1074                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1075
1076                 mask = (low2high) ? (mask<<1) : (mask>>1);
1077         }
1078         twreg.struc.enableB = 1;
1079         twreg.struc.clk = 0;
1080         twreg.struc.data = 0;
1081         twreg.struc.read_write = 1;
1082         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
1083
1084         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
1085         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
1086         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
1087         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
1088         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
1089         write_nic_word(dev, RFPinsOutput, 0x3a0);
1090         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
1091 }
1092
1093
1094 u32
1095 RF_ReadReg(
1096         struct net_device *dev,
1097         u8              offset
1098         )
1099 {
1100         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1101         u32                     data2Write;
1102         u8                      wlen;
1103         u8                      rlen;
1104         u8                      low2high;
1105         u32                     dataRead;
1106
1107         switch(priv->rf_chip)
1108         {
1109         case RFCHIPID_RTL8225:
1110         case RF_ZEBRA2:
1111         case RF_ZEBRA4:
1112                 switch(priv->RegThreeWireMode)
1113                 {
1114 #ifdef CONFIG_RTL818X_S
1115                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
1116                         {
1117                                 data2Write = ((u32)(offset&0x0f));
1118                                 wlen=16;
1119                                 HwHSSIThreeWire(
1120                                         dev,
1121                                         (u8*)(&data2Write),     // pDataBuf,
1122                                         wlen,                                   // nDataBufBitCnt,
1123                                         0,                                      // bSI
1124                                         0);                                     // bWrite
1125                                 dataRead= data2Write;
1126                         }
1127                         break;
1128
1129                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
1130                         {
1131                                 data2Write = ((u32)(offset&0x0f)) ;
1132                                 wlen=16;
1133                                 HwHSSIThreeWire(
1134                                         dev,
1135                                         (u8*)(&data2Write),     // pDataBuf,
1136                                         wlen,                                   // nDataBufBitCnt,
1137                                         1,                                      // bSI
1138                                         0                                       // bWrite
1139                                         );
1140                                 dataRead= data2Write;
1141                         }
1142                         break;
1143
1144 #endif
1145                         // Perform SW 3-wire programming by driver.
1146                         default:
1147                         {
1148                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
1149                                 wlen = 6;
1150                                 rlen = 12;
1151                                 low2high = 0;
1152                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
1153                         }
1154                         break;
1155                 }
1156                 break;
1157         default:
1158                 dataRead = 0;
1159                 break;
1160         }
1161
1162         return dataRead;
1163 }
1164
1165
1166 // by Owen on 04/07/14 for writing BB register successfully
1167 void
1168 WriteBBPortUchar(
1169         struct net_device *dev,
1170         u32             Data
1171         )
1172 {
1173         //u8    TimeoutCounter;
1174         u8      RegisterContent;
1175         u8      UCharData;
1176
1177         UCharData = (u8)((Data & 0x0000ff00) >> 8);
1178         PlatformIOWrite4Byte(dev, PhyAddr, Data);
1179         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
1180         {
1181                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
1182                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1183                 //if(UCharData == RegisterContent)
1184                 //      break;
1185         }
1186 }
1187
1188 u8
1189 ReadBBPortUchar(
1190         struct net_device *dev,
1191         u32             addr
1192         )
1193 {
1194         //u8    TimeoutCounter;
1195         u8      RegisterContent;
1196
1197         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
1198         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
1199
1200         return RegisterContent;
1201 }
1202 //{by amy 080312
1203 #ifdef CONFIG_RTL818X_S
1204 //
1205 //      Description:
1206 //              Perform Antenna settings with antenna diversity on 87SE.
1207 //    Created by Roger, 2008.01.25.
1208 //
1209 bool
1210 SetAntennaConfig87SE(
1211         struct net_device *dev,
1212         u8                      DefaultAnt,             // 0: Main, 1: Aux.
1213         bool            bAntDiversity   // 1:Enable, 0: Disable.
1214 )
1215 {
1216         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1217         bool   bAntennaSwitched = true;
1218
1219         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
1220
1221         // Threshold for antenna diversity.
1222         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1223
1224         if( bAntDiversity )  //  Enable Antenna Diversity.
1225         {
1226                 if( DefaultAnt == 1 )  // aux antenna
1227                 {
1228                         // Mac register, aux antenna
1229                         write_nic_byte(dev, ANTSEL, 0x00);
1230
1231                         // Config CCK RX antenna.
1232                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1233                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1234
1235                         // Config OFDM RX antenna.
1236                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1237                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1238                 }
1239                 else //  use main antenna
1240                 {
1241                         // Mac register, main antenna
1242                         write_nic_byte(dev, ANTSEL, 0x03);
1243                         //base band
1244                         // Config CCK RX antenna.
1245                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1246                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1247
1248                         // Config OFDM RX antenna.
1249                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1250                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1251                 }
1252         }
1253         else   // Disable Antenna Diversity.
1254         {
1255                 if( DefaultAnt == 1 ) // aux Antenna
1256                 {
1257                         // Mac register, aux antenna
1258                         write_nic_byte(dev, ANTSEL, 0x00);
1259
1260                         // Config CCK RX antenna.
1261                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1262                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1263
1264                         // Config OFDM RX antenna.
1265                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
1266                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1267                 }
1268                 else // main Antenna
1269                 {
1270                         // Mac register, main antenna
1271                         write_nic_byte(dev, ANTSEL, 0x03);
1272
1273                         // Config CCK RX antenna.
1274                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1275                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1276
1277                         // Config OFDM RX antenna.
1278                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1279                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1280                 }
1281         }
1282         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1283         return  bAntennaSwitched;
1284 }
1285 #endif
1286 //by amy 080312
1287 /*---------------------------------------------------------------
1288   * Hardware Initialization.
1289   * the code is ported from Windows source code
1290   ----------------------------------------------------------------*/
1291
1292 void
1293 ZEBRA_Config_85BASIC_HardCode(
1294         struct net_device *dev
1295         )
1296 {
1297
1298         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1299         u32                     i;
1300         u32     addr,data;
1301         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1302        u8                       u1b24E;
1303
1304 #ifdef CONFIG_RTL818X_S
1305
1306         //=============================================================================
1307         // 87S_PCIE :: RADIOCFG.TXT
1308         //=============================================================================
1309
1310
1311         // Page1 : reg16-reg30
1312         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1313         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1314         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1315
1316         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1317                 priv->card_8185 = VERSION_8187S_D;
1318
1319         // Page0 : reg0-reg15
1320
1321 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1322         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1323
1324         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1325
1326 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1327         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1328
1329 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1330         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1331
1332         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1333         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1334         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1335         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1336         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1337         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1338         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1339         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1340         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1341         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1342         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1343         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1344
1345
1346         // Page1 : reg16-reg30
1347         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1348
1349         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1350
1351         if(priv->card_8185 < VERSION_8187S_C)
1352         {
1353                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1354                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1355                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1356         }
1357         else
1358         {
1359                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1360                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1361                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1362         }
1363
1364
1365         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1366 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1367 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1368 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1369         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1370         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1371
1372         if(priv->card_8185 == VERSION_8187S_D)
1373         {
1374                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1375                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1376                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1377         }
1378         else
1379         {
1380                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1381                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1382                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1383         }
1384
1385         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1386
1387 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1388         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1389
1390         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1391         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1392         for(i=0;i<=36;i++)
1393         {
1394                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1395                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1396                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1397         }
1398
1399         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1400         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1401         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1402
1403         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1404         mdelay(10);     // Deay 10 ms. //0xfd
1405
1406 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1407         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1408         //mdelay(10);   // Deay 10 ms. //0xfd
1409
1410         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1411         mdelay(10);     // Deay 10 ms. //0xfd
1412
1413         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1414         mdelay(10);     // Deay 10 ms. //0xfd
1415
1416         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1417         mdelay(10);     // Deay 10 ms. //0xfd
1418
1419         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1420         mdelay(10);     // Deay 10 ms. //0xfd
1421
1422         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1423         mdelay(200);    // Deay 200 ms. //0xfd
1424         mdelay(10);     // Deay 10 ms. //0xfd
1425         mdelay(10);     // Deay 10 ms. //0xfd
1426
1427         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1428         mdelay(10);     // Deay 10 ms. //0xfd
1429
1430         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1431         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1432         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1433         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1434
1435         // DAC calibration off 20070702
1436         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1437         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1438 //{by amy 080312
1439         // For crystal calibration, added by Roger, 2007.12.11.
1440         if( priv->bXtalCalibration ) // reg 30.
1441         { // enable crystal calibration.
1442                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1443                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1444                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1445                 // So we should minus 4 BITs offset.
1446                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1447                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1448                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1449         }
1450         else
1451         { // using default value. Xin=6, Xout=6.
1452                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1453         }
1454 //by amy 080312
1455 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1456
1457         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1458 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1459         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1460         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1461         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1462         mdelay(10);     // Deay 10 ms. //0xfe
1463         mdelay(10);     // Deay 10 ms. //0xfe
1464         mdelay(10);     // Deay 10 ms. //0xfe
1465         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1466         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1467         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1468
1469 #if 0//-edward
1470         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1);
1471         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1472         RF_WriteReg(dev, 0x00, 0x009F);                 mdelay(1);
1473 #endif
1474         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1475         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1476         //power save parameters.
1477         u1b24E = read_nic_byte(dev, 0x24E);
1478         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1479
1480         //=============================================================================
1481
1482         //=============================================================================
1483         // CCKCONF.TXT
1484         //=============================================================================
1485
1486         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1487                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1488                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1489                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1490                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1491                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1492         */
1493 #if 0
1494         write_nic_dword(dev, PHY_ADR, 0x0100c880);
1495         write_nic_dword(dev, PHY_ADR, 0x01001c86);
1496         write_nic_dword(dev, PHY_ADR, 0x01007890);
1497         write_nic_dword(dev, PHY_ADR, 0x0100d0ae);
1498         write_nic_dword(dev, PHY_ADR, 0x010006af);
1499         write_nic_dword(dev, PHY_ADR, 0x01004681);
1500 #endif
1501         write_phy_cck(dev,0x00,0xc8);
1502         write_phy_cck(dev,0x06,0x1c);
1503         write_phy_cck(dev,0x10,0x78);
1504         write_phy_cck(dev,0x2e,0xd0);
1505         write_phy_cck(dev,0x2f,0x06);
1506         write_phy_cck(dev,0x01,0x46);
1507
1508         // power control
1509         write_nic_byte(dev, CCK_TXAGC, 0x10);
1510         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1511         write_nic_byte(dev, ANTSEL, 0x03);
1512 #else
1513         //=============================================================================
1514         // RADIOCFG.TXT
1515         //=============================================================================
1516
1517         RF_WriteReg(dev, 0x00, 0x00b7);                 mdelay(1);
1518         RF_WriteReg(dev, 0x01, 0x0ee0);                 mdelay(1);
1519         RF_WriteReg(dev, 0x02, 0x044d);                 mdelay(1);
1520         RF_WriteReg(dev, 0x03, 0x0441);                 mdelay(1);
1521         RF_WriteReg(dev, 0x04, 0x08c3);                 mdelay(1);
1522         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1523         RF_WriteReg(dev, 0x06, 0x00e6);                 mdelay(1);
1524         RF_WriteReg(dev, 0x07, 0x082a);                 mdelay(1);
1525         RF_WriteReg(dev, 0x08, 0x003f);                 mdelay(1);
1526         RF_WriteReg(dev, 0x09, 0x0335);                 mdelay(1);
1527         RF_WriteReg(dev, 0x0a, 0x09d4);                 mdelay(1);
1528         RF_WriteReg(dev, 0x0b, 0x07bb);                 mdelay(1);
1529         RF_WriteReg(dev, 0x0c, 0x0850);                 mdelay(1);
1530         RF_WriteReg(dev, 0x0d, 0x0cdf);                 mdelay(1);
1531         RF_WriteReg(dev, 0x0e, 0x002b);                 mdelay(1);
1532         RF_WriteReg(dev, 0x0f, 0x0114);                 mdelay(1);
1533
1534         RF_WriteReg(dev, 0x00, 0x01b7);                 mdelay(1);
1535
1536
1537         for(i=1;i<=95;i++)
1538         {
1539                 RF_WriteReg(dev, 0x01, i);      mdelay(1);
1540                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1541                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1542         }
1543
1544         RF_WriteReg(dev, 0x03, 0x0080);                 mdelay(1);      // write reg 18
1545         RF_WriteReg(dev, 0x05, 0x0004);                 mdelay(1);      // write reg 20
1546         RF_WriteReg(dev, 0x00, 0x00b7);                 mdelay(1);      // switch to reg0-reg15
1547         //0xfd
1548         //0xfd
1549         //0xfd
1550         RF_WriteReg(dev, 0x02, 0x0c4d);                 mdelay(1);
1551         mdelay(100);    // Deay 100 ms. //0xfe
1552         mdelay(100);    // Deay 100 ms. //0xfe
1553         RF_WriteReg(dev, 0x02, 0x044d);                 mdelay(1);
1554         RF_WriteReg(dev, 0x00, 0x02bf);                 mdelay(1);      //0x002f disable 6us corner change,  06f--> enable
1555
1556         //=============================================================================
1557
1558         //=============================================================================
1559         // CCKCONF.TXT
1560         //=============================================================================
1561
1562         //=============================================================================
1563
1564         //=============================================================================
1565         // Follow WMAC RTL8225_Config()
1566         //=============================================================================
1567
1568         // power control
1569         write_nic_byte(dev, CCK_TXAGC, 0x03);
1570         write_nic_byte(dev, OFDM_TXAGC, 0x07);
1571         write_nic_byte(dev, ANTSEL, 0x03);
1572
1573         //=============================================================================
1574
1575         // OFDM BBP setup
1576 //      SetOutputEnableOfRfPins(dev);//by amy
1577 #endif
1578
1579
1580
1581         //=============================================================================
1582         // AGC.txt
1583         //=============================================================================
1584
1585 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1586         write_phy_ofdm(dev, 0x00, 0x12);
1587         //WriteBBPortUchar(dev, 0x00001280);
1588
1589         for (i=0; i<128; i++)
1590         {
1591                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1592
1593                 data = ZEBRA_AGC[i+1];
1594                 data = data << 8;
1595                 data = data | 0x0000008F;
1596
1597                 addr = i + 0x80; //enable writing AGC table
1598                 addr = addr << 8;
1599                 addr = addr | 0x0000008E;
1600
1601                 WriteBBPortUchar(dev, data);
1602                 WriteBBPortUchar(dev, addr);
1603                 WriteBBPortUchar(dev, 0x0000008E);
1604         }
1605
1606         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1607         //WriteBBPortUchar(dev, 0x00001080);
1608
1609         //=============================================================================
1610
1611         //=============================================================================
1612         // OFDMCONF.TXT
1613         //=============================================================================
1614
1615         for(i=0; i<60; i++)
1616         {
1617                 u4bRegOffset=i;
1618                 u4bRegValue=OFDM_CONFIG[i];
1619
1620                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1621
1622                 WriteBBPortUchar(dev,
1623                                                 (0x00000080 |
1624                                                 (u4bRegOffset & 0x7f) |
1625                                                 ((u4bRegValue & 0xff) << 8)));
1626         }
1627
1628         //=============================================================================
1629 //by amy for antenna
1630         //=============================================================================
1631 //{by amy 080312
1632 #ifdef CONFIG_RTL818X_S
1633         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1634         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1635 #endif
1636 //by amy 080312}
1637 #if 0
1638         // Config Sw/Hw  Antenna Diversity
1639         if( priv->bSwAntennaDiverity )  //  Use SW+Hw Antenna Diversity
1640         {
1641                 if( priv->bDefaultAntenna1 == true )  // aux antenna
1642                 {
1643                         // Mac register, aux antenna
1644                         write_nic_byte(dev, ANTSEL, 0x00);
1645                         // Config CCK RX antenna.
1646                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1647                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1648                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1649                         // Config OFDM RX antenna.
1650                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1651                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1652                 }
1653                 else //  main antenna
1654                 {
1655                         // Mac register, main antenna
1656                         write_nic_byte(dev, ANTSEL, 0x03);
1657                         //base band
1658                         // Config CCK RX antenna.
1659                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1660                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1661                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
1662                         // Config OFDM RX antenna.
1663                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1664                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
1665                 }
1666         }
1667         else   // Disable Antenna Diversity
1668         {
1669                 if( priv->bDefaultAntenna1 == true ) // aux Antenna
1670                 {
1671                         // Mac register, aux antenna
1672                         write_nic_byte(dev, ANTSEL, 0x00);
1673                         // Config CCK RX antenna.
1674                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
1675                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1676                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1677                         // Config OFDM RX antenna.
1678                         write_phy_ofdm(dev, 0x0d, 0x54);   // Reg0d : 54
1679                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1680                 }
1681                 else // main Antenna
1682                 {
1683                         // Mac register, main antenna
1684                         write_nic_byte(dev, ANTSEL, 0x03);
1685                         // Config CCK RX antenna.
1686                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
1687                         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
1688                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1689                         // Config OFDM RX antenna.
1690                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
1691                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1692                 }
1693         }
1694 #endif
1695 //by amy for antenna
1696 }
1697
1698
1699 void
1700 UpdateInitialGain(
1701         struct net_device *dev
1702         )
1703 {
1704         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1705         //unsigned char* IGTable;
1706         //u8                    DIG_CurrentInitialGain = 4;
1707         //unsigned char u1Tmp;
1708
1709         //lzm add 080826
1710         if(priv->eRFPowerState != eRfOn)
1711         {
1712                 //Don't access BB/RF under disable PLL situation.
1713                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1714                 // Back to the original state
1715                 priv->InitialGain= priv->InitialGainBackUp;
1716                 return;
1717         }
1718
1719         switch(priv->rf_chip)
1720         {
1721 #if 0
1722         case RF_ZEBRA2:
1723                 // Dynamic set initial gain, by shien chang, 2006.07.14
1724                 switch(priv->InitialGain)
1725                 {
1726                         case 1: //m861dBm
1727                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm \n");
1728                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1729                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1730                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1731                                 break;
1732
1733                         case 2: //m862dBm
1734                                 DMESG("RTL8185B + 8225 Initial Gain State 2: -82 dBm \n");
1735                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1736                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1737                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1738                                 break;
1739
1740                         case 3: //m863dBm
1741                                 DMESG("RTL8185B + 8225 Initial Gain State 3: -82 dBm \n");
1742                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1743                                 write_nic_dword(dev, PhyAddr, 0x96a4);  mdelay(1);
1744                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1745                                 break;
1746
1747                         case 4: //m864dBm
1748                                 DMESG("RTL8185B + 8225 Initial Gain State 4: -78 dBm \n");
1749                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1750                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1751                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1752                                 break;
1753
1754                         case 5: //m82dBm
1755                                 DMESG("RTL8185B + 8225 Initial Gain State 5: -74 dBm \n");
1756                                 write_nic_dword(dev, PhyAddr, 0x3697);  mdelay(1);
1757                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1758                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1759                                 break;
1760
1761                         case 6: //m78dBm
1762                                 DMESG("RTL8185B + 8225 Initial Gain State 6: -70 dBm \n");
1763                                 write_nic_dword(dev, PhyAddr, 0x4697);  mdelay(1);
1764                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1765                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1766                                 break;
1767
1768                         case 7: //m74dBm
1769                                 DMESG("RTL8185B + 8225 Initial Gain State 7: -66 dBm \n");
1770                                 write_nic_dword(dev, PhyAddr, 0x5697);  mdelay(1);
1771                                 write_nic_dword(dev, PhyAddr, 0xa6a4);  mdelay(1);
1772                                 write_nic_dword(dev, PhyAddr, 0xfb85);  mdelay(1);
1773                                 break;
1774
1775                         default:        //MP
1776                                 DMESG("RTL8185B + 8225 Initial Gain State 1: -82 dBm (default)\n");
1777                                 write_nic_dword(dev, PhyAddr, 0x2697);  mdelay(1);
1778                                 write_nic_dword(dev, PhyAddr, 0x86a4);  mdelay(1);
1779                                 write_nic_dword(dev, PhyAddr, 0xfa85);  mdelay(1);
1780                                 break;
1781                 }
1782                 break;
1783 #endif
1784         case RF_ZEBRA4:
1785                 // Dynamic set initial gain, follow 87B
1786                 switch(priv->InitialGain)
1787                 {
1788                         case 1: //m861dBm
1789                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1790                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1791                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1792                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1793                                 break;
1794
1795                         case 2: //m862dBm
1796                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1797                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1798                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1799                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1800                                 break;
1801
1802                         case 3: //m863dBm
1803                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1804                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1805                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1806                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1807                                 break;
1808
1809                         case 4: //m864dBm
1810                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1811                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1812                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1813                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1814                                 break;
1815
1816                         case 5: //m82dBm
1817                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1818                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1819                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1820                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1821                                 break;
1822
1823                         case 6: //m78dBm
1824                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1825                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1826                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1827                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1828                                 break;
1829
1830                         case 7: //m74dBm
1831                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1832                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1833                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1834                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1835                                 break;
1836
1837                         case 8:
1838                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1839                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1840                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1841                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1842                                 break;
1843
1844
1845                         default:        //MP
1846                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1847                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1848                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1849                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1850                                 break;
1851                 }
1852                 break;
1853
1854
1855         default:
1856                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1857                 break;
1858         }
1859 }
1860 #ifdef CONFIG_RTL818X_S
1861 //
1862 //      Description:
1863 //              Tx Power tracking mechanism routine on 87SE.
1864 //      Created by Roger, 2007.12.11.
1865 //
1866 void
1867 InitTxPwrTracking87SE(
1868         struct net_device *dev
1869 )
1870 {
1871         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1872         u32     u4bRfReg;
1873
1874         u4bRfReg = RF_ReadReg(dev, 0x02);
1875
1876         // Enable Thermal meter indication.
1877         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1878         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1879 }
1880
1881 #endif
1882 void
1883 PhyConfig8185(
1884         struct net_device *dev
1885         )
1886 {
1887         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1888        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1889            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1890         // RF config
1891         switch(priv->rf_chip)
1892         {
1893         case RF_ZEBRA2:
1894         case RF_ZEBRA4:
1895                 ZEBRA_Config_85BASIC_HardCode( dev);
1896                 break;
1897         }
1898 //{by amy 080312
1899 #ifdef CONFIG_RTL818X_S
1900         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1901         if(priv->bDigMechanism)
1902         {
1903                 if(priv->InitialGain == 0)
1904                         priv->InitialGain = 4;
1905                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1906         }
1907
1908         //
1909         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1910         // We initialize thermal meter here to avoid unsuccessful configuration.
1911         // Added by Roger, 2007.12.11.
1912         //
1913         if(priv->bTxPowerTrack)
1914                 InitTxPwrTracking87SE(dev);
1915
1916 #endif
1917 //by amy 080312}
1918         priv->InitialGainBackUp= priv->InitialGain;
1919         UpdateInitialGain(dev);
1920
1921         return;
1922 }
1923
1924
1925
1926
1927 void
1928 HwConfigureRTL8185(
1929                 struct net_device *dev
1930                 )
1931 {
1932         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1933 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1934         u8              bUNIVERSAL_CONTROL_RL = 0;
1935
1936         u8              bUNIVERSAL_CONTROL_AGC = 1;
1937         u8              bUNIVERSAL_CONTROL_ANT = 1;
1938         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1939         u8              val8;
1940         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1941         //struct ieee80211_device *ieee = priv->ieee80211;
1942         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1943 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1944 //      {
1945 //              write_nic_word(dev, BRSR, 0xffff);
1946 //      }
1947 //      else
1948 //      {
1949 //              write_nic_word(dev, BRSR, 0x000f);
1950 //      }
1951 //by amy 080312}
1952         write_nic_word(dev, BRSR, 0x0fff);
1953         // Retry limit
1954         val8 = read_nic_byte(dev, CW_CONF);
1955
1956         if(bUNIVERSAL_CONTROL_RL)
1957                 val8 = val8 & 0xfd;
1958         else
1959                 val8 = val8 | 0x02;
1960
1961         write_nic_byte(dev, CW_CONF, val8);
1962
1963         // Tx AGC
1964         val8 = read_nic_byte(dev, TXAGC_CTL);
1965         if(bUNIVERSAL_CONTROL_AGC)
1966         {
1967                 write_nic_byte(dev, CCK_TXAGC, 128);
1968                 write_nic_byte(dev, OFDM_TXAGC, 128);
1969                 val8 = val8 & 0xfe;
1970         }
1971         else
1972         {
1973                 val8 = val8 | 0x01 ;
1974         }
1975
1976
1977         write_nic_byte(dev, TXAGC_CTL, val8);
1978
1979         // Tx Antenna including Feedback control
1980         val8 = read_nic_byte(dev, TXAGC_CTL );
1981
1982         if(bUNIVERSAL_CONTROL_ANT)
1983         {
1984                 write_nic_byte(dev, ANTSEL, 0x00);
1985                 val8 = val8 & 0xfd;
1986         }
1987         else
1988         {
1989                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1990         }
1991
1992         write_nic_byte(dev, TXAGC_CTL, val8);
1993
1994         // Auto Rate fallback control
1995         val8 = read_nic_byte(dev, RATE_FALLBACK);
1996         val8 &= 0x7c;
1997         if( bAUTO_RATE_FALLBACK_CTL )
1998         {
1999                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
2000
2001                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
2002                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
2003 //by amy
2004 #if 0
2005                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff);        // set 1M ~ 54M
2006 #endif
2007 #ifdef CONFIG_RTL818X_S
2008                 // Aadded by Roger, 2007.11.15.
2009                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
2010 #else
2011                 PlatformIOWrite2Byte(dev, ARFR, 0x0c00); //set 48Mbps, 54Mbps.
2012                 // By SD3 szuyi's request. by Roger, 2007.03.26.
2013 #endif
2014 //by amy
2015         }
2016         else
2017         {
2018         }
2019         write_nic_byte(dev, RATE_FALLBACK, val8);
2020 }
2021
2022
2023
2024 static void
2025 MacConfig_85BASIC_HardCode(
2026         struct net_device *dev)
2027 {
2028         //============================================================================
2029         // MACREG.TXT
2030         //============================================================================
2031         int                     nLinesRead = 0;
2032
2033         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
2034         int     i;
2035
2036         nLinesRead=sizeof(MAC_REG_TABLE)/2;
2037
2038         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
2039         {
2040                 u4bRegOffset=MAC_REG_TABLE[i][0];
2041                 u4bRegValue=MAC_REG_TABLE[i][1];
2042
2043                 if(u4bRegOffset == 0x5e)
2044                 {
2045                     u4bPageIndex = u4bRegValue;
2046                 }
2047                 else
2048                 {
2049                     u4bRegOffset |= (u4bPageIndex << 8);
2050                 }
2051                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
2052                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
2053         }
2054         //============================================================================
2055 }
2056
2057
2058
2059 static void
2060 MacConfig_85BASIC(
2061         struct net_device *dev)
2062 {
2063
2064        u8                       u1DA;
2065         MacConfig_85BASIC_HardCode(dev);
2066
2067         //============================================================================
2068
2069         // Follow TID_AC_MAP of WMac.
2070         write_nic_word(dev, TID_AC_MAP, 0xfa50);
2071
2072         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
2073         write_nic_word(dev, IntMig, 0x0000);
2074
2075         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
2076         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
2077         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
2078         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
2079
2080         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
2081         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
2082 //by amy
2083 #if 0
2084         write_nic_dword(dev, RFTiming, 0x00004001);
2085 #endif
2086 #ifdef CONFIG_RTL818X_S
2087         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
2088
2089         //Enable DA10 TX power saving
2090         u1DA = read_nic_byte(dev, PHYPR);
2091         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
2092
2093         //POWER:
2094         write_nic_word(dev, 0x360, 0x1000);
2095         write_nic_word(dev, 0x362, 0x1000);
2096
2097         // AFE.
2098         write_nic_word(dev, 0x370, 0x0560);
2099         write_nic_word(dev, 0x372, 0x0560);
2100         write_nic_word(dev, 0x374, 0x0DA4);
2101         write_nic_word(dev, 0x376, 0x0DA4);
2102         write_nic_word(dev, 0x378, 0x0560);
2103         write_nic_word(dev, 0x37A, 0x0560);
2104         write_nic_word(dev, 0x37C, 0x00EC);
2105 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
2106         write_nic_word(dev, 0x37E, 0x00EC);//+edward
2107 #else
2108        write_nic_dword(dev, RFTiming, 0x00004003);
2109 #endif
2110        write_nic_byte(dev, 0x24E,0x01);
2111 //by amy
2112
2113 }
2114
2115
2116
2117
2118 u8
2119 GetSupportedWirelessMode8185(
2120         struct net_device *dev
2121 )
2122 {
2123         u8                      btSupportedWirelessMode = 0;
2124         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2125
2126         switch(priv->rf_chip)
2127         {
2128         case RF_ZEBRA2:
2129         case RF_ZEBRA4:
2130                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
2131                 break;
2132         default:
2133                 btSupportedWirelessMode = WIRELESS_MODE_B;
2134                 break;
2135         }
2136
2137         return btSupportedWirelessMode;
2138 }
2139
2140 void
2141 ActUpdateChannelAccessSetting(
2142         struct net_device *dev,
2143         WIRELESS_MODE                   WirelessMode,
2144         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
2145         )
2146 {
2147         struct r8180_priv *priv = ieee80211_priv(dev);
2148         struct ieee80211_device *ieee = priv->ieee80211;
2149         AC_CODING       eACI;
2150         AC_PARAM        AcParam;
2151         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
2152         u8      bFollowLegacySetting = 0;
2153         u8   u1bAIFS;
2154
2155         //
2156         // <RJ_TODO_8185B>
2157         // TODO: We still don't know how to set up these registers, just follow WMAC to
2158         // verify 8185B FPAG.
2159         //
2160         // <RJ_TODO_8185B>
2161         // Jong said CWmin/CWmax register are not functional in 8185B,
2162         // so we shall fill channel access realted register into AC parameter registers,
2163         // even in nQBss.
2164         //
2165         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
2166         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
2167         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
2168         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2169         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
2170         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
2171
2172         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
2173         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2174         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
2175
2176         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
2177
2178         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
2179         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
2180         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
2181         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
2182
2183         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
2184
2185         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
2186
2187 #ifdef TODO
2188         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
2189         if( pStaQos->CurrentQosMode > QOS_DISABLE )
2190         { // QoS mode.
2191                 if(pStaQos->QBssWirelessMode == WirelessMode)
2192                 {
2193                         // Follow AC Parameters of the QBSS.
2194                         for(eACI = 0; eACI < AC_MAX; eACI++)
2195                         {
2196                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
2197                         }
2198                 }
2199                 else
2200                 {
2201                         // Follow Default WMM AC Parameters.
2202                         bFollowLegacySetting = 1;
2203                 }
2204         }
2205         else
2206 #endif
2207         { // Legacy 802.11.
2208                 bFollowLegacySetting = 1;
2209
2210         }
2211
2212         // this setting is copied from rtl8187B.  xiong-2006-11-13
2213         if(bFollowLegacySetting)
2214         {
2215
2216
2217                 //
2218                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
2219                 // 2005.12.01, by rcnjko.
2220                 //
2221                 AcParam.longData = 0;
2222                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
2223                 AcParam.f.AciAifsn.f.ACM = 0;
2224                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
2225                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
2226                 AcParam.f.TXOPLimit = 0;
2227
2228                 //lzm reserved 080826
2229 #if 1
2230 #ifdef THOMAS_TURBO
2231                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
2232                 if( ieee->current_network.Turbo_Enable == 1 )
2233                         AcParam.f.TXOPLimit = 0x01FF;
2234 #endif
2235                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
2236                 if (ieee->iw_mode == IW_MODE_ADHOC)
2237                         AcParam.f.TXOPLimit = 0x0020;
2238 #endif
2239
2240                 for(eACI = 0; eACI < AC_MAX; eACI++)
2241                 {
2242                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
2243                         {
2244                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
2245                                 AC_CODING       eACI;
2246                                 u8              u1bAIFS;
2247                                 u32             u4bAcParam;
2248
2249                                 // Retrive paramters to udpate.
2250                                 eACI = pAcParam->f.AciAifsn.f.ACI;
2251                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
2252                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
2253                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
2254                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
2255                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
2256
2257                                 switch(eACI)
2258                                 {
2259                                         case AC1_BK:
2260                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
2261                                                 break;
2262
2263                                         case AC0_BE:
2264                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
2265                                                 break;
2266
2267                                         case AC2_VI:
2268                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
2269                                                 break;
2270
2271                                         case AC3_VO:
2272                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
2273                                                 break;
2274
2275                                         default:
2276                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
2277                                                 break;
2278                                 }
2279
2280                                 // Cehck ACM bit.
2281                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2282                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
2283                                 {
2284                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
2285                                         AC_CODING       eACI = pAciAifsn->f.ACI;
2286
2287                                         //modified Joseph
2288                                         //for 8187B AsynIORead issue
2289 #ifdef TODO
2290                                         u8      AcmCtrl = pHalData->AcmControl;
2291 #else
2292                                         u8      AcmCtrl = 0;
2293 #endif
2294                                         if( pAciAifsn->f.ACM )
2295                                         { // ACM bit is 1.
2296                                                 switch(eACI)
2297                                                 {
2298                                                         case AC0_BE:
2299                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
2300                                                                 break;
2301
2302                                                         case AC2_VI:
2303                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
2304                                                                 break;
2305
2306                                                         case AC3_VO:
2307                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
2308                                                                 break;
2309
2310                                                         default:
2311                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
2312                                                                 break;
2313                                                 }
2314                                         }
2315                                         else
2316                                         { // ACM bit is 0.
2317                                                 switch(eACI)
2318                                                 {
2319                                                         case AC0_BE:
2320                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
2321                                                                 break;
2322
2323                                                         case AC2_VI:
2324                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
2325                                                                 break;
2326
2327                                                         case AC3_VO:
2328                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
2329                                                                 break;
2330
2331                                                         default:
2332                                                                 break;
2333                                                 }
2334                                         }
2335
2336                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2337
2338 #ifdef TO_DO
2339                                         pHalData->AcmControl = AcmCtrl;
2340 #endif
2341                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
2342                                         write_nic_byte(dev, ACM_CONTROL, 0);
2343                                 }
2344                         }
2345                 }
2346
2347
2348         }
2349 }
2350
2351 void
2352 ActSetWirelessMode8185(
2353         struct net_device *dev,
2354         u8                              btWirelessMode
2355         )
2356 {
2357         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2358         struct ieee80211_device *ieee = priv->ieee80211;
2359         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
2360         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2361
2362         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
2363         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
2364                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
2365                         btWirelessMode, btSupportedWirelessMode);
2366                 return;
2367         }
2368
2369         // 1. Assign wireless mode to swtich if necessary.
2370         if (btWirelessMode == WIRELESS_MODE_AUTO)
2371         {
2372                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
2373                 {
2374                         btWirelessMode = WIRELESS_MODE_A;
2375                 }
2376                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
2377                 {
2378                         btWirelessMode = WIRELESS_MODE_G;
2379                 }
2380                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
2381                 {
2382                         btWirelessMode = WIRELESS_MODE_B;
2383                 }
2384                 else
2385                 {
2386                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
2387                                          btSupportedWirelessMode);
2388                         btWirelessMode = WIRELESS_MODE_B;
2389                 }
2390         }
2391
2392
2393         // 2. Swtich band: RF or BB specific actions,
2394         // for example, refresh tables in omc8255, or change initial gain if necessary.
2395         switch(priv->rf_chip)
2396         {
2397         case RF_ZEBRA2:
2398         case RF_ZEBRA4:
2399                 {
2400                         // Nothing to do for Zebra to switch band.
2401                         // Update current wireless mode if we swtich to specified band successfully.
2402                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
2403                 }
2404                 break;
2405
2406         default:
2407                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
2408                 break;
2409         }
2410
2411         // 3. Change related setting.
2412         if( ieee->mode == WIRELESS_MODE_A ){
2413                 DMESG("WIRELESS_MODE_A\n");
2414         }
2415         else if( ieee->mode == WIRELESS_MODE_B ){
2416                 DMESG("WIRELESS_MODE_B\n");
2417         }
2418         else if( ieee->mode == WIRELESS_MODE_G ){
2419                 DMESG("WIRELESS_MODE_G\n");
2420         }
2421
2422         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
2423 }
2424
2425 void rtl8185b_irq_enable(struct net_device *dev)
2426 {
2427         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2428
2429         priv->irq_enabled = 1;
2430         write_nic_dword(dev, IMR, priv->IntrMask);
2431 }
2432 //by amy for power save
2433 void
2434 DrvIFIndicateDisassociation(
2435         struct net_device *dev,
2436         u16                     reason
2437         )
2438 {
2439         //printk("==> DrvIFIndicateDisassociation()\n");
2440
2441         // nothing is needed after disassociation request.
2442
2443         //printk("<== DrvIFIndicateDisassociation()\n");
2444 }
2445 void
2446 MgntDisconnectIBSS(
2447         struct net_device *dev
2448 )
2449 {
2450         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2451         u8                      i;
2452
2453         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
2454
2455         DrvIFIndicateDisassociation(dev, unspec_reason);
2456
2457 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
2458         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
2459
2460         priv->ieee80211->state = IEEE80211_NOLINK;
2461
2462         //Stop Beacon.
2463
2464         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
2465         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
2466         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
2467
2468         // Disable Beacon Queue Own bit, suggested by jong
2469 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
2470         ieee80211_stop_send_beacons(priv->ieee80211);
2471
2472         priv->ieee80211->link_change(dev);
2473         notify_wx_assoc_event(priv->ieee80211);
2474
2475         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
2476 #if 0
2477         if(pMgntInfo->bEnableSwBeaconTimer)
2478         {
2479                 // SwBeaconTimer will stop if pMgntInfo->mIbss==FALSE, see SwBeaconCallback() for details.
2480 // comment out by haich, 2007.10.01
2481 //#if DEV_BUS_TYPE==USB_INTERFACE
2482                 PlatformCancelTimer( Adapter, &pMgntInfo->SwBeaconTimer);
2483 //#endif
2484         }
2485 #endif
2486
2487 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
2488
2489 }
2490 void
2491 MlmeDisassociateRequest(
2492         struct net_device *dev,
2493         u8*                     asSta,
2494         u8                      asRsn
2495         )
2496 {
2497         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2498         u8 i;
2499
2500         SendDisassociation(priv->ieee80211, asSta, asRsn );
2501
2502         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
2503                 //ShuChen TODO: change media status.
2504                 //ShuChen TODO: What to do when disassociate.
2505                 DrvIFIndicateDisassociation(dev, unspec_reason);
2506
2507
2508         //      pMgntInfo->AsocTimestamp = 0;
2509                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2510 //              pMgntInfo->mBrates.Length = 0;
2511 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2512
2513                 ieee80211_disassociate(priv->ieee80211);
2514
2515
2516         }
2517
2518 }
2519
2520 void
2521 MgntDisconnectAP(
2522         struct net_device *dev,
2523         u8                      asRsn
2524 )
2525 {
2526         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2527
2528 //
2529 // Commented out by rcnjko, 2005.01.27:
2530 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2531 //
2532 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2533 //      SecClearAllKeys(Adapter);
2534
2535         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2536 #ifdef TODO
2537         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2538                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2539         {
2540                 SecClearAllKeys(Adapter);
2541                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2542         }
2543 #endif
2544         // 2004.10.11, by rcnjko.
2545         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2546         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2547
2548         priv->ieee80211->state = IEEE80211_NOLINK;
2549 //      pMgntInfo->AsocTimestamp = 0;
2550 }
2551 bool
2552 MgntDisconnect(
2553         struct net_device *dev,
2554         u8                      asRsn
2555 )
2556 {
2557         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2558         //
2559         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2560         //
2561 #ifdef TODO
2562         if(pMgntInfo->mPss != eAwake)
2563         {
2564                 //
2565                 // Using AwkaeTimer to prevent mismatch ps state.
2566                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2567                 //
2568                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2569                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2570         }
2571 #endif
2572
2573         // Indication of disassociation event.
2574         //DrvIFIndicateDisassociation(Adapter, asRsn);
2575         if(IS_DOT11D_ENABLE(priv->ieee80211))
2576                 Dot11d_Reset(priv->ieee80211);
2577         // In adhoc mode, update beacon frame.
2578         if( priv->ieee80211->state == IEEE80211_LINKED )
2579         {
2580                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2581                 {
2582 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2583                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2584                         MgntDisconnectIBSS(dev);
2585                 }
2586                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2587                 {
2588                         // We clear key here instead of MgntDisconnectAP() because that
2589                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2590                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2591                         // used to handle disassociation related things to AP, e.g. send Disassoc
2592                         // frame to AP.  2005.01.27, by rcnjko.
2593 //                      SecClearAllKeys(Adapter);
2594
2595 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2596                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2597                         MgntDisconnectAP(dev, asRsn);
2598                 }
2599
2600                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2601 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2602         }
2603
2604         return true;
2605 }
2606 //
2607 //      Description:
2608 //              Chang RF Power State.
2609 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2610 //
2611 //      Assumption:
2612 //              PASSIVE LEVEL.
2613 //
2614 bool
2615 SetRFPowerState(
2616         struct net_device *dev,
2617         RT_RF_POWER_STATE       eRFPowerState
2618         )
2619 {
2620         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2621         bool                    bResult = false;
2622
2623 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2624         if(eRFPowerState == priv->eRFPowerState)
2625         {
2626 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2627                 return bResult;
2628         }
2629
2630         switch(priv->rf_chip)
2631         {
2632                 case RF_ZEBRA2:
2633                 case RF_ZEBRA4:
2634                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2635                         break;
2636
2637                 default:
2638                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2639                         break;;
2640 }
2641 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2642
2643         return bResult;
2644 }
2645 void
2646 HalEnableRx8185Dummy(
2647         struct net_device *dev
2648         )
2649 {
2650 }
2651 void
2652 HalDisableRx8185Dummy(
2653         struct net_device *dev
2654         )
2655 {
2656 }
2657
2658 bool
2659 MgntActSet_RF_State(
2660         struct net_device *dev,
2661         RT_RF_POWER_STATE       StateToSet,
2662         u32     ChangeSource
2663         )
2664 {
2665         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2666         bool                            bActionAllowed = false;
2667         bool                            bConnectBySSID = false;
2668         RT_RF_POWER_STATE       rtState;
2669         u16                             RFWaitCounter = 0;
2670         unsigned long flag;
2671 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2672         //
2673         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2674         // Only one thread can change the RF state at one time, and others should wait to be executed.
2675         //
2676 #if 1
2677         while(true)
2678         {
2679 //              down(&priv->rf_state);
2680                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2681                 if(priv->RFChangeInProgress)
2682                 {
2683 //                      printk("====================>haha111111111\n");
2684 //                      up(&priv->rf_state);
2685 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2686                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2687                         // Set RF after the previous action is done.
2688                         while(priv->RFChangeInProgress)
2689                         {
2690                                 RFWaitCounter ++;
2691 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2692                                 udelay(1000); // 1 ms
2693
2694                                 // Wait too long, return FALSE to avoid to be stuck here.
2695                                 if(RFWaitCounter > 1000) // 1sec
2696                                 {
2697 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2698                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2699                                         // TODO: Reset RF state?
2700                                         return false;
2701                                 }
2702                         }
2703                 }
2704                 else
2705                 {
2706 //                      printk("========================>haha2\n");
2707                         priv->RFChangeInProgress = true;
2708 //                      up(&priv->rf_state);
2709                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2710                         break;
2711                 }
2712         }
2713 #endif
2714         rtState = priv->eRFPowerState;
2715
2716
2717         switch(StateToSet)
2718         {
2719         case eRfOn:
2720                 //
2721                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2722                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2723                 //
2724                 priv->RfOffReason &= (~ChangeSource);
2725
2726                 if(! priv->RfOffReason)
2727                 {
2728                         priv->RfOffReason = 0;
2729                         bActionAllowed = true;
2730
2731                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2732                         {
2733                                 bConnectBySSID = true;
2734                         }
2735                 }
2736                 else
2737 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2738                         ;
2739                 break;
2740
2741         case eRfOff:
2742                  // 070125, rcnjko: we always keep connected in AP mode.
2743
2744                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2745                         {
2746                                 //
2747                                 // 060808, Annie:
2748                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2749                                 //
2750
2751                                 //
2752                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2753                                 // because we do NOT need to set ssid to dummy ones.
2754                                 // Revised by Roger, 2007.12.04.
2755                                 //
2756                                 MgntDisconnect( dev, disas_lv_ss );
2757
2758                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2759                                 // 2007.05.28, by shien chang.
2760 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2761 //                              pMgntInfo->NumBssDesc = 0;
2762 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2763 //                              pMgntInfo->NumBssDesc4Query = 0;
2764                         }
2765
2766
2767
2768                 priv->RfOffReason |= ChangeSource;
2769                 bActionAllowed = true;
2770                 break;
2771
2772         case eRfSleep:
2773                 priv->RfOffReason |= ChangeSource;
2774                 bActionAllowed = true;
2775                 break;
2776
2777         default:
2778                 break;
2779         }
2780
2781         if(bActionAllowed)
2782         {
2783 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2784                 // Config HW to the specified mode.
2785 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2786                 SetRFPowerState(dev, StateToSet);
2787
2788                 // Turn on RF.
2789                 if(StateToSet == eRfOn)
2790                 {
2791                         HalEnableRx8185Dummy(dev);
2792                         if(bConnectBySSID)
2793                         {
2794                         // by amy not supported
2795 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2796                         }
2797                 }
2798                 // Turn off RF.
2799                 else if(StateToSet == eRfOff)
2800                 {
2801                         HalDisableRx8185Dummy(dev);
2802                 }
2803         }
2804         else
2805         {
2806         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2807         }
2808
2809         // Release RF spinlock
2810 //      down(&priv->rf_state);
2811         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2812         priv->RFChangeInProgress = false;
2813 //      up(&priv->rf_state);
2814         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2815 //      printk("<===MgntActSet_RF_State()\n");
2816         return bActionAllowed;
2817 }
2818 void
2819 InactivePowerSave(
2820         struct net_device *dev
2821         )
2822 {
2823         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2824         //u8 index = 0;
2825
2826         //
2827         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2828         // is really scheduled.
2829         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2830         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2831         // blocks the IPS procedure of switching RF.
2832         // By Bruce, 2007-12-25.
2833         //
2834         priv->bSwRfProcessing = true;
2835
2836         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2837
2838         //
2839         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2840         //
2841 #if 0
2842         while( index < 4 )
2843         {
2844                 if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
2845                         (pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
2846                 {
2847                         if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
2848                         pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, FALSE, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, TRUE, FALSE);
2849
2850                 }
2851                 index++;
2852         }
2853 #endif
2854         priv->bSwRfProcessing = false;
2855 }
2856
2857 //
2858 //      Description:
2859 //              Enter the inactive power save mode. RF will be off
2860 //      2007.08.17, by shien chang.
2861 //
2862 void
2863 IPSEnter(
2864         struct net_device *dev
2865         )
2866 {
2867         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2868         RT_RF_POWER_STATE rtState;
2869         //printk("==============================>enter IPS\n");
2870         if (priv->bInactivePs)
2871         {
2872                 rtState = priv->eRFPowerState;
2873
2874                 //
2875                 // Added by Bruce, 2007-12-25.
2876                 // Do not enter IPS in the following conditions:
2877                 // (1) RF is already OFF or Sleep
2878                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2879                 // (3) Connectted (only disconnected can trigger IPS)
2880                 // (4) IBSS (send Beacon)
2881                 // (5) AP mode (send Beacon)
2882                 //
2883                 if (rtState == eRfOn && !priv->bSwRfProcessing
2884                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2885                 {
2886         //              printk("IPSEnter(): Turn off RF.\n");
2887                         priv->eInactivePowerState = eRfOff;
2888                         InactivePowerSave(dev);
2889                 }
2890         }
2891 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2892 }
2893 void
2894 IPSLeave(
2895         struct net_device *dev
2896         )
2897 {
2898         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2899         RT_RF_POWER_STATE rtState;
2900         //printk("===================================>leave IPS\n");
2901         if (priv->bInactivePs)
2902         {
2903                 rtState = priv->eRFPowerState;
2904                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2905                 {
2906 //                      printk("IPSLeave(): Turn on RF.\n");
2907                         priv->eInactivePowerState = eRfOn;
2908                         InactivePowerSave(dev);
2909                 }
2910         }
2911 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2912 }
2913 //by amy for power save
2914 void rtl8185b_adapter_start(struct net_device *dev)
2915 {
2916       struct r8180_priv *priv = ieee80211_priv(dev);
2917         struct ieee80211_device *ieee = priv->ieee80211;
2918
2919         u8 SupportedWirelessMode;
2920         u8                      InitWirelessMode;
2921         u8                      bInvalidWirelessMode = 0;
2922         //int i;
2923         u8 tmpu8;
2924         //u8 u1tmp,u2tmp;
2925         u8 btCR9346;
2926         u8 TmpU1b;
2927         u8 btPSR;
2928
2929         //rtl8180_rtx_disable(dev);
2930 //{by amy 080312
2931         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2932 //by amy 080312}
2933         rtl8180_reset(dev);
2934
2935         priv->dma_poll_mask = 0;
2936         priv->dma_poll_stop_mask = 0;
2937
2938         //rtl8180_beacon_tx_disable(dev);
2939
2940         HwConfigureRTL8185(dev);
2941
2942         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2943         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2944
2945         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2946
2947         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2948
2949         write_nic_word(dev, BcnItv, 100);
2950         write_nic_word(dev, AtimWnd, 2);
2951
2952         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2953         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2954
2955         write_nic_byte(dev, WPA_CONFIG, 0);
2956
2957         MacConfig_85BASIC(dev);
2958
2959         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2960         // BT_DEMO_BOARD type
2961         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2962 //by amy
2963 //#ifdef CONFIG_RTL818X_S
2964                 // for jong required
2965 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2966 //#endif
2967 //by amy
2968         //BT_QA_BOARD
2969         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2970
2971         //-----------------------------------------------------------------------------
2972         // Set up PHY related.
2973         //-----------------------------------------------------------------------------
2974         // Enable Config3.PARAM_En to revise AnaaParm.
2975         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2976 //by amy
2977         tmpu8 = read_nic_byte(dev, CONFIG3);
2978 #ifdef CONFIG_RTL818X_S
2979         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2980 #else
2981         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En | CONFIG3_CLKRUN_En) );
2982 #endif
2983 //by amy
2984         // Turn on Analog power.
2985         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2986         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2987         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2988 //by amy
2989 #ifdef CONFIG_RTL818X_S
2990         write_nic_word(dev, ANAPARAM3, 0x0010);
2991 #else
2992       write_nic_byte(dev, ANAPARAM3, 0x00);
2993 #endif
2994 //by amy
2995
2996         write_nic_byte(dev, CONFIG3, tmpu8);
2997         write_nic_byte(dev, CR9346, 0x00);
2998 //{by amy 080312 for led
2999         // enable EEM0 and EEM1 in 9346CR
3000         btCR9346 = read_nic_byte(dev, CR9346);
3001         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
3002
3003         // B cut use LED1 to control HW RF on/off
3004         TmpU1b = read_nic_byte(dev, CONFIG5);
3005         TmpU1b = TmpU1b & ~BIT3;
3006         write_nic_byte(dev,CONFIG5, TmpU1b);
3007
3008         // disable EEM0 and EEM1 in 9346CR
3009         btCR9346 &= ~(0xC0);
3010         write_nic_byte(dev, CR9346, btCR9346);
3011
3012         //Enable Led (suggested by Jong)
3013         // B-cut RF Radio on/off  5e[3]=0
3014         btPSR = read_nic_byte(dev, PSR);
3015         write_nic_byte(dev, PSR, (btPSR | BIT3));
3016 //by amy 080312 for led}
3017         // setup initial timing for RFE.
3018         write_nic_word(dev, RFPinsOutput, 0x0480);
3019         SetOutputEnableOfRfPins(dev);
3020         write_nic_word(dev, RFPinsSelect, 0x2488);
3021
3022         // PHY config.
3023         PhyConfig8185(dev);
3024
3025         // We assume RegWirelessMode has already been initialized before,
3026         // however, we has to validate the wireless mode here and provide a reasonble
3027         // initialized value if necessary. 2005.01.13, by rcnjko.
3028         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
3029         if(     (ieee->mode != WIRELESS_MODE_B) &&
3030                 (ieee->mode != WIRELESS_MODE_G) &&
3031                 (ieee->mode != WIRELESS_MODE_A) &&
3032                 (ieee->mode != WIRELESS_MODE_AUTO))
3033         { // It should be one of B, G, A, or AUTO.
3034                 bInvalidWirelessMode = 1;
3035         }
3036         else
3037         { // One of B, G, A, or AUTO.
3038                 // Check if the wireless mode is supported by RF.
3039                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
3040                         (ieee->mode & SupportedWirelessMode) == 0 )
3041                 {
3042                         bInvalidWirelessMode = 1;
3043                 }
3044         }
3045
3046         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
3047         { // Auto or other invalid value.
3048                 // Assigne a wireless mode to initialize.
3049                 if((SupportedWirelessMode & WIRELESS_MODE_A))
3050                 {
3051                         InitWirelessMode = WIRELESS_MODE_A;
3052                 }
3053                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
3054                 {
3055                         InitWirelessMode = WIRELESS_MODE_G;
3056                 }
3057                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
3058                 {
3059                         InitWirelessMode = WIRELESS_MODE_B;
3060                 }
3061                 else
3062                 {
3063                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
3064                                  SupportedWirelessMode);
3065                         InitWirelessMode = WIRELESS_MODE_B;
3066                 }
3067
3068                 // Initialize RegWirelessMode if it is not a valid one.
3069                 if(bInvalidWirelessMode)
3070                 {
3071                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
3072                 }
3073         }
3074         else
3075         { // One of B, G, A.
3076                 InitWirelessMode = ieee->mode;
3077         }
3078 //by amy for power save
3079 #ifdef ENABLE_IPS
3080 //      printk("initialize ENABLE_IPS\n");
3081         priv->eRFPowerState = eRfOff;
3082         priv->RfOffReason = 0;
3083         {
3084         //      u32 tmp2;
3085         //      u32 tmp = jiffies;
3086                 MgntActSet_RF_State(dev, eRfOn, 0);
3087         //      tmp2 = jiffies;
3088         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3089         }
3090 //      DrvIFIndicateCurrentPhyStatus(priv);
3091                 //
3092                 // If inactive power mode is enabled, disable rf while in disconnected state.
3093                 // 2007.07.16, by shien chang.
3094                 //
3095         if (priv->bInactivePs)
3096         {
3097         //      u32 tmp2;
3098         //      u32 tmp = jiffies;
3099                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
3100         //      tmp2 = jiffies;
3101         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
3102
3103         }
3104 #endif
3105 //      IPSEnter(dev);
3106 //by amy for power save
3107 #ifdef TODO
3108         // Turn off RF if necessary. 2005.08.23, by rcnjko.
3109         // We shall turn off RF after setting CMDR, otherwise,
3110         // RF will be turnned on after we enable MAC Tx/Rx.
3111         if(Adapter->MgntInfo.RegRfOff == TRUE)
3112         {
3113                 SetRFPowerState8185(Adapter, RF_OFF);
3114         }
3115         else
3116         {
3117                 SetRFPowerState8185(Adapter, RF_ON);
3118         }
3119 #endif
3120
3121 /*   //these is equal with above TODO.
3122         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
3123         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
3124         RF_WriteReg(dev, 0x4, 0x9FF);
3125         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
3126         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
3127         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
3128         write_nic_byte(dev, CR9346, 0x00);
3129 */
3130
3131         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
3132
3133         //-----------------------------------------------------------------------------
3134
3135         rtl8185b_irq_enable(dev);
3136
3137         netif_start_queue(dev);
3138
3139  }
3140
3141
3142 void rtl8185b_rx_enable(struct net_device *dev)
3143 {
3144         u8 cmd;
3145         //u32 rxconf;
3146         /* for now we accept data, management & ctl frame*/
3147         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3148 #if 0
3149         rxconf=read_nic_dword(dev,RX_CONF);
3150         rxconf = rxconf &~ MAC_FILTER_MASK;
3151         rxconf = rxconf | (1<<ACCEPT_MNG_FRAME_SHIFT);
3152         rxconf = rxconf | (1<<ACCEPT_DATA_FRAME_SHIFT);
3153         rxconf = rxconf | (1<<ACCEPT_BCAST_FRAME_SHIFT);
3154         rxconf = rxconf | (1<<ACCEPT_MCAST_FRAME_SHIFT);
3155 //      rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3156         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3157
3158         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3159            dev->flags & IFF_PROMISC){
3160                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3161         }else{
3162                 rxconf = rxconf | (1<<ACCEPT_NICMAC_FRAME_SHIFT);
3163                 if(priv->card_8185 == 0)
3164                         rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3165         }
3166
3167         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3168                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3169                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3170         }*/
3171
3172         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3173                 rxconf = rxconf | (1<<ACCEPT_CTL_FRAME_SHIFT);
3174                 rxconf = rxconf | (1<<ACCEPT_ICVERR_FRAME_SHIFT);
3175                 rxconf = rxconf | (1<<ACCEPT_PWR_FRAME_SHIFT);
3176         }
3177
3178         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3179                 rxconf = rxconf | (1<<ACCEPT_CRCERR_FRAME_SHIFT);
3180
3181         //if(!priv->card_8185){
3182                 rxconf = rxconf &~ RX_FIFO_THRESHOLD_MASK;
3183                 rxconf = rxconf | (RX_FIFO_THRESHOLD_NONE<<RX_FIFO_THRESHOLD_SHIFT);
3184         //}
3185
3186         rxconf = rxconf | (1<<RX_AUTORESETPHY_SHIFT);
3187         rxconf = rxconf &~ MAX_RX_DMA_MASK;
3188         rxconf = rxconf | (MAX_RX_DMA_2048<<MAX_RX_DMA_SHIFT);
3189
3190         //if(!priv->card_8185)
3191                 rxconf = rxconf | RCR_ONLYERLPKT;
3192
3193         rxconf = rxconf &~ RCR_CS_MASK;
3194         if(!priv->card_8185)
3195                 rxconf |= (priv->rcr_csense<<RCR_CS_SHIFT);
3196 //      rxconf &=~ 0xfff00000;
3197 //      rxconf |= 0x90100000;//9014f76f;
3198         write_nic_dword(dev, RX_CONF, rxconf);
3199 #endif
3200
3201         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
3202
3203         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
3204            dev->flags & IFF_PROMISC){
3205                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
3206                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
3207         }
3208
3209         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
3210                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
3211                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
3212         }*/
3213
3214         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
3215                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
3216         }
3217
3218         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
3219                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
3220
3221         write_nic_dword(dev, RCR, priv->ReceiveConfig);
3222
3223         fix_rx_fifo(dev);
3224
3225 #ifdef DEBUG_RX
3226         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
3227 #endif
3228         cmd=read_nic_byte(dev,CMD);
3229         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
3230
3231 }
3232
3233 void rtl8185b_tx_enable(struct net_device *dev)
3234 {
3235         u8 cmd;
3236         //u8 tx_agc_ctl;
3237         u8 byte;
3238         //u32 txconf;
3239         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
3240
3241 #if 0
3242         txconf= read_nic_dword(dev,TX_CONF);
3243         if(priv->card_8185){
3244
3245
3246                 byte = read_nic_byte(dev,CW_CONF);
3247                 byte &= ~(1<<CW_CONF_PERPACKET_CW_SHIFT);
3248                 byte &= ~(1<<CW_CONF_PERPACKET_RETRY_SHIFT);
3249                 write_nic_byte(dev, CW_CONF, byte);
3250
3251                 tx_agc_ctl = read_nic_byte(dev, TX_AGC_CTL);
3252                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_GAIN_SHIFT);
3253                 tx_agc_ctl &= ~(1<<TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT);
3254                 tx_agc_ctl |=(1<<TX_AGC_CTL_FEEDBACK_ANT);
3255                 write_nic_byte(dev, TX_AGC_CTL, tx_agc_ctl);
3256                 /*
3257                 write_nic_word(dev, 0x5e, 0x01);
3258                 force_pci_posting(dev);
3259                 mdelay(1);
3260                 write_nic_word(dev, 0xfe, 0x10);
3261                 force_pci_posting(dev);
3262                 mdelay(1);
3263                 write_nic_word(dev, 0x5e, 0x00);
3264                 force_pci_posting(dev);
3265                 mdelay(1);
3266                 */
3267                 write_nic_byte(dev, 0xec, 0x3f); /* Disable early TX */
3268         }
3269
3270         if(priv->card_8185){
3271
3272                 txconf = txconf &~ (1<<TCR_PROBE_NOTIMESTAMP_SHIFT);
3273
3274         }else{
3275
3276                 if(hwseqnum)
3277                         txconf= txconf &~ (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3278                 else
3279                         txconf= txconf | (1<<TX_CONF_HEADER_AUTOICREMENT_SHIFT);
3280         }
3281
3282         txconf = txconf &~ TX_LOOPBACK_MASK;
3283         txconf = txconf | (TX_LOOPBACK_NONE <<TX_LOOPBACK_SHIFT);
3284         txconf = txconf &~ TCR_DPRETRY_MASK;
3285         txconf = txconf &~ TCR_RTSRETRY_MASK;
3286         txconf = txconf | (priv->retry_data<<TX_DPRETRY_SHIFT);
3287         txconf = txconf | (priv->retry_rts<<TX_RTSRETRY_SHIFT);
3288         txconf = txconf &~ (1<<TX_NOCRC_SHIFT);
3289
3290         if(priv->card_8185){
3291                 if(priv->hw_plcp_len)
3292                         txconf = txconf &~ TCR_PLCP_LEN;
3293                 else
3294                         txconf = txconf | TCR_PLCP_LEN;
3295         }else{
3296                 txconf = txconf &~ TCR_SAT;
3297         }
3298         txconf = txconf &~ TCR_MXDMA_MASK;
3299         txconf = txconf | (TCR_MXDMA_2048<<TCR_MXDMA_SHIFT);
3300         txconf = txconf | TCR_CWMIN;
3301         txconf = txconf | TCR_DISCW;
3302
3303 //      if(priv->ieee80211->hw_wep)
3304 //              txconf=txconf &~ (1<<TX_NOICV_SHIFT);
3305 //      else
3306                 txconf=txconf | (1<<TX_NOICV_SHIFT);
3307
3308         write_nic_dword(dev,TX_CONF,txconf);
3309 #endif
3310
3311         write_nic_dword(dev, TCR, priv->TransmitConfig);
3312         byte = read_nic_byte(dev, MSR);
3313         byte |= MSR_LINK_ENEDCA;
3314         write_nic_byte(dev, MSR, byte);
3315
3316         fix_tx_fifo(dev);
3317
3318 #ifdef DEBUG_TX
3319         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
3320 #endif
3321
3322         cmd=read_nic_byte(dev,CMD);
3323         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
3324
3325         //write_nic_dword(dev,TX_CONF,txconf);
3326
3327
3328 /*
3329         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
3330         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
3331         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
3332         */
3333 }
3334
3335
3336 #endif