SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2   This is part of the rtl8180-sa2400 driver
   3   released under the GPL (See file COPYING for details).
   4   Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5
   6   This files contains programming code for the rtl8225
   7   radio frontend.
   8
   9   *Many* thanks to Realtek Corp. for their great support!
  10
  11 */
  12
  13 #include "r8180_hw.h"
  14 #include "r8180_rtl8225.h"
  15 #include "r8180_93cx6.h"
  16
  17 #include "ieee80211/dot11d.h"
  18
  19 #ifdef CONFIG_RTL8185B
  20
  21 extern u8 rtl8225_agc[];
  22
  23 extern u32 rtl8225_chan[];
  24
  25 //2005.11.16
  26 u8 rtl8225z2_threshold[]={
  27         0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
  28 };
  29
  30 //      0xd 0x19 0x1b 0x21
  31 u8 rtl8225z2_gain_bg[]={
  32         0x23, 0x15, 0xa5, // -82-1dbm
  33         0x23, 0x15, 0xb5, // -82-2dbm
  34         0x23, 0x15, 0xc5, // -82-3dbm
  35         0x33, 0x15, 0xc5, // -78dbm
  36         0x43, 0x15, 0xc5, // -74dbm
  37         0x53, 0x15, 0xc5, // -70dbm
  38         0x63, 0x15, 0xc5, // -66dbm
  39 };
  40
  41 u8 rtl8225z2_gain_a[]={
  42         0x13,0x27,0x5a,//,0x37,// -82dbm
  43         0x23,0x23,0x58,//,0x37,// -82dbm
  44         0x33,0x1f,0x56,//,0x37,// -82dbm
  45         0x43,0x1b,0x54,//,0x37,// -78dbm
  46         0x53,0x17,0x51,//,0x37,// -74dbm
  47         0x63,0x24,0x4f,//,0x37,// -70dbm
  48         0x73,0x0f,0x4c,//,0x37,// -66dbm
  49 };
  50 #if 0
  51 u32 rtl8225_chan[] = {
  52         0,      //dummy channel 0
  53         0x085c, //1
  54         0x08dc, //2
  55         0x095c, //3
  56         0x09dc, //4
  57         0x0a5c, //5
  58         0x0adc, //6
  59         0x0b5c, //7
  60         0x0bdc, //8
  61         0x0c5c, //9
  62         0x0cdc, //10
  63         0x0d5c, //11
  64         0x0ddc, //12
  65         0x0e5c, //13
  66         //0x0f5c, //14
  67         0x0f72, // 14
  68 };
  69 #endif
  70
  71 //-
  72 u16 rtl8225z2_rxgain[]={
  73         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
  74         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
  75         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
  76         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
  77         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
  78         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
  79         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
  80         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
  81         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
  82         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
  83         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
  84         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
  85
  86 };
  87
  88 //2005.11.16,
  89 u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[]={
  90         0x00,0x01,0x02,0x03,0x04,0x05,
  91         0x06,0x07,0x08,0x09,0x0a,0x0b,
  92         0x0c,0x0d,0x0e,0x0f,0x10,0x11,
  93         0x12,0x13,0x14,0x15,0x16,0x17,
  94         0x18,0x19,0x1a,0x1b,0x1c,0x1d,
  95         0x1e,0x1f,0x20,0x21,0x22,0x23,
  96 };
  97
  98 #if 0
  99 //-
 100 u8 rtl8225_agc[]={
 101         0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9e,0x9d,0x9c,0x9b,0x9a,0x99,0x98,0x97,0x96,
 102         0x95,0x94,0x93,0x92,0x91,0x90,0x8f,0x8e,0x8d,0x8c,0x8b,0x8a,0x89,0x88,0x87,0x86,
 103         0x85,0x84,0x83,0x82,0x81,0x80,0x3f,0x3e,0x3d,0x3c,0x3b,0x3a,0x39,0x38,0x37,0x36,
 104         0x35,0x34,0x33,0x32,0x31,0x30,0x2f,0x2e,0x2d,0x2c,0x2b,0x2a,0x29,0x28,0x27,0x26,
 105         0x25,0x24,0x23,0x22,0x21,0x20,0x1f,0x1e,0x1d,0x1c,0x1b,0x1a,0x19,0x18,0x17,0x16,
 106         0x15,0x14,0x13,0x12,0x11,0x10,0x0f,0x0e,0x0d,0x0c,0x0b,0x0a,0x09,0x08,0x07,0x06,
 107         0x05,0x04,0x03,0x02,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
 108         0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
 109 };
 110 #endif
 111 /*
 112  from 0 to 0x23
 113 u8 rtl8225_tx_gain_cck_ofdm[]={
 114         0x02,0x06,0x0e,0x1e,0x3e,0x7e
 115 };
 116 */
 117
 118 //-
 119 u8 rtl8225z2_tx_power_ofdm[]={
 120         0x42,0x00,0x40,0x00,0x40
 121 };
 122
 123
 124 //-
 125 u8 rtl8225z2_tx_power_cck_ch14[]={
 126         0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00
 127 };
 128
 129
 130 //-
 131 u8 rtl8225z2_tx_power_cck[]={
 132         0x36,0x35,0x2e,0x25,0x1c,0x12,0x09,0x04
 133 };
 134
 135
 136 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 137 {
 138         u8* rtl8225_gain;
 139         struct r8180_priv *priv = ieee80211_priv(dev);
 140
 141         u8 mode = priv->ieee80211->mode;
 142
 143         if(mode == IEEE_B || mode == IEEE_G)
 144                 rtl8225_gain = rtl8225z2_gain_bg;
 145         else
 146                 rtl8225_gain = rtl8225z2_gain_a;
 147
 148         //write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 3]);
 149         //write_phy_ofdm(dev, 0x19, rtl8225_gain[gain * 3 + 1]);
 150         //write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 2]);
 151         //2005.11.17, by ch-hsu
 152         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 153         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 154         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 155         write_phy_ofdm(dev, 0x21, 0x37);
 156
 157 }
 158
 159 #if 0
 160
 161 void rtl8225_set_gain(struct net_device *dev, short gain)
 162 {
 163         struct r8180_priv *priv = ieee80211_priv(dev);
 164
 165         rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
 166
 167         if(priv->card_8185 == 2)
 168                 write_phy_ofdm(dev, 0x21, 0x27);
 169         else
 170                 write_phy_ofdm(dev, 0x21, 0x37);
 171
 172         write_phy_ofdm(dev, 0x25, 0x20);
 173         write_phy_ofdm(dev, 0x11, 0x6);
 174
 175         if(priv->card_8185 == 1 && priv->card_8185_Bversion)
 176                 write_phy_ofdm(dev, 0x27, 0x8);
 177         else
 178                 write_phy_ofdm(dev, 0x27, 0x88);
 179
 180         write_phy_ofdm(dev, 0x14, 0);
 181         write_phy_ofdm(dev, 0x16, 0);
 182         write_phy_ofdm(dev, 0x15, 0x40);
 183         write_phy_ofdm(dev, 0x17, 0x40);
 184
 185         write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 4]);
 186         write_phy_ofdm(dev, 0x23, rtl8225_gain[gain * 4 + 1]);
 187         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 4 + 2]);
 188         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 4 + 3]);
 189         //rtl8225_set_gain_usb(dev, gain);
 190 }
 191 #endif
 192
 193 u32 read_rtl8225(struct net_device *dev, u8 adr)
 194 {
 195         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 196         u32 dataRead;
 197         u32 mask;
 198         u16 oval,oval2,oval3,tmp;
 199 //      ThreeWireReg twreg;
 200 //      ThreeWireReg tdata;
 201         int i;
 202         short bit, rw;
 203
 204         u8 wLength = 6;
 205         u8 rLength = 12;
 206         u8 low2high = 0;
 207
 208         oval = read_nic_word(dev, RFPinsOutput);
 209         oval2 = read_nic_word(dev, RFPinsEnable);
 210         oval3 = read_nic_word(dev, RFPinsSelect);
 211
 212         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 213         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 214
 215         dataRead = 0;
 216
 217         oval &= ~0xf;
 218
 219         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
 220
 221         write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
 222
 223         rw = 0;
 224
 225         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 226         for(i = 0; i < wLength/2; i++)
 227         {
 228                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 229                 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
 230
 231                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 232                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 233
 234                 mask = (low2high) ? (mask<<1): (mask>>1);
 235
 236                 if(i == 2)
 237                 {
 238                         rw = BB_HOST_BANG_RW;
 239                         write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 240                         write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
 241                         break;
 242                 }
 243
 244                 bit = ((data2Write&mask) != 0) ? 1: 0;
 245
 246                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 247                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 248
 249                 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
 250
 251                 mask = (low2high) ? (mask<<1) : (mask>>1);
 252         }
 253
 254         //twreg.struc.clk = 0;
 255         //twreg.struc.data = 0;
 256         write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
 257         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 258
 259         // We must set data pin to HW controled, otherwise RF can't driver it and
 260         // value RF register won't be able to read back properly. 2006.06.13, by rcnjko.
 261         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 262
 263         for(i = 0; i < rLength; i++)
 264         {
 265                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 266
 267                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 268                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 269                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 270                 tmp = read_nic_word(dev, RFPinsInput);
 271
 272                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 273
 274                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 275
 276                 mask = (low2high) ? (mask<<1) : (mask>>1);
 277         }
 278
 279         write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
 280
 281         write_nic_word(dev, RFPinsEnable, oval2);
 282         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 283         write_nic_word(dev, RFPinsOutput, 0x3a0);
 284
 285         return dataRead;
 286
 287 }
 288 #if 0
 289 void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
 290 {
 291         int i;
 292         u16 out,select;
 293         u8 bit;
 294         u32 bangdata = (data << 4) | (adr & 0xf);
 295         struct r8180_priv *priv = ieee80211_priv(dev);
 296
 297         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
 298
 299         write_nic_word(dev,RFPinsEnable,
 300                 (read_nic_word(dev,RFPinsEnable) | 0x7));
 301
 302         select = read_nic_word(dev, RFPinsSelect);
 303
 304         write_nic_word(dev, RFPinsSelect, select | 0x7 |
 305                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
 306
 307         force_pci_posting(dev);
 308         udelay(10);
 309
 310         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN );//| 0x1fff);
 311
 312         force_pci_posting(dev);
 313         udelay(2);
 314
 315         write_nic_word(dev, RFPinsOutput, out);
 316
 317         force_pci_posting(dev);
 318         udelay(10);
 319
 320
 321         for(i=15; i>=0;i--){
 322
 323                 bit = (bangdata & (1<<i)) >> i;
 324
 325                 write_nic_word(dev, RFPinsOutput, bit | out);
 326
 327                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
 328                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
 329
 330                 i--;
 331                 bit = (bangdata & (1<<i)) >> i;
 332
 333                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
 334                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
 335
 336                 write_nic_word(dev, RFPinsOutput, bit | out);
 337
 338         }
 339
 340         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
 341
 342         force_pci_posting(dev);
 343         udelay(10);
 344
 345         write_nic_word(dev, RFPinsOutput, out |
 346                 ((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
 347
 348         write_nic_word(dev, RFPinsSelect, select |
 349                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
 350
 351         if(priv->card_type == USB)
 352                 mdelay(2);
 353         else
 354                 rtl8185_rf_pins_enable(dev);
 355 }
 356
 357 #endif
 358 short rtl8225_is_V_z2(struct net_device *dev)
 359 {
 360         short vz2 = 1;
 361         //int i;
 362         /* sw to reg pg 1 */
 363         //write_rtl8225(dev, 0, 0x1b7);
 364         //write_rtl8225(dev, 0, 0x0b7);
 365
 366         /* reg 8 pg 1 = 23*/
 367         //printk(KERN_WARNING "RF Rigisters:\n");
 368 #if 0
 369         for(i = 0; i <= 0xf; i++)
 370                 printk(KERN_WARNING "%08x,", read_rtl8225(dev, i));
 371         //printk(KERN_WARNING "reg[9]@pg1 = 0x%x\n", read_rtl8225(dev, 0x0F));
 372
 373 //      printk(KERN_WARNING "RF:\n");
 374 #endif
 375         if( read_rtl8225(dev, 8) != 0x588)
 376                 vz2 = 0;
 377
 378         else    /* reg 9 pg 1 = 24 */
 379                 if( read_rtl8225(dev, 9) != 0x700)
 380                         vz2 = 0;
 381
 382         /* sw back to pg 0 */
 383         write_rtl8225(dev, 0, 0xb7);
 384
 385         return vz2;
 386
 387 }
 388
 389 #if 0
 390 void rtl8225_rf_close(struct net_device *dev)
 391 {
 392         write_rtl8225(dev, 0x4, 0x1f);
 393
 394         force_pci_posting(dev);
 395         mdelay(1);
 396
 397         rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_OFF);
 398         rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_OFF);
 399 }
 400 #endif
 401 #if 0
 402 short rtl8225_rf_set_sens(struct net_device *dev, short sens)
 403 {
 404         if (sens <0 || sens > 6) return -1;
 405
 406         if(sens > 4)
 407                 write_rtl8225(dev, 0x0c, 0x850);
 408         else
 409                 write_rtl8225(dev, 0x0c, 0x50);
 410
 411         sens= 6-sens;
 412         rtl8225_set_gain(dev, sens);
 413
 414         write_phy_cck(dev, 0x41, rtl8225_threshold[sens]);
 415         return 0;
 416
 417 }
 418 #endif
 419
 420
 421 void rtl8225z2_rf_close(struct net_device *dev)
 422 {
 423         RF_WriteReg(dev, 0x4, 0x1f);
 424
 425         force_pci_posting(dev);
 426         mdelay(1);
 427
 428         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 429         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 430 }
 431
 432 //
 433 //      Description:
 434 //              Map dBm into Tx power index according to
 435 //              current HW model, for example, RF and PA, and
 436 //              current wireless mode.
 437 //
 438 s8
 439 DbmToTxPwrIdx(
 440         struct r8180_priv *priv,
 441         WIRELESS_MODE   WirelessMode,
 442         s32                     PowerInDbm
 443         )
 444 {
 445         bool bUseDefault = true;
 446         s8 TxPwrIdx = 0;
 447
 448 #ifdef CONFIG_RTL818X_S
 449         //
 450         // 071011, SD3 SY:
 451         // OFDM Power in dBm = Index * 0.5 + 0
 452         // CCK Power in dBm = Index * 0.25 + 13
 453         //
 454         if(priv->card_8185 >= VERSION_8187S_B)
 455         {
 456                 s32 tmp = 0;
 457
 458                 if(WirelessMode == WIRELESS_MODE_G)
 459                 {
 460                         bUseDefault = false;
 461                         tmp = (2 * PowerInDbm);
 462
 463                         if(tmp < 0)
 464                                 TxPwrIdx = 0;
 465                         else if(tmp > 40) // 40 means 20 dBm.
 466                                 TxPwrIdx = 40;
 467                         else
 468                                 TxPwrIdx = (s8)tmp;
 469                 }
 470                 else if(WirelessMode == WIRELESS_MODE_B)
 471                 {
 472                         bUseDefault = false;
 473                         tmp = (4 * PowerInDbm) - 52;
 474
 475                         if(tmp < 0)
 476                                 TxPwrIdx = 0;
 477                         else if(tmp > 28) // 28 means 20 dBm.
 478                                 TxPwrIdx = 28;
 479                         else
 480                                 TxPwrIdx = (s8)tmp;
 481                 }
 482         }
 483 #endif
 484
 485         //
 486         // TRUE if we want to use a default implementation.
 487         // We shall set it to FALSE when we have exact translation formular
 488         // for target IC. 070622, by rcnjko.
 489         //
 490         if(bUseDefault)
 491         {
 492                 if(PowerInDbm < 0)
 493                         TxPwrIdx = 0;
 494                 else if(PowerInDbm > 35)
 495                         TxPwrIdx = 35;
 496                 else
 497                         TxPwrIdx = (u8)PowerInDbm;
 498         }
 499
 500         return TxPwrIdx;
 501 }
 502
 503 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 504 {
 505         struct r8180_priv *priv = ieee80211_priv(dev);
 506
 507 //      int GainIdx;
 508 //      int GainSetting;
 509         //int i;
 510         //u8 power;
 511         //u8 *cck_power_table;
 512         u8 max_cck_power_level;
 513         //u8 min_cck_power_level;
 514         u8 max_ofdm_power_level;
 515         u8 min_ofdm_power_level;
 516 //      u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312
 517 //      u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312
 518         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312
 519         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312
 520 #if 0
 521         //
 522         // CCX 2 S31, AP control of client transmit power:
 523         // 1. We shall not exceed Cell Power Limit as possible as we can.
 524         // 2. Tolerance is +/- 5dB.
 525         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
 526         //
 527         // TODO:
 528         // 1. 802.11h power contraint
 529         //
 530         // 071011, by rcnjko.
 531         //
 532         if(     priv->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
 533                 priv->bWithCcxCellPwr &&
 534                 ch == priv->dot11CurrentChannelNumber)
 535         {
 536                 u8 CckCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
 537                 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(dev, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
 538
 539                 printk("CCX Cell Limit: %d dBm => CCK Tx power index : %d, OFDM Tx power index: %d\n",
 540                         priv->CcxCellPwr, CckCellPwrIdx, OfdmCellPwrIdx);
 541                 printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
 542                         channel, CckTxPwrIdx, OfdmTxPwrIdx);
 543
 544                 if(cck_power_level > CckCellPwrIdx)
 545                         cck_power_level = CckCellPwrIdx;
 546                 if(ofdm_power_level > OfdmCellPwrIdx)
 547                         ofdm_power_level = OfdmCellPwrIdx;
 548
 549                 printk("Altered CCK Tx power index : %d, OFDM Tx power index: %d\n",
 550                         CckTxPwrIdx, OfdmTxPwrIdx);
 551         }
 552 #endif
 553         if(IS_DOT11D_ENABLE(priv->ieee80211) &&
 554                 IS_DOT11D_STATE_DONE(priv->ieee80211) )
 555         {
 556                 //PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211);
 557                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 558                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
 559                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
 560
 561                 //printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx);
 562
 563                 //printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
 564                 //      ch, cck_power_level, ofdm_power_level);
 565
 566                 if(cck_power_level > CckMaxPwrIdx)
 567                         cck_power_level = CckMaxPwrIdx;
 568                 if(ofdm_power_level > OfdmMaxPwrIdx)
 569                         ofdm_power_level = OfdmMaxPwrIdx;
 570         }
 571
 572         //priv->CurrentCckTxPwrIdx = cck_power_level;
 573         //priv->CurrentOfdmTxPwrIdx = ofdm_power_level;
 574
 575         max_cck_power_level = 15;
 576         max_ofdm_power_level = 25; //  12 -> 25
 577         min_ofdm_power_level = 10;
 578
 579 #ifdef CONFIG_RTL8185B
 580 #ifdef CONFIG_RTL818X_S
 581
 582         if(cck_power_level > 35)
 583         {
 584                 cck_power_level = 35;
 585         }
 586         //
 587         // Set up CCK TXAGC. suggested by SD3 SY.
 588         //
 589        write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) );
 590        //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
 591        force_pci_posting(dev);
 592         mdelay(1);
 593 #else
 594
 595         /* CCK power setting */
 596         if(cck_power_level > max_cck_power_level)
 597                 cck_power_level = max_cck_power_level;
 598
 599         cck_power_level += priv->cck_txpwr_base;
 600
 601         if(cck_power_level > 35)
 602                 cck_power_level = 35;
 603
 604         if(ch == 14)
 605                 cck_power_table = rtl8225z2_tx_power_cck_ch14;
 606         else
 607                 cck_power_table = rtl8225z2_tx_power_cck;
 608
 609
 610         for(i=0;i<8;i++){
 611
 612                 power = cck_power_table[i];
 613                 write_phy_cck(dev, 0x44 + i, power);
 614         }
 615
 616         //write_nic_byte(dev, TX_GAIN_CCK, power);
 617         //2005.11.17,
 618         write_nic_byte(dev, CCK_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]);
 619
 620         force_pci_posting(dev);
 621         mdelay(1);
 622 #endif
 623 #endif
 624         /* OFDM power setting */
 625 //  Old:
 626 //      if(ofdm_power_level > max_ofdm_power_level)
 627 //              ofdm_power_level = 35;
 628 //      ofdm_power_level += min_ofdm_power_level;
 629 //  Latest:
 630 /*      if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
 631                 ofdm_power_level = max_ofdm_power_level;
 632         else
 633                 ofdm_power_level += min_ofdm_power_level;
 634
 635         ofdm_power_level += priv->ofdm_txpwr_base;
 636 */
 637         if(ofdm_power_level > 35)
 638                 ofdm_power_level = 35;
 639
 640 //      rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
 641
 642         //rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON);
 643
 644         if (priv->up == 0) {
 645                 //must add these for rtl8185B down, xiong-2006-11-21
 646                 write_phy_ofdm(dev,2,0x42);
 647                 write_phy_ofdm(dev,5,0);
 648                 write_phy_ofdm(dev,6,0x40);
 649                 write_phy_ofdm(dev,7,0);
 650                 write_phy_ofdm(dev,8,0x40);
 651         }
 652
 653         //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
 654         //2005.11.17,
 655 #ifdef CONFIG_RTL818X_S
 656         write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
 657 #else
 658         write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]*2);
 659 #endif
 660         if(ofdm_power_level<=11)
 661         {
 662 //            write_nic_dword(dev,PHY_ADR,0x00005c87);
 663 //            write_nic_dword(dev,PHY_ADR,0x00005c89);
 664                 write_phy_ofdm(dev,0x07,0x5c);
 665                 write_phy_ofdm(dev,0x09,0x5c);
 666         }
 667         if(ofdm_power_level<=17)
 668         {
 669 //             write_nic_dword(dev,PHY_ADR,0x00005487);
 670 //             write_nic_dword(dev,PHY_ADR,0x00005489);
 671                 write_phy_ofdm(dev,0x07,0x54);
 672                 write_phy_ofdm(dev,0x09,0x54);
 673         }
 674         else
 675         {
 676 //             write_nic_dword(dev,PHY_ADR,0x00005087);
 677 //             write_nic_dword(dev,PHY_ADR,0x00005089);
 678                 write_phy_ofdm(dev,0x07,0x50);
 679                 write_phy_ofdm(dev,0x09,0x50);
 680         }
 681         force_pci_posting(dev);
 682         mdelay(1);
 683
 684 }
 685 #if 0
 686 /* switch between mode B and G */
 687 void rtl8225_set_mode(struct net_device *dev, short modeb)
 688 {
 689         write_phy_ofdm(dev, 0x15, (modeb ? 0x0 : 0x40));
 690         write_phy_ofdm(dev, 0x17, (modeb ? 0x0 : 0x40));
 691 }
 692 #endif
 693
 694 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 695 {
 696 /*
 697         short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
 698                 ieee80211_is_54g(priv->ieee80211->current_network)) ||
 699                 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
 700 */
 701         rtl8225z2_SetTXPowerLevel(dev, ch);
 702
 703         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 704
 705         //YJ,add,080828, if set channel failed, write again
 706         if((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 707         {
 708                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 709         }
 710
 711         mdelay(1);
 712
 713         force_pci_posting(dev);
 714         mdelay(10);
 715 //deleted by David : 2006/8/9
 716 #if 0
 717         write_nic_byte(dev,SIFS,0x22);// SIFS: 0x22
 718
 719         if(gset)
 720                 write_nic_byte(dev,DIFS,20); //DIFS: 20
 721         else
 722                 write_nic_byte(dev,DIFS,0x24); //DIFS: 36
 723
 724         if(priv->ieee80211->state == IEEE80211_LINKED &&
 725                 ieee80211_is_shortslot(priv->ieee80211->current_network))
 726                 write_nic_byte(dev,SLOT,0x9); //SLOT: 9
 727
 728         else
 729                 write_nic_byte(dev,SLOT,0x14); //SLOT: 20 (0x14)
 730
 731
 732         if(gset){
 733                 write_nic_byte(dev,EIFS,91 - 20); // EIFS: 91 (0x5B)
 734                 write_nic_byte(dev,CW_VAL,0x73); //CW VALUE: 0x37
 735                 //DMESG("using G net params");
 736         }else{
 737                 write_nic_byte(dev,EIFS,91 - 0x24); // EIFS: 91 (0x5B)
 738                 write_nic_byte(dev,CW_VAL,0xa5); //CW VALUE: 0x37
 739                 //DMESG("using B net params");
 740         }
 741 #endif
 742
 743 }
 744 #if 0
 745 void rtl8225_host_pci_init(struct net_device *dev)
 746 {
 747         write_nic_word(dev, RFPinsOutput, 0x480);
 748
 749         rtl8185_rf_pins_enable(dev);
 750
 751         //if(priv->card_8185 == 2 && priv->enable_gpio0 ) /* version D */
 752         //write_nic_word(dev, RFPinsSelect, 0x88);
 753         //else
 754         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO); /* 0x488 | SW_CONTROL_GPIO */
 755
 756         write_nic_byte(dev, GP_ENABLE, 0);
 757
 758         force_pci_posting(dev);
 759         mdelay(200);
 760
 761         write_nic_word(dev, GP_ENABLE, 0xff & (~(1<<6))); /* bit 6 is for RF on/off detection */
 762
 763
 764 }
 765
 766 void rtl8225_host_usb_init(struct net_device *dev)
 767 {
 768         write_nic_byte(dev,RFPinsSelect+1,0);
 769
 770         write_nic_byte(dev,GPIO,0);
 771
 772         write_nic_byte_E(dev,0x53,read_nic_byte_E(dev,0x53) | (1<<7));
 773
 774         write_nic_byte(dev,RFPinsSelect+1,4);
 775
 776         write_nic_byte(dev,GPIO,0x20);
 777
 778         write_nic_byte(dev,GP_ENABLE,0);
 779
 780
 781         /* Config BB & RF */
 782         write_nic_word(dev, RFPinsOutput, 0x80);
 783
 784         write_nic_word(dev, RFPinsSelect, 0x80);
 785
 786         write_nic_word(dev, RFPinsEnable, 0x80);
 787
 788
 789         mdelay(100);
 790
 791         mdelay(1000);
 792
 793 }
 794 #endif
 795 void rtl8225z2_rf_init(struct net_device *dev)
 796 {
 797         struct r8180_priv *priv = ieee80211_priv(dev);
 798         int i;
 799         short channel = 1;
 800         u16     brsr;
 801         u32     data,addr;
 802
 803         priv->chan = channel;
 804
 805 //      rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
 806
 807
 808         if(priv->card_type == USB)
 809                 rtl8225_host_usb_init(dev);
 810         else
 811                 rtl8225_host_pci_init(dev);
 812
 813         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 814
 815         brsr = read_nic_word(dev, BRSR);
 816
 817         write_nic_word(dev, BRSR, 0xffff);
 818
 819
 820         write_nic_dword(dev, RF_PARA, 0x100044);
 821
 822         #if 1  //0->1
 823         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 824         write_nic_byte(dev, CONFIG3, 0x44);
 825         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 826         #endif
 827
 828
 829         rtl8185_rf_pins_enable(dev);
 830
 831 //              mdelay(1000);
 832
 833         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 834
 835
 836         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 837
 838         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 839
 840         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 841
 842
 843         write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
 844
 845
 846
 847         write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
 848 //      }
 849
 850         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 851
 852         write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel]));  mdelay(1);
 853
 854         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 855
 856         write_rtl8225(dev, 0x9, 0x335);  mdelay(1);
 857
 858         write_rtl8225(dev, 0xa, 0x9d4);  mdelay(1);
 859
 860         write_rtl8225(dev, 0xb, 0x7bb);  mdelay(1);
 861
 862         write_rtl8225(dev, 0xc, 0x850);  mdelay(1);
 863
 864
 865         write_rtl8225(dev, 0xd, 0xcdf);   mdelay(1);
 866
 867         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 868
 869         write_rtl8225(dev, 0xf, 0x114);
 870
 871
 872         mdelay(100);
 873
 874
 875         //if(priv->card_type != USB) /* maybe not needed even for 8185 */
 876 //      write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
 877
 878         write_rtl8225(dev, 0x0, 0x1b7);
 879
 880         for(i=0;i<95;i++){
 881                 write_rtl8225(dev, 0x1, (u8)(i+1));
 882
 883                 #if 0
 884                 if(priv->phy_ver == 1)
 885                         /* version A */
 886                         write_rtl8225(dev, 0x2, rtl8225a_rxgain[i]);
 887                 else
 888                 #endif
 889                 /* version B & C & D*/
 890
 891                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 892         }
 893         write_rtl8225(dev, 0x3, 0x80);
 894         write_rtl8225(dev, 0x5, 0x4);
 895
 896         write_rtl8225(dev, 0x0, 0xb7);
 897
 898         write_rtl8225(dev, 0x2, 0xc4d);
 899
 900         if(priv->card_type == USB){
 901         //      force_pci_posting(dev);
 902                 mdelay(200);
 903
 904                 write_rtl8225(dev, 0x2, 0x44d);
 905
 906         //      force_pci_posting(dev);
 907                 mdelay(100);
 908
 909         }//End of if(priv->card_type == USB)
 910         /* FIXME!! rtl8187 we have to check if calibrarion
 911          * is successful and eventually cal. again (repeat
 912          * the two write on reg 2)
 913         */
 914         // Check for calibration status, 2005.11.17,
 915         data = read_rtl8225(dev, 6);
 916         if (!(data&0x00000080))
 917         {
 918                 write_rtl8225(dev, 0x02, 0x0c4d);
 919                 force_pci_posting(dev); mdelay(200);
 920                 write_rtl8225(dev, 0x02, 0x044d);
 921                 force_pci_posting(dev); mdelay(100);
 922                 data = read_rtl8225(dev, 6);
 923                 if (!(data&0x00000080))
 924                         {
 925                                 DMESGW("RF Calibration Failed!!!!\n");
 926                         }
 927         }
 928         //force_pci_posting(dev);
 929
 930         mdelay(200); //200 for 8187
 931
 932
 933 //      //if(priv->card_type != USB){
 934 //              write_rtl8225(dev, 0x2, 0x44d);
 935 //              write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
 936 //              write_rtl8225(dev, 0x2, 0x47d);
 937 //
 938 //              force_pci_posting(dev);
 939 //              mdelay(100);
 940 //
 941 //              write_rtl8225(dev, 0x2, 0x44d);
 942 //      //}
 943
 944         write_rtl8225(dev, 0x0, 0x2bf);
 945
 946         if(priv->card_type != USB)
 947                 rtl8185_rf_pins_enable(dev);
 948         //set up ZEBRA AGC table, 2005.11.17,
 949         for(i=0;i<128;i++){
 950                 data = rtl8225_agc[i];
 951
 952                 addr = i + 0x80; //enable writing AGC table
 953                 write_phy_ofdm(dev, 0xb, data);
 954
 955                 mdelay(1);
 956                 write_phy_ofdm(dev, 0xa, addr);
 957
 958                 mdelay(1);
 959         }
 960 #if 0
 961         for(i=0;i<128;i++){
 962                 write_phy_ofdm(dev, 0xb, rtl8225_agc[i]);
 963
 964                 mdelay(1);
 965                 write_phy_ofdm(dev, 0xa, (u8)i+ 0x80);
 966
 967                 mdelay(1);
 968         }
 969 #endif
 970
 971         force_pci_posting(dev);
 972         mdelay(1);
 973
 974         write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
 975         write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
 976         write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
 977         write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
 978         write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
 979         write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
 980         write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
 981         write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
 982         write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
 983         write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
 984
 985         write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
 986
 987         //write_phy_ofdm(dev, 0x18, 0xef);
 988         //      }
 989         //}
 990         write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
 991
 992         write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
 993
 994
 995         //if(priv->card_type != USB)
 996         write_phy_ofdm(dev, 0xd, 0x43);
 997
 998         write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
 999
1000
1001         #if 0
1002         if(priv->card_8185 == 1){
1003                 if(priv->card_8185_Bversion)
1004                         write_phy_ofdm(dev, 0xf, 0x20);/*ver B*/
1005                 else
1006                         write_phy_ofdm(dev, 0xf, 0x28);/*ver C*/
1007         }else{
1008         #endif
1009         write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
1010 /*ver D & 8187*/
1011 //      }
1012
1013 //      if(priv->card_8185 == 1 && priv->card_8185_Bversion)
1014 //              write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
1015 //      else
1016         write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
1017 /*ver C & D & 8187*/
1018
1019         write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
1020 /*agc resp time 700*/
1021
1022
1023 //      if(priv->card_8185 == 2){
1024         /* Ver D & 8187*/
1025         write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
1026
1027         write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
1028
1029 #if 0
1030         }else{
1031                 /* Ver B & C*/
1032                 write_phy_ofdm(dev, 0x12, 0x0);
1033                 write_phy_ofdm(dev, 0x13, 0x0);
1034         }
1035 #endif
1036         write_phy_ofdm(dev, 0x14, 0x0); mdelay(1);
1037         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
1038         write_phy_ofdm(dev, 0x16, 0x0); mdelay(1);
1039         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
1040
1041 //      if (priv->card_type == USB)
1042 //              write_phy_ofdm(dev, 0x18, 0xef);
1043
1044         write_phy_ofdm(dev, 0x18, 0xef);mdelay(1);
1045
1046
1047         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
1048         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
1049         write_phy_ofdm(dev, 0x1b, 0x15);mdelay(1);
1050
1051         write_phy_ofdm(dev, 0x1c, 0x4);mdelay(1);
1052
1053         write_phy_ofdm(dev, 0x1d, 0xc5);mdelay(1); //2005.11.17,
1054
1055         write_phy_ofdm(dev, 0x1e, 0x95);mdelay(1);
1056
1057         write_phy_ofdm(dev, 0x1f, 0x75);        mdelay(1);
1058
1059 //      }
1060
1061         write_phy_ofdm(dev, 0x20, 0x1f);mdelay(1);
1062
1063         write_phy_ofdm(dev, 0x21, 0x17);mdelay(1);
1064
1065         write_phy_ofdm(dev, 0x22, 0x16);mdelay(1);
1066
1067 //      if(priv->card_type != USB)
1068         write_phy_ofdm(dev, 0x23, 0x80);mdelay(1); //FIXME maybe not needed // <>
1069
1070         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
1071         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
1072         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
1073
1074         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
1075
1076
1077         // <> Set init. gain to m74dBm.
1078
1079         rtl8225z2_set_gain(dev,4);
1080
1081         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
1082         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
1083         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
1084         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
1085         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
1086
1087         write_phy_cck(dev, 0x7, 0x78);mdelay(1);
1088  /* Ver C & D & 8187*/
1089
1090         write_phy_cck(dev, 0x8, 0x2e);mdelay(1);
1091
1092         write_phy_cck(dev, 0x10, ((priv->card_type == USB) ? 0x9b: 0x93)); mdelay(1);
1093         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
1094         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
1095 #if 0
1096         if(priv->card_8185 == 1 && priv->card_8185_Bversion)
1097                 write_phy_cck(dev, 0x13, 0x98); /* Ver B */
1098         else
1099 #endif
1100         write_phy_cck(dev, 0x13, 0xd0); /* Ver C & D & 8187*/
1101
1102         write_phy_cck(dev, 0x19, 0x0);
1103         write_phy_cck(dev, 0x1a, 0xa0);
1104         write_phy_cck(dev, 0x1b, 0x8);
1105         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
1106
1107         write_phy_cck(dev, 0x41, 0x8d);mdelay(1);
1108
1109
1110         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
1111         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
1112
1113
1114         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
1115         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
1116         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
1117         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
1118         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
1119         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
1120         write_phy_cck(dev, 0x4a, 0x9); mdelay(1);
1121         write_phy_cck(dev, 0x4b, 0x4); mdelay(1);
1122         write_phy_cck(dev, 0x4c, 0x5);mdelay(1);
1123
1124
1125         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
1126
1127
1128
1129 // <>
1130 //      // TESTR 0xb 8187
1131 //      write_phy_cck(dev, 0x10, 0x93);// & 0xfb);
1132 //
1133 //      //if(priv->card_type != USB){
1134 //              write_phy_ofdm(dev, 0x2, 0x62);
1135 //              write_phy_ofdm(dev, 0x6, 0x0);
1136 //              write_phy_ofdm(dev, 0x8, 0x0);
1137 //      //}
1138
1139         rtl8225z2_SetTXPowerLevel(dev, channel);
1140 #ifdef CONFIG_RTL818X_S
1141         write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
1142 #else
1143         write_phy_cck(dev, 0x10, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
1144 #endif
1145         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* Rx ant A, 0x10 for B */
1146
1147         rtl8185_tx_antenna(dev, 0x3); /* TX ant A, 0x0 for B */
1148
1149         /* switch to high-speed 3-wire
1150          * last digit. 2 for both cck and ofdm
1151          */
1152         if(priv->card_type == USB)
1153                 write_nic_dword(dev, 0x94, 0x3dc00002);
1154         else{
1155                 write_nic_dword(dev, 0x94, 0x15c00002);
1156                 rtl8185_rf_pins_enable(dev);
1157         }
1158
1159 //      if(priv->card_type != USB)
1160 //      rtl8225_set_gain(dev, 4); /* FIXME this '1' is random */ // <>
1161 //       rtl8225_set_mode(dev, 1); /* FIXME start in B mode */ // <>
1162 //
1163 //      /* make sure is waken up! */
1164 //      write_rtl8225(dev,0x4, 0x9ff);
1165 //      rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1166 //      rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1167
1168         rtl8225_rf_set_chan(dev, priv->chan);
1169
1170         //write_nic_word(dev,BRSR,brsr);
1171
1172         //rtl8225z2_rf_set_mode(dev);
1173 }
1174
1175 void rtl8225z2_rf_set_mode(struct net_device *dev)
1176 {
1177         struct r8180_priv *priv = ieee80211_priv(dev);
1178
1179         if(priv->ieee80211->mode == IEEE_A)
1180         {
1181                 write_rtl8225(dev, 0x5, 0x1865);
1182                 write_nic_dword(dev, RF_PARA, 0x10084);
1183                 write_nic_dword(dev, RF_TIMING, 0xa8008);
1184                 write_phy_ofdm(dev, 0x0, 0x0);
1185                 write_phy_ofdm(dev, 0xa, 0x6);
1186                 write_phy_ofdm(dev, 0xb, 0x99);
1187                 write_phy_ofdm(dev, 0xf, 0x20);
1188                 write_phy_ofdm(dev, 0x11, 0x7);
1189
1190                 rtl8225z2_set_gain(dev,4);
1191
1192                 write_phy_ofdm(dev,0x15, 0x40);
1193                 write_phy_ofdm(dev,0x17, 0x40);
1194
1195                 write_nic_dword(dev, 0x94,0x10000000);
1196         }else{
1197
1198                 write_rtl8225(dev, 0x5, 0x1864);
1199                 write_nic_dword(dev, RF_PARA, 0x10044);
1200                 write_nic_dword(dev, RF_TIMING, 0xa8008);
1201                 write_phy_ofdm(dev, 0x0, 0x1);
1202                 write_phy_ofdm(dev, 0xa, 0x6);
1203                 write_phy_ofdm(dev, 0xb, 0x99);
1204                 write_phy_ofdm(dev, 0xf, 0x20);
1205                 write_phy_ofdm(dev, 0x11, 0x7);
1206
1207                 rtl8225z2_set_gain(dev,4);
1208
1209                 write_phy_ofdm(dev,0x15, 0x40);
1210                 write_phy_ofdm(dev,0x17, 0x40);
1211
1212                 write_nic_dword(dev, 0x94,0x04000002);
1213         }
1214 }
1215
1216 //lzm mod 080826
1217 //#define MAX_DOZE_WAITING_TIMES_85B 64
1218 //#define MAX_POLLING_24F_TIMES_87SE    5
1219 #define MAX_DOZE_WAITING_TIMES_85B              20
1220 #define MAX_POLLING_24F_TIMES_87SE                      10
1221 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
1222
1223 bool
1224 SetZebraRFPowerState8185(
1225         struct net_device *dev,
1226         RT_RF_POWER_STATE       eRFPowerState
1227         )
1228 {
1229         struct r8180_priv *priv = ieee80211_priv(dev);
1230         u8                      btCR9346, btConfig3;
1231         bool bActionAllowed= true, bTurnOffBB = true;//lzm mod 080826
1232         //u32                   DWordContent;
1233         u8                      u1bTmp;
1234         int                     i;
1235         //u16                   u2bTFPC = 0;
1236         bool            bResult = true;
1237         u8                      QueueID;
1238
1239         if(priv->SetRFPowerStateInProgress == true)
1240                 return false;
1241
1242         priv->SetRFPowerStateInProgress = true;
1243
1244         // enable EEM0 and EEM1 in 9346CR
1245         btCR9346 = read_nic_byte(dev, CR9346);
1246         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
1247         // enable PARM_En in Config3
1248         btConfig3 = read_nic_byte(dev, CONFIG3);
1249         write_nic_byte(dev, CONFIG3, (btConfig3|CONFIG3_PARM_En) );
1250
1251         switch( priv->rf_chip )
1252         {
1253         case RF_ZEBRA2:
1254                 switch( eRFPowerState )
1255                 {
1256                 case eRfOn:
1257                         RF_WriteReg(dev,0x4,0x9FF);
1258
1259                         write_nic_dword(dev, ANAPARAM, ANAPARM_ON);
1260                         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON);
1261
1262                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
1263
1264                         //Follow 87B, Isaiah 2007-04-27
1265                         u1bTmp = read_nic_byte(dev, 0x24E);
1266                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );// 070124 SD1 Alex: turn on CCK and OFDM.
1267                         break;
1268
1269                 case eRfSleep:
1270                         break;
1271
1272                 case eRfOff:
1273                         break;
1274
1275                 default:
1276                         bResult = false;
1277                         break;
1278                 }
1279                 break;
1280
1281         case RF_ZEBRA4:
1282                 switch( eRFPowerState )
1283                 {
1284                 case eRfOn:
1285                         //printk("===================================power on@jiffies:%d\n",jiffies);
1286                         write_nic_word(dev, 0x37C, 0x00EC);
1287
1288                         //turn on AFE
1289                         write_nic_byte(dev, 0x54, 0x00);
1290                         write_nic_byte(dev, 0x62, 0x00);
1291
1292                         //lzm mod 080826
1293                         //turn on RF
1294                         //RF_WriteReg(dev, 0x0, 0x009f); //mdelay(1);
1295                         //RF_WriteReg(dev, 0x4, 0x0972); //mdelay(1);
1296                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1297                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1298                         //turn on RF again, suggested by SD3 stevenl.
1299                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1300                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1301
1302                         //turn on BB
1303 //                      write_nic_dword(dev, PhyAddr, 0x4090); //ofdm 10=00
1304 //                      write_nic_dword(dev, PhyAddr, 0x4092); //ofdm 12=00
1305                         write_phy_ofdm(dev,0x10,0x40);
1306                         write_phy_ofdm(dev,0x12,0x40);
1307                         //Avoid power down at init time.
1308                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
1309
1310                         u1bTmp = read_nic_byte(dev, 0x24E);
1311                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );
1312
1313                         break;
1314
1315                 case eRfSleep:
1316                         // Make sure BusyQueue is empty befor turn off RFE pwoer.
1317                         //printk("===================================power sleep@jiffies:%d\n",jiffies);
1318
1319                         for(QueueID = 0, i = 0; QueueID < 6; )
1320                         {
1321                                 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1322                                 {
1323                                         QueueID++;
1324                                         continue;
1325                                 }
1326 #if 0           //reserved amy
1327                                 else if(priv->NdisAdapter.CurrentPowerState != NdisDeviceStateD0)
1328                                 {
1329                                         RT_TRACE(COMP_POWER, DBG_LOUD, ("eRfSleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", (pMgntInfo->TxPollingTimes+1), QueueID));
1330                                         break;
1331                                 }
1332 #endif
1333                                 else//lzm mod 080826
1334                                 {
1335                                         priv->TxPollingTimes ++;
1336                                         if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1337                                                 {
1338                                                         //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B():eRfSleep:  %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", LPS_MAX_SLEEP_WAITING_TIMES_87SE, QueueID));
1339                                                         bActionAllowed=false;
1340                                                         break;
1341                                                 }
1342                                                 else
1343                                                 {
1344                                                         udelay(10);  // Windows may delay 3~16ms actually.
1345                                                         //RT_TRACE(COMP_POWER, DBG_LOUD, ("eRfSleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (pMgntInfo->TxPollingTimes), QueueID));
1346                                                 }
1347                                 }
1348
1349                                 //lzm del 080826
1350                                 //if(i >= MAX_DOZE_WAITING_TIMES_85B)
1351                                 //{
1352                                         //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1353                                         //break;
1354                                 //}
1355                         }
1356
1357                         if(bActionAllowed)//lzm add 080826
1358                         {
1359                                 //turn off BB RXIQ matrix to cut off rx signal
1360 //                              write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1361 //                              write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1362                                 write_phy_ofdm(dev,0x10,0x00);
1363                                 write_phy_ofdm(dev,0x12,0x00);
1364                                 //turn off RF
1365                                 RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1366                                 RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1367                                 //turn off AFE except PLL
1368                                 write_nic_byte(dev, 0x62, 0xff);
1369                                 write_nic_byte(dev, 0x54, 0xec);
1370 //                              mdelay(10);
1371
1372 #if 1
1373                                 mdelay(1);
1374                                 {
1375                                         int i = 0;
1376                                         while (true)
1377                                         {
1378                                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
1379                                                 if ((tmp24F == 0x01) || (tmp24F == 0x09))
1380                                                 {
1381                                                         bTurnOffBB = true;
1382                                                         break;
1383                                                 }
1384                                                 else//lzm mod 080826
1385                                                 {
1386                                                         udelay(10);
1387                                                         i++;
1388                                                         priv->TxPollingTimes++;
1389
1390                                                         if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1391                                                         {
1392                                                                 //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times Rx Mac0x24F=0x%x !!!\n\n\n", i, u1bTmp24F));
1393                                                                 bTurnOffBB=false;
1394                                                                 break;
1395                                                         }
1396                                                         else
1397                                                         {
1398                                                                 udelay(10);// Windows may delay 3~16ms actually.
1399                                                                 //RT_TRACE(COMP_POWER, DBG_LOUD,("(%d)eRfSleep- u1bTmp24F= 0x%X\n", i, u1bTmp24F));
1400
1401                                                         }
1402                                                 }
1403
1404                                                 //lzm del 080826
1405                                                 //if (i > MAX_POLLING_24F_TIMES_87SE)
1406                                                 //      break;
1407                                         }
1408                                 }
1409 #endif
1410                                 if (bTurnOffBB)//lzm mod 080826
1411                                 {
1412                                 //turn off BB
1413                                 u1bTmp = read_nic_byte(dev, 0x24E);
1414                                 write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1415
1416                                 //turn off AFE PLL
1417                                 //write_nic_byte(dev, 0x54, 0xec);
1418                                 //write_nic_word(dev, 0x37C, 0x00ec);
1419                                 write_nic_byte(dev, 0x54, 0xFC);  //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1420                                 write_nic_word(dev, 0x37C, 0x00FC);//[ECS] FC-> EC->FC, asked by SD3 Stevenl
1421                                 }
1422                         }
1423                         break;
1424
1425                 case eRfOff:
1426                         // Make sure BusyQueue is empty befor turn off RFE pwoer.
1427                         //printk("===================================power off@jiffies:%d\n",jiffies);
1428                         for(QueueID = 0, i = 0; QueueID < 6; )
1429                         {
1430                                 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1431                                 {
1432                                         QueueID++;
1433                                         continue;
1434                                 }
1435 #if 0
1436                                 else if(Adapter->NdisAdapter.CurrentPowerState != NdisDeviceStateD0)
1437                                 {
1438                                         RT_TRACE(COMP_POWER, DBG_LOUD, ("%d times TcbBusyQueue[%d] !=0 but lower power state!\n", (i+1), QueueID));
1439                                         break;
1440                                 }
1441 #endif
1442                                 else
1443                                 {
1444                                         udelay(10);
1445                                         i++;
1446                                 }
1447
1448                                 if(i >= MAX_DOZE_WAITING_TIMES_85B)
1449                                 {
1450                                         //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1451                                         break;
1452                                 }
1453                         }
1454
1455                         //turn off BB RXIQ matrix to cut off rx signal
1456 //                      write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1457 //                      write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1458                         write_phy_ofdm(dev,0x10,0x00);
1459                         write_phy_ofdm(dev,0x12,0x00);
1460                         //turn off RF
1461                         RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1462                         RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1463                         //turn off AFE except PLL
1464                         write_nic_byte(dev, 0x62, 0xff);
1465                         write_nic_byte(dev, 0x54, 0xec);
1466 //                      mdelay(10);
1467 #if 1
1468                         mdelay(1);
1469                         {
1470                                 int i = 0;
1471                                 while (true)
1472                                 {
1473                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
1474                                         if ((tmp24F == 0x01) || (tmp24F == 0x09))
1475                                         {
1476                                                 bTurnOffBB = true;
1477                                                 break;
1478                                         }
1479                                         else
1480                                         {
1481                                                 bTurnOffBB = false;
1482                                                 udelay(10);
1483                                                 i++;
1484                                         }
1485                                         if (i > MAX_POLLING_24F_TIMES_87SE)
1486                                                 break;
1487                                 }
1488                         }
1489 #endif
1490                         if (bTurnOffBB)//lzm mod 080826
1491                         {
1492
1493                         //turn off BB
1494                         u1bTmp = read_nic_byte(dev, 0x24E);
1495                         write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1496                         //turn off AFE PLL (80M)
1497                         //write_nic_byte(dev, 0x54, 0xec);
1498                         //write_nic_word(dev, 0x37C, 0x00ec);
1499                         write_nic_byte(dev, 0x54, 0xFC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1500                         write_nic_word(dev, 0x37C, 0x00FC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1501                         }
1502
1503                         break;
1504
1505                 default:
1506                         bResult = false;
1507                         printk("SetZebraRFPowerState8185(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1508                         break;
1509                 }
1510                 break;
1511         }
1512
1513         // disable PARM_En in Config3
1514         btConfig3 &= ~(CONFIG3_PARM_En);
1515         write_nic_byte(dev, CONFIG3, btConfig3);
1516         // disable EEM0 and EEM1 in 9346CR
1517         btCR9346 &= ~(0xC0);
1518         write_nic_byte(dev, CR9346, btCR9346);
1519
1520         if(bResult && bActionAllowed)//lzm mod 080826
1521         {
1522                 // Update current RF state variable.
1523                 priv->eRFPowerState = eRFPowerState;
1524 #if 0
1525                 switch(priv->eRFPowerState)
1526                 {
1527                 case eRfOff:
1528                         //
1529                         //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
1530                         //
1531                         if(priv->RfOffReason==RF_CHANGE_BY_IPS )
1532                         {
1533                                 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK);
1534                         }
1535                         else
1536                         {
1537                                 // Turn off LED if RF is not ON.
1538                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1539                         }
1540                         break;
1541
1542                 case eRfOn:
1543                         // Turn on RF we are still linked, which might happen when
1544                         // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
1545                         if( pMgntInfo->bMediaConnect == TRUE )
1546                         {
1547                                 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1548                         }
1549                         break;
1550
1551                 default:
1552                         // do nothing.
1553                         break;
1554                 }
1555 #endif
1556
1557         }
1558
1559         priv->SetRFPowerStateInProgress = false;
1560
1561         return (bResult && bActionAllowed) ;
1562 }
1563 void rtl8225z4_rf_sleep(struct net_device *dev)
1564 {
1565         //
1566         // Turn off RF power.
1567         //
1568         //printk("=========>%s()\n", __func__);
1569         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1570         //mdelay(2);    //FIXME
1571 }
1572 void rtl8225z4_rf_wakeup(struct net_device *dev)
1573 {
1574         //
1575         // Turn on RF power.
1576         //
1577         //printk("=========>%s()\n", __func__);
1578         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1579 }
1580 #endif
1581