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   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /*
  29  *
  30  * Helper functions to abstract board specific data about
  31  * network ports from the rest of the cvmx-helper files.
  32  */
  33
  34 #include <asm/octeon/octeon.h>
  35 #include <asm/octeon/cvmx-bootinfo.h>
  36
  37 #include "cvmx-config.h"
  38
  39 #include "cvmx-mdio.h"
  40
  41 #include "cvmx-helper.h"
  42 #include "cvmx-helper-util.h"
  43 #include "cvmx-helper-board.h"
  44
  45 #include "cvmx-gmxx-defs.h"
  46 #include "cvmx-asxx-defs.h"
  47
  48 /**
  49  * cvmx_override_board_link_get(int ipd_port) is a function
  50  * pointer. It is meant to allow customization of the process of
  51  * talking to a PHY to determine link speed. It is called every
  52  * time a PHY must be polled for link status. Users should set
  53  * this pointer to a function before calling any cvmx-helper
  54  * operations.
  55  */
  56 cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
  57     NULL;
  58
  59 /**
  60  * Return the MII PHY address associated with the given IPD
  61  * port. A result of -1 means there isn't a MII capable PHY
  62  * connected to this port. On chips supporting multiple MII
  63  * busses the bus number is encoded in bits <15:8>.
  64  *
  65  * This function must be modified for every new Octeon board.
  66  * Internally it uses switch statements based on the cvmx_sysinfo
  67  * data to determine board types and revisions. It replies on the
  68  * fact that every Octeon board receives a unique board type
  69  * enumeration from the bootloader.
  70  *
  71  * @ipd_port: Octeon IPD port to get the MII address for.
  72  *
  73  * Returns MII PHY address and bus number or -1.
  74  */
  75 int cvmx_helper_board_get_mii_address(int ipd_port)
  76 {
  77         switch (cvmx_sysinfo_get()->board_type) {
  78         case CVMX_BOARD_TYPE_SIM:
  79                 /* Simulator doesn't have MII */
  80                 return -1;
  81         case CVMX_BOARD_TYPE_EBT3000:
  82         case CVMX_BOARD_TYPE_EBT5800:
  83         case CVMX_BOARD_TYPE_THUNDER:
  84         case CVMX_BOARD_TYPE_NICPRO2:
  85                 /* Interface 0 is SPI4, interface 1 is RGMII */
  86                 if ((ipd_port >= 16) && (ipd_port < 20))
  87                         return ipd_port - 16;
  88                 else
  89                         return -1;
  90         case CVMX_BOARD_TYPE_KODAMA:
  91         case CVMX_BOARD_TYPE_EBH3100:
  92         case CVMX_BOARD_TYPE_HIKARI:
  93         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
  94         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
  95         case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
  96                 /*
  97                  * Port 0 is WAN connected to a PHY, Port 1 is GMII
  98                  * connected to a switch
  99                  */
 100                 if (ipd_port == 0)
 101                         return 4;
 102                 else if (ipd_port == 1)
 103                         return 9;
 104                 else
 105                         return -1;
 106         case CVMX_BOARD_TYPE_NAC38:
 107                 /* Board has 8 RGMII ports PHYs are 0-7 */
 108                 if ((ipd_port >= 0) && (ipd_port < 4))
 109                         return ipd_port;
 110                 else if ((ipd_port >= 16) && (ipd_port < 20))
 111                         return ipd_port - 16 + 4;
 112                 else
 113                         return -1;
 114         case CVMX_BOARD_TYPE_EBH3000:
 115                 /* Board has dual SPI4 and no PHYs */
 116                 return -1;
 117         case CVMX_BOARD_TYPE_EBH5200:
 118         case CVMX_BOARD_TYPE_EBH5201:
 119         case CVMX_BOARD_TYPE_EBT5200:
 120                 /*
 121                  * Board has 4 SGMII ports. The PHYs start right after the MII
 122                  * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
 123                  */
 124                 if ((ipd_port >= 0) && (ipd_port < 4))
 125                         return ipd_port + 2;
 126                 else
 127                         return -1;
 128         case CVMX_BOARD_TYPE_EBH5600:
 129         case CVMX_BOARD_TYPE_EBH5601:
 130         case CVMX_BOARD_TYPE_EBH5610:
 131                 /*
 132                  * Board has 8 SGMII ports. 4 connect out, two connect
 133                  * to a switch, and 2 loop to each other
 134                  */
 135                 if ((ipd_port >= 0) && (ipd_port < 4))
 136                         return ipd_port + 1;
 137                 else
 138                         return -1;
 139         case CVMX_BOARD_TYPE_CUST_NB5:
 140                 if (ipd_port == 2)
 141                         return 4;
 142                 else
 143                         return -1;
 144         case CVMX_BOARD_TYPE_NIC_XLE_4G:
 145                 /* Board has 4 SGMII ports. connected QLM3(interface 1) */
 146                 if ((ipd_port >= 16) && (ipd_port < 20))
 147                         return ipd_port - 16 + 1;
 148                 else
 149                         return -1;
 150         case CVMX_BOARD_TYPE_BBGW_REF:
 151                 /*
 152                  * No PHYs are connected to Octeon, everything is
 153                  * through switch.
 154                  */
 155                 return -1;
 156         }
 157
 158         /* Some unknown board. Somebody forgot to update this function... */
 159         cvmx_dprintf
 160             ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
 161              cvmx_sysinfo_get()->board_type);
 162         return -1;
 163 }
 164
 165 /**
 166  * This function is the board specific method of determining an
 167  * ethernet ports link speed. Most Octeon boards have Marvell PHYs
 168  * and are handled by the fall through case. This function must be
 169  * updated for boards that don't have the normal Marvell PHYs.
 170  *
 171  * This function must be modified for every new Octeon board.
 172  * Internally it uses switch statements based on the cvmx_sysinfo
 173  * data to determine board types and revisions. It relies on the
 174  * fact that every Octeon board receives a unique board type
 175  * enumeration from the bootloader.
 176  *
 177  * @ipd_port: IPD input port associated with the port we want to get link
 178  *                 status for.
 179  *
 180  * Returns The ports link status. If the link isn't fully resolved, this must
 181  *         return zero.
 182  */
 183 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 184 {
 185         cvmx_helper_link_info_t result;
 186         int phy_addr;
 187         int is_broadcom_phy = 0;
 188
 189         /* Give the user a chance to override the processing of this function */
 190         if (cvmx_override_board_link_get)
 191                 return cvmx_override_board_link_get(ipd_port);
 192
 193         /* Unless we fix it later, all links are defaulted to down */
 194         result.u64 = 0;
 195
 196         /*
 197          * This switch statement should handle all ports that either don't use
 198          * Marvell PHYS, or don't support in-band status.
 199          */
 200         switch (cvmx_sysinfo_get()->board_type) {
 201         case CVMX_BOARD_TYPE_SIM:
 202                 /* The simulator gives you a simulated 1Gbps full duplex link */
 203                 result.s.link_up = 1;
 204                 result.s.full_duplex = 1;
 205                 result.s.speed = 1000;
 206                 return result;
 207         case CVMX_BOARD_TYPE_EBH3100:
 208         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
 209         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
 210         case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
 211                 /* Port 1 on these boards is always Gigabit */
 212                 if (ipd_port == 1) {
 213                         result.s.link_up = 1;
 214                         result.s.full_duplex = 1;
 215                         result.s.speed = 1000;
 216                         return result;
 217                 }
 218                 /* Fall through to the generic code below */
 219                 break;
 220         case CVMX_BOARD_TYPE_CUST_NB5:
 221                 /* Port 1 on these boards is always Gigabit */
 222                 if (ipd_port == 1) {
 223                         result.s.link_up = 1;
 224                         result.s.full_duplex = 1;
 225                         result.s.speed = 1000;
 226                         return result;
 227                 } else          /* The other port uses a broadcom PHY */
 228                         is_broadcom_phy = 1;
 229                 break;
 230         case CVMX_BOARD_TYPE_BBGW_REF:
 231                 /* Port 1 on these boards is always Gigabit */
 232                 if (ipd_port == 2) {
 233                         /* Port 2 is not hooked up */
 234                         result.u64 = 0;
 235                         return result;
 236                 } else {
 237                         /* Ports 0 and 1 connect to the switch */
 238                         result.s.link_up = 1;
 239                         result.s.full_duplex = 1;
 240                         result.s.speed = 1000;
 241                         return result;
 242                 }
 243                 break;
 244         }
 245
 246         phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
 247         if (phy_addr != -1) {
 248                 if (is_broadcom_phy) {
 249                         /*
 250                          * Below we are going to read SMI/MDIO
 251                          * register 0x19 which works on Broadcom
 252                          * parts
 253                          */
 254                         int phy_status =
 255                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 256                                            0x19);
 257                         switch ((phy_status >> 8) & 0x7) {
 258                         case 0:
 259                                 result.u64 = 0;
 260                                 break;
 261                         case 1:
 262                                 result.s.link_up = 1;
 263                                 result.s.full_duplex = 0;
 264                                 result.s.speed = 10;
 265                                 break;
 266                         case 2:
 267                                 result.s.link_up = 1;
 268                                 result.s.full_duplex = 1;
 269                                 result.s.speed = 10;
 270                                 break;
 271                         case 3:
 272                                 result.s.link_up = 1;
 273                                 result.s.full_duplex = 0;
 274                                 result.s.speed = 100;
 275                                 break;
 276                         case 4:
 277                                 result.s.link_up = 1;
 278                                 result.s.full_duplex = 1;
 279                                 result.s.speed = 100;
 280                                 break;
 281                         case 5:
 282                                 result.s.link_up = 1;
 283                                 result.s.full_duplex = 1;
 284                                 result.s.speed = 100;
 285                                 break;
 286                         case 6:
 287                                 result.s.link_up = 1;
 288                                 result.s.full_duplex = 0;
 289                                 result.s.speed = 1000;
 290                                 break;
 291                         case 7:
 292                                 result.s.link_up = 1;
 293                                 result.s.full_duplex = 1;
 294                                 result.s.speed = 1000;
 295                                 break;
 296                         }
 297                 } else {
 298                         /*
 299                          * This code assumes we are using a Marvell
 300                          * Gigabit PHY. All the speed information can
 301                          * be read from register 17 in one
 302                          * go. Somebody using a different PHY will
 303                          * need to handle it above in the board
 304                          * specific area.
 305                          */
 306                         int phy_status =
 307                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
 308
 309                         /*
 310                          * If the resolve bit 11 isn't set, see if
 311                          * autoneg is turned off (bit 12, reg 0). The
 312                          * resolve bit doesn't get set properly when
 313                          * autoneg is off, so force it.
 314                          */
 315                         if ((phy_status & (1 << 11)) == 0) {
 316                                 int auto_status =
 317                                     cvmx_mdio_read(phy_addr >> 8,
 318                                                    phy_addr & 0xff, 0);
 319                                 if ((auto_status & (1 << 12)) == 0)
 320                                         phy_status |= 1 << 11;
 321                         }
 322
 323                         /*
 324                          * Only return a link if the PHY has finished
 325                          * auto negotiation and set the resolved bit
 326                          * (bit 11)
 327                          */
 328                         if (phy_status & (1 << 11)) {
 329                                 result.s.link_up = 1;
 330                                 result.s.full_duplex = ((phy_status >> 13) & 1);
 331                                 switch ((phy_status >> 14) & 3) {
 332                                 case 0: /* 10 Mbps */
 333                                         result.s.speed = 10;
 334                                         break;
 335                                 case 1: /* 100 Mbps */
 336                                         result.s.speed = 100;
 337                                         break;
 338                                 case 2: /* 1 Gbps */
 339                                         result.s.speed = 1000;
 340                                         break;
 341                                 case 3: /* Illegal */
 342                                         result.u64 = 0;
 343                                         break;
 344                                 }
 345                         }
 346                 }
 347         } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
 348                    || OCTEON_IS_MODEL(OCTEON_CN58XX)
 349                    || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
 350                 /*
 351                  * We don't have a PHY address, so attempt to use
 352                  * in-band status. It is really important that boards
 353                  * not supporting in-band status never get
 354                  * here. Reading broken in-band status tends to do bad
 355                  * things
 356                  */
 357                 union cvmx_gmxx_rxx_rx_inbnd inband_status;
 358                 int interface = cvmx_helper_get_interface_num(ipd_port);
 359                 int index = cvmx_helper_get_interface_index_num(ipd_port);
 360                 inband_status.u64 =
 361                     cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
 362
 363                 result.s.link_up = inband_status.s.status;
 364                 result.s.full_duplex = inband_status.s.duplex;
 365                 switch (inband_status.s.speed) {
 366                 case 0: /* 10 Mbps */
 367                         result.s.speed = 10;
 368                         break;
 369                 case 1: /* 100 Mbps */
 370                         result.s.speed = 100;
 371                         break;
 372                 case 2: /* 1 Gbps */
 373                         result.s.speed = 1000;
 374                         break;
 375                 case 3: /* Illegal */
 376                         result.u64 = 0;
 377                         break;
 378                 }
 379         } else {
 380                 /*
 381                  * We don't have a PHY address and we don't have
 382                  * in-band status. There is no way to determine the
 383                  * link speed. Return down assuming this port isn't
 384                  * wired
 385                  */
 386                 result.u64 = 0;
 387         }
 388
 389         /* If link is down, return all fields as zero. */
 390         if (!result.s.link_up)
 391                 result.u64 = 0;
 392
 393         return result;
 394 }
 395
 396 /**
 397  * This function as a board specific method of changing the PHY
 398  * speed, duplex, and auto-negotiation. This programs the PHY and
 399  * not Octeon. This can be used to force Octeon's links to
 400  * specific settings.
 401  *
 402  * @phy_addr:  The address of the PHY to program
 403  * @enable_autoneg:
 404  *                  Non zero if you want to enable auto-negotiation.
 405  * @link_info: Link speed to program. If the speed is zero and auto-negotiation
 406  *                  is enabled, all possible negotiation speeds are advertised.
 407  *
 408  * Returns Zero on success, negative on failure
 409  */
 410 int cvmx_helper_board_link_set_phy(int phy_addr,
 411                                    cvmx_helper_board_set_phy_link_flags_types_t
 412                                    link_flags,
 413                                    cvmx_helper_link_info_t link_info)
 414 {
 415
 416         /* Set the flow control settings based on link_flags */
 417         if ((link_flags & set_phy_link_flags_flow_control_mask) !=
 418             set_phy_link_flags_flow_control_dont_touch) {
 419                 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
 420                 reg_autoneg_adver.u16 =
 421                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 422                                    CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
 423                 reg_autoneg_adver.s.asymmetric_pause =
 424                     (link_flags & set_phy_link_flags_flow_control_mask) ==
 425                     set_phy_link_flags_flow_control_enable;
 426                 reg_autoneg_adver.s.pause =
 427                     (link_flags & set_phy_link_flags_flow_control_mask) ==
 428                     set_phy_link_flags_flow_control_enable;
 429                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 430                                 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
 431                                 reg_autoneg_adver.u16);
 432         }
 433
 434         /* If speed isn't set and autoneg is on advertise all supported modes */
 435         if ((link_flags & set_phy_link_flags_autoneg)
 436             && (link_info.s.speed == 0)) {
 437                 cvmx_mdio_phy_reg_control_t reg_control;
 438                 cvmx_mdio_phy_reg_status_t reg_status;
 439                 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
 440                 cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
 441                 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 442
 443                 reg_status.u16 =
 444                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 445                                    CVMX_MDIO_PHY_REG_STATUS);
 446                 reg_autoneg_adver.u16 =
 447                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 448                                    CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
 449                 reg_autoneg_adver.s.advert_100base_t4 =
 450                     reg_status.s.capable_100base_t4;
 451                 reg_autoneg_adver.s.advert_10base_tx_full =
 452                     reg_status.s.capable_10_full;
 453                 reg_autoneg_adver.s.advert_10base_tx_half =
 454                     reg_status.s.capable_10_half;
 455                 reg_autoneg_adver.s.advert_100base_tx_full =
 456                     reg_status.s.capable_100base_x_full;
 457                 reg_autoneg_adver.s.advert_100base_tx_half =
 458                     reg_status.s.capable_100base_x_half;
 459                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 460                                 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
 461                                 reg_autoneg_adver.u16);
 462                 if (reg_status.s.capable_extended_status) {
 463                         reg_extended_status.u16 =
 464                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 465                                            CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
 466                         reg_control_1000.u16 =
 467                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 468                                            CVMX_MDIO_PHY_REG_CONTROL_1000);
 469                         reg_control_1000.s.advert_1000base_t_full =
 470                             reg_extended_status.s.capable_1000base_t_full;
 471                         reg_control_1000.s.advert_1000base_t_half =
 472                             reg_extended_status.s.capable_1000base_t_half;
 473                         cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 474                                         CVMX_MDIO_PHY_REG_CONTROL_1000,
 475                                         reg_control_1000.u16);
 476                 }
 477                 reg_control.u16 =
 478                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 479                                    CVMX_MDIO_PHY_REG_CONTROL);
 480                 reg_control.s.autoneg_enable = 1;
 481                 reg_control.s.restart_autoneg = 1;
 482                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 483                                 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
 484         } else if ((link_flags & set_phy_link_flags_autoneg)) {
 485                 cvmx_mdio_phy_reg_control_t reg_control;
 486                 cvmx_mdio_phy_reg_status_t reg_status;
 487                 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
 488                 cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
 489                 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
 490
 491                 reg_status.u16 =
 492                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 493                                    CVMX_MDIO_PHY_REG_STATUS);
 494                 reg_autoneg_adver.u16 =
 495                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 496                                    CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
 497                 reg_autoneg_adver.s.advert_100base_t4 = 0;
 498                 reg_autoneg_adver.s.advert_10base_tx_full = 0;
 499                 reg_autoneg_adver.s.advert_10base_tx_half = 0;
 500                 reg_autoneg_adver.s.advert_100base_tx_full = 0;
 501                 reg_autoneg_adver.s.advert_100base_tx_half = 0;
 502                 if (reg_status.s.capable_extended_status) {
 503                         reg_extended_status.u16 =
 504                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 505                                            CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
 506                         reg_control_1000.u16 =
 507                             cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 508                                            CVMX_MDIO_PHY_REG_CONTROL_1000);
 509                         reg_control_1000.s.advert_1000base_t_full = 0;
 510                         reg_control_1000.s.advert_1000base_t_half = 0;
 511                 }
 512                 switch (link_info.s.speed) {
 513                 case 10:
 514                         reg_autoneg_adver.s.advert_10base_tx_full =
 515                             link_info.s.full_duplex;
 516                         reg_autoneg_adver.s.advert_10base_tx_half =
 517                             !link_info.s.full_duplex;
 518                         break;
 519                 case 100:
 520                         reg_autoneg_adver.s.advert_100base_tx_full =
 521                             link_info.s.full_duplex;
 522                         reg_autoneg_adver.s.advert_100base_tx_half =
 523                             !link_info.s.full_duplex;
 524                         break;
 525                 case 1000:
 526                         reg_control_1000.s.advert_1000base_t_full =
 527                             link_info.s.full_duplex;
 528                         reg_control_1000.s.advert_1000base_t_half =
 529                             !link_info.s.full_duplex;
 530                         break;
 531                 }
 532                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 533                                 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
 534                                 reg_autoneg_adver.u16);
 535                 if (reg_status.s.capable_extended_status)
 536                         cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 537                                         CVMX_MDIO_PHY_REG_CONTROL_1000,
 538                                         reg_control_1000.u16);
 539                 reg_control.u16 =
 540                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 541                                    CVMX_MDIO_PHY_REG_CONTROL);
 542                 reg_control.s.autoneg_enable = 1;
 543                 reg_control.s.restart_autoneg = 1;
 544                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 545                                 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
 546         } else {
 547                 cvmx_mdio_phy_reg_control_t reg_control;
 548                 reg_control.u16 =
 549                     cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
 550                                    CVMX_MDIO_PHY_REG_CONTROL);
 551                 reg_control.s.autoneg_enable = 0;
 552                 reg_control.s.restart_autoneg = 1;
 553                 reg_control.s.duplex = link_info.s.full_duplex;
 554                 if (link_info.s.speed == 1000) {
 555                         reg_control.s.speed_msb = 1;
 556                         reg_control.s.speed_lsb = 0;
 557                 } else if (link_info.s.speed == 100) {
 558                         reg_control.s.speed_msb = 0;
 559                         reg_control.s.speed_lsb = 1;
 560                 } else if (link_info.s.speed == 10) {
 561                         reg_control.s.speed_msb = 0;
 562                         reg_control.s.speed_lsb = 0;
 563                 }
 564                 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
 565                                 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
 566         }
 567         return 0;
 568 }
 569
 570 /**
 571  * This function is called by cvmx_helper_interface_probe() after it
 572  * determines the number of ports Octeon can support on a specific
 573  * interface. This function is the per board location to override
 574  * this value. It is called with the number of ports Octeon might
 575  * support and should return the number of actual ports on the
 576  * board.
 577  *
 578  * This function must be modifed for every new Octeon board.
 579  * Internally it uses switch statements based on the cvmx_sysinfo
 580  * data to determine board types and revisions. It relys on the
 581  * fact that every Octeon board receives a unique board type
 582  * enumeration from the bootloader.
 583  *
 584  * @interface: Interface to probe
 585  * @supported_ports:
 586  *                  Number of ports Octeon supports.
 587  *
 588  * Returns Number of ports the actual board supports. Many times this will
 589  *         simple be "support_ports".
 590  */
 591 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
 592 {
 593         switch (cvmx_sysinfo_get()->board_type) {
 594         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
 595                 if (interface == 0)
 596                         return 2;
 597                 break;
 598         case CVMX_BOARD_TYPE_BBGW_REF:
 599                 if (interface == 0)
 600                         return 2;
 601                 break;
 602         case CVMX_BOARD_TYPE_NIC_XLE_4G:
 603                 if (interface == 0)
 604                         return 0;
 605                 break;
 606                 /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
 607                    which we don't support. Disable ports connected to it */
 608         case CVMX_BOARD_TYPE_EBH5600:
 609                 if (interface == 1)
 610                         return 0;
 611                 break;
 612         }
 613         return supported_ports;
 614 }
 615
 616 /**
 617  * Enable packet input/output from the hardware. This function is
 618  * called after by cvmx_helper_packet_hardware_enable() to
 619  * perform board specific initialization. For most boards
 620  * nothing is needed.
 621  *
 622  * @interface: Interface to enable
 623  *
 624  * Returns Zero on success, negative on failure
 625  */
 626 int __cvmx_helper_board_hardware_enable(int interface)
 627 {
 628         if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
 629                 if (interface == 0) {
 630                         /* Different config for switch port */
 631                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
 632                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
 633                         /*
 634                          * Boards with gigabit WAN ports need a
 635                          * different setting that is compatible with
 636                          * 100 Mbit settings
 637                          */
 638                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
 639                                        0xc);
 640                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
 641                                        0xc);
 642                 }
 643         } else if (cvmx_sysinfo_get()->board_type ==
 644                    CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
 645                 /*
 646                  * Broadcom PHYs require differnet ASX
 647                  * clocks. Unfortunately many boards don't define a
 648                  * new board Id and simply mangle the
 649                  * CN3010_EVB_HS5
 650                  */
 651                 if (interface == 0) {
 652                         /*
 653                          * Some boards use a hacked up bootloader that
 654                          * identifies them as CN3010_EVB_HS5
 655                          * evaluation boards.  This leads to all kinds
 656                          * of configuration problems.  Detect one
 657                          * case, and print warning, while trying to do
 658                          * the right thing.
 659                          */
 660                         int phy_addr = cvmx_helper_board_get_mii_address(0);
 661                         if (phy_addr != -1) {
 662                                 int phy_identifier =
 663                                     cvmx_mdio_read(phy_addr >> 8,
 664                                                    phy_addr & 0xff, 0x2);
 665                                 /* Is it a Broadcom PHY? */
 666                                 if (phy_identifier == 0x0143) {
 667                                         cvmx_dprintf("\n");
 668                                         cvmx_dprintf("ERROR:\n");
 669                                         cvmx_dprintf
 670                                             ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
 671                                         cvmx_dprintf
 672                                             ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
 673                                         cvmx_dprintf
 674                                             ("ERROR: All boards require a unique board type to identify them.\n");
 675                                         cvmx_dprintf("ERROR:\n");
 676                                         cvmx_dprintf("\n");
 677                                         cvmx_wait(1000000000);
 678                                         cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX
 679                                                        (0, interface), 5);
 680                                         cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX
 681                                                        (0, interface), 5);
 682                                 }
 683                         }
 684                 }
 685         }
 686         return 0;
 687 }
 688
 689 cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
 690 {
 691         switch (cvmx_sysinfo_get()->board_type) {
 692         case CVMX_BOARD_TYPE_BBGW_REF:
 693                 return USB_CLOCK_TYPE_CRYSTAL_12;
 694         }
 695         return USB_CLOCK_TYPE_REF_48;
 696 }
 697
 698 int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
 699 {
 700         switch (cvmx_sysinfo_get()->board_type) {
 701         case CVMX_BOARD_TYPE_NIC_XLE_4G:
 702                 return 0;
 703         }
 704
 705         return supported_ports;
 706 }