3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_address_map.h - Contains the register mapping for the ET1310
13 *------------------------------------------------------------------------------
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58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
92 * Interrupt status reg at address 0x0018
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
115 * Same masks as above
119 * Software reset reg at address 0x0028
125 * 5: mac_stat_sw_reset
131 * SLV Timer reg at address 0x002C (low 24 bits)
135 * MSI Configuration reg at address 0x0030
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
142 * Loopback reg located at address 0x0034
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
152 struct global_regs { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
171 /* START OF TXDMA REGISTER ADDRESS MAP */
174 * txdma control status reg at address 0x1000
177 #define ET_TXDMA_CSR_HALT 0x00000001
178 #define ET_TXDMA_DROP_TLP 0x00000002
179 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_CACHE_SHIFT 4
181 #define ET_TXDMA_SNGL_EPKT 0x00000100
182 #define ET_TXDMA_CLASS 0x00001E00
185 * structure for txdma packet ring base address hi reg in txdma address map
186 * located at address 0x1004
187 * Defined earlier (u32)
191 * structure for txdma packet ring base address low reg in txdma address map
192 * located at address 0x1008
193 * Defined earlier (u32)
197 * structure for txdma packet ring number of descriptor reg in txdma address
198 * map. Located at address 0x100C
204 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
205 #define ET_DMA12_WRAP 0x1000
206 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x0400
208 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x0010
211 #define INDEX12(x) ((x) & ET_DMA12_MASK)
212 #define INDEX10(x) ((x) & ET_DMA10_MASK)
213 #define INDEX4(x) ((x) & ET_DMA4_MASK)
215 extern inline void add_10bit(u32 *v, int n)
217 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
220 extern inline void add_12bit(u32 *v, int n)
222 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
226 * 10bit DMA with wrap
227 * txdma tx queue write address reg in txdma address map at 0x1010
228 * txdma tx queue write address external reg in txdma address map at 0x1014
229 * txdma tx queue read address reg in txdma address map at 0x1018
232 * txdma status writeback address hi reg in txdma address map at0x101C
233 * txdma status writeback address lo reg in txdma address map at 0x1020
235 * 10bit DMA with wrap
236 * txdma service request reg in txdma address map at 0x1024
237 * structure for txdma service complete reg in txdma address map at 0x1028
240 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
241 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
243 * txdma error reg in txdma address map at address 0x1034
253 * Tx DMA Module of JAGCore Address Mapping
254 * Located at address 0x1000
256 struct txdma_regs { /* Location: */
257 u32 csr; /* 0x1000 */
258 u32 pr_base_hi; /* 0x1004 */
259 u32 pr_base_lo; /* 0x1008 */
260 u32 pr_num_des; /* 0x100C */
261 u32 txq_wr_addr; /* 0x1010 */
262 u32 txq_wr_addr_ext; /* 0x1014 */
263 u32 txq_rd_addr; /* 0x1018 */
264 u32 dma_wb_base_hi; /* 0x101C */
265 u32 dma_wb_base_lo; /* 0x1020 */
266 u32 service_request; /* 0x1024 */
267 u32 service_complete; /* 0x1028 */
268 u32 cache_rd_index; /* 0x102C */
269 u32 cache_wr_index; /* 0x1030 */
270 u32 TxDmaError; /* 0x1034 */
271 u32 DescAbortCount; /* 0x1038 */
272 u32 PayloadAbortCnt; /* 0x103c */
273 u32 WriteBackAbortCnt; /* 0x1040 */
274 u32 DescTimeoutCnt; /* 0x1044 */
275 u32 PayloadTimeoutCnt; /* 0x1048 */
276 u32 WriteBackTimeoutCnt; /* 0x104c */
277 u32 DescErrorCount; /* 0x1050 */
278 u32 PayloadErrorCnt; /* 0x1054 */
279 u32 WriteBackErrorCnt; /* 0x1058 */
280 u32 DroppedTLPCount; /* 0x105c */
281 u32 NewServiceComplete; /* 0x1060 */
282 u32 EthernetPacketCount; /* 0x1064 */
285 /* END OF TXDMA REGISTER ADDRESS MAP */
288 /* START OF RXDMA REGISTER ADDRESS MAP */
291 * structure for control status reg in rxdma address map
292 * Located at address 0x2000
306 * 15: pkt_drop_disable
314 * structure for dma writeback lo reg in rxdma address map
315 * located at address 0x2004
316 * Defined earlier (u32)
320 * structure for dma writeback hi reg in rxdma address map
321 * located at address 0x2008
322 * Defined earlier (u32)
326 * structure for number of packets done reg in rxdma address map
327 * located at address 0x200C
334 * structure for max packet time reg in rxdma address map
335 * located at address 0x2010
342 * structure for rx queue read address reg in rxdma address map
343 * located at address 0x2014
344 * Defined earlier (u32)
348 * structure for rx queue read address external reg in rxdma address map
349 * located at address 0x2018
350 * Defined earlier (u32)
354 * structure for rx queue write address reg in rxdma address map
355 * located at address 0x201C
356 * Defined earlier (u32)
360 * structure for packet status ring base address lo reg in rxdma address map
361 * located at address 0x2020
362 * Defined earlier (u32)
366 * structure for packet status ring base address hi reg in rxdma address map
367 * located at address 0x2024
368 * Defined earlier (u32)
372 * structure for packet status ring number of descriptors reg in rxdma address
373 * map. Located at address 0x2028
380 * structure for packet status ring available offset reg in rxdma address map
381 * located at address 0x202C
389 * structure for packet status ring full offset reg in rxdma address map
390 * located at address 0x2030
398 * structure for packet status ring access index reg in rxdma address map
399 * located at address 0x2034
406 * structure for packet status ring minimum descriptors reg in rxdma address
407 * map. Located at address 0x2038
414 * structure for free buffer ring base lo address reg in rxdma address map
415 * located at address 0x203C
416 * Defined earlier (u32)
420 * structure for free buffer ring base hi address reg in rxdma address map
421 * located at address 0x2040
422 * Defined earlier (u32)
426 * structure for free buffer ring number of descriptors reg in rxdma address
427 * map. Located at address 0x2044
434 * structure for free buffer ring 0 available offset reg in rxdma address map
435 * located at address 0x2048
436 * Defined earlier (u32)
440 * structure for free buffer ring 0 full offset reg in rxdma address map
441 * located at address 0x204C
442 * Defined earlier (u32)
446 * structure for free buffer cache 0 full offset reg in rxdma address map
447 * located at address 0x2050
454 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
455 * located at address 0x2054
462 * structure for free buffer ring 1 base address lo reg in rxdma address map
463 * located at address 0x2058 - 0x205C
464 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
468 * structure for free buffer ring 1 number of descriptors reg in rxdma address
469 * map. Located at address 0x2060
470 * Defined earlier (RXDMA_FBR_NUM_DES_t)
474 * structure for free buffer ring 1 available offset reg in rxdma address map
475 * located at address 0x2064
476 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
480 * structure for free buffer ring 1 full offset reg in rxdma address map
481 * located at address 0x2068
482 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
486 * structure for free buffer cache 1 read index reg in rxdma address map
487 * located at address 0x206C
488 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
492 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
493 * located at address 0x2070
494 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
498 * Rx DMA Module of JAGCore Address Mapping
499 * Located at address 0x2000
501 struct rxdma_regs { /* Location: */
502 u32 csr; /* 0x2000 */
503 u32 dma_wb_base_lo; /* 0x2004 */
504 u32 dma_wb_base_hi; /* 0x2008 */
505 u32 num_pkt_done; /* 0x200C */
506 u32 max_pkt_time; /* 0x2010 */
507 u32 rxq_rd_addr; /* 0x2014 */
508 u32 rxq_rd_addr_ext; /* 0x2018 */
509 u32 rxq_wr_addr; /* 0x201C */
510 u32 psr_base_lo; /* 0x2020 */
511 u32 psr_base_hi; /* 0x2024 */
512 u32 psr_num_des; /* 0x2028 */
513 u32 psr_avail_offset; /* 0x202C */
514 u32 psr_full_offset; /* 0x2030 */
515 u32 psr_access_index; /* 0x2034 */
516 u32 psr_min_des; /* 0x2038 */
517 u32 fbr0_base_lo; /* 0x203C */
518 u32 fbr0_base_hi; /* 0x2040 */
519 u32 fbr0_num_des; /* 0x2044 */
520 u32 fbr0_avail_offset; /* 0x2048 */
521 u32 fbr0_full_offset; /* 0x204C */
522 u32 fbr0_rd_index; /* 0x2050 */
523 u32 fbr0_min_des; /* 0x2054 */
524 u32 fbr1_base_lo; /* 0x2058 */
525 u32 fbr1_base_hi; /* 0x205C */
526 u32 fbr1_num_des; /* 0x2060 */
527 u32 fbr1_avail_offset; /* 0x2064 */
528 u32 fbr1_full_offset; /* 0x2068 */
529 u32 fbr1_rd_index; /* 0x206C */
530 u32 fbr1_min_des; /* 0x2070 */
533 /* END OF RXDMA REGISTER ADDRESS MAP */
536 /* START OF TXMAC REGISTER ADDRESS MAP */
539 * structure for control reg in txmac address map
540 * located at address 0x3000
542 typedef union _TXMAC_CTL_t {
545 #ifdef _BIT_FIELDS_HTOL
546 u32 unused:24; /* bits 8-31 */
547 u32 cklseg_diable:1; /* bit 7 */
548 u32 ckbcnt_disable:1; /* bit 6 */
549 u32 cksegnum:1; /* bit 5 */
550 u32 async_disable:1; /* bit 4 */
551 u32 fc_disable:1; /* bit 3 */
552 u32 mcif_disable:1; /* bit 2 */
553 u32 mif_disable:1; /* bit 1 */
554 u32 txmac_en:1; /* bit 0 */
556 u32 txmac_en:1; /* bit 0 */
557 u32 mif_disable:1; /* bit 1 mac interface */
558 u32 mcif_disable:1; /* bit 2 mem. contr. interface */
559 u32 fc_disable:1; /* bit 3 */
560 u32 async_disable:1; /* bit 4 */
561 u32 cksegnum:1; /* bit 5 */
562 u32 ckbcnt_disable:1; /* bit 6 */
563 u32 cklseg_diable:1; /* bit 7 */
564 u32 unused:24; /* bits 8-31 */
567 } TXMAC_CTL_t, *PTXMAC_CTL_t;
570 * structure for shadow pointer reg in txmac address map
571 * located at address 0x3004
579 * structure for error count reg in txmac address map
580 * located at address 0x3008
582 typedef union _TXMAC_ERR_CNT_t {
585 #ifdef _BIT_FIELDS_HTOL
586 u32 unused:20; /* bits 12-31 */
587 u32 reserved:4; /* bits 8-11 */
588 u32 txq_underrun:4; /* bits 4-7 */
589 u32 fifo_underrun:4; /* bits 0-3 */
591 u32 fifo_underrun:4; /* bits 0-3 */
592 u32 txq_underrun:4; /* bits 4-7 */
593 u32 reserved:4; /* bits 8-11 */
594 u32 unused:20; /* bits 12-31 */
597 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
600 * structure for max fill reg in txmac address map
601 * located at address 0x300C
607 * structure for cf parameter reg in txmac address map
608 * located at address 0x3010
614 * structure for tx test reg in txmac address map
615 * located at address 0x3014
620 * 10-0: txq test pointer
624 * structure for error reg in txmac address map
625 * located at address 0x3018
627 typedef union _TXMAC_ERR_t {
630 #ifdef _BIT_FIELDS_HTOL
631 u32 unused2:23; /* bits 9-31 */
632 u32 fifo_underrun:1; /* bit 8 */
633 u32 unused1:2; /* bits 6-7 */
634 u32 ctrl2_err:1; /* bit 5 */
635 u32 txq_underrun:1; /* bit 4 */
636 u32 bcnt_err:1; /* bit 3 */
637 u32 lseg_err:1; /* bit 2 */
638 u32 segnum_err:1; /* bit 1 */
639 u32 seg0_err:1; /* bit 0 */
641 u32 seg0_err:1; /* bit 0 */
642 u32 segnum_err:1; /* bit 1 */
643 u32 lseg_err:1; /* bit 2 */
644 u32 bcnt_err:1; /* bit 3 */
645 u32 txq_underrun:1; /* bit 4 */
646 u32 ctrl2_err:1; /* bit 5 */
647 u32 unused1:2; /* bits 6-7 */
648 u32 fifo_underrun:1; /* bit 8 */
649 u32 unused2:23; /* bits 9-31 */
652 } TXMAC_ERR_t, *PTXMAC_ERR_t;
655 * structure for error interrupt reg in txmac address map
656 * located at address 0x301C
658 typedef union _TXMAC_ERR_INT_t {
661 #ifdef _BIT_FIELDS_HTOL
662 u32 unused2:23; /* bits 9-31 */
663 u32 fifo_underrun:1; /* bit 8 */
664 u32 unused1:2; /* bits 6-7 */
665 u32 ctrl2_err:1; /* bit 5 */
666 u32 txq_underrun:1; /* bit 4 */
667 u32 bcnt_err:1; /* bit 3 */
668 u32 lseg_err:1; /* bit 2 */
669 u32 segnum_err:1; /* bit 1 */
670 u32 seg0_err:1; /* bit 0 */
672 u32 seg0_err:1; /* bit 0 */
673 u32 segnum_err:1; /* bit 1 */
674 u32 lseg_err:1; /* bit 2 */
675 u32 bcnt_err:1; /* bit 3 */
676 u32 txq_underrun:1; /* bit 4 */
677 u32 ctrl2_err:1; /* bit 5 */
678 u32 unused1:2; /* bits 6-7 */
679 u32 fifo_underrun:1; /* bit 8 */
680 u32 unused2:23; /* bits 9-31 */
683 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
686 * structure for error interrupt reg in txmac address map
687 * located at address 0x3020
695 * Tx MAC Module of JAGCore Address Mapping
697 typedef struct _TXMAC_t { /* Location: */
698 TXMAC_CTL_t ctl; /* 0x3000 */
699 u32 shadow_ptr; /* 0x3004 */
700 TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */
701 u32 max_fill; /* 0x300C */
702 u32 cf_param; /* 0x3010 */
703 u32 tx_test; /* 0x3014 */
704 TXMAC_ERR_t err; /* 0x3018 */
705 TXMAC_ERR_INT_t err_int; /* 0x301C */
706 u32 bp_ctrl; /* 0x3020 */
707 } TXMAC_t, *PTXMAC_t;
709 /* END OF TXMAC REGISTER ADDRESS MAP */
711 /* START OF RXMAC REGISTER ADDRESS MAP */
714 * structure for rxmac control reg in rxmac address map
715 * located at address 0x4000
717 typedef union _RXMAC_CTRL_t {
720 #ifdef _BIT_FIELDS_HTOL
721 u32 reserved:25; /* bits 7-31 */
722 u32 rxmac_int_disable:1; /* bit 6 */
723 u32 async_disable:1; /* bit 5 */
724 u32 mif_disable:1; /* bit 4 */
725 u32 wol_disable:1; /* bit 3 */
726 u32 pkt_filter_disable:1; /* bit 2 */
727 u32 mcif_disable:1; /* bit 1 */
728 u32 rxmac_en:1; /* bit 0 */
730 u32 rxmac_en:1; /* bit 0 */
731 u32 mcif_disable:1; /* bit 1 */
732 u32 pkt_filter_disable:1; /* bit 2 */
733 u32 wol_disable:1; /* bit 3 */
734 u32 mif_disable:1; /* bit 4 */
735 u32 async_disable:1; /* bit 5 */
736 u32 rxmac_int_disable:1; /* bit 6 */
737 u32 reserved:25; /* bits 7-31 */
740 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
743 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
744 * located at address 0x4004
746 typedef union _RXMAC_WOL_CTL_CRC0_t {
749 #ifdef _BIT_FIELDS_HTOL
750 u32 crc0:16; /* bits 16-31 */
751 u32 reserve:4; /* bits 12-15 */
752 u32 ignore_pp:1; /* bit 11 */
753 u32 ignore_mp:1; /* bit 10 */
754 u32 clr_intr:1; /* bit 9 */
755 u32 ignore_link_chg:1; /* bit 8 */
756 u32 ignore_uni:1; /* bit 7 */
757 u32 ignore_multi:1; /* bit 6 */
758 u32 ignore_broad:1; /* bit 5 */
759 u32 valid_crc4:1; /* bit 4 */
760 u32 valid_crc3:1; /* bit 3 */
761 u32 valid_crc2:1; /* bit 2 */
762 u32 valid_crc1:1; /* bit 1 */
763 u32 valid_crc0:1; /* bit 0 */
765 u32 valid_crc0:1; /* bit 0 */
766 u32 valid_crc1:1; /* bit 1 */
767 u32 valid_crc2:1; /* bit 2 */
768 u32 valid_crc3:1; /* bit 3 */
769 u32 valid_crc4:1; /* bit 4 */
770 u32 ignore_broad:1; /* bit 5 */
771 u32 ignore_multi:1; /* bit 6 */
772 u32 ignore_uni:1; /* bit 7 */
773 u32 ignore_link_chg:1; /* bit 8 */
774 u32 clr_intr:1; /* bit 9 */
775 u32 ignore_mp:1; /* bit 10 */
776 u32 ignore_pp:1; /* bit 11 */
777 u32 reserve:4; /* bits 12-15 */
778 u32 crc0:16; /* bits 16-31 */
781 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
784 * structure for CRC 1 and CRC 2 reg in rxmac address map
785 * located at address 0x4008
787 typedef union _RXMAC_WOL_CRC12_t {
790 #ifdef _BIT_FIELDS_HTOL
791 u32 crc2:16; /* bits 16-31 */
792 u32 crc1:16; /* bits 0-15 */
794 u32 crc1:16; /* bits 0-15 */
795 u32 crc2:16; /* bits 16-31 */
798 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
801 * structure for CRC 3 and CRC 4 reg in rxmac address map
802 * located at address 0x400C
804 typedef union _RXMAC_WOL_CRC34_t {
807 #ifdef _BIT_FIELDS_HTOL
808 u32 crc4:16; /* bits 16-31 */
809 u32 crc3:16; /* bits 0-15 */
811 u32 crc3:16; /* bits 0-15 */
812 u32 crc4:16; /* bits 16-31 */
815 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
818 * structure for Wake On Lan Source Address Lo reg in rxmac address map
819 * located at address 0x4010
821 typedef union _RXMAC_WOL_SA_LO_t {
824 #ifdef _BIT_FIELDS_HTOL
825 u32 sa3:8; /* bits 24-31 */
826 u32 sa4:8; /* bits 16-23 */
827 u32 sa5:8; /* bits 8-15 */
828 u32 sa6:8; /* bits 0-7 */
830 u32 sa6:8; /* bits 0-7 */
831 u32 sa5:8; /* bits 8-15 */
832 u32 sa4:8; /* bits 16-23 */
833 u32 sa3:8; /* bits 24-31 */
836 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
839 * structure for Wake On Lan Source Address Hi reg in rxmac address map
840 * located at address 0x4014
842 typedef union _RXMAC_WOL_SA_HI_t {
845 #ifdef _BIT_FIELDS_HTOL
846 u32 reserved:16; /* bits 16-31 */
847 u32 sa1:8; /* bits 8-15 */
848 u32 sa2:8; /* bits 0-7 */
850 u32 sa2:8; /* bits 0-7 */
851 u32 sa1:8; /* bits 8-15 */
852 u32 reserved:16; /* bits 16-31 */
855 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
858 * structure for Wake On Lan mask reg in rxmac address map
859 * located at address 0x4018 - 0x4064
860 * Defined earlier (u32)
864 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
865 * located at address 0x4068
867 typedef union _RXMAC_UNI_PF_ADDR1_t {
870 #ifdef _BIT_FIELDS_HTOL
871 u32 addr1_3:8; /* bits 24-31 */
872 u32 addr1_4:8; /* bits 16-23 */
873 u32 addr1_5:8; /* bits 8-15 */
874 u32 addr1_6:8; /* bits 0-7 */
876 u32 addr1_6:8; /* bits 0-7 */
877 u32 addr1_5:8; /* bits 8-15 */
878 u32 addr1_4:8; /* bits 16-23 */
879 u32 addr1_3:8; /* bits 24-31 */
882 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
885 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
886 * located at address 0x406C
888 typedef union _RXMAC_UNI_PF_ADDR2_t {
891 #ifdef _BIT_FIELDS_HTOL
892 u32 addr2_3:8; /* bits 24-31 */
893 u32 addr2_4:8; /* bits 16-23 */
894 u32 addr2_5:8; /* bits 8-15 */
895 u32 addr2_6:8; /* bits 0-7 */
897 u32 addr2_6:8; /* bits 0-7 */
898 u32 addr2_5:8; /* bits 8-15 */
899 u32 addr2_4:8; /* bits 16-23 */
900 u32 addr2_3:8; /* bits 24-31 */
903 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
906 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
907 * located at address 0x4070
909 typedef union _RXMAC_UNI_PF_ADDR3_t {
912 #ifdef _BIT_FIELDS_HTOL
913 u32 addr2_1:8; /* bits 24-31 */
914 u32 addr2_2:8; /* bits 16-23 */
915 u32 addr1_1:8; /* bits 8-15 */
916 u32 addr1_2:8; /* bits 0-7 */
918 u32 addr1_2:8; /* bits 0-7 */
919 u32 addr1_1:8; /* bits 8-15 */
920 u32 addr2_2:8; /* bits 16-23 */
921 u32 addr2_1:8; /* bits 24-31 */
924 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
927 * structure for Multicast Hash reg in rxmac address map
928 * located at address 0x4074 - 0x4080
929 * Defined earlier (u32)
933 * structure for Packet Filter Control reg in rxmac address map
934 * located at address 0x4084
936 typedef union _RXMAC_PF_CTRL_t {
939 #ifdef _BIT_FIELDS_HTOL
940 u32 unused2:9; /* bits 23-31 */
941 u32 min_pkt_size:7; /* bits 16-22 */
942 u32 unused1:12; /* bits 4-15 */
943 u32 filter_frag_en:1; /* bit 3 */
944 u32 filter_uni_en:1; /* bit 2 */
945 u32 filter_multi_en:1; /* bit 1 */
946 u32 filter_broad_en:1; /* bit 0 */
948 u32 filter_broad_en:1; /* bit 0 */
949 u32 filter_multi_en:1; /* bit 1 */
950 u32 filter_uni_en:1; /* bit 2 */
951 u32 filter_frag_en:1; /* bit 3 */
952 u32 unused1:12; /* bits 4-15 */
953 u32 min_pkt_size:7; /* bits 16-22 */
954 u32 unused2:9; /* bits 23-31 */
957 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
960 * structure for Memory Controller Interface Control Max Segment reg in rxmac
961 * address map. Located at address 0x4088
963 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
966 #ifdef _BIT_FIELDS_HTOL
967 u32 reserved:22; /* bits 10-31 */
968 u32 max_size:8; /* bits 2-9 */
969 u32 fc_en:1; /* bit 1 */
970 u32 seg_en:1; /* bit 0 */
972 u32 seg_en:1; /* bit 0 */
973 u32 fc_en:1; /* bit 1 */
974 u32 max_size:8; /* bits 2-9 */
975 u32 reserved:22; /* bits 10-31 */
978 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
981 * structure for Memory Controller Interface Water Mark reg in rxmac address
982 * map. Located at address 0x408C
984 typedef union _RXMAC_MCIF_WATER_MARK_t {
987 #ifdef _BIT_FIELDS_HTOL
988 u32 reserved2:6; /* bits 26-31 */
989 u32 mark_hi:10; /* bits 16-25 */
990 u32 reserved1:6; /* bits 10-15 */
991 u32 mark_lo:10; /* bits 0-9 */
993 u32 mark_lo:10; /* bits 0-9 */
994 u32 reserved1:6; /* bits 10-15 */
995 u32 mark_hi:10; /* bits 16-25 */
996 u32 reserved2:6; /* bits 26-31 */
999 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1002 * structure for Rx Queue Dialog reg in rxmac address map.
1003 * located at address 0x4090
1005 typedef union _RXMAC_RXQ_DIAG_t {
1008 #ifdef _BIT_FIELDS_HTOL
1009 u32 reserved2:6; /* bits 26-31 */
1010 u32 rd_ptr:10; /* bits 16-25 */
1011 u32 reserved1:6; /* bits 10-15 */
1012 u32 wr_ptr:10; /* bits 0-9 */
1014 u32 wr_ptr:10; /* bits 0-9 */
1015 u32 reserved1:6; /* bits 10-15 */
1016 u32 rd_ptr:10; /* bits 16-25 */
1017 u32 reserved2:6; /* bits 26-31 */
1020 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1023 * structure for space availiable reg in rxmac address map.
1024 * located at address 0x4094
1026 typedef union _RXMAC_SPACE_AVAIL_t {
1029 #ifdef _BIT_FIELDS_HTOL
1030 u32 reserved2:15; /* bits 17-31 */
1031 u32 space_avail_en:1; /* bit 16 */
1032 u32 reserved1:6; /* bits 10-15 */
1033 u32 space_avail:10; /* bits 0-9 */
1035 u32 space_avail:10; /* bits 0-9 */
1036 u32 reserved1:6; /* bits 10-15 */
1037 u32 space_avail_en:1; /* bit 16 */
1038 u32 reserved2:15; /* bits 17-31 */
1041 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1044 * structure for management interface reg in rxmac address map.
1045 * located at address 0x4098
1047 typedef union _RXMAC_MIF_CTL_t {
1050 #ifdef _BIT_FIELDS_HTOL
1051 u32 reserve:14; /* bits 18-31 */
1052 u32 drop_pkt_en:1; /* bit 17 */
1053 u32 drop_pkt_mask:17; /* bits 0-16 */
1055 u32 drop_pkt_mask:17; /* bits 0-16 */
1056 u32 drop_pkt_en:1; /* bit 17 */
1057 u32 reserve:14; /* bits 18-31 */
1060 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1063 * structure for Error reg in rxmac address map.
1064 * located at address 0x409C
1066 typedef union _RXMAC_ERROR_REG_t {
1069 #ifdef _BIT_FIELDS_HTOL
1070 u32 reserve:28; /* bits 4-31 */
1071 u32 mif:1; /* bit 3 */
1072 u32 async:1; /* bit 2 */
1073 u32 pkt_filter:1; /* bit 1 */
1074 u32 mcif:1; /* bit 0 */
1076 u32 mcif:1; /* bit 0 */
1077 u32 pkt_filter:1; /* bit 1 */
1078 u32 async:1; /* bit 2 */
1079 u32 mif:1; /* bit 3 */
1080 u32 reserve:28; /* bits 4-31 */
1083 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1086 * Rx MAC Module of JAGCore Address Mapping
1088 typedef struct _RXMAC_t { /* Location: */
1089 RXMAC_CTRL_t ctrl; /* 0x4000 */
1090 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1091 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1092 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1093 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1094 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1095 u32 mask0_word0; /* 0x4018 */
1096 u32 mask0_word1; /* 0x401C */
1097 u32 mask0_word2; /* 0x4020 */
1098 u32 mask0_word3; /* 0x4024 */
1099 u32 mask1_word0; /* 0x4028 */
1100 u32 mask1_word1; /* 0x402C */
1101 u32 mask1_word2; /* 0x4030 */
1102 u32 mask1_word3; /* 0x4034 */
1103 u32 mask2_word0; /* 0x4038 */
1104 u32 mask2_word1; /* 0x403C */
1105 u32 mask2_word2; /* 0x4040 */
1106 u32 mask2_word3; /* 0x4044 */
1107 u32 mask3_word0; /* 0x4048 */
1108 u32 mask3_word1; /* 0x404C */
1109 u32 mask3_word2; /* 0x4050 */
1110 u32 mask3_word3; /* 0x4054 */
1111 u32 mask4_word0; /* 0x4058 */
1112 u32 mask4_word1; /* 0x405C */
1113 u32 mask4_word2; /* 0x4060 */
1114 u32 mask4_word3; /* 0x4064 */
1115 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1116 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1117 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1118 u32 multi_hash1; /* 0x4074 */
1119 u32 multi_hash2; /* 0x4078 */
1120 u32 multi_hash3; /* 0x407C */
1121 u32 multi_hash4; /* 0x4080 */
1122 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1123 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1124 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1125 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1126 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1128 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1129 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1130 } RXMAC_t, *PRXMAC_t;
1132 /* END OF TXMAC REGISTER ADDRESS MAP */
1135 /* START OF MAC REGISTER ADDRESS MAP */
1138 * structure for configuration #1 reg in mac address map.
1139 * located at address 0x5000
1159 #define CFG1_LOOPBACK 0x00000100
1160 #define CFG1_RX_FLOW 0x00000020
1161 #define CFG1_TX_FLOW 0x00000010
1162 #define CFG1_RX_ENABLE 0x00000004
1163 #define CFG1_TX_ENABLE 0x00000001
1164 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1167 * structure for configuration #2 reg in mac address map.
1168 * located at address 0x5004
1184 * structure for Interpacket gap reg in mac address map.
1185 * located at address 0x5008
1188 * 30-24: non B2B ipg 1
1190 * 22-16: non B2B ipg 2
1191 * 15-8: Min ifg enforce
1194 * structure for half duplex reg in mac address map.
1195 * located at address 0x500C
1197 * 23-20: Alt BEB trunc
1198 * 19: Alt BEB enable
1202 * 15-12: re-xmit max
1204 * 9-0: collision window
1208 * structure for Maximum Frame Length reg in mac address map.
1209 * located at address 0x5010: bits 0-15 hold the length.
1213 * structure for Reserve 1 reg in mac address map.
1214 * located at address 0x5014 - 0x5018
1215 * Defined earlier (u32)
1219 * structure for Test reg in mac address map.
1220 * located at address 0x501C
1221 * test: bits 0-2, rest unused
1225 * structure for MII Management Configuration reg in mac address map.
1226 * located at address 0x5020
1228 * 31: reset MII mgmt
1230 * 5: scan auto increment
1231 * 4: preamble supress
1233 * 2-0: mgmt clock reset
1237 * structure for MII Management Command reg in mac address map.
1238 * located at address 0x5024
1244 * structure for MII Management Address reg in mac address map.
1245 * located at address 0x5028
1252 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1255 * structure for MII Management Control reg in mac address map.
1256 * located at address 0x502C
1262 * structure for MII Management Status reg in mac address map.
1263 * located at address 0x5030
1269 * structure for MII Management Indicators reg in mac address map.
1270 * located at address 0x5034
1277 #define MGMT_BUSY 0x00000001 /* busy */
1278 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1281 * structure for Interface Control reg in mac address map.
1282 * located at address 0x5038
1284 * 31: reset if module
1297 * 8: disable link fail
1300 * 0: enable jabber protection
1304 * structure for Interface Status reg in mac address map.
1305 * located at address 0x503C
1307 typedef union _MAC_IF_STAT_t {
1310 #ifdef _BIT_FIELDS_HTOL
1311 u32 reserved:22; /* bits 10-31 */
1312 u32 excess_defer:1; /* bit 9 */
1313 u32 clash:1; /* bit 8 */
1314 u32 phy_jabber:1; /* bit 7 */
1315 u32 phy_link_ok:1; /* bit 6 */
1316 u32 phy_full_duplex:1; /* bit 5 */
1317 u32 phy_speed:1; /* bit 4 */
1318 u32 pe100x_link_fail:1; /* bit 3 */
1319 u32 pe10t_loss_carrie:1; /* bit 2 */
1320 u32 pe10t_sqe_error:1; /* bit 1 */
1321 u32 pe10t_jabber:1; /* bit 0 */
1323 u32 pe10t_jabber:1; /* bit 0 */
1324 u32 pe10t_sqe_error:1; /* bit 1 */
1325 u32 pe10t_loss_carrie:1; /* bit 2 */
1326 u32 pe100x_link_fail:1; /* bit 3 */
1327 u32 phy_speed:1; /* bit 4 */
1328 u32 phy_full_duplex:1; /* bit 5 */
1329 u32 phy_link_ok:1; /* bit 6 */
1330 u32 phy_jabber:1; /* bit 7 */
1331 u32 clash:1; /* bit 8 */
1332 u32 excess_defer:1; /* bit 9 */
1333 u32 reserved:22; /* bits 10-31 */
1336 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1339 * structure for Mac Station Address, Part 1 reg in mac address map.
1340 * located at address 0x5040
1342 typedef union _MAC_STATION_ADDR1_t {
1345 #ifdef _BIT_FIELDS_HTOL
1346 u32 Octet6:8; /* bits 24-31 */
1347 u32 Octet5:8; /* bits 16-23 */
1348 u32 Octet4:8; /* bits 8-15 */
1349 u32 Octet3:8; /* bits 0-7 */
1351 u32 Octet3:8; /* bits 0-7 */
1352 u32 Octet4:8; /* bits 8-15 */
1353 u32 Octet5:8; /* bits 16-23 */
1354 u32 Octet6:8; /* bits 24-31 */
1357 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1360 * structure for Mac Station Address, Part 2 reg in mac address map.
1361 * located at address 0x5044
1363 typedef union _MAC_STATION_ADDR2_t {
1366 #ifdef _BIT_FIELDS_HTOL
1367 u32 Octet2:8; /* bits 24-31 */
1368 u32 Octet1:8; /* bits 16-23 */
1369 u32 reserved:16; /* bits 0-15 */
1371 u32 reserved:16; /* bit 0-15 */
1372 u32 Octet1:8; /* bits 16-23 */
1373 u32 Octet2:8; /* bits 24-31 */
1376 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1379 * MAC Module of JAGCore Address Mapping
1381 typedef struct _MAC_t { /* Location: */
1382 u32 cfg1; /* 0x5000 */
1383 u32 cfg2; /* 0x5004 */
1384 u32 ipg; /* 0x5008 */
1385 u32 hfdp; /* 0x500C */
1386 u32 max_fm_len; /* 0x5010 */
1387 u32 rsv1; /* 0x5014 */
1388 u32 rsv2; /* 0x5018 */
1389 u32 mac_test; /* 0x501C */
1390 u32 mii_mgmt_cfg; /* 0x5020 */
1391 u32 mii_mgmt_cmd; /* 0x5024 */
1392 u32 mii_mgmt_addr; /* 0x5028 */
1393 u32 mii_mgmt_ctrl; /* 0x502C */
1394 u32 mii_mgmt_stat; /* 0x5030 */
1395 u32 mii_mgmt_indicator; /* 0x5034 */
1396 u32 if_ctrl; /* 0x5038 */
1397 MAC_IF_STAT_t if_stat; /* 0x503C */
1398 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1399 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1402 /* END OF MAC REGISTER ADDRESS MAP */
1404 /* START OF MAC STAT REGISTER ADDRESS MAP */
1407 * structure for Carry Register One and it's Mask Register reg located in mac
1408 * stat address map address 0x6130 and 0x6138.
1438 * structure for Carry Register Two Mask Register reg in mac stat address map.
1439 * located at address 0x613C
1465 * MAC STATS Module of JAGCore Address Mapping
1467 typedef struct _MAC_STAT_t { /* Location: */
1468 u32 pad[32]; /* 0x6000 - 607C */
1470 /* Tx/Rx 0-64 Byte Frame Counter */
1471 u32 TR64; /* 0x6080 */
1473 /* Tx/Rx 65-127 Byte Frame Counter */
1474 u32 TR127; /* 0x6084 */
1476 /* Tx/Rx 128-255 Byte Frame Counter */
1477 u32 TR255; /* 0x6088 */
1479 /* Tx/Rx 256-511 Byte Frame Counter */
1480 u32 TR511; /* 0x608C */
1482 /* Tx/Rx 512-1023 Byte Frame Counter */
1483 u32 TR1K; /* 0x6090 */
1485 /* Tx/Rx 1024-1518 Byte Frame Counter */
1486 u32 TRMax; /* 0x6094 */
1488 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1489 u32 TRMgv; /* 0x6098 */
1491 /* Rx Byte Counter */
1492 u32 RByt; /* 0x609C */
1494 /* Rx Packet Counter */
1495 u32 RPkt; /* 0x60A0 */
1497 /* Rx FCS Error Counter */
1498 u32 RFcs; /* 0x60A4 */
1500 /* Rx Multicast Packet Counter */
1501 u32 RMca; /* 0x60A8 */
1503 /* Rx Broadcast Packet Counter */
1504 u32 RBca; /* 0x60AC */
1506 /* Rx Control Frame Packet Counter */
1507 u32 RxCf; /* 0x60B0 */
1509 /* Rx Pause Frame Packet Counter */
1510 u32 RxPf; /* 0x60B4 */
1512 /* Rx Unknown OP Code Counter */
1513 u32 RxUo; /* 0x60B8 */
1515 /* Rx Alignment Error Counter */
1516 u32 RAln; /* 0x60BC */
1518 /* Rx Frame Length Error Counter */
1519 u32 RFlr; /* 0x60C0 */
1521 /* Rx Code Error Counter */
1522 u32 RCde; /* 0x60C4 */
1524 /* Rx Carrier Sense Error Counter */
1525 u32 RCse; /* 0x60C8 */
1527 /* Rx Undersize Packet Counter */
1528 u32 RUnd; /* 0x60CC */
1530 /* Rx Oversize Packet Counter */
1531 u32 ROvr; /* 0x60D0 */
1533 /* Rx Fragment Counter */
1534 u32 RFrg; /* 0x60D4 */
1536 /* Rx Jabber Counter */
1537 u32 RJbr; /* 0x60D8 */
1540 u32 RDrp; /* 0x60DC */
1542 /* Tx Byte Counter */
1543 u32 TByt; /* 0x60E0 */
1545 /* Tx Packet Counter */
1546 u32 TPkt; /* 0x60E4 */
1548 /* Tx Multicast Packet Counter */
1549 u32 TMca; /* 0x60E8 */
1551 /* Tx Broadcast Packet Counter */
1552 u32 TBca; /* 0x60EC */
1554 /* Tx Pause Control Frame Counter */
1555 u32 TxPf; /* 0x60F0 */
1557 /* Tx Deferral Packet Counter */
1558 u32 TDfr; /* 0x60F4 */
1560 /* Tx Excessive Deferral Packet Counter */
1561 u32 TEdf; /* 0x60F8 */
1563 /* Tx Single Collision Packet Counter */
1564 u32 TScl; /* 0x60FC */
1566 /* Tx Multiple Collision Packet Counter */
1567 u32 TMcl; /* 0x6100 */
1569 /* Tx Late Collision Packet Counter */
1570 u32 TLcl; /* 0x6104 */
1572 /* Tx Excessive Collision Packet Counter */
1573 u32 TXcl; /* 0x6108 */
1575 /* Tx Total Collision Packet Counter */
1576 u32 TNcl; /* 0x610C */
1578 /* Tx Pause Frame Honored Counter */
1579 u32 TPfh; /* 0x6110 */
1581 /* Tx Drop Frame Counter */
1582 u32 TDrp; /* 0x6114 */
1584 /* Tx Jabber Frame Counter */
1585 u32 TJbr; /* 0x6118 */
1587 /* Tx FCS Error Counter */
1588 u32 TFcs; /* 0x611C */
1590 /* Tx Control Frame Counter */
1591 u32 TxCf; /* 0x6120 */
1593 /* Tx Oversize Frame Counter */
1594 u32 TOvr; /* 0x6124 */
1596 /* Tx Undersize Frame Counter */
1597 u32 TUnd; /* 0x6128 */
1599 /* Tx Fragments Frame Counter */
1600 u32 TFrg; /* 0x612C */
1602 /* Carry Register One Register */
1603 u32 Carry1; /* 0x6130 */
1605 /* Carry Register Two Register */
1606 u32 Carry2; /* 0x6134 */
1608 /* Carry Register One Mask Register */
1609 u32 Carry1M; /* 0x6138 */
1611 /* Carry Register Two Mask Register */
1612 u32 Carry2M; /* 0x613C */
1613 } MAC_STAT_t, *PMAC_STAT_t;
1615 /* END OF MAC STAT REGISTER ADDRESS MAP */
1618 /* START OF MMC REGISTER ADDRESS MAP */
1621 * Main Memory Controller Control reg in mmc address map.
1622 * located at address 0x7000
1625 #define ET_MMC_ENABLE 1
1626 #define ET_MMC_ARB_DISABLE 2
1627 #define ET_MMC_RXMAC_DISABLE 4
1628 #define ET_MMC_TXMAC_DISABLE 8
1629 #define ET_MMC_TXDMA_DISABLE 16
1630 #define ET_MMC_RXDMA_DISABLE 32
1631 #define ET_MMC_FORCE_CE 64
1634 * Main Memory Controller Host Memory Access Address reg in mmc
1635 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1638 #define ET_SRAM_REQ_ACCESS 1
1639 #define ET_SRAM_WR_ACCESS 2
1640 #define ET_SRAM_IS_CTRL 4
1643 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1644 * address map. Located at address 0x7008 - 0x7014
1645 * Defined earlier (u32)
1649 * Memory Control Module of JAGCore Address Mapping
1651 typedef struct _MMC_t { /* Location: */
1652 u32 mmc_ctrl; /* 0x7000 */
1653 u32 sram_access; /* 0x7004 */
1654 u32 sram_word1; /* 0x7008 */
1655 u32 sram_word2; /* 0x700C */
1656 u32 sram_word3; /* 0x7010 */
1657 u32 sram_word4; /* 0x7014 */
1660 /* END OF MMC REGISTER ADDRESS MAP */
1664 * JAGCore Address Mapping
1666 typedef struct _ADDRESS_MAP_t {
1667 struct global_regs global;
1668 /* unused section of global address map */
1669 u8 unused_global[4096 - sizeof(struct global_regs)];
1670 struct txdma_regs txdma;
1671 /* unused section of txdma address map */
1672 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1673 struct rxdma_regs rxdma;
1674 /* unused section of rxdma address map */
1675 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1677 /* unused section of txmac address map */
1678 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1680 /* unused section of rxmac address map */
1681 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1683 /* unused section of mac address map */
1684 u8 unused_mac[4096 - sizeof(MAC_t)];
1686 /* unused section of mac stat address map */
1687 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1689 /* unused section of mmc address map */
1690 u8 unused_mmc[4096 - sizeof(MMC_t)];
1691 /* unused section of address map */
1692 u8 unused_[1015808];
1694 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1695 u8 unused__[524288]; /* unused section of address map */
1696 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1698 #endif /* _ET1310_ADDRESS_MAP_H_ */