2 * $Id: pmcc4_drv.c,v 3.1 2007/08/15 23:32:17 rickd PMCC4_3_1B $
6 /*-----------------------------------------------------------------------------
9 * Copyright (C) 2007 One Stop Systems, Inc.
10 * Copyright (C) 2002-2006 SBE, Inc.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * For further information, contact via email: support@onestopsystems.com
23 * One Stop Systems, Inc. Escondido, California U.S.A.
24 *-----------------------------------------------------------------------------
26 * RCS revision: $Revision: 3.1 $
27 * Last changed on $Date: 2007/08/15 23:32:17 $
28 * Changed by $Author: rickd $
29 *-----------------------------------------------------------------------------
30 * $Log: pmcc4_drv.c,v $
31 * Revision 3.1 2007/08/15 23:32:17 rickd
32 * Use 'if 0' instead of GNU comment delimeter to avoid line wrap induced compiler errors.
34 * Revision 3.0 2007/08/15 22:19:55 rickd
35 * Correct sizeof() castings and pi->regram to support 64bit compatibility.
37 * Revision 2.10 2006/04/21 00:56:40 rickd
38 * workqueue files now prefixed with <sbecom> prefix.
40 * Revision 2.9 2005/11/01 19:22:49 rickd
41 * Add sanity checks against max_port for ioctl functions.
43 * Revision 2.8 2005/10/27 18:59:25 rickd
44 * Code cleanup. Default channel config to HDLC_FCS16.
46 * Revision 2.7 2005/10/18 18:16:30 rickd
47 * Further NCOMM code repairs - (1) interrupt matrix usage inconsistant
48 * for indexing into nciInterrupt[][], code missing double parameters.
49 * (2) check input of ncomm interrupt registration cardID for correct
52 * Revision 2.6 2005/10/17 23:55:28 rickd
53 * Initial port of NCOMM support patches from original work found
54 * in pmc_c4t1e1 as updated by NCOMM. Ref: CONFIG_SBE_PMCC4_NCOMM.
55 * Corrected NCOMMs wanpmcC4T1E1_getBaseAddress() to correctly handle
58 * Revision 2.5 2005/10/13 23:01:28 rickd
59 * Correct panic for illegal address reference w/in get_brdinfo on
60 * first_if/last_if name acquistion under Linux 2.6
62 * Revision 2.4 2005/10/13 21:20:19 rickd
63 * Correction of c4_cleanup() wherein next should be acquired before
64 * ci_t structure is free'd.
66 * Revision 2.3 2005/10/13 19:20:10 rickd
67 * Correct driver removal cleanup code for multiple boards.
69 * Revision 2.2 2005/10/11 18:34:04 rickd
70 * New routine added to determine number of ports (comets) on board.
72 * Revision 2.1 2005/10/05 00:48:13 rickd
73 * Add some RX activation trace code.
75 * Revision 2.0 2005/09/28 00:10:06 rickd
76 * Implement 2.6 workqueue for TX/RX restart. Correction to
77 * hardware register boundary checks allows expanded access of MUSYCC.
78 * Implement new musycc reg&bits namings.
80 *-----------------------------------------------------------------------------
83 char OSSIid_pmcc4_drvc[] =
84 "@(#)pmcc4_drv.c - $Revision: 3.1 $ (c) Copyright 2002-2007 One Stop Systems, Inc.";
86 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
88 #if defined (__FreeBSD__) || defined (__NetBSD__)
89 #include <sys/param.h>
90 #include <sys/systm.h>
91 #include <sys/errno.h>
93 #include <linux/types.h>
94 #include "pmcc4_sysdep.h"
95 #include <linux/errno.h>
96 #include <linux/kernel.h>
97 #include <linux/sched.h> /* include for timer */
98 #include <linux/timer.h> /* include for timer */
99 #include <linux/hdlc.h>
103 #include "sbecom_inline_linux.h"
105 #include "pmcc4_private.h"
107 #include "pmcc4_ioctls.h"
112 #ifdef SBE_INCLUDE_SYMBOLS
115 #define STATIC static
119 #define KERN_WARN KERN_WARNING
121 /* forward references */
122 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
123 status_t c4_wk_chan_init (mpi_t *, mch_t *);
124 void c4_wq_port_cleanup (mpi_t *);
125 status_t c4_wq_port_init (mpi_t *);
128 int c4_loop_port (ci_t *, int, u_int8_t);
129 status_t c4_set_port (ci_t *, int);
130 status_t musycc_chan_down (ci_t *, int);
132 u_int32_t musycc_chan_proto (int);
133 status_t musycc_dump_ring (ci_t *, unsigned int);
134 status_t __init musycc_init (ci_t *);
135 void musycc_init_mdt (mpi_t *);
136 void musycc_serv_req (mpi_t *, u_int32_t);
137 void musycc_update_timeslots (mpi_t *);
139 extern void musycc_update_tx_thp (mch_t *);
140 extern int log_level;
143 extern int max_rxdesc_used, max_rxdesc_default;
144 extern int max_txdesc_used, max_txdesc_default;
146 #if defined (__powerpc__)
147 extern void *memset (void *s, int c, size_t n);
151 int drvr_state = SBE_DRVR_INIT;
153 ci_t *CI; /* dummy pointer to board ZEROE's data -
158 sbecom_set_loglevel (int d)
161 * The code within the following -if- clause is a backdoor debug facility
162 * which can be used to display the state of a board's channel.
166 unsigned int channum = d - (LOG_DEBUG + 1); /* convert to ZERO
169 (void) musycc_dump_ring ((ci_t *) CI, channum); /* CI implies support
175 printk ("%s: log level changed from %d to %d\n", THIS_MODULE->name, log_level, d);
176 log_level = d; /* set new */
178 printk ("%s: log level is %d\n", THIS_MODULE->name, log_level);
184 c4_find_chan (int channum)
190 for (ci = c4_list; ci; ci = ci->next)
191 for (portnum = 0; portnum < ci->max_port; portnum++)
192 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
194 if ((ch = ci->port[portnum].chan[gchan]))
196 if ((ch->state != UNASSIGNED) &&
197 (ch->channum == channum))
211 pr_warning("c4_new() entered, ci needs %u.\n",
212 (unsigned int) sizeof (ci_t));
215 ci = (ci_t *) OS_kmalloc (sizeof (ci_t));
219 ci->state = C_INIT; /* mark as hardware not available */
222 ci->brdno = ci->next ? ci->next->brdno + 1 : 0;
224 pr_warning("failed CI malloc, size %u.\n",
225 (unsigned int) sizeof (ci_t));
228 CI = ci; /* DEBUG, only board 0 usage */
234 * Check port state and set LED states using watchdog or ioctl...
235 * also check for in-band SF loopback commands (& cause results if they are there)
237 * Alarm function depends on comet bits indicating change in
238 * link status (linkMask) to keep the link status indication straight.
240 * Indications are only LED and system log -- except when ioctl is invoked.
242 * "alarmed" record (a.k.a. copyVal, in some cases below) decodes as:
244 * RMAI (E1 only) 0x100
247 * link returned 0x20 (link was down, now it's back and 'port get' hasn't run)
248 * change in LED 0x10 (update LED register because value has changed)
254 * note "link has returned" indication is reset on read
255 * (e.g. by use of the c4_control port get command)
258 #define sbeLinkMask 0x41 /* change in signal status (lost/recovered) +
260 #define sbeLinkChange 0x40
261 #define sbeLinkDown 0x01
262 #define sbeAlarmsMask 0x07 /* red / yellow / blue alarm conditions */
263 #define sbeE1AlarmsMask 0x107 /* alarm conditions */
265 #define COMET_LBCMD_READ 0x80 /* read only (do not set, return read value) */
268 checkPorts (ci_t * ci)
270 #ifndef CONFIG_SBE_PMCC4_NCOMM
272 * PORT POINT - NCOMM needs to avoid this code since the polling of
273 * alarms conflicts with NCOMM's interrupt servicing implementation.
277 volatile u_int32_t value;
278 u_int32_t copyVal, LEDval;
283 for (portnum = 0; portnum < ci->max_port; portnum++)
285 copyVal = 0x12f & (ci->alarmed[portnum]); /* port's alarm record */
286 comet = ci->port[portnum].cometbase;
287 value = pci_read_32 ((u_int32_t *) &comet->cdrc_ists) & sbeLinkMask; /* link loss reg */
289 if (value & sbeLinkChange) /* is there a change in the link stuff */
291 /* if there's been a change (above) and yet it's the same (below) */
292 if (!(((copyVal >> 3) & sbeLinkDown) ^ (value & sbeLinkDown)))
294 if (value & sbeLinkDown)
295 printk (KERN_WARN "%s: Port %d momentarily recovered.\n",
296 ci->devname, portnum);
299 "%s: Warning: Port %d link was briefly down.\n",
300 ci->devname, portnum);
301 } else if (value & sbeLinkDown)
302 printk (KERN_WARN "%s: Warning: Port %d link is down.\n",
303 ci->devname, portnum);
306 printk (KERN_WARN "%s: Port %d link has recovered.\n",
307 ci->devname, portnum);
308 copyVal |= 0x20; /* record link transition to up */
310 copyVal |= 0x10; /* change (link) --> update LEDs */
312 copyVal &= 0x137; /* clear LED & link old history bits &
314 if (value & sbeLinkDown)
315 copyVal |= 0x08; /* record link status (now) */
317 { /* if link is up, do this */
318 copyVal |= 0x40; /* LED indicate link is up */
319 /* Alarm things & the like ... first if E1, then if T1 */
320 if (IS_FRAME_ANY_E1 (ci->port[portnum].p.port_mode))
323 * first check Codeword (SaX) changes & CRC and
324 * sub-multi-frame errors
327 * note these errors are printed every time they are detected
330 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_nat_ists); /* codeword */
332 { /* if errors (crc or smf only) */
335 "%s: E1 Port %d Codeword Sa4 change detected.\n",
336 ci->devname, portnum);
339 "%s: E1 Port %d Codeword Sa5 change detected.\n",
340 ci->devname, portnum);
343 "%s: E1 Port %d Codeword Sa6 change detected.\n",
344 ci->devname, portnum);
347 "%s: E1 Port %d Codeword Sa7 change detected.\n",
348 ci->devname, portnum);
351 "%s: E1 Port %d Codeword Sa8 change detected.\n",
352 ci->devname, portnum);
354 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_mists); /* crc & smf */
356 { /* if errors (crc or smf only) */
357 if (value & sbeE1CRC)
358 printk (KERN_WARN "%s: E1 Port %d CRC-4 error(s) detected.\n",
359 ci->devname, portnum);
360 if (value & sbeE1errSMF) /* error in sub-multiframe */
361 printk (KERN_WARN "%s: E1 Port %d received errored SMF.\n",
362 ci->devname, portnum);
364 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_masts) & 0xcc; /* alarms */
366 * pack alarms together (bitmiser), and construct similar to
369 /* RAI,RMAI,.,.,LOF,AIS,.,. ==> RMAI,.,.,.,.,.,RAI,LOF,AIS */
371 value = (value >> 2);
375 value |= 0x40; /* RAI */
377 value |= 0x100; /* RMAI */
379 } /* finished packing alarm in handy order */
380 if (value != (copyVal & sbeE1AlarmsMask))
381 { /* if alarms changed */
382 copyVal |= 0x10;/* change LED status */
383 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
385 copyVal &= ~sbeRedAlm;
386 printk (KERN_WARN "%s: E1 Port %d LOF alarm ended.\n",
387 ci->devname, portnum);
388 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
390 copyVal |= sbeRedAlm;
391 printk (KERN_WARN "%s: E1 Warning: Port %d LOF alarm.\n",
392 ci->devname, portnum);
393 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
395 copyVal &= ~sbeYelAlm;
396 printk (KERN_WARN "%s: E1 Port %d RAI alarm ended.\n",
397 ci->devname, portnum);
398 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
400 copyVal |= sbeYelAlm;
401 printk (KERN_WARN "%s: E1 Warning: Port %d RAI alarm.\n",
402 ci->devname, portnum);
403 } else if ((copyVal & sbeE1RMAI) && !(value & sbeE1RMAI))
405 copyVal &= ~sbeE1RMAI;
406 printk (KERN_WARN "%s: E1 Port %d RMAI alarm ended.\n",
407 ci->devname, portnum);
408 } else if (!(copyVal & sbeE1RMAI) && (value & sbeE1RMAI))
410 copyVal |= sbeE1RMAI;
411 printk (KERN_WARN "%s: E1 Warning: Port %d RMAI alarm.\n",
412 ci->devname, portnum);
413 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
415 copyVal &= ~sbeAISAlm;
416 printk (KERN_WARN "%s: E1 Port %d AIS alarm ended.\n",
417 ci->devname, portnum);
418 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
420 copyVal |= sbeAISAlm;
421 printk (KERN_WARN "%s: E1 Warning: Port %d AIS alarm.\n",
422 ci->devname, portnum);
425 /* end of E1 alarm code */
428 value = pci_read_32 ((u_int32_t *) &comet->t1_almi_ists); /* alarms */
429 value &= sbeAlarmsMask;
430 if (value != (copyVal & sbeAlarmsMask))
431 { /* if alarms changed */
432 copyVal |= 0x10;/* change LED status */
433 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
435 copyVal &= ~sbeRedAlm;
436 printk (KERN_WARN "%s: Port %d red alarm ended.\n",
437 ci->devname, portnum);
438 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
440 copyVal |= sbeRedAlm;
441 printk (KERN_WARN "%s: Warning: Port %d red alarm.\n",
442 ci->devname, portnum);
443 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
445 copyVal &= ~sbeYelAlm;
446 printk (KERN_WARN "%s: Port %d yellow (RAI) alarm ended.\n",
447 ci->devname, portnum);
448 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
450 copyVal |= sbeYelAlm;
451 printk (KERN_WARN "%s: Warning: Port %d yellow (RAI) alarm.\n",
452 ci->devname, portnum);
453 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
455 copyVal &= ~sbeAISAlm;
456 printk (KERN_WARN "%s: Port %d blue (AIS) alarm ended.\n",
457 ci->devname, portnum);
458 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
460 copyVal |= sbeAISAlm;
461 printk (KERN_WARN "%s: Warning: Port %d blue (AIS) alarm.\n",
462 ci->devname, portnum);
465 } /* end T1 mode alarm checks */
467 if (copyVal & sbeAlarmsMask)
468 copyVal |= 0x80; /* if alarm turn yel LED on */
470 LEDval |= 0x100; /* tag if LED values have changed */
471 LEDval |= ((copyVal & 0xc0) >> (6 - (portnum * 2)));
473 ci->alarmed[portnum] &= 0xfffff000; /* out with the old (it's fff
475 ci->alarmed[portnum] |= (copyVal); /* in with the new */
478 * enough with the alarms and LED's, now let's check for loopback
482 if (IS_FRAME_ANY_T1 (ci->port[portnum].p.port_mode))
485 * begin in-band (SF) loopback code detection -- start by reading
488 value = pci_read_32 ((u_int32_t *) &comet->ibcd_ies); /* detect reg. */
489 value &= 0x3; /* trim to handy bits */
491 { /* activate loopback (sets for deactivate
493 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
495 if (copyVal != COMET_MDIAG_LINELB) /* don't do it again if
496 * already in that mode */
497 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
501 { /* deactivate loopback (sets for activate
503 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
505 if (copyVal != COMET_MDIAG_LBOFF) /* don't do it again if
506 * already in that mode */
507 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
511 if (IS_FRAME_ANY_T1ESF (ci->port[portnum].p.port_mode))
512 { /* if a T1 ESF mode */
513 /* begin ESF loopback code */
514 value = pci_read_32 ((u_int32_t *) &comet->t1_rboc_sts) & 0x3f; /* read command */
516 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
519 c4_loop_port (ci, portnum, COMET_MDIAG_PAYLB); /* put port in payload
521 if ((value == 0x1c) || (value == 0x19) || (value == 0x12))
522 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
524 if (log_level >= LOG_DEBUG)
526 printk (KERN_WARN "%s: BOC value = %x on Port %d\n",
527 ci->devname, value, portnum);
528 /* end ESF loopback code */
532 /* if something is new, update LED's */
534 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, LEDval & 0xff);
535 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
540 c4_watchdog (ci_t * ci)
543 //unsigned long flags;
546 if (drvr_state != SBE_DRVR_AVAILABLE)
548 if (log_level >= LOG_MONITOR)
549 printk ("%s: drvr not available (%x)\n", THIS_MODULE->name, drvr_state);
553 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
559 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,41)
561 { /* is there a state change to search for */
564 ci->wd_notify = 0; /* reset notification */
565 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
567 for (port = 0; port < ci->max_port; port++)
569 mch_t *ch = ci->port[port].chan[gchan];
571 if (!ch || ci->state != C_RUNNING) /* state changed while
572 * acquiring semaphore */
574 if (ch->state == UP)/* channel must be set up */
577 #ifdef RLD_TRANS_DEBUG
578 if (1 || log_level >= LOG_MONITOR)
580 if (log_level >= LOG_MONITOR)
582 printk ("%s: watchdog reviving Port %d Channel %d [%d] sts %x/%x, start_TX %x free %x start_RX %x\n",
583 ci->devname, ch->channum, port, gchan, ch->channum,
584 ch->p.status, ch->status,
585 ch->ch_start_tx, ch->txd_free, ch->ch_start_rx);
588 /**********************************/
589 /** check for RX restart request **/
590 /**********************************/
592 if (ch->ch_start_rx &&
593 (ch->status & RX_ENABLED)) /* requires start on
596 ch->ch_start_rx = 0; /* we are restarting RX... */
597 #ifdef RLD_TRANS_DEBUG
598 printk ("++ c4_watchdog() CHAN RX ACTIVATE: chan %d\n", ch->channum);
600 #ifdef RLD_RXACT_DEBUG
603 static int hereb4 = 7;
608 md = &ch->mdr[ch->rxix_irq_srv];
609 printk ("++ c4_watchdog[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
610 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status), ch->s.rx_packets);
611 musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
615 musycc_serv_req (ch->up, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
617 /**********************************/
618 /** check for TX restart request **/
619 /**********************************/
621 if (ch->ch_start_tx &&
622 (ch->status & TX_ENABLED)) /* requires start on
628 * find next unprocessed message, then set TX thp to
631 musycc_update_tx_thp (ch);
634 spin_lock_irqsave (&ch->ch_txlock, flags);
636 md = ch->txd_irq_srv;
639 printk ("-- c4_watchdog[%d]: WARNING, starting NULL md\n", ch->channum);
640 printk ("-- chan %d txd_irq_srv %p sts %x usr_add %p sts %x, txpkt %lu\n",
641 ch->channum, ch->txd_irq_srv, le32_to_cpu ((struct mdesc *) (ch->txd_irq_srv)->status),
642 ch->txd_usr_add, le32_to_cpu ((struct mdesc *) (ch->txd_usr_add)->status),
645 spin_unlock_irqrestore (&ch->ch_txlock, flags);
647 } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
649 #ifdef RLD_TRANS_DEBUG
650 printk ("++ c4_watchdog[%d] CHAN TX ACTIVATE: start_tx %x\n", ch->channum, ch->ch_start_tx);
652 ch->ch_start_tx = 0; /* we are restarting
655 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for
658 musycc_serv_req (ch->up, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | gchan);
659 #ifdef RLD_TRANS_DEBUG
660 if (1 || log_level >= LOG_MONITOR)
662 if (log_level >= LOG_MONITOR)
664 printk ("++ SACK[P%d/C%d] ack'd, continuing...\n", ch->up->portnum, ch->channum);
675 SD_SEM_GIVE (&ci->sem_wdbusy);/* release per-board hold */
690 next = ci->next; /* protect <next> from upcoming <free> */
691 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
692 for (portnum = 0; portnum < ci->max_port; portnum++)
694 pi = &ci->port[portnum];
695 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
696 c4_wq_port_cleanup (pi);
698 for (j = 0; j < MUSYCC_NCHANS; j++)
701 OS_kfree (pi->chan[j]); /* free mch_t struct */
703 OS_kfree (pi->regram_saved);
706 /* obsolete - watchdog is now static w/in ci_t */
707 OS_free_watchdog (ci->wd);
709 OS_kfree (ci->iqd_p_saved);
711 ci = next; /* cleanup next board, if any */
717 * This function issues a write to all comet chips and expects the same data
718 * to be returned from the subsequent read. This determines the board build
719 * to be a 1-port, 2-port, or 4-port build. The value returned represents a
720 * bit-mask of the found ports. Only certain configurations are considered
721 * VALID or LEGAL builds.
725 c4_get_portcfg (ci_t * ci)
729 u_int32_t wdata, rdata;
731 wdata = COMET_MDIAG_LBOFF; /* take port out of any loopback mode */
734 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
736 comet = ci->port[portnum].cometbase;
737 pci_write_32 ((u_int32_t *) &comet->mdiag, wdata);
738 rdata = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
740 mask |= 1 << portnum;
746 /* nothing herein should generate interrupts */
749 c4_init (ci_t * ci, u_char *func0, u_char *func1)
753 static u_int32_t count = 0;
758 ci->intlog.this_status_new = 0;
759 atomic_set (&ci->bh_pending, 0);
761 ci->reg = (struct musycc_globalr *) func0;
762 ci->eeprombase = (u_int32_t *) (func1 + EEPROM_OFFSET);
763 ci->cpldbase = (c4cpld_t *) ((u_int32_t *) (func1 + ISPLD_OFFSET));
765 /*** PORT POINT - the following is the first access of any type to the hardware ***/
766 #ifdef CONFIG_SBE_PMCC4_NCOMM
767 /* NCOMM driver uses INTB interrupt to monitor CPLD register */
768 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC);
770 /* standard driver POLLS for INTB via CPLD register */
771 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
777 /* need comet addresses available for determination of hardware build */
778 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
780 pi = &ci->port[portnum];
781 pi->cometbase = (comet_t *) ((u_int32_t *) (func1 + COMET_OFFSET (portnum)));
782 pi->reg = (struct musycc_globalr *) ((u_char *) ci->reg + (portnum * 0x800));
783 pi->portnum = portnum;
784 pi->p.portnum = portnum;
787 printk ("Comet-%d: addr = %p\n", portnum, pi->cometbase);
790 pmsk = c4_get_portcfg (ci);
800 case 0x7: /* not built, but could be... */
809 pr_warning("%s: illegal port configuration (%x)\n",
811 return SBE_DRVR_FAIL;
814 printk (">> %s: c4_get_build - pmsk %x max_port %x\n", ci->devname, pmsk, ci->max_port);
818 for (portnum = 0; portnum < ci->max_port; portnum++)
820 pi = &ci->port[portnum];
822 pi->sr_last = 0xffffffff;
823 pi->p.port_mode = CFG_FRAME_SF; /* T1 B8ZS, the default */
824 pi->p.portP = (CFG_CLK_PORT_EXTERNAL | CFG_LBO_LH0); /* T1 defaults */
826 OS_sem_init (&pi->sr_sem_busy, SEM_AVAILABLE);
827 OS_sem_init (&pi->sr_sem_wait, SEM_TAKEN);
829 for (j = 0; j < 32; j++)
832 pi->tsm[j] = 0; /* no assignments, all available */
835 /* allocate channel structures for this port */
836 for (j = 0; j < MUSYCC_NCHANS; j++)
838 ch = OS_kmalloc (sizeof (mch_t));
842 ch->state = UNASSIGNED;
844 ch->gchan = (-1); /* channel assignment not yet known */
845 ch->channum = (-1); /* channel assignment not yet known */
846 ch->p.card = ci->brdno;
847 ch->p.port = portnum;
848 ch->p.channum = (-1); /* channel assignment not yet known */
849 ch->p.mode_56k = 0; /* default is 64kbps mode */
852 pr_warning("failed mch_t malloc, port %d channel %d size %u.\n",
853 portnum, j, (unsigned int) sizeof (mch_t));
862 * Set LEDs through their paces to supply visual proof that LEDs are
863 * functional and not burnt out nor broken.
865 * YELLOW + GREEN -> OFF.
868 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds,
869 PMCC4_CPLD_LED_GREEN | PMCC4_CPLD_LED_YELLOW);
870 OS_uwait (750000, "leds");
871 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
874 OS_init_watchdog (&ci->wd, (void (*) (void *)) c4_watchdog, ci, WATCHDOG_TIMEOUT);
875 return SBE_DRVR_SUCCESS;
879 /* better be fully setup to handle interrupts when you call this */
886 /* PORT POINT: this routine generates first interrupt */
887 if ((ret = musycc_init (ci)) != SBE_DRVR_SUCCESS)
891 ci->p.framing_type = FRAMING_CBP;
892 ci->p.h110enable = 1;
898 ci->p.clock = 0; /* Use internal clocking until set to
900 c4_card_set_params (ci, &ci->p);
902 OS_start_watchdog (&ci->wd);
903 return SBE_DRVR_SUCCESS;
907 /* This function sets the loopback mode (or clears it, as the case may be). */
910 c4_loop_port (ci_t * ci, int portnum, u_int8_t cmd)
913 volatile u_int32_t loopValue;
915 comet = ci->port[portnum].cometbase;
916 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
918 if (cmd & COMET_LBCMD_READ)
919 return loopValue; /* return the read value */
921 if (loopValue != cmd)
925 case COMET_MDIAG_LINELB:
926 /* set(SF)loopback down (turn off) code length to 6 bits */
927 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x05);
929 case COMET_MDIAG_LBOFF:
930 /* set (SF) loopback up (turn on) code length to 5 bits */
931 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x00);
935 pci_write_32 ((u_int32_t *) &comet->mdiag, cmd);
936 if (log_level >= LOG_WARN)
937 printk ("%s: loopback mode changed to %2x from %2x on Port %d\n",
938 ci->devname, cmd, loopValue, portnum);
939 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
940 if (loopValue != cmd)
942 if (log_level >= LOG_ERROR)
943 printk ("%s: write to loop register failed, unknown state for Port %d\n",
944 ci->devname, portnum);
948 if (log_level >= LOG_WARN)
949 printk ("%s: loopback already in that mode (%2x)\n", ci->devname, loopValue);
955 /* c4_frame_rw: read or write the comet register specified
956 * (modifies use of port_param to non-standard use of struct)
958 * pp.portnum (one guess)
959 * pp.port_mode offset of register
960 * pp.portP write (or not, i.e. read)
961 * pp.portStatus write value
963 * pp.portStatus also used to return read value
964 * pp.portP also used during write, to return old reg value
968 c4_frame_rw (ci_t * ci, struct sbecom_port_param * pp)
971 volatile u_int32_t data;
973 if (pp->portnum >= ci->max_port)/* sanity check */
976 comet = ci->port[pp->portnum].cometbase;
977 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
980 { /* control says this is a register
982 if (pp->portStatus == data)
983 printk ("%s: Port %d already that value! Writing again anyhow.\n",
984 ci->devname, pp->portnum);
985 pp->portP = (u_int8_t) data;
986 pci_write_32 ((u_int32_t *) comet + pp->port_mode,
988 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
990 pp->portStatus = (u_int8_t) data;
995 /* c4_pld_rw: read or write the pld register specified
996 * (modifies use of port_param to non-standard use of struct)
998 * pp.port_mode offset of register
999 * pp.portP write (or not, i.e. read)
1000 * pp.portStatus write value
1002 * pp.portStatus also used to return read value
1003 * pp.portP also used during write, to return old reg value
1007 c4_pld_rw (ci_t * ci, struct sbecom_port_param * pp)
1009 volatile u_int32_t *regaddr;
1010 volatile u_int32_t data;
1011 int regnum = pp->port_mode;
1013 regaddr = (u_int32_t *) ci->cpldbase + regnum;
1014 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
1017 { /* control says this is a register
1019 pp->portP = (u_int8_t) data;
1020 pci_write_32 ((u_int32_t *) regaddr, pp->portStatus);
1021 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
1023 pp->portStatus = (u_int8_t) data;
1027 /* c4_musycc_rw: read or write the musycc register specified
1028 * (modifies use of port_param to non-standard use of struct)
1030 * mcp.RWportnum port number and write indication bit (0x80)
1031 * mcp.offset offset of register
1032 * mcp.value write value going in and read value returning
1035 /* PORT POINT: TX Subchannel Map registers are write-only
1036 * areas within the MUSYCC and always return FF */
1037 /* PORT POINT: regram and reg structures are minorly different and <offset> ioctl
1038 * settings are aligned with the <reg> struct musycc_globalr{} usage.
1039 * Also, regram is separately allocated shared memory, allocated for each port.
1040 * PORT POINT: access offsets of 0x6000 for Msg Cfg Desc Tbl are for 4-port MUSYCC
1041 * only. (An 8-port MUSYCC has 0x16000 offsets for accessing its upper 4 tables.)
1045 c4_musycc_rw (ci_t * ci, struct c4_musycc_param * mcp)
1048 volatile u_int32_t *dph; /* hardware implemented register */
1049 u_int32_t *dpr = 0; /* RAM image of registers for group command
1051 int offset = mcp->offset % 0x800; /* group relative address
1052 * offset, mcp->portnum is
1054 int portnum, ramread = 0;
1055 volatile u_int32_t data;
1058 * Sanity check hardware accessibility. The 0x6000 portion handles port
1059 * numbers associated with Msg Descr Tbl decoding.
1061 portnum = (mcp->offset % 0x6000) / 0x800;
1062 if (portnum >= ci->max_port)
1064 pi = &ci->port[portnum];
1065 if (mcp->offset >= 0x6000)
1066 offset += 0x6000; /* put back in MsgCfgDesc address offset */
1067 dph = (u_int32_t *) ((u_long) pi->reg + offset);
1069 /* read of TX are from RAM image, since hardware returns FF */
1070 dpr = (u_int32_t *) ((u_long) pi->regram + offset);
1071 if (mcp->offset < 0x6000) /* non MsgDesc Tbl accesses might require
1074 if (offset >= 0x200 && offset < 0x380)
1076 if (offset >= 0x10 && offset < 0x200)
1079 /* read register from RAM or hardware, depending... */
1083 //printk ("c4_musycc_rw: RAM addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dpr, data, portnum, offset, ramread); /* RLD DEBUG */
1086 data = pci_read_32 ((u_int32_t *) dph);
1087 //printk ("c4_musycc_rw: REG addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dph, data, portnum, offset, ramread); /* RLD DEBUG */
1091 if (mcp->RWportnum & 0x80)
1092 { /* control says this is a register
1094 if (mcp->value == data)
1095 printk ("%s: musycc grp%d already that value! writing again anyhow.\n",
1096 ci->devname, (mcp->RWportnum & 0x7));
1097 /* write register RAM */
1100 /* write hardware register */
1101 pci_write_32 ((u_int32_t *) dph, mcp->value);
1103 mcp->value = data; /* return the read value (or the 'old
1104 * value', if is write) */
1109 c4_get_port (ci_t * ci, int portnum)
1111 if (portnum >= ci->max_port) /* sanity check */
1114 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
1117 ci->port[portnum].p.portStatus = (u_int8_t) ci->alarmed[portnum];
1118 ci->alarmed[portnum] &= 0xdf;
1119 SD_SEM_GIVE (&ci->sem_wdbusy); /* release per-board hold */
1124 c4_set_port (ci_t * ci, int portnum)
1127 struct sbecom_port_param *pp;
1132 if (portnum >= ci->max_port) /* sanity check */
1135 pi = &ci->port[portnum];
1136 pp = &ci->port[portnum].p;
1137 e1mode = IS_FRAME_ANY_E1 (pp->port_mode);
1138 if (log_level >= LOG_MONITOR2)
1140 printk ("%s: c4_set_port[%d]: entered, e1mode = %x, openchans %d.\n",
1142 portnum, e1mode, pi->openchans);
1145 return EBUSY; /* group needs initialization only for
1146 * first channel of a group */
1148 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
1152 if ((ret = c4_wq_port_init (pi))) /* create/init
1153 * workqueue_struct */
1158 init_comet (ci, pi->cometbase, pp->port_mode, 1 /* clockmaster == true */ , pp->portP);
1159 clck = pci_read_32 ((u_int32_t *) &ci->cpldbase->mclk) & PMCC4_CPLD_MCLK_MASK;
1161 clck |= 1 << portnum;
1163 clck &= 0xf ^ (1 << portnum);
1165 pci_write_32 ((u_int32_t *) &ci->cpldbase->mclk, clck);
1166 pci_write_32 ((u_int32_t *) &ci->cpldbase->mcsr, PMCC4_CPLD_MCSR_IND);
1167 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
1169 /*********************************************************************/
1170 /* ERRATA: If transparent mode is used, do not set OOFMP_DISABLE bit */
1171 /*********************************************************************/
1174 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
1175 MUSYCC_GRCD_TX_ENABLE |
1176 MUSYCC_GRCD_OOFMP_DISABLE |
1177 MUSYCC_GRCD_SF_ALIGN | /* per MUSYCC ERRATA,
1179 MUSYCC_GRCD_COFAIRQ_DISABLE |
1180 MUSYCC_GRCD_MC_ENABLE |
1181 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
1184 __constant_cpu_to_le32 ((e1mode ? 1 : 0) |
1185 MUSYCC_PCD_TXSYNC_RISING |
1186 MUSYCC_PCD_RXSYNC_RISING |
1187 MUSYCC_PCD_RXDATA_RISING);
1189 /* Message length descriptor */
1190 pi->regram->mld = __constant_cpu_to_le32 (max_mru | (max_mru << 16));
1193 for (i = 0; i < 32; i++)
1196 /*** ASSIGNMENT NOTES: ***/
1197 /*** Group's channel ZERO unavailable if E1. ***/
1198 /*** Group's channel 16 unavailable if E1 CAS. ***/
1199 /*** Group's channels 24-31 unavailable if T1. ***/
1201 if (((i == 0) && e1mode) ||
1202 ((i == 16) && ((pp->port_mode == CFG_FRAME_E1CRC_CAS) || (pp->port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
1203 || ((i > 23) && (!e1mode)))
1205 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
1208 pi->tsm[i] = 0x00; /* make tslot available for assignment */
1211 for (i = 0; i < MUSYCC_NCHANS; i++)
1213 pi->regram->ttsm[i] = 0;
1214 pi->regram->rtsm[i] = 0;
1217 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
1218 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
1220 musycc_init_mdt (pi);
1222 pi->group_is_set = 1;
1228 unsigned int max_int = 0;
1231 c4_new_chan (ci_t * ci, int portnum, int channum, void *user)
1237 if (c4_find_chan (channum)) /* a new channel shouldn't already exist */
1240 if (portnum >= ci->max_port) /* sanity check */
1243 pi = &(ci->port[portnum]);
1244 /* find any available channel within this port */
1245 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
1247 ch = pi->chan[gchan];
1248 if (ch && ch->state == UNASSIGNED) /* no assignment is good! */
1251 if (gchan == MUSYCC_NCHANS) /* exhausted table, all were assigned */
1256 /* NOTE: mch_t already cleared during OS_kmalloc() */
1260 ch->channum = channum; /* mark our channel assignment */
1261 ch->p.channum = channum;
1263 ch->p.card = ci->brdno;
1264 ch->p.port = portnum;
1266 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1267 ch->p.idlecode = CFG_CH_FLAG_7E;
1268 ch->p.pad_fill_count = 2;
1269 spin_lock_init (&ch->ch_rxlock);
1270 spin_lock_init (&ch->ch_txlock);
1272 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
1276 if ((ret = c4_wk_chan_init (pi, ch)))
1281 /* save off interface assignments which bound a board */
1282 if (ci->first_if == 0) /* first channel registered is assumed to
1283 * be the lowest channel */
1285 ci->first_if = ci->last_if = user;
1286 ci->first_channum = ci->last_channum = channum;
1290 if (ci->last_channum < channum) /* higher number channel found */
1291 ci->last_channum = channum;
1297 c4_del_chan (int channum)
1301 if (!(ch = c4_find_chan (channum)))
1303 if (ch->state == UP)
1304 musycc_chan_down ((ci_t *) 0, channum);
1305 ch->state = UNASSIGNED;
1308 ch->p.channum = (-1);
1313 c4_del_chan_stats (int channum)
1317 if (!(ch = c4_find_chan (channum)))
1320 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1326 c4_set_chan (int channum, struct sbecom_chan_param * p)
1331 if (!(ch = c4_find_chan (channum)))
1335 if (ch->p.card != p->card ||
1336 ch->p.port != p->port ||
1337 ch->p.channum != p->channum)
1341 if (!(ch->up->group_is_set))
1343 return EIO; /* out of order, SET_PORT command
1344 * required prior to first group's
1345 * SET_CHAN command */
1348 * Check for change of parameter settings in order to invoke closing of
1349 * channel prior to hardware poking.
1352 if (ch->p.status != p->status || ch->p.chan_mode != p->chan_mode ||
1353 ch->p.data_inv != p->data_inv || ch->p.intr_mask != p->intr_mask ||
1354 ch->txd_free < ch->txd_num) /* to clear out queued messages */
1355 x = 1; /* we have a change requested */
1356 for (i = 0; i < 32; i++) /* check for timeslot mapping changes */
1357 if (ch->p.bitmask[i] != p->bitmask[i])
1358 x = 1; /* we have a change requested */
1360 if (x && (ch->state == UP)) /* if change request and channel is
1365 if ((ret = musycc_chan_down ((ci_t *) 0, channum)))
1367 if ((ret = c4_chan_up (ch->up->up, channum)))
1369 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1377 c4_get_chan (int channum, struct sbecom_chan_param * p)
1381 if (!(ch = c4_find_chan (channum)))
1388 c4_get_chan_stats (int channum, struct sbecom_chan_stats * p)
1392 if (!(ch = c4_find_chan (channum)))
1395 p->tx_pending = atomic_read (&ch->tx_pending);
1400 c4_fifo_alloc (mpi_t * pi, int chan, int *len)
1402 int i, l = 0, start = 0, max = 0, maxstart = 0;
1404 for (i = 0; i < 32; i++)
1406 if (pi->fifomap[i] != -1)
1423 if (log_level >= LOG_WARN)
1425 "%s: wanted to allocate %d fifo space, but got only %d\n",
1426 pi->up->devname, *len, max);
1429 if (log_level >= LOG_DEBUG)
1430 printk ("%s: allocated %d fifo at %d for channel %d/%d\n",
1431 pi->up->devname, max, start, chan, pi->p.portnum);
1432 for (i = maxstart; i < (maxstart + max); i++)
1433 pi->fifomap[i] = chan;
1438 c4_fifo_free (mpi_t * pi, int chan)
1442 if (log_level >= LOG_DEBUG)
1443 printk ("%s: deallocated fifo for channel %d/%d\n",
1444 pi->up->devname, chan, pi->p.portnum);
1445 for (i = 0; i < 32; i++)
1446 if (pi->fifomap[i] == chan)
1447 pi->fifomap[i] = -1;
1452 c4_chan_up (ci_t * ci, int channum)
1458 int nts, nbuf, txnum, rxnum;
1459 int addr, i, j, gchan;
1460 u_int32_t tmp; /* for optimizing conversion across BE
1463 if (!(ch = c4_find_chan (channum)))
1465 if (ch->state == UP)
1467 if (log_level >= LOG_MONITOR)
1468 printk ("%s: channel already UP, graceful early exit\n", ci->devname);
1473 /* find nts ('number of timeslots') */
1475 for (i = 0; i < 32; i++)
1477 if (ch->p.bitmask[i] & pi->tsm[i])
1479 if (1 || log_level >= LOG_WARN)
1481 printk ("%s: c4_chan_up[%d] EINVAL (attempt to cfg in-use or unavailable TimeSlot[%d])\n",
1482 ci->devname, channum, i);
1483 printk ("+ ask4 %x, currently %x\n", ch->p.bitmask[i], pi->tsm[i]);
1487 for (j = 0; j < 8; j++)
1488 if (ch->p.bitmask[i] & (1 << j))
1492 nbuf = nts / 8 ? nts / 8 : 1;
1495 /* if( log_level >= LOG_WARN) */
1496 printk ("%s: c4_chan_up[%d] ENOBUFS (no TimeSlots assigned)\n", ci->devname, channum);
1497 return ENOBUFS; /* this should not happen */
1499 addr = c4_fifo_alloc (pi, gchan, &nbuf);
1502 /* Setup the Time Slot Map */
1503 musycc_update_timeslots (pi);
1505 /* ch->tx_limit = nts; */
1506 ch->s.tx_pending = 0;
1508 /* Set Channel Configuration Descriptors */
1512 ccd = musycc_chan_proto (ch->p.chan_mode) << MUSYCC_CCD_PROTO_SHIFT;
1513 if ((ch->p.chan_mode == CFG_CH_PROTO_ISLP_MODE) ||
1514 (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1516 ccd |= MUSYCC_CCD_FCS_XFER; /* Non FSC Mode */
1518 ccd |= 2 << MUSYCC_CCD_MAX_LENGTH; /* Select second MTU */
1519 ccd |= ch->p.intr_mask;
1520 ccd |= addr << MUSYCC_CCD_BUFFER_LOC;
1521 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1522 ccd |= (nbuf) << MUSYCC_CCD_BUFFER_LENGTH;
1524 ccd |= (nbuf - 1) << MUSYCC_CCD_BUFFER_LENGTH;
1526 if (ch->p.data_inv & CFG_CH_DINV_TX)
1527 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1528 pi->regram->tcct[gchan] = cpu_to_le32 (ccd);
1530 if (ch->p.data_inv & CFG_CH_DINV_RX)
1531 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1533 ccd &= ~MUSYCC_CCD_INVERT_DATA; /* take away data inversion */
1534 pi->regram->rcct[gchan] = cpu_to_le32 (ccd);
1538 /* Reread the Channel Configuration Descriptor for this channel */
1539 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_RX_DIRECTION | gchan);
1540 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_TX_DIRECTION | gchan);
1543 * Figure out how many buffers we want. If the customer has changed from
1544 * the defaults, then use the changed values. Otherwise, use Transparent
1545 * mode's specific minimum default settings.
1547 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1549 if (max_rxdesc_used == max_rxdesc_default) /* use default setting */
1550 max_rxdesc_used = MUSYCC_RXDESC_TRANS;
1551 if (max_txdesc_used == max_txdesc_default) /* use default setting */
1552 max_txdesc_used = MUSYCC_TXDESC_TRANS;
1555 * Increase counts when hyperchanneling, since this implies an increase
1556 * in throughput per channel
1558 rxnum = max_rxdesc_used + (nts / 4);
1559 txnum = max_txdesc_used + (nts / 4);
1563 if (log_level >= LOG_MONITOR)
1564 printk ("%s: mode %x rxnum %d (rxused %d def %d) txnum %d (txused %d def %d)\n",
1565 ci->devname, ch->p.chan_mode,
1566 rxnum, max_rxdesc_used, max_rxdesc_default,
1567 txnum, max_txdesc_used, max_txdesc_default);
1570 ch->rxd_num = rxnum;
1571 ch->txd_num = txnum;
1572 ch->rxix_irq_srv = 0;
1574 ch->mdr = OS_kmalloc (sizeof (struct mdesc) * rxnum);
1575 ch->mdt = OS_kmalloc (sizeof (struct mdesc) * txnum);
1576 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1577 tmp = __constant_cpu_to_le32 (max_mru | EOBIRQ_ENABLE);
1579 tmp = __constant_cpu_to_le32 (max_mru);
1581 for (i = 0, md = ch->mdr; i < rxnum; i++, md++)
1583 if (i == (rxnum - 1))
1585 md->snext = &ch->mdr[0];/* wrapness */
1588 md->snext = &ch->mdr[i + 1];
1590 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1592 if (!(m = OS_mem_token_alloc (max_mru)))
1594 if (log_level >= LOG_MONITOR)
1595 printk ("%s: c4_chan_up[%d] - token alloc failure, size = %d.\n", ci->devname, channum, max_mru);
1599 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m)));
1600 md->status = tmp | MUSYCC_RX_OWNED; /* MUSYCC owns RX descriptor **
1602 * MUSYCC_RX_OWNED = 0 so no
1603 * need to byteSwap */
1606 for (i = 0, md = ch->mdt; i < txnum; i++, md++)
1608 md->status = HOST_TX_OWNED; /* Host owns TX descriptor ** CODING
1609 * NOTE: HOST_TX_OWNED = 0 so no need to
1613 if (i == (txnum - 1))
1615 md->snext = &ch->mdt[0];/* wrapness */
1618 md->snext = &ch->mdt[i + 1];
1620 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1622 ch->txd_irq_srv = ch->txd_usr_add = &ch->mdt[0];
1623 ch->txd_free = txnum;
1625 ch->txd_required = 0;
1627 /* Configure it into the chip */
1628 tmp = cpu_to_le32 (OS_vtophys (&ch->mdt[0]));
1629 pi->regram->thp[gchan] = tmp;
1630 pi->regram->tmp[gchan] = tmp;
1632 tmp = cpu_to_le32 (OS_vtophys (&ch->mdr[0]));
1633 pi->regram->rhp[gchan] = tmp;
1634 pi->regram->rmp[gchan] = tmp;
1636 /* Activate the Channel */
1638 if (ch->p.status & RX_ENABLED)
1640 #ifdef RLD_TRANS_DEBUG
1641 printk ("++ c4_chan_up() CHAN RX ACTIVATE: chan %d\n", ch->channum);
1643 ch->ch_start_rx = 0; /* we are restarting RX... */
1644 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
1646 if (ch->p.status & TX_ENABLED)
1648 #ifdef RLD_TRANS_DEBUG
1649 printk ("++ c4_chan_up() CHAN TX ACTIVATE: chan %d <delayed>\n", ch->channum);
1651 ch->ch_start_tx = CH_START_TX_1ST; /* we are delaying start
1652 * until receipt from user of
1653 * first packet to transmit. */
1655 ch->status = ch->p.status;
1662 /* Don't leak all the previously allocated mbufs in this loop */
1664 OS_mem_token_free (ch->mdr[i].mem_token);
1676 /* stop the hardware from servicing & interrupting */
1679 c4_stopwd (ci_t * ci)
1681 OS_stop_watchdog (&ci->wd);
1682 SD_SEM_TAKE (&ci->sem_wdbusy, "_stop_"); /* ensure WD not running */
1683 SD_SEM_GIVE (&ci->sem_wdbusy);
1688 sbecom_get_brdinfo (ci_t * ci, struct sbe_brd_info * bip, u_int8_t *bsn)
1694 bip->brdno = ci->brdno; /* our board number */
1695 bip->brd_id = ci->brd_id;
1696 bip->brd_hdw_id = ci->hdw_bid;
1697 bip->brd_chan_cnt = MUSYCC_NCHANS * ci->max_port; /* number of channels
1699 bip->brd_port_cnt = ci->max_port; /* number of ports being used */
1700 bip->brd_pci_speed = BINFO_PCI_SPEED_unk; /* PCI speed not yet
1705 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1706 np = (char *) hdlc_to_name (ci->first_if);
1709 struct net_device *dev;
1711 dev = (struct net_device *) ci->first_if;
1712 np = (char *) dev->name;
1715 strncpy (bip->first_iname, np, CHNM_STRLEN - 1);
1717 strcpy (bip->first_iname, "<NULL>");
1720 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1721 np = (char *) hdlc_to_name (ci->last_if);
1724 struct net_device *dev;
1726 dev = (struct net_device *) ci->last_if;
1727 np = (char *) dev->name;
1730 strncpy (bip->last_iname, np, CHNM_STRLEN - 1);
1732 strcpy (bip->last_iname, "<NULL>");
1736 for (i = 0; i < 3; i++)
1738 bip->brd_mac_addr[i] = *bsn++;
1742 bip->brd_mac_addr[i] = *bsn;
1743 sn = (sn << 8) | *bsn++;
1747 for (i = 0; i < 6; i++)
1748 bip->brd_mac_addr[i] = 0;
1755 c4_get_iidinfo (ci_t * ci, struct sbe_iid_info * iip)
1757 struct net_device *dev;
1760 if (!(dev = getuserbychan (iip->channum)))
1763 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1764 np = (char *) hdlc_to_name (dev_to_hdlc (dev));
1768 strncpy (iip->iname, np, CHNM_STRLEN - 1);
1773 #ifdef CONFIG_SBE_PMCC4_NCOMM
1774 void (*nciInterrupt[MAX_BOARDS][4]) (void);
1775 extern void wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler);
1778 wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler)
1780 if (cardID < MAX_BOARDS) /* sanity check */
1781 nciInterrupt[cardID][deviceID] = handler;
1785 c4_ebus_intr_th_handler (void *devp)
1787 ci_t *ci = (ci_t *) devp;
1788 volatile u_int32_t ists;
1792 /* which COMET caused the interrupt */
1794 ists = pci_read_32 ((u_int32_t *) &ci->cpldbase->intr);
1795 if (ists & PMCC4_CPLD_INTR_CMT_1)
1798 if (nciInterrupt[brdno][0] != NULL)
1799 (*nciInterrupt[brdno][0]) ();
1801 if (ists & PMCC4_CPLD_INTR_CMT_2)
1804 if (nciInterrupt[brdno][1] != NULL)
1805 (*nciInterrupt[brdno][1]) ();
1807 if (ists & PMCC4_CPLD_INTR_CMT_3)
1810 if (nciInterrupt[brdno][2] != NULL)
1811 (*nciInterrupt[brdno][2]) ();
1813 if (ists & PMCC4_CPLD_INTR_CMT_4)
1816 if (nciInterrupt[brdno][3] != NULL)
1817 (*nciInterrupt[brdno][3]) ();
1820 /*** Test code just de-implements the asserted interrupt. Alternate
1821 vendor will supply COMET interrupt handling code herein or such.
1823 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
1826 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,20)
1829 return IRQ_RETVAL (handled);
1835 wanpmcC4T1E1_getBaseAddress (int cardID, int deviceID)
1838 unsigned long base = 0;
1843 if (ci->brdno == cardID) /* found valid device */
1845 if (deviceID < ci->max_port) /* comet is supported */
1846 base = ((unsigned long) ci->port[deviceID].cometbase);
1849 ci = ci->next; /* next board, if any */
1854 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
1857 /*** End-of-File ***/