2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/bug.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/delay.h>
23 #include <linux/irq.h>
24 #include <linux/device.h>
25 #include <linux/spi/spi.h>
26 #include <linux/spi/spi_bitbang.h>
27 #include <linux/platform_device.h>
28 #include <linux/fsl_devices.h>
30 #include <linux/of_platform.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_spi.h>
35 #include <sysdev/fsl_soc.h>
39 /* SPI Controller registers */
40 struct mpc83xx_spi_reg {
50 /* SPI Controller mode register definitions */
51 #define SPMODE_LOOP (1 << 30)
52 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
53 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
54 #define SPMODE_DIV16 (1 << 27)
55 #define SPMODE_REV (1 << 26)
56 #define SPMODE_MS (1 << 25)
57 #define SPMODE_ENABLE (1 << 24)
58 #define SPMODE_LEN(x) ((x) << 20)
59 #define SPMODE_PM(x) ((x) << 16)
60 #define SPMODE_OP (1 << 14)
61 #define SPMODE_CG(x) ((x) << 7)
64 * Default for SPI Mode:
65 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
67 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
68 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
70 /* SPIE register values */
71 #define SPIE_NE 0x00000200 /* Not empty */
72 #define SPIE_NF 0x00000100 /* Not full */
74 /* SPIM register values */
75 #define SPIM_NE 0x00000200 /* Not empty */
76 #define SPIM_NF 0x00000100 /* Not full */
78 /* SPI Controller driver's private data. */
80 struct mpc83xx_spi_reg __iomem *base;
82 /* rx & tx bufs from the spi_transfer */
86 /* functions to deal with different sized buffers */
87 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
88 u32(*get_tx) (struct mpc83xx_spi *);
93 unsigned nsecs; /* (clock cycle time)/2 */
95 u32 spibrg; /* SPIBRG input clock */
96 u32 rx_shift; /* RX data reg shift when in qe mode */
97 u32 tx_shift; /* TX data reg shift when in qe mode */
103 struct workqueue_struct *workqueue;
104 struct work_struct work;
106 struct list_head queue;
109 struct completion done;
112 struct spi_mpc83xx_cs {
113 /* functions to deal with different sized buffers */
114 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
115 u32 (*get_tx) (struct mpc83xx_spi *);
116 u32 rx_shift; /* RX data reg shift when in qe mode */
117 u32 tx_shift; /* TX data reg shift when in qe mode */
118 u32 hw_mode; /* Holds HW mode register settings */
121 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
126 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
131 #define MPC83XX_SPI_RX_BUF(type) \
133 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
135 type * rx = mpc83xx_spi->rx; \
136 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
137 mpc83xx_spi->rx = rx; \
140 #define MPC83XX_SPI_TX_BUF(type) \
142 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
145 const type * tx = mpc83xx_spi->tx; \
148 data = *tx++ << mpc83xx_spi->tx_shift; \
149 mpc83xx_spi->tx = tx; \
153 MPC83XX_SPI_RX_BUF(u8)
154 MPC83XX_SPI_RX_BUF(u16)
155 MPC83XX_SPI_RX_BUF(u32)
156 MPC83XX_SPI_TX_BUF(u8)
157 MPC83XX_SPI_TX_BUF(u16)
158 MPC83XX_SPI_TX_BUF(u32)
160 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
162 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
163 struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
164 bool pol = spi->mode & SPI_CS_HIGH;
165 struct spi_mpc83xx_cs *cs = spi->controller_state;
167 if (value == BITBANG_CS_INACTIVE) {
168 if (pdata->cs_control)
169 pdata->cs_control(spi, !pol);
172 if (value == BITBANG_CS_ACTIVE) {
173 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
175 mpc83xx_spi->rx_shift = cs->rx_shift;
176 mpc83xx_spi->tx_shift = cs->tx_shift;
177 mpc83xx_spi->get_rx = cs->get_rx;
178 mpc83xx_spi->get_tx = cs->get_tx;
180 if (cs->hw_mode != regval) {
182 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
184 regval = cs->hw_mode;
185 /* Turn off IRQs locally to minimize time that
188 local_irq_save(flags);
189 /* Turn off SPI unit prior changing mode */
190 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
191 mpc83xx_spi_write_reg(mode, regval);
192 local_irq_restore(flags);
194 if (pdata->cs_control)
195 pdata->cs_control(spi, pol);
200 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
202 struct mpc83xx_spi *mpc83xx_spi;
204 u8 bits_per_word, pm;
206 struct spi_mpc83xx_cs *cs = spi->controller_state;
208 mpc83xx_spi = spi_master_get_devdata(spi->master);
211 bits_per_word = t->bits_per_word;
218 /* spi_transfer level calls that work per-word */
220 bits_per_word = spi->bits_per_word;
222 /* Make sure its a bit width we support [4..16, 32] */
223 if ((bits_per_word < 4)
224 || ((bits_per_word > 16) && (bits_per_word != 32)))
228 hz = spi->max_speed_hz;
232 if (bits_per_word <= 8) {
233 cs->get_rx = mpc83xx_spi_rx_buf_u8;
234 cs->get_tx = mpc83xx_spi_tx_buf_u8;
235 if (mpc83xx_spi->qe_mode) {
239 } else if (bits_per_word <= 16) {
240 cs->get_rx = mpc83xx_spi_rx_buf_u16;
241 cs->get_tx = mpc83xx_spi_tx_buf_u16;
242 if (mpc83xx_spi->qe_mode) {
246 } else if (bits_per_word <= 32) {
247 cs->get_rx = mpc83xx_spi_rx_buf_u32;
248 cs->get_tx = mpc83xx_spi_tx_buf_u32;
252 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
254 if (bits_per_word <= 8)
260 mpc83xx_spi->rx_shift = cs->rx_shift;
261 mpc83xx_spi->tx_shift = cs->tx_shift;
262 mpc83xx_spi->get_rx = cs->get_rx;
263 mpc83xx_spi->get_tx = cs->get_tx;
265 if (bits_per_word == 32)
268 bits_per_word = bits_per_word - 1;
270 /* mask out bits we are going to set */
271 cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
274 cs->hw_mode |= SPMODE_LEN(bits_per_word);
276 if ((mpc83xx_spi->spibrg / hz) > 64) {
277 cs->hw_mode |= SPMODE_DIV16;
278 pm = mpc83xx_spi->spibrg / (hz * 64);
280 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
281 "Will use %d Hz instead.\n", dev_name(&spi->dev),
282 hz, mpc83xx_spi->spibrg / 1024);
286 pm = mpc83xx_spi->spibrg / (hz * 4);
290 cs->hw_mode |= SPMODE_PM(pm);
291 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
292 if (cs->hw_mode != regval) {
294 __be32 __iomem *mode = &mpc83xx_spi->base->mode;
296 regval = cs->hw_mode;
297 /* Turn off IRQs locally to minimize time
298 * that SPI is disabled
300 local_irq_save(flags);
301 /* Turn off SPI unit prior changing mode */
302 mpc83xx_spi_write_reg(mode, regval & ~SPMODE_ENABLE);
303 mpc83xx_spi_write_reg(mode, regval);
304 local_irq_restore(flags);
309 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
311 struct mpc83xx_spi *mpc83xx_spi;
312 u32 word, len, bits_per_word;
314 mpc83xx_spi = spi_master_get_devdata(spi->master);
316 mpc83xx_spi->tx = t->tx_buf;
317 mpc83xx_spi->rx = t->rx_buf;
318 bits_per_word = spi->bits_per_word;
319 if (t->bits_per_word)
320 bits_per_word = t->bits_per_word;
322 if (bits_per_word > 8) {
323 /* invalid length? */
328 if (bits_per_word > 16) {
329 /* invalid length? */
334 mpc83xx_spi->count = len;
336 INIT_COMPLETION(mpc83xx_spi->done);
339 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
342 word = mpc83xx_spi->get_tx(mpc83xx_spi);
343 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
345 wait_for_completion(&mpc83xx_spi->done);
347 /* disable rx ints */
348 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
350 return mpc83xx_spi->count;
353 static void mpc83xx_spi_work(struct work_struct *work)
355 struct mpc83xx_spi *mpc83xx_spi =
356 container_of(work, struct mpc83xx_spi, work);
358 spin_lock_irq(&mpc83xx_spi->lock);
359 mpc83xx_spi->busy = 1;
360 while (!list_empty(&mpc83xx_spi->queue)) {
361 struct spi_message *m;
362 struct spi_device *spi;
363 struct spi_transfer *t = NULL;
365 int status, nsecs = 50;
367 m = container_of(mpc83xx_spi->queue.next,
368 struct spi_message, queue);
369 list_del_init(&m->queue);
370 spin_unlock_irq(&mpc83xx_spi->lock);
375 list_for_each_entry(t, &m->transfers, transfer_list) {
376 if (t->bits_per_word || t->speed_hz) {
377 /* Don't allow changes if CS is active */
381 status = mpc83xx_spi_setup_transfer(spi, t);
387 mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
388 cs_change = t->cs_change;
390 status = mpc83xx_spi_bufs(spi, t);
395 m->actual_length += t->len;
398 udelay(t->delay_usecs);
402 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
408 m->complete(m->context);
410 if (status || !cs_change) {
412 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
415 mpc83xx_spi_setup_transfer(spi, NULL);
417 spin_lock_irq(&mpc83xx_spi->lock);
419 mpc83xx_spi->busy = 0;
420 spin_unlock_irq(&mpc83xx_spi->lock);
423 static int mpc83xx_spi_setup(struct spi_device *spi)
425 struct mpc83xx_spi *mpc83xx_spi;
428 struct spi_mpc83xx_cs *cs = spi->controller_state;
430 if (!spi->max_speed_hz)
434 cs = kzalloc(sizeof *cs, GFP_KERNEL);
437 spi->controller_state = cs;
439 mpc83xx_spi = spi_master_get_devdata(spi->master);
441 hw_mode = cs->hw_mode; /* Save orginal settings */
442 cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
443 /* mask out bits we are going to set */
444 cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
445 | SPMODE_REV | SPMODE_LOOP);
447 if (spi->mode & SPI_CPHA)
448 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
449 if (spi->mode & SPI_CPOL)
450 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
451 if (!(spi->mode & SPI_LSB_FIRST))
452 cs->hw_mode |= SPMODE_REV;
453 if (spi->mode & SPI_LOOP)
454 cs->hw_mode |= SPMODE_LOOP;
456 retval = mpc83xx_spi_setup_transfer(spi, NULL);
458 cs->hw_mode = hw_mode; /* Restore settings */
462 #if 0 /* Don't think this is needed */
463 /* NOTE we _need_ to call chipselect() early, ideally with adapter
464 * setup, unless the hardware defaults cooperate to avoid confusion
465 * between normal (active low) and inverted chipselects.
468 /* deselect chip (low or high) */
469 spin_lock(&mpc83xx_spi->lock);
470 if (!mpc83xx_spi->busy)
471 mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
472 spin_unlock(&mpc83xx_spi->lock);
477 static irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
479 struct mpc83xx_spi *mpc83xx_spi = context_data;
481 irqreturn_t ret = IRQ_NONE;
483 /* Get interrupt events(tx/rx) */
484 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
486 /* We need handle RX first */
487 if (event & SPIE_NE) {
488 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
491 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
496 if ((event & SPIE_NF) == 0)
497 /* spin until TX is done */
499 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
503 mpc83xx_spi->count -= 1;
504 if (mpc83xx_spi->count) {
505 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
506 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
508 complete(&mpc83xx_spi->done);
511 /* Clear the events */
512 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
516 static int mpc83xx_spi_transfer(struct spi_device *spi,
517 struct spi_message *m)
519 struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
522 m->actual_length = 0;
523 m->status = -EINPROGRESS;
525 spin_lock_irqsave(&mpc83xx_spi->lock, flags);
526 list_add_tail(&m->queue, &mpc83xx_spi->queue);
527 queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
528 spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
534 static void mpc83xx_spi_cleanup(struct spi_device *spi)
536 kfree(spi->controller_state);
539 static struct spi_master * __devinit
540 mpc83xx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
542 struct fsl_spi_platform_data *pdata = dev->platform_data;
543 struct spi_master *master;
544 struct mpc83xx_spi *mpc83xx_spi;
548 master = spi_alloc_master(dev, sizeof(struct mpc83xx_spi));
549 if (master == NULL) {
554 dev_set_drvdata(dev, master);
556 /* the spi->mode bits understood by this driver: */
557 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
558 | SPI_LSB_FIRST | SPI_LOOP;
560 master->setup = mpc83xx_spi_setup;
561 master->transfer = mpc83xx_spi_transfer;
562 master->cleanup = mpc83xx_spi_cleanup;
564 mpc83xx_spi = spi_master_get_devdata(master);
565 mpc83xx_spi->qe_mode = pdata->qe_mode;
566 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
567 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
568 mpc83xx_spi->spibrg = pdata->sysclk;
570 mpc83xx_spi->rx_shift = 0;
571 mpc83xx_spi->tx_shift = 0;
572 if (mpc83xx_spi->qe_mode) {
573 mpc83xx_spi->rx_shift = 16;
574 mpc83xx_spi->tx_shift = 24;
577 init_completion(&mpc83xx_spi->done);
579 mpc83xx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
580 if (mpc83xx_spi->base == NULL) {
585 mpc83xx_spi->irq = irq;
587 /* Register for SPI Interrupt */
588 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
589 0, "mpc83xx_spi", mpc83xx_spi);
594 master->bus_num = pdata->bus_num;
595 master->num_chipselect = pdata->max_chipselect;
597 /* SPI controller initializations */
598 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
599 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
600 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
601 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
603 /* Enable SPI interface */
604 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
608 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
609 spin_lock_init(&mpc83xx_spi->lock);
610 init_completion(&mpc83xx_spi->done);
611 INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
612 INIT_LIST_HEAD(&mpc83xx_spi->queue);
614 mpc83xx_spi->workqueue = create_singlethread_workqueue(
615 dev_name(master->dev.parent));
616 if (mpc83xx_spi->workqueue == NULL) {
621 ret = spi_register_master(master);
626 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
627 dev_name(dev), mpc83xx_spi->base, mpc83xx_spi->irq);
632 destroy_workqueue(mpc83xx_spi->workqueue);
634 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
636 iounmap(mpc83xx_spi->base);
638 spi_master_put(master);
643 static int __devexit mpc83xx_spi_remove(struct device *dev)
645 struct mpc83xx_spi *mpc83xx_spi;
646 struct spi_master *master;
648 master = dev_get_drvdata(dev);
649 mpc83xx_spi = spi_master_get_devdata(master);
651 flush_workqueue(mpc83xx_spi->workqueue);
652 destroy_workqueue(mpc83xx_spi->workqueue);
653 spi_unregister_master(master);
655 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
656 iounmap(mpc83xx_spi->base);
661 struct mpc83xx_spi_probe_info {
662 struct fsl_spi_platform_data pdata;
667 static struct mpc83xx_spi_probe_info *
668 to_of_pinfo(struct fsl_spi_platform_data *pdata)
670 return container_of(pdata, struct mpc83xx_spi_probe_info, pdata);
673 static void mpc83xx_spi_cs_control(struct spi_device *spi, bool on)
675 struct device *dev = spi->dev.parent;
676 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
677 u16 cs = spi->chip_select;
678 int gpio = pinfo->gpios[cs];
679 bool alow = pinfo->alow_flags[cs];
681 gpio_set_value(gpio, on ^ alow);
684 static int of_mpc83xx_spi_get_chipselects(struct device *dev)
686 struct device_node *np = dev_archdata_get_node(&dev->archdata);
687 struct fsl_spi_platform_data *pdata = dev->platform_data;
688 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
693 ngpios = of_gpio_count(np);
696 * SPI w/o chip-select line. One SPI device is still permitted
699 pdata->max_chipselect = 1;
703 pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
706 memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
708 pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
710 if (!pinfo->alow_flags) {
712 goto err_alloc_flags;
715 for (; i < ngpios; i++) {
717 enum of_gpio_flags flags;
719 gpio = of_get_gpio_flags(np, i, &flags);
720 if (!gpio_is_valid(gpio)) {
721 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
725 ret = gpio_request(gpio, dev_name(dev));
727 dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
731 pinfo->gpios[i] = gpio;
732 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
734 ret = gpio_direction_output(pinfo->gpios[i],
735 pinfo->alow_flags[i]);
737 dev_err(dev, "can't set output direction for gpio "
738 "#%d: %d\n", i, ret);
743 pdata->max_chipselect = ngpios;
744 pdata->cs_control = mpc83xx_spi_cs_control;
750 if (gpio_is_valid(pinfo->gpios[i]))
751 gpio_free(pinfo->gpios[i]);
755 kfree(pinfo->alow_flags);
756 pinfo->alow_flags = NULL;
763 static int of_mpc83xx_spi_free_chipselects(struct device *dev)
765 struct fsl_spi_platform_data *pdata = dev->platform_data;
766 struct mpc83xx_spi_probe_info *pinfo = to_of_pinfo(pdata);
772 for (i = 0; i < pdata->max_chipselect; i++) {
773 if (gpio_is_valid(pinfo->gpios[i]))
774 gpio_free(pinfo->gpios[i]);
778 kfree(pinfo->alow_flags);
782 static int __devinit of_mpc83xx_spi_probe(struct of_device *ofdev,
783 const struct of_device_id *ofid)
785 struct device *dev = &ofdev->dev;
786 struct device_node *np = ofdev->node;
787 struct mpc83xx_spi_probe_info *pinfo;
788 struct fsl_spi_platform_data *pdata;
789 struct spi_master *master;
795 pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
799 pdata = &pinfo->pdata;
800 dev->platform_data = pdata;
802 /* Allocate bus num dynamically. */
805 /* SPI controller is either clocked from QE or SoC clock. */
806 pdata->sysclk = get_brgfreq();
807 if (pdata->sysclk == -1) {
808 pdata->sysclk = fsl_get_sys_freq();
809 if (pdata->sysclk == -1) {
815 prop = of_get_property(np, "mode", NULL);
816 if (prop && !strcmp(prop, "cpu-qe"))
819 ret = of_mpc83xx_spi_get_chipselects(dev);
823 ret = of_address_to_resource(np, 0, &mem);
827 ret = of_irq_to_resource(np, 0, &irq);
833 master = mpc83xx_spi_probe(dev, &mem, irq.start);
834 if (IS_ERR(master)) {
835 ret = PTR_ERR(master);
839 of_register_spi_devices(master, np);
844 of_mpc83xx_spi_free_chipselects(dev);
850 static int __devexit of_mpc83xx_spi_remove(struct of_device *ofdev)
854 ret = mpc83xx_spi_remove(&ofdev->dev);
857 of_mpc83xx_spi_free_chipselects(&ofdev->dev);
861 static const struct of_device_id of_mpc83xx_spi_match[] = {
862 { .compatible = "fsl,spi" },
865 MODULE_DEVICE_TABLE(of, of_mpc83xx_spi_match);
867 static struct of_platform_driver of_mpc83xx_spi_driver = {
868 .name = "mpc83xx_spi",
869 .match_table = of_mpc83xx_spi_match,
870 .probe = of_mpc83xx_spi_probe,
871 .remove = __devexit_p(of_mpc83xx_spi_remove),
874 #ifdef CONFIG_MPC832x_RDB
877 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
878 * only. The driver should go away soon, since newer MPC8323E-RDB's device
879 * tree can work with OpenFirmware driver. But for now we support old trees
882 static int __devinit plat_mpc83xx_spi_probe(struct platform_device *pdev)
884 struct resource *mem;
886 struct spi_master *master;
888 if (!pdev->dev.platform_data)
891 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
895 irq = platform_get_irq(pdev, 0);
899 master = mpc83xx_spi_probe(&pdev->dev, mem, irq);
901 return PTR_ERR(master);
905 static int __devexit plat_mpc83xx_spi_remove(struct platform_device *pdev)
907 return mpc83xx_spi_remove(&pdev->dev);
910 MODULE_ALIAS("platform:mpc83xx_spi");
911 static struct platform_driver mpc83xx_spi_driver = {
912 .probe = plat_mpc83xx_spi_probe,
913 .remove = __exit_p(plat_mpc83xx_spi_remove),
915 .name = "mpc83xx_spi",
916 .owner = THIS_MODULE,
920 static bool legacy_driver_failed;
922 static void __init legacy_driver_register(void)
924 legacy_driver_failed = platform_driver_register(&mpc83xx_spi_driver);
927 static void __exit legacy_driver_unregister(void)
929 if (legacy_driver_failed)
931 platform_driver_unregister(&mpc83xx_spi_driver);
934 static void __init legacy_driver_register(void) {}
935 static void __exit legacy_driver_unregister(void) {}
936 #endif /* CONFIG_MPC832x_RDB */
938 static int __init mpc83xx_spi_init(void)
940 legacy_driver_register();
941 return of_register_platform_driver(&of_mpc83xx_spi_driver);
944 static void __exit mpc83xx_spi_exit(void)
946 of_unregister_platform_driver(&of_mpc83xx_spi_driver);
947 legacy_driver_unregister();
950 module_init(mpc83xx_spi_init);
951 module_exit(mpc83xx_spi_exit);
953 MODULE_AUTHOR("Kumar Gala");
954 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
955 MODULE_LICENSE("GPL");