SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/spi_imx.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 Juergen Beisert
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation
  17  * 51 Franklin Street, Fifth Floor
  18  * Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/gpio.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/types.h>
  36
  37 #include <mach/spi.h>
  38
  39 #define DRIVER_NAME "spi_imx"
  40
  41 #define MXC_CSPIRXDATA          0x00
  42 #define MXC_CSPITXDATA          0x04
  43 #define MXC_CSPICTRL            0x08
  44 #define MXC_CSPIINT             0x0c
  45 #define MXC_RESET               0x1c
  46
  47 /* generic defines to abstract from the different register layouts */
  48 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  49 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  50
  51 struct spi_imx_config {
  52         unsigned int speed_hz;
  53         unsigned int bpw;
  54         unsigned int mode;
  55         int cs;
  56 };
  57
  58 struct spi_imx_data {
  59         struct spi_bitbang bitbang;
  60
  61         struct completion xfer_done;
  62         void *base;
  63         int irq;
  64         struct clk *clk;
  65         unsigned long spi_clk;
  66         int *chipselect;
  67
  68         unsigned int count;
  69         void (*tx)(struct spi_imx_data *);
  70         void (*rx)(struct spi_imx_data *);
  71         void *rx_buf;
  72         const void *tx_buf;
  73         unsigned int txfifo; /* number of words pushed in tx FIFO */
  74
  75         /* SoC specific functions */
  76         void (*intctrl)(struct spi_imx_data *, int);
  77         int (*config)(struct spi_imx_data *, struct spi_imx_config *);
  78         void (*trigger)(struct spi_imx_data *);
  79         int (*rx_available)(struct spi_imx_data *);
  80 };
  81
  82 #define MXC_SPI_BUF_RX(type)                                            \
  83 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
  84 {                                                                       \
  85         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
  86                                                                         \
  87         if (spi_imx->rx_buf) {                                          \
  88                 *(type *)spi_imx->rx_buf = val;                         \
  89                 spi_imx->rx_buf += sizeof(type);                        \
  90         }                                                               \
  91 }
  92
  93 #define MXC_SPI_BUF_TX(type)                                            \
  94 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
  95 {                                                                       \
  96         type val = 0;                                                   \
  97                                                                         \
  98         if (spi_imx->tx_buf) {                                          \
  99                 val = *(type *)spi_imx->tx_buf;                         \
 100                 spi_imx->tx_buf += sizeof(type);                        \
 101         }                                                               \
 102                                                                         \
 103         spi_imx->count -= sizeof(type);                                 \
 104                                                                         \
 105         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 106 }
 107
 108 MXC_SPI_BUF_RX(u8)
 109 MXC_SPI_BUF_TX(u8)
 110 MXC_SPI_BUF_RX(u16)
 111 MXC_SPI_BUF_TX(u16)
 112 MXC_SPI_BUF_RX(u32)
 113 MXC_SPI_BUF_TX(u32)
 114
 115 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 116  * (which is currently not the case in this driver)
 117  */
 118 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 119         256, 384, 512, 768, 1024};
 120
 121 /* MX21, MX27 */
 122 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 123                 unsigned int fspi)
 124 {
 125         int i, max;
 126
 127         if (cpu_is_mx21())
 128                 max = 18;
 129         else
 130                 max = 16;
 131
 132         for (i = 2; i < max; i++)
 133                 if (fspi * mxc_clkdivs[i] >= fin)
 134                         return i;
 135
 136         return max;
 137 }
 138
 139 /* MX1, MX31, MX35 */
 140 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 141                 unsigned int fspi)
 142 {
 143         int i, div = 4;
 144
 145         for (i = 0; i < 7; i++) {
 146                 if (fspi * div >= fin)
 147                         return i;
 148                 div <<= 1;
 149         }
 150
 151         return 7;
 152 }
 153
 154 #define MX31_INTREG_TEEN        (1 << 0)
 155 #define MX31_INTREG_RREN        (1 << 3)
 156
 157 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 158 #define MX31_CSPICTRL_MASTER    (1 << 1)
 159 #define MX31_CSPICTRL_XCH       (1 << 2)
 160 #define MX31_CSPICTRL_POL       (1 << 4)
 161 #define MX31_CSPICTRL_PHA       (1 << 5)
 162 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 163 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 164 #define MX31_CSPICTRL_BC_SHIFT  8
 165 #define MX35_CSPICTRL_BL_SHIFT  20
 166 #define MX31_CSPICTRL_CS_SHIFT  24
 167 #define MX35_CSPICTRL_CS_SHIFT  12
 168 #define MX31_CSPICTRL_DR_SHIFT  16
 169
 170 #define MX31_CSPISTATUS         0x14
 171 #define MX31_STATUS_RR          (1 << 3)
 172
 173 /* These functions also work for the i.MX35, but be aware that
 174  * the i.MX35 has a slightly different register layout for bits
 175  * we do not use here.
 176  */
 177 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 178 {
 179         unsigned int val = 0;
 180
 181         if (enable & MXC_INT_TE)
 182                 val |= MX31_INTREG_TEEN;
 183         if (enable & MXC_INT_RR)
 184                 val |= MX31_INTREG_RREN;
 185
 186         writel(val, spi_imx->base + MXC_CSPIINT);
 187 }
 188
 189 static void mx31_trigger(struct spi_imx_data *spi_imx)
 190 {
 191         unsigned int reg;
 192
 193         reg = readl(spi_imx->base + MXC_CSPICTRL);
 194         reg |= MX31_CSPICTRL_XCH;
 195         writel(reg, spi_imx->base + MXC_CSPICTRL);
 196 }
 197
 198 static int mx31_config(struct spi_imx_data *spi_imx,
 199                 struct spi_imx_config *config)
 200 {
 201         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 202
 203         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 204                 MX31_CSPICTRL_DR_SHIFT;
 205
 206         if (cpu_is_mx31())
 207                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 208         else if (cpu_is_mx35()) {
 209                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 210                 reg |= MX31_CSPICTRL_SSCTL;
 211         }
 212
 213         if (config->mode & SPI_CPHA)
 214                 reg |= MX31_CSPICTRL_PHA;
 215         if (config->mode & SPI_CPOL)
 216                 reg |= MX31_CSPICTRL_POL;
 217         if (config->mode & SPI_CS_HIGH)
 218                 reg |= MX31_CSPICTRL_SSPOL;
 219         if (config->cs < 0) {
 220                 if (cpu_is_mx31())
 221                         reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
 222                 else if (cpu_is_mx35())
 223                         reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 224         }
 225
 226         writel(reg, spi_imx->base + MXC_CSPICTRL);
 227
 228         return 0;
 229 }
 230
 231 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 232 {
 233         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 234 }
 235
 236 #define MX27_INTREG_RR          (1 << 4)
 237 #define MX27_INTREG_TEEN        (1 << 9)
 238 #define MX27_INTREG_RREN        (1 << 13)
 239
 240 #define MX27_CSPICTRL_POL       (1 << 5)
 241 #define MX27_CSPICTRL_PHA       (1 << 6)
 242 #define MX27_CSPICTRL_SSPOL     (1 << 8)
 243 #define MX27_CSPICTRL_XCH       (1 << 9)
 244 #define MX27_CSPICTRL_ENABLE    (1 << 10)
 245 #define MX27_CSPICTRL_MASTER    (1 << 11)
 246 #define MX27_CSPICTRL_DR_SHIFT  14
 247 #define MX27_CSPICTRL_CS_SHIFT  19
 248
 249 static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
 250 {
 251         unsigned int val = 0;
 252
 253         if (enable & MXC_INT_TE)
 254                 val |= MX27_INTREG_TEEN;
 255         if (enable & MXC_INT_RR)
 256                 val |= MX27_INTREG_RREN;
 257
 258         writel(val, spi_imx->base + MXC_CSPIINT);
 259 }
 260
 261 static void mx27_trigger(struct spi_imx_data *spi_imx)
 262 {
 263         unsigned int reg;
 264
 265         reg = readl(spi_imx->base + MXC_CSPICTRL);
 266         reg |= MX27_CSPICTRL_XCH;
 267         writel(reg, spi_imx->base + MXC_CSPICTRL);
 268 }
 269
 270 static int mx27_config(struct spi_imx_data *spi_imx,
 271                 struct spi_imx_config *config)
 272 {
 273         unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
 274
 275         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
 276                 MX27_CSPICTRL_DR_SHIFT;
 277         reg |= config->bpw - 1;
 278
 279         if (config->mode & SPI_CPHA)
 280                 reg |= MX27_CSPICTRL_PHA;
 281         if (config->mode & SPI_CPOL)
 282                 reg |= MX27_CSPICTRL_POL;
 283         if (config->mode & SPI_CS_HIGH)
 284                 reg |= MX27_CSPICTRL_SSPOL;
 285         if (config->cs < 0)
 286                 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
 287
 288         writel(reg, spi_imx->base + MXC_CSPICTRL);
 289
 290         return 0;
 291 }
 292
 293 static int mx27_rx_available(struct spi_imx_data *spi_imx)
 294 {
 295         return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
 296 }
 297
 298 #define MX1_INTREG_RR           (1 << 3)
 299 #define MX1_INTREG_TEEN         (1 << 8)
 300 #define MX1_INTREG_RREN         (1 << 11)
 301
 302 #define MX1_CSPICTRL_POL        (1 << 4)
 303 #define MX1_CSPICTRL_PHA        (1 << 5)
 304 #define MX1_CSPICTRL_XCH        (1 << 8)
 305 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 306 #define MX1_CSPICTRL_MASTER     (1 << 10)
 307 #define MX1_CSPICTRL_DR_SHIFT   13
 308
 309 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 310 {
 311         unsigned int val = 0;
 312
 313         if (enable & MXC_INT_TE)
 314                 val |= MX1_INTREG_TEEN;
 315         if (enable & MXC_INT_RR)
 316                 val |= MX1_INTREG_RREN;
 317
 318         writel(val, spi_imx->base + MXC_CSPIINT);
 319 }
 320
 321 static void mx1_trigger(struct spi_imx_data *spi_imx)
 322 {
 323         unsigned int reg;
 324
 325         reg = readl(spi_imx->base + MXC_CSPICTRL);
 326         reg |= MX1_CSPICTRL_XCH;
 327         writel(reg, spi_imx->base + MXC_CSPICTRL);
 328 }
 329
 330 static int mx1_config(struct spi_imx_data *spi_imx,
 331                 struct spi_imx_config *config)
 332 {
 333         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 334
 335         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 336                 MX1_CSPICTRL_DR_SHIFT;
 337         reg |= config->bpw - 1;
 338
 339         if (config->mode & SPI_CPHA)
 340                 reg |= MX1_CSPICTRL_PHA;
 341         if (config->mode & SPI_CPOL)
 342                 reg |= MX1_CSPICTRL_POL;
 343
 344         writel(reg, spi_imx->base + MXC_CSPICTRL);
 345
 346         return 0;
 347 }
 348
 349 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 350 {
 351         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 352 }
 353
 354 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 355 {
 356         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 357         unsigned int cs = 0;
 358         int gpio = spi_imx->chipselect[spi->chip_select];
 359         struct spi_imx_config config;
 360
 361         if (spi->mode & SPI_CS_HIGH)
 362                 cs = 1;
 363
 364         if (is_active == BITBANG_CS_INACTIVE) {
 365                 if (gpio >= 0)
 366                         gpio_set_value(gpio, !cs);
 367                 return;
 368         }
 369
 370         config.bpw = spi->bits_per_word;
 371         config.speed_hz = spi->max_speed_hz;
 372         config.mode = spi->mode;
 373         config.cs = spi_imx->chipselect[spi->chip_select];
 374
 375         spi_imx->config(spi_imx, &config);
 376
 377         /* Initialize the functions for transfer */
 378         if (config.bpw <= 8) {
 379                 spi_imx->rx = spi_imx_buf_rx_u8;
 380                 spi_imx->tx = spi_imx_buf_tx_u8;
 381         } else if (config.bpw <= 16) {
 382                 spi_imx->rx = spi_imx_buf_rx_u16;
 383                 spi_imx->tx = spi_imx_buf_tx_u16;
 384         } else if (config.bpw <= 32) {
 385                 spi_imx->rx = spi_imx_buf_rx_u32;
 386                 spi_imx->tx = spi_imx_buf_tx_u32;
 387         } else
 388                 BUG();
 389
 390         if (gpio >= 0)
 391                 gpio_set_value(gpio, cs);
 392
 393         return;
 394 }
 395
 396 static void spi_imx_push(struct spi_imx_data *spi_imx)
 397 {
 398         while (spi_imx->txfifo < 8) {
 399                 if (!spi_imx->count)
 400                         break;
 401                 spi_imx->tx(spi_imx);
 402                 spi_imx->txfifo++;
 403         }
 404
 405         spi_imx->trigger(spi_imx);
 406 }
 407
 408 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 409 {
 410         struct spi_imx_data *spi_imx = dev_id;
 411
 412         while (spi_imx->rx_available(spi_imx)) {
 413                 spi_imx->rx(spi_imx);
 414                 spi_imx->txfifo--;
 415         }
 416
 417         if (spi_imx->count) {
 418                 spi_imx_push(spi_imx);
 419                 return IRQ_HANDLED;
 420         }
 421
 422         if (spi_imx->txfifo) {
 423                 /* No data left to push, but still waiting for rx data,
 424                  * enable receive data available interrupt.
 425                  */
 426                 spi_imx->intctrl(spi_imx, MXC_INT_RR);
 427                 return IRQ_HANDLED;
 428         }
 429
 430         spi_imx->intctrl(spi_imx, 0);
 431         complete(&spi_imx->xfer_done);
 432
 433         return IRQ_HANDLED;
 434 }
 435
 436 static int spi_imx_setupxfer(struct spi_device *spi,
 437                                  struct spi_transfer *t)
 438 {
 439         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 440         struct spi_imx_config config;
 441
 442         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 443         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 444         config.mode = spi->mode;
 445
 446         spi_imx->config(spi_imx, &config);
 447
 448         return 0;
 449 }
 450
 451 static int spi_imx_transfer(struct spi_device *spi,
 452                                 struct spi_transfer *transfer)
 453 {
 454         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 455
 456         spi_imx->tx_buf = transfer->tx_buf;
 457         spi_imx->rx_buf = transfer->rx_buf;
 458         spi_imx->count = transfer->len;
 459         spi_imx->txfifo = 0;
 460
 461         init_completion(&spi_imx->xfer_done);
 462
 463         spi_imx_push(spi_imx);
 464
 465         spi_imx->intctrl(spi_imx, MXC_INT_TE);
 466
 467         wait_for_completion(&spi_imx->xfer_done);
 468
 469         return transfer->len;
 470 }
 471
 472 static int spi_imx_setup(struct spi_device *spi)
 473 {
 474         if (!spi->bits_per_word)
 475                 spi->bits_per_word = 8;
 476
 477         pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__,
 478                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
 479
 480         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
 481
 482         return 0;
 483 }
 484
 485 static void spi_imx_cleanup(struct spi_device *spi)
 486 {
 487 }
 488
 489 static int __init spi_imx_probe(struct platform_device *pdev)
 490 {
 491         struct spi_imx_master *mxc_platform_info;
 492         struct spi_master *master;
 493         struct spi_imx_data *spi_imx;
 494         struct resource *res;
 495         int i, ret;
 496
 497         mxc_platform_info = (struct spi_imx_master *)pdev->dev.platform_data;
 498         if (!mxc_platform_info) {
 499                 dev_err(&pdev->dev, "can't get the platform data\n");
 500                 return -EINVAL;
 501         }
 502
 503         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
 504         if (!master)
 505                 return -ENOMEM;
 506
 507         platform_set_drvdata(pdev, master);
 508
 509         master->bus_num = pdev->id;
 510         master->num_chipselect = mxc_platform_info->num_chipselect;
 511
 512         spi_imx = spi_master_get_devdata(master);
 513         spi_imx->bitbang.master = spi_master_get(master);
 514         spi_imx->chipselect = mxc_platform_info->chipselect;
 515
 516         for (i = 0; i < master->num_chipselect; i++) {
 517                 if (spi_imx->chipselect[i] < 0)
 518                         continue;
 519                 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
 520                 if (ret) {
 521                         i--;
 522                         while (i > 0)
 523                                 if (spi_imx->chipselect[i] >= 0)
 524                                         gpio_free(spi_imx->chipselect[i--]);
 525                         dev_err(&pdev->dev, "can't get cs gpios");
 526                         goto out_master_put;
 527                 }
 528                 gpio_direction_output(spi_imx->chipselect[i], 1);
 529         }
 530
 531         spi_imx->bitbang.chipselect = spi_imx_chipselect;
 532         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
 533         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
 534         spi_imx->bitbang.master->setup = spi_imx_setup;
 535         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
 536
 537         init_completion(&spi_imx->xfer_done);
 538
 539         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 540         if (!res) {
 541                 dev_err(&pdev->dev, "can't get platform resource\n");
 542                 ret = -ENOMEM;
 543                 goto out_gpio_free;
 544         }
 545
 546         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 547                 dev_err(&pdev->dev, "request_mem_region failed\n");
 548                 ret = -EBUSY;
 549                 goto out_gpio_free;
 550         }
 551
 552         spi_imx->base = ioremap(res->start, resource_size(res));
 553         if (!spi_imx->base) {
 554                 ret = -EINVAL;
 555                 goto out_release_mem;
 556         }
 557
 558         spi_imx->irq = platform_get_irq(pdev, 0);
 559         if (!spi_imx->irq) {
 560                 ret = -EINVAL;
 561                 goto out_iounmap;
 562         }
 563
 564         ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
 565         if (ret) {
 566                 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
 567                 goto out_iounmap;
 568         }
 569
 570         if (cpu_is_mx31() || cpu_is_mx35()) {
 571                 spi_imx->intctrl = mx31_intctrl;
 572                 spi_imx->config = mx31_config;
 573                 spi_imx->trigger = mx31_trigger;
 574                 spi_imx->rx_available = mx31_rx_available;
 575         } else  if (cpu_is_mx27() || cpu_is_mx21()) {
 576                 spi_imx->intctrl = mx27_intctrl;
 577                 spi_imx->config = mx27_config;
 578                 spi_imx->trigger = mx27_trigger;
 579                 spi_imx->rx_available = mx27_rx_available;
 580         } else if (cpu_is_mx1()) {
 581                 spi_imx->intctrl = mx1_intctrl;
 582                 spi_imx->config = mx1_config;
 583                 spi_imx->trigger = mx1_trigger;
 584                 spi_imx->rx_available = mx1_rx_available;
 585         } else
 586                 BUG();
 587
 588         spi_imx->clk = clk_get(&pdev->dev, NULL);
 589         if (IS_ERR(spi_imx->clk)) {
 590                 dev_err(&pdev->dev, "unable to get clock\n");
 591                 ret = PTR_ERR(spi_imx->clk);
 592                 goto out_free_irq;
 593         }
 594
 595         clk_enable(spi_imx->clk);
 596         spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
 597
 598         if (!cpu_is_mx31() || !cpu_is_mx35())
 599                 writel(1, spi_imx->base + MXC_RESET);
 600
 601         spi_imx->intctrl(spi_imx, 0);
 602
 603         ret = spi_bitbang_start(&spi_imx->bitbang);
 604         if (ret) {
 605                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
 606                 goto out_clk_put;
 607         }
 608
 609         dev_info(&pdev->dev, "probed\n");
 610
 611         return ret;
 612
 613 out_clk_put:
 614         clk_disable(spi_imx->clk);
 615         clk_put(spi_imx->clk);
 616 out_free_irq:
 617         free_irq(spi_imx->irq, spi_imx);
 618 out_iounmap:
 619         iounmap(spi_imx->base);
 620 out_release_mem:
 621         release_mem_region(res->start, resource_size(res));
 622 out_gpio_free:
 623         for (i = 0; i < master->num_chipselect; i++)
 624                 if (spi_imx->chipselect[i] >= 0)
 625                         gpio_free(spi_imx->chipselect[i]);
 626 out_master_put:
 627         spi_master_put(master);
 628         kfree(master);
 629         platform_set_drvdata(pdev, NULL);
 630         return ret;
 631 }
 632
 633 static int __exit spi_imx_remove(struct platform_device *pdev)
 634 {
 635         struct spi_master *master = platform_get_drvdata(pdev);
 636         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 637         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 638         int i;
 639
 640         spi_bitbang_stop(&spi_imx->bitbang);
 641
 642         writel(0, spi_imx->base + MXC_CSPICTRL);
 643         clk_disable(spi_imx->clk);
 644         clk_put(spi_imx->clk);
 645         free_irq(spi_imx->irq, spi_imx);
 646         iounmap(spi_imx->base);
 647
 648         for (i = 0; i < master->num_chipselect; i++)
 649                 if (spi_imx->chipselect[i] >= 0)
 650                         gpio_free(spi_imx->chipselect[i]);
 651
 652         spi_master_put(master);
 653
 654         release_mem_region(res->start, resource_size(res));
 655
 656         platform_set_drvdata(pdev, NULL);
 657
 658         return 0;
 659 }
 660
 661 static struct platform_driver spi_imx_driver = {
 662         .driver = {
 663                    .name = DRIVER_NAME,
 664                    .owner = THIS_MODULE,
 665                    },
 666         .probe = spi_imx_probe,
 667         .remove = __exit_p(spi_imx_remove),
 668 };
 669
 670 static int __init spi_imx_init(void)
 671 {
 672         return platform_driver_register(&spi_imx_driver);
 673 }
 674
 675 static void __exit spi_imx_exit(void)
 676 {
 677         platform_driver_unregister(&spi_imx_driver);
 678 }
 679
 680 module_init(spi_imx_init);
 681 module_exit(spi_imx_exit);
 682
 683 MODULE_DESCRIPTION("SPI Master Controller driver");
 684 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 685 MODULE_LICENSE("GPL");