SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/spi/spi_bfin5xx.c

   1 /*
   2  * File:        drivers/spi/bfin5xx_spi.c
   3  * Maintainer:
   4  *              Bryan Wu <bryan.wu@analog.com>
   5  * Original Author:
   6  *              Luke Yang (Analog Devices Inc.)
   7  *
   8  * Created:     March. 10th 2006
   9  * Description: SPI controller driver for Blackfin BF5xx
  10  * Bugs:        Enter bugs at http://blackfin.uclinux.org/
  11  *
  12  * Modified:
  13  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
  14  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
  15  *      July  17, 2007  add support for BF54x SPI0 controller (Bryan Wu)
  16  *      July  30, 2007  add platfrom_resource interface to support multi-port
  17  *                      SPI controller (Bryan Wu)
  18  *
  19  * Copyright 2004-2007 Analog Devices Inc.
  20  *
  21  * This program is free software ;  you can redistribute it and/or modify
  22  * it under the terms of the GNU General Public License as published by
  23  * the Free Software Foundation ;  either version 2, or (at your option)
  24  * any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful,
  27  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
  28  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  29  * GNU General Public License for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License
  32  * along with this program ;  see the file COPYING.
  33  * If not, write to the Free Software Foundation,
  34  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  35  */
  36
  37 #include <linux/init.h>
  38 #include <linux/module.h>
  39 #include <linux/delay.h>
  40 #include <linux/device.h>
  41 #include <linux/io.h>
  42 #include <linux/ioport.h>
  43 #include <linux/irq.h>
  44 #include <linux/errno.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/spi/spi.h>
  49 #include <linux/workqueue.h>
  50
  51 #include <asm/dma.h>
  52 #include <asm/portmux.h>
  53 #include <asm/bfin5xx_spi.h>
  54
  55 #define DRV_NAME        "bfin-spi"
  56 #define DRV_AUTHOR      "Bryan Wu, Luke Yang"
  57 #define DRV_DESC        "Blackfin BF5xx on-chip SPI Contoller Driver"
  58 #define DRV_VERSION     "1.0"
  59
  60 MODULE_AUTHOR(DRV_AUTHOR);
  61 MODULE_DESCRIPTION(DRV_DESC);
  62 MODULE_LICENSE("GPL");
  63
  64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  65
  66 static u32 spi_dma_ch;
  67 static u32 spi_regs_base;
  68
  69 #define DEFINE_SPI_REG(reg, off) \
  70 static inline u16 read_##reg(void) \
  71         { return bfin_read16(spi_regs_base + off); } \
  72 static inline void write_##reg(u16 v) \
  73         {bfin_write16(spi_regs_base + off, v); }
  74
  75 DEFINE_SPI_REG(CTRL, 0x00)
  76 DEFINE_SPI_REG(FLAG, 0x04)
  77 DEFINE_SPI_REG(STAT, 0x08)
  78 DEFINE_SPI_REG(TDBR, 0x0C)
  79 DEFINE_SPI_REG(RDBR, 0x10)
  80 DEFINE_SPI_REG(BAUD, 0x14)
  81 DEFINE_SPI_REG(SHAW, 0x18)
  82 #define START_STATE ((void*)0)
  83 #define RUNNING_STATE ((void*)1)
  84 #define DONE_STATE ((void*)2)
  85 #define ERROR_STATE ((void*)-1)
  86 #define QUEUE_RUNNING 0
  87 #define QUEUE_STOPPED 1
  88 int dma_requested;
  89
  90 struct driver_data {
  91         /* Driver model hookup */
  92         struct platform_device *pdev;
  93
  94         /* SPI framework hookup */
  95         struct spi_master *master;
  96
  97         /* BFIN hookup */
  98         struct bfin5xx_spi_master *master_info;
  99
 100         /* Driver message queue */
 101         struct workqueue_struct *workqueue;
 102         struct work_struct pump_messages;
 103         spinlock_t lock;
 104         struct list_head queue;
 105         int busy;
 106         int run;
 107
 108         /* Message Transfer pump */
 109         struct tasklet_struct pump_transfers;
 110
 111         /* Current message transfer state info */
 112         struct spi_message *cur_msg;
 113         struct spi_transfer *cur_transfer;
 114         struct chip_data *cur_chip;
 115         size_t len_in_bytes;
 116         size_t len;
 117         void *tx;
 118         void *tx_end;
 119         void *rx;
 120         void *rx_end;
 121         int dma_mapped;
 122         dma_addr_t rx_dma;
 123         dma_addr_t tx_dma;
 124         size_t rx_map_len;
 125         size_t tx_map_len;
 126         u8 n_bytes;
 127         int cs_change;
 128         void (*write) (struct driver_data *);
 129         void (*read) (struct driver_data *);
 130         void (*duplex) (struct driver_data *);
 131 };
 132
 133 struct chip_data {
 134         u16 ctl_reg;
 135         u16 baud;
 136         u16 flag;
 137
 138         u8 chip_select_num;
 139         u8 n_bytes;
 140         u8 width;               /* 0 or 1 */
 141         u8 enable_dma;
 142         u8 bits_per_word;       /* 8 or 16 */
 143         u8 cs_change_per_word;
 144         u8 cs_chg_udelay;
 145         void (*write) (struct driver_data *);
 146         void (*read) (struct driver_data *);
 147         void (*duplex) (struct driver_data *);
 148 };
 149
 150 static void bfin_spi_enable(struct driver_data *drv_data)
 151 {
 152         u16 cr;
 153
 154         cr = read_CTRL();
 155         write_CTRL(cr | BIT_CTL_ENABLE);
 156 }
 157
 158 static void bfin_spi_disable(struct driver_data *drv_data)
 159 {
 160         u16 cr;
 161
 162         cr = read_CTRL();
 163         write_CTRL(cr & (~BIT_CTL_ENABLE));
 164 }
 165
 166 /* Caculate the SPI_BAUD register value based on input HZ */
 167 static u16 hz_to_spi_baud(u32 speed_hz)
 168 {
 169         u_long sclk = get_sclk();
 170         u16 spi_baud = (sclk / (2 * speed_hz));
 171
 172         if ((sclk % (2 * speed_hz)) > 0)
 173                 spi_baud++;
 174
 175         return spi_baud;
 176 }
 177
 178 static int flush(struct driver_data *drv_data)
 179 {
 180         unsigned long limit = loops_per_jiffy << 1;
 181
 182         /* wait for stop and clear stat */
 183         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
 184                 continue;
 185
 186         write_STAT(BIT_STAT_CLR);
 187
 188         return limit;
 189 }
 190
 191 /* Chip select operation functions for cs_change flag */
 192 static void cs_active(struct chip_data *chip)
 193 {
 194         u16 flag = read_FLAG();
 195
 196         flag |= chip->flag;
 197         flag &= ~(chip->flag << 8);
 198
 199         write_FLAG(flag);
 200 }
 201
 202 static void cs_deactive(struct chip_data *chip)
 203 {
 204         u16 flag = read_FLAG();
 205
 206         flag |= (chip->flag << 8);
 207
 208         write_FLAG(flag);
 209 }
 210
 211 #define MAX_SPI_SSEL    7
 212
 213 /* stop controller and re-config current chip*/
 214 static int restore_state(struct driver_data *drv_data)
 215 {
 216         struct chip_data *chip = drv_data->cur_chip;
 217         int ret = 0;
 218
 219         /* Clear status and disable clock */
 220         write_STAT(BIT_STAT_CLR);
 221         bfin_spi_disable(drv_data);
 222         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
 223
 224         /* Load the registers */
 225         write_CTRL(chip->ctl_reg);
 226         write_BAUD(chip->baud);
 227         cs_active(chip);
 228
 229         if (ret)
 230                 dev_dbg(&drv_data->pdev->dev,
 231                         ": request chip select number %d failed\n",
 232                         chip->chip_select_num);
 233
 234         return ret;
 235 }
 236
 237 /* used to kick off transfer in rx mode */
 238 static unsigned short dummy_read(void)
 239 {
 240         unsigned short tmp;
 241         tmp = read_RDBR();
 242         return tmp;
 243 }
 244
 245 static void null_writer(struct driver_data *drv_data)
 246 {
 247         u8 n_bytes = drv_data->n_bytes;
 248
 249         while (drv_data->tx < drv_data->tx_end) {
 250                 write_TDBR(0);
 251                 while ((read_STAT() & BIT_STAT_TXS))
 252                         continue;
 253                 drv_data->tx += n_bytes;
 254         }
 255 }
 256
 257 static void null_reader(struct driver_data *drv_data)
 258 {
 259         u8 n_bytes = drv_data->n_bytes;
 260         dummy_read();
 261
 262         while (drv_data->rx < drv_data->rx_end) {
 263                 while (!(read_STAT() & BIT_STAT_RXS))
 264                         continue;
 265                 dummy_read();
 266                 drv_data->rx += n_bytes;
 267         }
 268 }
 269
 270 static void u8_writer(struct driver_data *drv_data)
 271 {
 272         dev_dbg(&drv_data->pdev->dev,
 273                 "cr8-s is 0x%x\n", read_STAT());
 274         while (drv_data->tx < drv_data->tx_end) {
 275                 write_TDBR(*(u8 *) (drv_data->tx));
 276                 while (read_STAT() & BIT_STAT_TXS)
 277                         continue;
 278                 ++drv_data->tx;
 279         }
 280
 281         /* poll for SPI completion before returning */
 282         while (!(read_STAT() & BIT_STAT_SPIF))
 283                 continue;
 284 }
 285
 286 static void u8_cs_chg_writer(struct driver_data *drv_data)
 287 {
 288         struct chip_data *chip = drv_data->cur_chip;
 289
 290         while (drv_data->tx < drv_data->tx_end) {
 291                 cs_active(chip);
 292
 293                 write_TDBR(*(u8 *) (drv_data->tx));
 294                 while (read_STAT() & BIT_STAT_TXS)
 295                         continue;
 296                 while (!(read_STAT() & BIT_STAT_SPIF))
 297                         continue;
 298                 cs_deactive(chip);
 299
 300                 if (chip->cs_chg_udelay)
 301                         udelay(chip->cs_chg_udelay);
 302                 ++drv_data->tx;
 303         }
 304         cs_deactive(chip);
 305
 306 }
 307
 308 static void u8_reader(struct driver_data *drv_data)
 309 {
 310         dev_dbg(&drv_data->pdev->dev,
 311                 "cr-8 is 0x%x\n", read_STAT());
 312
 313         /* clear TDBR buffer before read(else it will be shifted out) */
 314         write_TDBR(0xFFFF);
 315
 316         dummy_read();
 317         while (drv_data->rx < drv_data->rx_end - 1) {
 318                 while (!(read_STAT() & BIT_STAT_RXS))
 319                         continue;
 320                 *(u8 *) (drv_data->rx) = read_RDBR();
 321                 ++drv_data->rx;
 322         }
 323
 324         while (!(read_STAT() & BIT_STAT_RXS))
 325                 continue;
 326         *(u8 *) (drv_data->rx) = read_SHAW();
 327         ++drv_data->rx;
 328 }
 329
 330 static void u8_cs_chg_reader(struct driver_data *drv_data)
 331 {
 332         struct chip_data *chip = drv_data->cur_chip;
 333
 334         while (drv_data->rx < drv_data->rx_end) {
 335                 cs_active(chip);
 336
 337                 read_RDBR();    /* kick off */
 338                 while (!(read_STAT() & BIT_STAT_RXS))
 339                         continue;
 340                 while (!(read_STAT() & BIT_STAT_SPIF))
 341                         continue;
 342                 *(u8 *) (drv_data->rx) = read_SHAW();
 343                 cs_deactive(chip);
 344
 345                 if (chip->cs_chg_udelay)
 346                         udelay(chip->cs_chg_udelay);
 347                 ++drv_data->rx;
 348         }
 349         cs_deactive(chip);
 350
 351 }
 352
 353 static void u8_duplex(struct driver_data *drv_data)
 354 {
 355         /* in duplex mode, clk is triggered by writing of TDBR */
 356         while (drv_data->rx < drv_data->rx_end) {
 357                 write_TDBR(*(u8 *) (drv_data->tx));
 358                 while (!(read_STAT() & BIT_STAT_SPIF))
 359                         continue;
 360                 while (!(read_STAT() & BIT_STAT_RXS))
 361                         continue;
 362                 *(u8 *) (drv_data->rx) = read_RDBR();
 363                 ++drv_data->rx;
 364                 ++drv_data->tx;
 365         }
 366 }
 367
 368 static void u8_cs_chg_duplex(struct driver_data *drv_data)
 369 {
 370         struct chip_data *chip = drv_data->cur_chip;
 371
 372         while (drv_data->rx < drv_data->rx_end) {
 373                 cs_active(chip);
 374
 375
 376                 write_TDBR(*(u8 *) (drv_data->tx));
 377                 while (!(read_STAT() & BIT_STAT_SPIF))
 378                         continue;
 379                 while (!(read_STAT() & BIT_STAT_RXS))
 380                         continue;
 381                 *(u8 *) (drv_data->rx) = read_RDBR();
 382                 cs_deactive(chip);
 383
 384                 if (chip->cs_chg_udelay)
 385                         udelay(chip->cs_chg_udelay);
 386                 ++drv_data->rx;
 387                 ++drv_data->tx;
 388         }
 389         cs_deactive(chip);
 390 }
 391
 392 static void u16_writer(struct driver_data *drv_data)
 393 {
 394         dev_dbg(&drv_data->pdev->dev,
 395                 "cr16 is 0x%x\n", read_STAT());
 396
 397         while (drv_data->tx < drv_data->tx_end) {
 398                 write_TDBR(*(u16 *) (drv_data->tx));
 399                 while ((read_STAT() & BIT_STAT_TXS))
 400                         continue;
 401                 drv_data->tx += 2;
 402         }
 403
 404         /* poll for SPI completion before returning */
 405         while (!(read_STAT() & BIT_STAT_SPIF))
 406                 continue;
 407 }
 408
 409 static void u16_cs_chg_writer(struct driver_data *drv_data)
 410 {
 411         struct chip_data *chip = drv_data->cur_chip;
 412
 413         while (drv_data->tx < drv_data->tx_end) {
 414                 cs_active(chip);
 415
 416                 write_TDBR(*(u16 *) (drv_data->tx));
 417                 while ((read_STAT() & BIT_STAT_TXS))
 418                         continue;
 419                 while (!(read_STAT() & BIT_STAT_SPIF))
 420                         continue;
 421                 cs_deactive(chip);
 422
 423                 if (chip->cs_chg_udelay)
 424                         udelay(chip->cs_chg_udelay);
 425                 drv_data->tx += 2;
 426         }
 427         cs_deactive(chip);
 428 }
 429
 430 static void u16_reader(struct driver_data *drv_data)
 431 {
 432         dev_dbg(&drv_data->pdev->dev,
 433                 "cr-16 is 0x%x\n", read_STAT());
 434         dummy_read();
 435
 436         while (drv_data->rx < (drv_data->rx_end - 2)) {
 437                 while (!(read_STAT() & BIT_STAT_RXS))
 438                         continue;
 439                 *(u16 *) (drv_data->rx) = read_RDBR();
 440                 drv_data->rx += 2;
 441         }
 442
 443         while (!(read_STAT() & BIT_STAT_RXS))
 444                 continue;
 445         *(u16 *) (drv_data->rx) = read_SHAW();
 446         drv_data->rx += 2;
 447 }
 448
 449 static void u16_cs_chg_reader(struct driver_data *drv_data)
 450 {
 451         struct chip_data *chip = drv_data->cur_chip;
 452
 453         while (drv_data->rx < drv_data->rx_end) {
 454                 cs_active(chip);
 455
 456                 read_RDBR();    /* kick off */
 457                 while (!(read_STAT() & BIT_STAT_RXS))
 458                         continue;
 459                 while (!(read_STAT() & BIT_STAT_SPIF))
 460                         continue;
 461                 *(u16 *) (drv_data->rx) = read_SHAW();
 462                 cs_deactive(chip);
 463
 464                 if (chip->cs_chg_udelay)
 465                         udelay(chip->cs_chg_udelay);
 466                 drv_data->rx += 2;
 467         }
 468         cs_deactive(chip);
 469 }
 470
 471 static void u16_duplex(struct driver_data *drv_data)
 472 {
 473         /* in duplex mode, clk is triggered by writing of TDBR */
 474         while (drv_data->tx < drv_data->tx_end) {
 475                 write_TDBR(*(u16 *) (drv_data->tx));
 476                 while (!(read_STAT() & BIT_STAT_SPIF))
 477                         continue;
 478                 while (!(read_STAT() & BIT_STAT_RXS))
 479                         continue;
 480                 *(u16 *) (drv_data->rx) = read_RDBR();
 481                 drv_data->rx += 2;
 482                 drv_data->tx += 2;
 483         }
 484 }
 485
 486 static void u16_cs_chg_duplex(struct driver_data *drv_data)
 487 {
 488         struct chip_data *chip = drv_data->cur_chip;
 489
 490         while (drv_data->tx < drv_data->tx_end) {
 491                 cs_active(chip);
 492
 493                 write_TDBR(*(u16 *) (drv_data->tx));
 494                 while (!(read_STAT() & BIT_STAT_SPIF))
 495                         continue;
 496                 while (!(read_STAT() & BIT_STAT_RXS))
 497                         continue;
 498                 *(u16 *) (drv_data->rx) = read_RDBR();
 499                 cs_deactive(chip);
 500
 501                 if (chip->cs_chg_udelay)
 502                         udelay(chip->cs_chg_udelay);
 503                 drv_data->rx += 2;
 504                 drv_data->tx += 2;
 505         }
 506         cs_deactive(chip);
 507 }
 508
 509 /* test if ther is more transfer to be done */
 510 static void *next_transfer(struct driver_data *drv_data)
 511 {
 512         struct spi_message *msg = drv_data->cur_msg;
 513         struct spi_transfer *trans = drv_data->cur_transfer;
 514
 515         /* Move to next transfer */
 516         if (trans->transfer_list.next != &msg->transfers) {
 517                 drv_data->cur_transfer =
 518                     list_entry(trans->transfer_list.next,
 519                                struct spi_transfer, transfer_list);
 520                 return RUNNING_STATE;
 521         } else
 522                 return DONE_STATE;
 523 }
 524
 525 /*
 526  * caller already set message->status;
 527  * dma and pio irqs are blocked give finished message back
 528  */
 529 static void giveback(struct driver_data *drv_data)
 530 {
 531         struct chip_data *chip = drv_data->cur_chip;
 532         struct spi_transfer *last_transfer;
 533         unsigned long flags;
 534         struct spi_message *msg;
 535
 536         spin_lock_irqsave(&drv_data->lock, flags);
 537         msg = drv_data->cur_msg;
 538         drv_data->cur_msg = NULL;
 539         drv_data->cur_transfer = NULL;
 540         drv_data->cur_chip = NULL;
 541         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 542         spin_unlock_irqrestore(&drv_data->lock, flags);
 543
 544         last_transfer = list_entry(msg->transfers.prev,
 545                                    struct spi_transfer, transfer_list);
 546
 547         msg->state = NULL;
 548
 549         /* disable chip select signal. And not stop spi in autobuffer mode */
 550         if (drv_data->tx_dma != 0xFFFF) {
 551                 cs_deactive(chip);
 552                 bfin_spi_disable(drv_data);
 553         }
 554
 555         if (!drv_data->cs_change)
 556                 cs_deactive(chip);
 557
 558         if (msg->complete)
 559                 msg->complete(msg->context);
 560 }
 561
 562 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 563 {
 564         struct driver_data *drv_data = (struct driver_data *)dev_id;
 565         struct spi_message *msg = drv_data->cur_msg;
 566         struct chip_data *chip = drv_data->cur_chip;
 567
 568         dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
 569         clear_dma_irqstat(spi_dma_ch);
 570
 571         /* Wait for DMA to complete */
 572         while (get_dma_curr_irqstat(spi_dma_ch) & DMA_RUN)
 573                 continue;
 574
 575         /*
 576          * wait for the last transaction shifted out.  HRM states:
 577          * at this point there may still be data in the SPI DMA FIFO waiting
 578          * to be transmitted ... software needs to poll TXS in the SPI_STAT
 579          * register until it goes low for 2 successive reads
 580          */
 581         if (drv_data->tx != NULL) {
 582                 while ((read_STAT() & TXS) ||
 583                        (read_STAT() & TXS))
 584                         continue;
 585         }
 586
 587         while (!(read_STAT() & SPIF))
 588                 continue;
 589
 590         bfin_spi_disable(drv_data);
 591
 592         msg->actual_length += drv_data->len_in_bytes;
 593
 594         if (drv_data->cs_change)
 595                 cs_deactive(chip);
 596
 597         /* Move to next transfer */
 598         msg->state = next_transfer(drv_data);
 599
 600         /* Schedule transfer tasklet */
 601         tasklet_schedule(&drv_data->pump_transfers);
 602
 603         /* free the irq handler before next transfer */
 604         dev_dbg(&drv_data->pdev->dev,
 605                 "disable dma channel irq%d\n",
 606                 spi_dma_ch);
 607         dma_disable_irq(spi_dma_ch);
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static void pump_transfers(unsigned long data)
 613 {
 614         struct driver_data *drv_data = (struct driver_data *)data;
 615         struct spi_message *message = NULL;
 616         struct spi_transfer *transfer = NULL;
 617         struct spi_transfer *previous = NULL;
 618         struct chip_data *chip = NULL;
 619         u8 width;
 620         u16 cr, dma_width, dma_config;
 621         u32 tranf_success = 1;
 622
 623         /* Get current state information */
 624         message = drv_data->cur_msg;
 625         transfer = drv_data->cur_transfer;
 626         chip = drv_data->cur_chip;
 627         /*
 628          * if msg is error or done, report it back using complete() callback
 629          */
 630
 631          /* Handle for abort */
 632         if (message->state == ERROR_STATE) {
 633                 message->status = -EIO;
 634                 giveback(drv_data);
 635                 return;
 636         }
 637
 638         /* Handle end of message */
 639         if (message->state == DONE_STATE) {
 640                 message->status = 0;
 641                 giveback(drv_data);
 642                 return;
 643         }
 644
 645         /* Delay if requested at end of transfer */
 646         if (message->state == RUNNING_STATE) {
 647                 previous = list_entry(transfer->transfer_list.prev,
 648                                       struct spi_transfer, transfer_list);
 649                 if (previous->delay_usecs)
 650                         udelay(previous->delay_usecs);
 651         }
 652
 653         /* Setup the transfer state based on the type of transfer */
 654         if (flush(drv_data) == 0) {
 655                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 656                 message->status = -EIO;
 657                 giveback(drv_data);
 658                 return;
 659         }
 660
 661         if (transfer->tx_buf != NULL) {
 662                 drv_data->tx = (void *)transfer->tx_buf;
 663                 drv_data->tx_end = drv_data->tx + transfer->len;
 664                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
 665                         transfer->tx_buf, drv_data->tx_end);
 666         } else {
 667                 drv_data->tx = NULL;
 668         }
 669
 670         if (transfer->rx_buf != NULL) {
 671                 drv_data->rx = transfer->rx_buf;
 672                 drv_data->rx_end = drv_data->rx + transfer->len;
 673                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
 674                         transfer->rx_buf, drv_data->rx_end);
 675         } else {
 676                 drv_data->rx = NULL;
 677         }
 678
 679         drv_data->rx_dma = transfer->rx_dma;
 680         drv_data->tx_dma = transfer->tx_dma;
 681         drv_data->len_in_bytes = transfer->len;
 682         drv_data->cs_change = transfer->cs_change;
 683
 684         width = chip->width;
 685         if (width == CFG_SPI_WORDSIZE16) {
 686                 drv_data->len = (transfer->len) >> 1;
 687         } else {
 688                 drv_data->len = transfer->len;
 689         }
 690         drv_data->write = drv_data->tx ? chip->write : null_writer;
 691         drv_data->read = drv_data->rx ? chip->read : null_reader;
 692         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
 693         dev_dbg(&drv_data->pdev->dev, "transfer: ",
 694                 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
 695                 drv_data->write, chip->write, null_writer);
 696
 697         /* speed and width has been set on per message */
 698         message->state = RUNNING_STATE;
 699         dma_config = 0;
 700
 701         /* restore spi status for each spi transfer */
 702         if (transfer->speed_hz) {
 703                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
 704         } else {
 705                 write_BAUD(chip->baud);
 706         }
 707         cs_active(chip);
 708
 709         dev_dbg(&drv_data->pdev->dev,
 710                 "now pumping a transfer: width is %d, len is %d\n",
 711                 width, transfer->len);
 712
 713         /*
 714          * Try to map dma buffer and do a dma transfer if
 715          * successful use different way to r/w according to
 716          * drv_data->cur_chip->enable_dma
 717          */
 718         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
 719
 720                 write_STAT(BIT_STAT_CLR);
 721                 disable_dma(spi_dma_ch);
 722                 clear_dma_irqstat(spi_dma_ch);
 723                 bfin_spi_disable(drv_data);
 724
 725                 /* config dma channel */
 726                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
 727                 if (width == CFG_SPI_WORDSIZE16) {
 728                         set_dma_x_count(spi_dma_ch, drv_data->len);
 729                         set_dma_x_modify(spi_dma_ch, 2);
 730                         dma_width = WDSIZE_16;
 731                 } else {
 732                         set_dma_x_count(spi_dma_ch, drv_data->len);
 733                         set_dma_x_modify(spi_dma_ch, 1);
 734                         dma_width = WDSIZE_8;
 735                 }
 736
 737                 /* set transfer width,direction. And enable spi */
 738                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 739
 740                 /* dirty hack for autobuffer DMA mode */
 741                 if (drv_data->tx_dma == 0xFFFF) {
 742                         dev_dbg(&drv_data->pdev->dev,
 743                                 "doing autobuffer DMA out.\n");
 744
 745                         /* no irq in autobuffer mode */
 746                         dma_config =
 747                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
 748                         set_dma_config(spi_dma_ch, dma_config);
 749                         set_dma_start_addr(spi_dma_ch,
 750                                         (unsigned long)drv_data->tx);
 751                         enable_dma(spi_dma_ch);
 752                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 753                                    (CFG_SPI_ENABLE << 14));
 754
 755                         /* just return here, there can only be one transfer in this mode */
 756                         message->status = 0;
 757                         giveback(drv_data);
 758                         return;
 759                 }
 760
 761                 /* In dma mode, rx or tx must be NULL in one transfer */
 762                 if (drv_data->rx != NULL) {
 763                         /* set transfer mode, and enable SPI */
 764                         dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
 765
 766                         /* disable SPI before write to TDBR */
 767                         write_CTRL(cr & ~BIT_CTL_ENABLE);
 768
 769                         /* clear tx reg soformer data is not shifted out */
 770                         write_TDBR(0xFF);
 771
 772                         set_dma_x_count(spi_dma_ch, drv_data->len);
 773
 774                         /* start dma */
 775                         dma_enable_irq(spi_dma_ch);
 776                         dma_config = (WNR | RESTART | dma_width | DI_EN);
 777                         set_dma_config(spi_dma_ch, dma_config);
 778                         set_dma_start_addr(spi_dma_ch,
 779                                         (unsigned long)drv_data->rx);
 780                         enable_dma(spi_dma_ch);
 781
 782                         cr |=
 783                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
 784                                                               14);
 785                         /* set transfer mode, and enable SPI */
 786                         write_CTRL(cr);
 787                 } else if (drv_data->tx != NULL) {
 788                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
 789
 790                         /* start dma */
 791                         dma_enable_irq(spi_dma_ch);
 792                         dma_config = (RESTART | dma_width | DI_EN);
 793                         set_dma_config(spi_dma_ch, dma_config);
 794                         set_dma_start_addr(spi_dma_ch,
 795                                         (unsigned long)drv_data->tx);
 796                         enable_dma(spi_dma_ch);
 797
 798                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
 799                                    (CFG_SPI_ENABLE << 14));
 800
 801                 }
 802         } else {
 803                 /* IO mode write then read */
 804                 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
 805
 806                 write_STAT(BIT_STAT_CLR);
 807
 808                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
 809                         /* full duplex mode */
 810                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
 811                                (drv_data->rx_end - drv_data->rx));
 812                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 813                         cr |= CFG_SPI_WRITE | (width << 8) |
 814                                 (CFG_SPI_ENABLE << 14);
 815                         dev_dbg(&drv_data->pdev->dev,
 816                                 "IO duplex: cr is 0x%x\n", cr);
 817
 818                         write_CTRL(cr);
 819
 820                         drv_data->duplex(drv_data);
 821
 822                         if (drv_data->tx != drv_data->tx_end)
 823                                 tranf_success = 0;
 824                 } else if (drv_data->tx != NULL) {
 825                         /* write only half duplex */
 826                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 827                         cr |= CFG_SPI_WRITE | (width << 8) |
 828                                 (CFG_SPI_ENABLE << 14);
 829                         dev_dbg(&drv_data->pdev->dev,
 830                                 "IO write: cr is 0x%x\n", cr);
 831
 832                         write_CTRL(cr);
 833
 834                         drv_data->write(drv_data);
 835
 836                         if (drv_data->tx != drv_data->tx_end)
 837                                 tranf_success = 0;
 838                 } else if (drv_data->rx != NULL) {
 839                         /* read only half duplex */
 840                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
 841                         cr |= CFG_SPI_READ | (width << 8) |
 842                                 (CFG_SPI_ENABLE << 14);
 843                         dev_dbg(&drv_data->pdev->dev,
 844                                 "IO read: cr is 0x%x\n", cr);
 845
 846                         write_CTRL(cr);
 847
 848                         drv_data->read(drv_data);
 849                         if (drv_data->rx != drv_data->rx_end)
 850                                 tranf_success = 0;
 851                 }
 852
 853                 if (!tranf_success) {
 854                         dev_dbg(&drv_data->pdev->dev,
 855                                 "IO write error!\n");
 856                         message->state = ERROR_STATE;
 857                 } else {
 858                         /* Update total byte transfered */
 859                         message->actual_length += drv_data->len;
 860
 861                         if (drv_data->cs_change)
 862                                 cs_deactive(chip);
 863
 864                         /* Move to next transfer of this msg */
 865                         message->state = next_transfer(drv_data);
 866                 }
 867
 868                 /* Schedule next transfer tasklet */
 869                 tasklet_schedule(&drv_data->pump_transfers);
 870
 871         }
 872 }
 873
 874 /* pop a msg from queue and kick off real transfer */
 875 static void pump_messages(struct work_struct *work)
 876 {
 877         struct driver_data *drv_data;
 878         unsigned long flags;
 879
 880         drv_data = container_of(work, struct driver_data, pump_messages);
 881
 882         /* Lock queue and check for queue work */
 883         spin_lock_irqsave(&drv_data->lock, flags);
 884         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
 885                 /* pumper kicked off but no work to do */
 886                 drv_data->busy = 0;
 887                 spin_unlock_irqrestore(&drv_data->lock, flags);
 888                 return;
 889         }
 890
 891         /* Make sure we are not already running a message */
 892         if (drv_data->cur_msg) {
 893                 spin_unlock_irqrestore(&drv_data->lock, flags);
 894                 return;
 895         }
 896
 897         /* Extract head of queue */
 898         drv_data->cur_msg = list_entry(drv_data->queue.next,
 899                                        struct spi_message, queue);
 900
 901         /* Setup the SSP using the per chip configuration */
 902         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
 903         if (restore_state(drv_data)) {
 904                 spin_unlock_irqrestore(&drv_data->lock, flags);
 905                 return;
 906         };
 907
 908         list_del_init(&drv_data->cur_msg->queue);
 909
 910         /* Initial message state */
 911         drv_data->cur_msg->state = START_STATE;
 912         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
 913                                             struct spi_transfer, transfer_list);
 914
 915         dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
 916                 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
 917                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
 918                 drv_data->cur_chip->ctl_reg);
 919
 920         dev_dbg(&drv_data->pdev->dev,
 921                 "the first transfer len is %d\n",
 922                 drv_data->cur_transfer->len);
 923
 924         /* Mark as busy and launch transfers */
 925         tasklet_schedule(&drv_data->pump_transfers);
 926
 927         drv_data->busy = 1;
 928         spin_unlock_irqrestore(&drv_data->lock, flags);
 929 }
 930
 931 /*
 932  * got a msg to transfer, queue it in drv_data->queue.
 933  * And kick off message pumper
 934  */
 935 static int transfer(struct spi_device *spi, struct spi_message *msg)
 936 {
 937         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&drv_data->lock, flags);
 941
 942         if (drv_data->run == QUEUE_STOPPED) {
 943                 spin_unlock_irqrestore(&drv_data->lock, flags);
 944                 return -ESHUTDOWN;
 945         }
 946
 947         msg->actual_length = 0;
 948         msg->status = -EINPROGRESS;
 949         msg->state = START_STATE;
 950
 951         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
 952         list_add_tail(&msg->queue, &drv_data->queue);
 953
 954         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
 955                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
 956
 957         spin_unlock_irqrestore(&drv_data->lock, flags);
 958
 959         return 0;
 960 }
 961
 962 #define MAX_SPI_SSEL    7
 963
 964 static u16 ssel[3][MAX_SPI_SSEL] = {
 965         {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
 966         P_SPI0_SSEL4, P_SPI0_SSEL5,
 967         P_SPI0_SSEL6, P_SPI0_SSEL7},
 968
 969         {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
 970         P_SPI1_SSEL4, P_SPI1_SSEL5,
 971         P_SPI1_SSEL6, P_SPI1_SSEL7},
 972
 973         {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
 974         P_SPI2_SSEL4, P_SPI2_SSEL5,
 975         P_SPI2_SSEL6, P_SPI2_SSEL7},
 976 };
 977
 978 /* first setup for new devices */
 979 static int setup(struct spi_device *spi)
 980 {
 981         struct bfin5xx_spi_chip *chip_info = NULL;
 982         struct chip_data *chip;
 983         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
 984         u8 spi_flg;
 985
 986         /* Abort device setup if requested features are not supported */
 987         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
 988                 dev_err(&spi->dev, "requested mode not fully supported\n");
 989                 return -EINVAL;
 990         }
 991
 992         /* Zero (the default) here means 8 bits */
 993         if (!spi->bits_per_word)
 994                 spi->bits_per_word = 8;
 995
 996         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 997                 return -EINVAL;
 998
 999         /* Only alloc (or use chip_info) on first setup */
1000         chip = spi_get_ctldata(spi);
1001         if (chip == NULL) {
1002                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1003                 if (!chip)
1004                         return -ENOMEM;
1005
1006                 chip->enable_dma = 0;
1007                 chip_info = spi->controller_data;
1008         }
1009
1010         /* chip_info isn't always needed */
1011         if (chip_info) {
1012                 /* Make sure people stop trying to set fields via ctl_reg
1013                  * when they should actually be using common SPI framework.
1014                  * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1015                  * Not sure if a user actually needs/uses any of these,
1016                  * but let's assume (for now) they do.
1017                  */
1018                 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1019                         dev_err(&spi->dev, "do not set bits in ctl_reg "
1020                                 "that the SPI framework manages\n");
1021                         return -EINVAL;
1022                 }
1023
1024                 chip->enable_dma = chip_info->enable_dma != 0
1025                     && drv_data->master_info->enable_dma;
1026                 chip->ctl_reg = chip_info->ctl_reg;
1027                 chip->bits_per_word = chip_info->bits_per_word;
1028                 chip->cs_change_per_word = chip_info->cs_change_per_word;
1029                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1030         }
1031
1032         /* translate common spi framework into our register */
1033         if (spi->mode & SPI_CPOL)
1034                 chip->ctl_reg |= CPOL;
1035         if (spi->mode & SPI_CPHA)
1036                 chip->ctl_reg |= CPHA;
1037         if (spi->mode & SPI_LSB_FIRST)
1038                 chip->ctl_reg |= LSBF;
1039         /* we dont support running in slave mode (yet?) */
1040         chip->ctl_reg |= MSTR;
1041
1042         /*
1043          * if any one SPI chip is registered and wants DMA, request the
1044          * DMA channel for it
1045          */
1046         if (chip->enable_dma && !dma_requested) {
1047                 /* register dma irq handler */
1048                 if (request_dma(spi_dma_ch, "BF53x_SPI_DMA") < 0) {
1049                         dev_dbg(&spi->dev,
1050                                 "Unable to request BlackFin SPI DMA channel\n");
1051                         return -ENODEV;
1052                 }
1053                 if (set_dma_callback(spi_dma_ch, (void *)dma_irq_handler,
1054                         drv_data) < 0) {
1055                         dev_dbg(&spi->dev, "Unable to set dma callback\n");
1056                         return -EPERM;
1057                 }
1058                 dma_disable_irq(spi_dma_ch);
1059                 dma_requested = 1;
1060         }
1061
1062         /*
1063          * Notice: for blackfin, the speed_hz is the value of register
1064          * SPI_BAUD, not the real baudrate
1065          */
1066         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1067         spi_flg = ~(1 << (spi->chip_select));
1068         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1069         chip->chip_select_num = spi->chip_select;
1070
1071         switch (chip->bits_per_word) {
1072         case 8:
1073                 chip->n_bytes = 1;
1074                 chip->width = CFG_SPI_WORDSIZE8;
1075                 chip->read = chip->cs_change_per_word ?
1076                         u8_cs_chg_reader : u8_reader;
1077                 chip->write = chip->cs_change_per_word ?
1078                         u8_cs_chg_writer : u8_writer;
1079                 chip->duplex = chip->cs_change_per_word ?
1080                         u8_cs_chg_duplex : u8_duplex;
1081                 break;
1082
1083         case 16:
1084                 chip->n_bytes = 2;
1085                 chip->width = CFG_SPI_WORDSIZE16;
1086                 chip->read = chip->cs_change_per_word ?
1087                         u16_cs_chg_reader : u16_reader;
1088                 chip->write = chip->cs_change_per_word ?
1089                         u16_cs_chg_writer : u16_writer;
1090                 chip->duplex = chip->cs_change_per_word ?
1091                         u16_cs_chg_duplex : u16_duplex;
1092                 break;
1093
1094         default:
1095                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1096                                 chip->bits_per_word);
1097                 kfree(chip);
1098                 return -ENODEV;
1099         }
1100
1101         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1102                         spi->modalias, chip->width, chip->enable_dma);
1103         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1104                         chip->ctl_reg, chip->flag);
1105
1106         spi_set_ctldata(spi, chip);
1107
1108         dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1109         if ((chip->chip_select_num > 0)
1110                 && (chip->chip_select_num <= spi->master->num_chipselect))
1111                 peripheral_request(ssel[spi->master->bus_num]
1112                         [chip->chip_select_num-1], DRV_NAME);
1113
1114         return 0;
1115 }
1116
1117 /*
1118  * callback for spi framework.
1119  * clean driver specific data
1120  */
1121 static void cleanup(struct spi_device *spi)
1122 {
1123         struct chip_data *chip = spi_get_ctldata(spi);
1124
1125         if ((chip->chip_select_num > 0)
1126                 && (chip->chip_select_num <= spi->master->num_chipselect))
1127                 peripheral_free(ssel[spi->master->bus_num]
1128                                         [chip->chip_select_num-1]);
1129
1130         kfree(chip);
1131 }
1132
1133 static inline int init_queue(struct driver_data *drv_data)
1134 {
1135         INIT_LIST_HEAD(&drv_data->queue);
1136         spin_lock_init(&drv_data->lock);
1137
1138         drv_data->run = QUEUE_STOPPED;
1139         drv_data->busy = 0;
1140
1141         /* init transfer tasklet */
1142         tasklet_init(&drv_data->pump_transfers,
1143                      pump_transfers, (unsigned long)drv_data);
1144
1145         /* init messages workqueue */
1146         INIT_WORK(&drv_data->pump_messages, pump_messages);
1147         drv_data->workqueue =
1148             create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1149         if (drv_data->workqueue == NULL)
1150                 return -EBUSY;
1151
1152         return 0;
1153 }
1154
1155 static inline int start_queue(struct driver_data *drv_data)
1156 {
1157         unsigned long flags;
1158
1159         spin_lock_irqsave(&drv_data->lock, flags);
1160
1161         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1162                 spin_unlock_irqrestore(&drv_data->lock, flags);
1163                 return -EBUSY;
1164         }
1165
1166         drv_data->run = QUEUE_RUNNING;
1167         drv_data->cur_msg = NULL;
1168         drv_data->cur_transfer = NULL;
1169         drv_data->cur_chip = NULL;
1170         spin_unlock_irqrestore(&drv_data->lock, flags);
1171
1172         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1173
1174         return 0;
1175 }
1176
1177 static inline int stop_queue(struct driver_data *drv_data)
1178 {
1179         unsigned long flags;
1180         unsigned limit = 500;
1181         int status = 0;
1182
1183         spin_lock_irqsave(&drv_data->lock, flags);
1184
1185         /*
1186          * This is a bit lame, but is optimized for the common execution path.
1187          * A wait_queue on the drv_data->busy could be used, but then the common
1188          * execution path (pump_messages) would be required to call wake_up or
1189          * friends on every SPI message. Do this instead
1190          */
1191         drv_data->run = QUEUE_STOPPED;
1192         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1193                 spin_unlock_irqrestore(&drv_data->lock, flags);
1194                 msleep(10);
1195                 spin_lock_irqsave(&drv_data->lock, flags);
1196         }
1197
1198         if (!list_empty(&drv_data->queue) || drv_data->busy)
1199                 status = -EBUSY;
1200
1201         spin_unlock_irqrestore(&drv_data->lock, flags);
1202
1203         return status;
1204 }
1205
1206 static inline int destroy_queue(struct driver_data *drv_data)
1207 {
1208         int status;
1209
1210         status = stop_queue(drv_data);
1211         if (status != 0)
1212                 return status;
1213
1214         destroy_workqueue(drv_data->workqueue);
1215
1216         return 0;
1217 }
1218
1219 static int setup_pin_mux(int action, int bus_num)
1220 {
1221
1222         u16 pin_req[3][4] = {
1223                 {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1224                 {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1225                 {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
1226         };
1227
1228         if (action) {
1229                 if (peripheral_request_list(pin_req[bus_num], DRV_NAME))
1230                         return -EFAULT;
1231         } else {
1232                 peripheral_free_list(pin_req[bus_num]);
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1239 {
1240         struct device *dev = &pdev->dev;
1241         struct bfin5xx_spi_master *platform_info;
1242         struct spi_master *master;
1243         struct driver_data *drv_data = 0;
1244         struct resource *res;
1245         int status = 0;
1246
1247         platform_info = dev->platform_data;
1248
1249         /* Allocate master with space for drv_data */
1250         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1251         if (!master) {
1252                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1253                 return -ENOMEM;
1254         }
1255
1256         drv_data = spi_master_get_devdata(master);
1257         drv_data->master = master;
1258         drv_data->master_info = platform_info;
1259         drv_data->pdev = pdev;
1260
1261         master->bus_num = pdev->id;
1262         master->num_chipselect = platform_info->num_chipselect;
1263         master->cleanup = cleanup;
1264         master->setup = setup;
1265         master->transfer = transfer;
1266
1267         /* Find and map our resources */
1268         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269         if (res == NULL) {
1270                 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1271                 status = -ENOENT;
1272                 goto out_error_get_res;
1273         }
1274
1275         spi_regs_base = (u32) ioremap(res->start, (res->end - res->start)+1);
1276         if (!spi_regs_base) {
1277                 dev_err(dev, "Cannot map IO\n");
1278                 status = -ENXIO;
1279                 goto out_error_ioremap;
1280         }
1281
1282         spi_dma_ch = platform_get_irq(pdev, 0);
1283         if (spi_dma_ch < 0) {
1284                 dev_err(dev, "No DMA channel specified\n");
1285                 status = -ENOENT;
1286                 goto out_error_no_dma_ch;
1287         }
1288
1289         /* Initial and start queue */
1290         status = init_queue(drv_data);
1291         if (status != 0) {
1292                 dev_err(dev, "problem initializing queue\n");
1293                 goto out_error_queue_alloc;
1294         }
1295
1296         status = start_queue(drv_data);
1297         if (status != 0) {
1298                 dev_err(dev, "problem starting queue\n");
1299                 goto out_error_queue_alloc;
1300         }
1301
1302         /* Register with the SPI framework */
1303         platform_set_drvdata(pdev, drv_data);
1304         status = spi_register_master(master);
1305         if (status != 0) {
1306                 dev_err(dev, "problem registering spi master\n");
1307                 goto out_error_queue_alloc;
1308         }
1309
1310         if (setup_pin_mux(1, master->bus_num)) {
1311                 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1312                 goto out_error;
1313         }
1314
1315         dev_info(dev, "%s, Version %s, regs_base @ 0x%08x\n",
1316                 DRV_DESC, DRV_VERSION, spi_regs_base);
1317         return status;
1318
1319 out_error_queue_alloc:
1320         destroy_queue(drv_data);
1321 out_error_no_dma_ch:
1322         iounmap((void *) spi_regs_base);
1323 out_error_ioremap:
1324 out_error_get_res:
1325 out_error:
1326         spi_master_put(master);
1327
1328         return status;
1329 }
1330
1331 /* stop hardware and remove the driver */
1332 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1333 {
1334         struct driver_data *drv_data = platform_get_drvdata(pdev);
1335         int status = 0;
1336
1337         if (!drv_data)
1338                 return 0;
1339
1340         /* Remove the queue */
1341         status = destroy_queue(drv_data);
1342         if (status != 0)
1343                 return status;
1344
1345         /* Disable the SSP at the peripheral and SOC level */
1346         bfin_spi_disable(drv_data);
1347
1348         /* Release DMA */
1349         if (drv_data->master_info->enable_dma) {
1350                 if (dma_channel_active(spi_dma_ch))
1351                         free_dma(spi_dma_ch);
1352         }
1353
1354         /* Disconnect from the SPI framework */
1355         spi_unregister_master(drv_data->master);
1356
1357         setup_pin_mux(0, drv_data->master->bus_num);
1358
1359         /* Prevent double remove */
1360         platform_set_drvdata(pdev, NULL);
1361
1362         return 0;
1363 }
1364
1365 #ifdef CONFIG_PM
1366 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1367 {
1368         struct driver_data *drv_data = platform_get_drvdata(pdev);
1369         int status = 0;
1370
1371         status = stop_queue(drv_data);
1372         if (status != 0)
1373                 return status;
1374
1375         /* stop hardware */
1376         bfin_spi_disable(drv_data);
1377
1378         return 0;
1379 }
1380
1381 static int bfin5xx_spi_resume(struct platform_device *pdev)
1382 {
1383         struct driver_data *drv_data = platform_get_drvdata(pdev);
1384         int status = 0;
1385
1386         /* Enable the SPI interface */
1387         bfin_spi_enable(drv_data);
1388
1389         /* Start the queue running */
1390         status = start_queue(drv_data);
1391         if (status != 0) {
1392                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1393                 return status;
1394         }
1395
1396         return 0;
1397 }
1398 #else
1399 #define bfin5xx_spi_suspend NULL
1400 #define bfin5xx_spi_resume NULL
1401 #endif                          /* CONFIG_PM */
1402
1403 MODULE_ALIAS("bfin-spi-master");        /* for platform bus hotplug */
1404 static struct platform_driver bfin5xx_spi_driver = {
1405         .driver = {
1406                 .name   = DRV_NAME,
1407                 .owner  = THIS_MODULE,
1408         },
1409         .suspend        = bfin5xx_spi_suspend,
1410         .resume         = bfin5xx_spi_resume,
1411         .remove         = __devexit_p(bfin5xx_spi_remove),
1412 };
1413
1414 static int __init bfin5xx_spi_init(void)
1415 {
1416         return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1417 }
1418 module_init(bfin5xx_spi_init);
1419
1420 static void __exit bfin5xx_spi_exit(void)
1421 {
1422         platform_driver_unregister(&bfin5xx_spi_driver);
1423 }
1424 module_exit(bfin5xx_spi_exit);