2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
4 * Copyright (C) 2007, 2008 Magnus Damm
6 * Based on intc2.c and ipr.c
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/sh_intc.h>
24 #include <linux/sysdev.h>
25 #include <linux/list.h>
26 #include <linux/topology.h>
28 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
29 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
30 ((addr_e) << 16) | ((addr_d << 24)))
32 #define _INTC_SHIFT(h) (h & 0x1f)
33 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
34 #define _INTC_FN(h) ((h >> 9) & 0xf)
35 #define _INTC_MODE(h) ((h >> 13) & 0x7)
36 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
37 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
39 struct intc_handle_int {
44 struct intc_desc_int {
45 struct list_head list;
46 struct sys_device sysdev;
53 struct intc_handle_int *prio;
55 struct intc_handle_int *sense;
56 unsigned int nr_sense;
60 static LIST_HEAD(intc_list);
63 #define IS_SMP(x) x.smp
64 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
65 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
68 #define INTC_REG(d, x, c) (d->reg[(x)])
69 #define SMP_NR(d, x) 1
72 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
73 static unsigned long ack_handle[NR_IRQS];
75 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
77 struct irq_chip *chip = get_irq_chip(irq);
78 return container_of(chip, struct intc_desc_int, chip);
81 static inline unsigned int set_field(unsigned int value,
82 unsigned int field_value,
85 unsigned int width = _INTC_WIDTH(handle);
86 unsigned int shift = _INTC_SHIFT(handle);
88 value &= ~(((1 << width) - 1) << shift);
89 value |= field_value << shift;
93 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
95 __raw_writeb(set_field(0, data, h), addr);
96 (void)__raw_readb(addr); /* Defeat write posting */
99 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
101 __raw_writew(set_field(0, data, h), addr);
102 (void)__raw_readw(addr); /* Defeat write posting */
105 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
107 __raw_writel(set_field(0, data, h), addr);
108 (void)__raw_readl(addr); /* Defeat write posting */
111 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
114 local_irq_save(flags);
115 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
116 (void)__raw_readb(addr); /* Defeat write posting */
117 local_irq_restore(flags);
120 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
123 local_irq_save(flags);
124 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
125 (void)__raw_readw(addr); /* Defeat write posting */
126 local_irq_restore(flags);
129 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
132 local_irq_save(flags);
133 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
134 (void)__raw_readl(addr); /* Defeat write posting */
135 local_irq_restore(flags);
138 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
140 static void (*intc_reg_fns[])(unsigned long addr,
142 unsigned long data) = {
143 [REG_FN_WRITE_BASE + 0] = write_8,
144 [REG_FN_WRITE_BASE + 1] = write_16,
145 [REG_FN_WRITE_BASE + 3] = write_32,
146 [REG_FN_MODIFY_BASE + 0] = modify_8,
147 [REG_FN_MODIFY_BASE + 1] = modify_16,
148 [REG_FN_MODIFY_BASE + 3] = modify_32,
151 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
152 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
153 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
154 MODE_PRIO_REG, /* Priority value written to enable interrupt */
155 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
158 static void intc_mode_field(unsigned long addr,
159 unsigned long handle,
160 void (*fn)(unsigned long,
165 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
168 static void intc_mode_zero(unsigned long addr,
169 unsigned long handle,
170 void (*fn)(unsigned long,
178 static void intc_mode_prio(unsigned long addr,
179 unsigned long handle,
180 void (*fn)(unsigned long,
185 fn(addr, handle, intc_prio_level[irq]);
188 static void (*intc_enable_fns[])(unsigned long addr,
189 unsigned long handle,
190 void (*fn)(unsigned long,
193 unsigned int irq) = {
194 [MODE_ENABLE_REG] = intc_mode_field,
195 [MODE_MASK_REG] = intc_mode_zero,
196 [MODE_DUAL_REG] = intc_mode_field,
197 [MODE_PRIO_REG] = intc_mode_prio,
198 [MODE_PCLR_REG] = intc_mode_prio,
201 static void (*intc_disable_fns[])(unsigned long addr,
202 unsigned long handle,
203 void (*fn)(unsigned long,
206 unsigned int irq) = {
207 [MODE_ENABLE_REG] = intc_mode_zero,
208 [MODE_MASK_REG] = intc_mode_field,
209 [MODE_DUAL_REG] = intc_mode_field,
210 [MODE_PRIO_REG] = intc_mode_zero,
211 [MODE_PCLR_REG] = intc_mode_field,
214 static inline void _intc_enable(unsigned int irq, unsigned long handle)
216 struct intc_desc_int *d = get_intc_desc(irq);
220 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
221 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
222 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
223 [_INTC_FN(handle)], irq);
227 static void intc_enable(unsigned int irq)
229 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
232 static void intc_disable(unsigned int irq)
234 struct intc_desc_int *d = get_intc_desc(irq);
235 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
239 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
240 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
241 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
242 [_INTC_FN(handle)], irq);
246 static int intc_set_wake(unsigned int irq, unsigned int on)
248 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
251 static void intc_mask_ack(unsigned int irq)
253 struct intc_desc_int *d = get_intc_desc(irq);
254 unsigned long handle = ack_handle[irq];
259 /* read register and write zero only to the assocaited bit */
262 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
263 switch (_INTC_FN(handle)) {
264 case REG_FN_MODIFY_BASE + 0: /* 8bit */
266 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
268 case REG_FN_MODIFY_BASE + 1: /* 16bit */
270 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
272 case REG_FN_MODIFY_BASE + 3: /* 32bit */
274 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
283 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
289 /* this doesn't scale well, but...
291 * this function should only be used for cerain uncommon
292 * operations such as intc_set_priority() and intc_set_sense()
293 * and in those rare cases performance doesn't matter that much.
294 * keeping the memory footprint low is more important.
296 * one rather simple way to speed this up and still keep the
297 * memory footprint down is to make sure the array is sorted
298 * and then perform a bisect to lookup the irq.
301 for (i = 0; i < nr_hp; i++) {
302 if ((hp + i)->irq != irq)
311 int intc_set_priority(unsigned int irq, unsigned int prio)
313 struct intc_desc_int *d = get_intc_desc(irq);
314 struct intc_handle_int *ihp;
316 if (!intc_prio_level[irq] || prio <= 1)
319 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
321 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
324 intc_prio_level[irq] = prio;
327 * only set secondary masking method directly
328 * primary masking method is using intc_prio_level[irq]
329 * priority level will be set during next enable()
332 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
333 _intc_enable(irq, ihp->handle);
338 #define VALID(x) (x | 0x80)
340 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
341 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
342 [IRQ_TYPE_EDGE_RISING] = VALID(1),
343 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
344 /* SH7706, SH7707 and SH7709 do not support high level triggered */
345 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
346 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
347 !defined(CONFIG_CPU_SUBTYPE_SH7709)
348 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
352 static int intc_set_sense(unsigned int irq, unsigned int type)
354 struct intc_desc_int *d = get_intc_desc(irq);
355 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
356 struct intc_handle_int *ihp;
362 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
364 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
365 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
370 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
371 unsigned long address)
375 for (k = 0; k < d->nr_reg; k++) {
376 if (d->reg[k] == address)
384 static intc_enum __init intc_grp_id(struct intc_desc *desc,
387 struct intc_group *g = desc->groups;
390 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
391 g = desc->groups + i;
393 for (j = 0; g->enum_ids[j]; j++) {
394 if (g->enum_ids[j] != enum_id)
404 static unsigned int __init intc_mask_data(struct intc_desc *desc,
405 struct intc_desc_int *d,
406 intc_enum enum_id, int do_grps)
408 struct intc_mask_reg *mr = desc->mask_regs;
409 unsigned int i, j, fn, mode;
410 unsigned long reg_e, reg_d;
412 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
413 mr = desc->mask_regs + i;
415 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
416 if (mr->enum_ids[j] != enum_id)
419 if (mr->set_reg && mr->clr_reg) {
420 fn = REG_FN_WRITE_BASE;
421 mode = MODE_DUAL_REG;
425 fn = REG_FN_MODIFY_BASE;
427 mode = MODE_ENABLE_REG;
431 mode = MODE_MASK_REG;
437 fn += (mr->reg_width >> 3) - 1;
438 return _INTC_MK(fn, mode,
439 intc_get_reg(d, reg_e),
440 intc_get_reg(d, reg_d),
442 (mr->reg_width - 1) - j);
447 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
452 static unsigned int __init intc_prio_data(struct intc_desc *desc,
453 struct intc_desc_int *d,
454 intc_enum enum_id, int do_grps)
456 struct intc_prio_reg *pr = desc->prio_regs;
457 unsigned int i, j, fn, mode, bit;
458 unsigned long reg_e, reg_d;
460 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
461 pr = desc->prio_regs + i;
463 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
464 if (pr->enum_ids[j] != enum_id)
467 if (pr->set_reg && pr->clr_reg) {
468 fn = REG_FN_WRITE_BASE;
469 mode = MODE_PCLR_REG;
473 fn = REG_FN_MODIFY_BASE;
474 mode = MODE_PRIO_REG;
481 fn += (pr->reg_width >> 3) - 1;
483 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
485 bit = pr->reg_width - ((j + 1) * pr->field_width);
487 return _INTC_MK(fn, mode,
488 intc_get_reg(d, reg_e),
489 intc_get_reg(d, reg_d),
490 pr->field_width, bit);
495 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
500 static unsigned int __init intc_ack_data(struct intc_desc *desc,
501 struct intc_desc_int *d,
504 struct intc_mask_reg *mr = desc->ack_regs;
505 unsigned int i, j, fn, mode;
506 unsigned long reg_e, reg_d;
508 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
509 mr = desc->ack_regs + i;
511 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
512 if (mr->enum_ids[j] != enum_id)
515 fn = REG_FN_MODIFY_BASE;
516 mode = MODE_ENABLE_REG;
520 fn += (mr->reg_width >> 3) - 1;
521 return _INTC_MK(fn, mode,
522 intc_get_reg(d, reg_e),
523 intc_get_reg(d, reg_d),
525 (mr->reg_width - 1) - j);
532 static unsigned int __init intc_sense_data(struct intc_desc *desc,
533 struct intc_desc_int *d,
536 struct intc_sense_reg *sr = desc->sense_regs;
537 unsigned int i, j, fn, bit;
539 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
540 sr = desc->sense_regs + i;
542 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
543 if (sr->enum_ids[j] != enum_id)
546 fn = REG_FN_MODIFY_BASE;
547 fn += (sr->reg_width >> 3) - 1;
549 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
551 bit = sr->reg_width - ((j + 1) * sr->field_width);
553 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
554 0, sr->field_width, bit);
561 static void __init intc_register_irq(struct intc_desc *desc,
562 struct intc_desc_int *d,
566 struct intc_handle_int *hp;
567 unsigned int data[2], primary;
569 /* Prefer single interrupt source bitmap over other combinations:
570 * 1. bitmap, single interrupt source
571 * 2. priority, single interrupt source
572 * 3. bitmap, multiple interrupt sources (groups)
573 * 4. priority, multiple interrupt sources (groups)
576 data[0] = intc_mask_data(desc, d, enum_id, 0);
577 data[1] = intc_prio_data(desc, d, enum_id, 0);
580 if (!data[0] && data[1])
583 if (!data[0] && !data[1])
584 pr_warning("intc: missing unique irq mask for "
585 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
587 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
588 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
593 BUG_ON(!data[primary]); /* must have primary masking method */
595 disable_irq_nosync(irq);
596 set_irq_chip_and_handler_name(irq, &d->chip,
597 handle_level_irq, "level");
598 set_irq_chip_data(irq, (void *)data[primary]);
600 /* set priority level
601 * - this needs to be at least 2 for 5-bit priorities on 7780
603 intc_prio_level[irq] = 2;
605 /* enable secondary masking method if present */
607 _intc_enable(irq, data[!primary]);
609 /* add irq to d->prio list if priority is available */
611 hp = d->prio + d->nr_prio;
613 hp->handle = data[1];
617 * only secondary priority should access registers, so
618 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
621 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
622 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
627 /* add irq to d->sense list if sense is available */
628 data[0] = intc_sense_data(desc, d, enum_id);
630 (d->sense + d->nr_sense)->irq = irq;
631 (d->sense + d->nr_sense)->handle = data[0];
635 /* irq should be disabled by default */
639 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
642 static unsigned int __init save_reg(struct intc_desc_int *d,
658 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
660 generic_handle_irq((unsigned int)get_irq_data(irq));
663 void __init register_intc_controller(struct intc_desc *desc)
665 unsigned int i, k, smp;
666 struct intc_desc_int *d;
668 d = kzalloc(sizeof(*d), GFP_NOWAIT);
670 INIT_LIST_HEAD(&d->list);
671 list_add(&d->list, &intc_list);
673 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
674 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
675 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
676 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
678 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
680 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
684 if (desc->mask_regs) {
685 for (i = 0; i < desc->nr_mask_regs; i++) {
686 smp = IS_SMP(desc->mask_regs[i]);
687 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
688 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
692 if (desc->prio_regs) {
693 d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
695 for (i = 0; i < desc->nr_prio_regs; i++) {
696 smp = IS_SMP(desc->prio_regs[i]);
697 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
698 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
702 if (desc->sense_regs) {
703 d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
705 for (i = 0; i < desc->nr_sense_regs; i++) {
706 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
710 d->chip.name = desc->name;
711 d->chip.mask = intc_disable;
712 d->chip.unmask = intc_enable;
713 d->chip.mask_ack = intc_disable;
714 d->chip.enable = intc_enable;
715 d->chip.disable = intc_disable;
716 d->chip.shutdown = intc_disable;
717 d->chip.set_type = intc_set_sense;
718 d->chip.set_wake = intc_set_wake;
720 if (desc->ack_regs) {
721 for (i = 0; i < desc->nr_ack_regs; i++)
722 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
724 d->chip.mask_ack = intc_mask_ack;
727 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
729 /* register the vectors one by one */
730 for (i = 0; i < desc->nr_vectors; i++) {
731 struct intc_vect *vect = desc->vectors + i;
732 unsigned int irq = evt2irq(vect->vect);
733 struct irq_desc *irq_desc;
738 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
739 if (unlikely(!irq_desc)) {
740 pr_info("can't get irq_desc for %d\n", irq);
744 intc_register_irq(desc, d, vect->enum_id, irq);
746 for (k = i + 1; k < desc->nr_vectors; k++) {
747 struct intc_vect *vect2 = desc->vectors + k;
748 unsigned int irq2 = evt2irq(vect2->vect);
750 if (vect->enum_id != vect2->enum_id)
754 * In the case of multi-evt handling and sparse
755 * IRQ support, each vector still needs to have
756 * its own backing irq_desc.
758 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
759 if (unlikely(!irq_desc)) {
760 pr_info("can't get irq_desc for %d\n", irq2);
766 /* redirect this interrupts to the first one */
767 set_irq_chip_and_handler_name(irq2, &d->chip,
768 intc_redirect_irq, "redirect");
769 set_irq_data(irq2, (void *)irq);
774 static int intc_suspend(struct sys_device *dev, pm_message_t state)
776 struct intc_desc_int *d;
777 struct irq_desc *desc;
780 /* get intc controller associated with this sysdev */
781 d = container_of(dev, struct intc_desc_int, sysdev);
783 switch (state.event) {
785 if (d->state.event != PM_EVENT_FREEZE)
787 for_each_irq_desc(irq, desc) {
788 if (desc->chip != &d->chip)
790 if (desc->status & IRQ_DISABLED)
796 case PM_EVENT_FREEZE:
797 /* nothing has to be done */
799 case PM_EVENT_SUSPEND:
800 /* enable wakeup irqs belonging to this intc controller */
801 for_each_irq_desc(irq, desc) {
802 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
812 static int intc_resume(struct sys_device *dev)
814 return intc_suspend(dev, PMSG_ON);
817 static struct sysdev_class intc_sysdev_class = {
819 .suspend = intc_suspend,
820 .resume = intc_resume,
823 /* register this intc as sysdev to allow suspend/resume */
824 static int __init register_intc_sysdevs(void)
826 struct intc_desc_int *d;
830 error = sysdev_class_register(&intc_sysdev_class);
832 list_for_each_entry(d, &intc_list, list) {
834 d->sysdev.cls = &intc_sysdev_class;
835 error = sysdev_register(&d->sysdev);
843 pr_warning("intc: sysdev registration error\n");
848 device_initcall(register_intc_sysdevs);