SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/byteorder.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_cmnd.h>
  34 #include <scsi/scsi_host.h>
  35 #include <scsi/scsi_tcq.h>
  36 #include <scsi/scsi_dbg.h>
  37 #include <scsi/scsi_eh.h>
  38
  39 #define DRV_NAME "stex"
  40 #define ST_DRIVER_VERSION "4.6.0000.4"
  41 #define ST_VER_MAJOR            4
  42 #define ST_VER_MINOR            6
  43 #define ST_OEM                  0
  44 #define ST_BUILD_VER            4
  45
  46 enum {
  47         /* MU register offset */
  48         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  49         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  50         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  51         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  52         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  53         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  54         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  55         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  56         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  57         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  58
  59         YIOA_STATUS                             = 0x00,
  60         YH2I_INT                                = 0x20,
  61         YINT_EN                                 = 0x34,
  62         YI2H_INT                                = 0x9c,
  63         YI2H_INT_C                              = 0xa0,
  64         YH2I_REQ                                = 0xc0,
  65         YH2I_REQ_HI                             = 0xc4,
  66
  67         /* MU register value */
  68         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  69         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  70         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  71         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  72         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  73
  74         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  75         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  76         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  77         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  78         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  79         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  80
  81         /* MU status code */
  82         MU_STATE_STARTING                       = 1,
  83         MU_STATE_STARTED                        = 2,
  84         MU_STATE_RESETTING                      = 3,
  85         MU_STATE_FAILED                         = 4,
  86
  87         MU_MAX_DELAY                            = 120,
  88         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  89         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  90         MU_HARD_RESET_WAIT                      = 30000,
  91         HMU_PARTNER_TYPE                        = 2,
  92
  93         /* firmware returned values */
  94         SRB_STATUS_SUCCESS                      = 0x01,
  95         SRB_STATUS_ERROR                        = 0x04,
  96         SRB_STATUS_BUSY                         = 0x05,
  97         SRB_STATUS_INVALID_REQUEST              = 0x06,
  98         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  99         SRB_SEE_SENSE                           = 0x80,
 100
 101         /* task attribute */
 102         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 103         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 104         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 105         TASK_ATTRIBUTE_ACA                      = 0x4,
 106
 107         SS_STS_NORMAL                           = 0x80000000,
 108         SS_STS_DONE                             = 0x40000000,
 109         SS_STS_HANDSHAKE                        = 0x20000000,
 110
 111         SS_HEAD_HANDSHAKE                       = 0x80,
 112
 113         SS_H2I_INT_RESET                        = 0x100,
 114
 115         SS_I2H_REQUEST_RESET                    = 0x2000,
 116
 117         SS_MU_OPERATIONAL                       = 0x80000000,
 118
 119         STEX_CDB_LENGTH                         = 16,
 120         STATUS_VAR_LEN                          = 128,
 121
 122         /* sg flags */
 123         SG_CF_EOT                               = 0x80, /* end of table */
 124         SG_CF_64B                               = 0x40, /* 64 bit item */
 125         SG_CF_HOST                              = 0x20, /* sg in host memory */
 126         MSG_DATA_DIR_ND                         = 0,
 127         MSG_DATA_DIR_IN                         = 1,
 128         MSG_DATA_DIR_OUT                        = 2,
 129
 130         st_shasta                               = 0,
 131         st_vsc                                  = 1,
 132         st_yosemite                             = 2,
 133         st_seq                                  = 3,
 134         st_yel                                  = 4,
 135
 136         PASSTHRU_REQ_TYPE                       = 0x00000001,
 137         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 138         ST_INTERNAL_TIMEOUT                     = 180,
 139
 140         ST_TO_CMD                               = 0,
 141         ST_FROM_CMD                             = 1,
 142
 143         /* vendor specific commands of Promise */
 144         MGT_CMD                                 = 0xd8,
 145         SINBAND_MGT_CMD                         = 0xd9,
 146         ARRAY_CMD                               = 0xe0,
 147         CONTROLLER_CMD                          = 0xe1,
 148         DEBUGGING_CMD                           = 0xe2,
 149         PASSTHRU_CMD                            = 0xe3,
 150
 151         PASSTHRU_GET_ADAPTER                    = 0x05,
 152         PASSTHRU_GET_DRVVER                     = 0x10,
 153
 154         CTLR_CONFIG_CMD                         = 0x03,
 155         CTLR_SHUTDOWN                           = 0x0d,
 156
 157         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 158         CTLR_POWER_SAVING                       = 0x01,
 159
 160         PASSTHRU_SIGNATURE                      = 0x4e415041,
 161         MGT_CMD_SIGNATURE                       = 0xba,
 162
 163         INQUIRY_EVPD                            = 0x01,
 164
 165         ST_ADDITIONAL_MEM                       = 0x200000,
 166         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 167 };
 168
 169 struct st_sgitem {
 170         u8 ctrl;        /* SG_CF_xxx */
 171         u8 reserved[3];
 172         __le32 count;
 173         __le64 addr;
 174 };
 175
 176 struct st_ss_sgitem {
 177         __le32 addr;
 178         __le32 addr_hi;
 179         __le32 count;
 180 };
 181
 182 struct st_sgtable {
 183         __le16 sg_count;
 184         __le16 max_sg_count;
 185         __le32 sz_in_byte;
 186 };
 187
 188 struct st_msg_header {
 189         __le64 handle;
 190         u8 flag;
 191         u8 channel;
 192         __le16 timeout;
 193         u32 reserved;
 194 };
 195
 196 struct handshake_frame {
 197         __le64 rb_phy;          /* request payload queue physical address */
 198         __le16 req_sz;          /* size of each request payload */
 199         __le16 req_cnt;         /* count of reqs the buffer can hold */
 200         __le16 status_sz;       /* size of each status payload */
 201         __le16 status_cnt;      /* count of status the buffer can hold */
 202         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 203         u8 partner_type;        /* who sends this frame */
 204         u8 reserved0[7];
 205         __le32 partner_ver_major;
 206         __le32 partner_ver_minor;
 207         __le32 partner_ver_oem;
 208         __le32 partner_ver_build;
 209         __le32 extra_offset;    /* NEW */
 210         __le32 extra_size;      /* NEW */
 211         __le32 scratch_size;
 212         u32 reserved1;
 213 };
 214
 215 struct req_msg {
 216         __le16 tag;
 217         u8 lun;
 218         u8 target;
 219         u8 task_attr;
 220         u8 task_manage;
 221         u8 data_dir;
 222         u8 payload_sz;          /* payload size in 4-byte, not used */
 223         u8 cdb[STEX_CDB_LENGTH];
 224         u32 variable[0];
 225 };
 226
 227 struct status_msg {
 228         __le16 tag;
 229         u8 lun;
 230         u8 target;
 231         u8 srb_status;
 232         u8 scsi_status;
 233         u8 reserved;
 234         u8 payload_sz;          /* payload size in 4-byte */
 235         u8 variable[STATUS_VAR_LEN];
 236 };
 237
 238 struct ver_info {
 239         u32 major;
 240         u32 minor;
 241         u32 oem;
 242         u32 build;
 243         u32 reserved[2];
 244 };
 245
 246 struct st_frame {
 247         u32 base[6];
 248         u32 rom_addr;
 249
 250         struct ver_info drv_ver;
 251         struct ver_info bios_ver;
 252
 253         u32 bus;
 254         u32 slot;
 255         u32 irq_level;
 256         u32 irq_vec;
 257         u32 id;
 258         u32 subid;
 259
 260         u32 dimm_size;
 261         u8 dimm_type;
 262         u8 reserved[3];
 263
 264         u32 channel;
 265         u32 reserved1;
 266 };
 267
 268 struct st_drvver {
 269         u32 major;
 270         u32 minor;
 271         u32 oem;
 272         u32 build;
 273         u32 signature[2];
 274         u8 console_id;
 275         u8 host_no;
 276         u8 reserved0[2];
 277         u32 reserved[3];
 278 };
 279
 280 struct st_ccb {
 281         struct req_msg *req;
 282         struct scsi_cmnd *cmd;
 283
 284         void *sense_buffer;
 285         unsigned int sense_bufflen;
 286         int sg_count;
 287
 288         u32 req_type;
 289         u8 srb_status;
 290         u8 scsi_status;
 291         u8 reserved[2];
 292 };
 293
 294 struct st_hba {
 295         void __iomem *mmio_base;        /* iomapped PCI memory space */
 296         void *dma_mem;
 297         dma_addr_t dma_handle;
 298         size_t dma_size;
 299
 300         struct Scsi_Host *host;
 301         struct pci_dev *pdev;
 302
 303         struct req_msg * (*alloc_rq) (struct st_hba *);
 304         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 305         void (*send) (struct st_hba *, struct req_msg *, u16);
 306
 307         u32 req_head;
 308         u32 req_tail;
 309         u32 status_head;
 310         u32 status_tail;
 311
 312         struct status_msg *status_buffer;
 313         void *copy_buffer; /* temp buffer for driver-handled commands */
 314         struct st_ccb *ccb;
 315         struct st_ccb *wait_ccb;
 316         __le32 *scratch;
 317
 318         char work_q_name[20];
 319         struct workqueue_struct *work_q;
 320         struct work_struct reset_work;
 321         wait_queue_head_t reset_waitq;
 322         unsigned int mu_status;
 323         unsigned int cardtype;
 324         int msi_enabled;
 325         int out_req_cnt;
 326         u32 extra_offset;
 327         u16 rq_count;
 328         u16 rq_size;
 329         u16 sts_count;
 330 };
 331
 332 struct st_card_info {
 333         struct req_msg * (*alloc_rq) (struct st_hba *);
 334         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 335         void (*send) (struct st_hba *, struct req_msg *, u16);
 336         unsigned int max_id;
 337         unsigned int max_lun;
 338         unsigned int max_channel;
 339         u16 rq_count;
 340         u16 rq_size;
 341         u16 sts_count;
 342 };
 343
 344 static int msi;
 345 module_param(msi, int, 0);
 346 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 347
 348 static const char console_inq_page[] =
 349 {
 350         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 351         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 352         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 353         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 354         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 355         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 356         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 357         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 358 };
 359
 360 MODULE_AUTHOR("Ed Lin");
 361 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 362 MODULE_LICENSE("GPL");
 363 MODULE_VERSION(ST_DRIVER_VERSION);
 364
 365 static void stex_gettime(__le64 *time)
 366 {
 367         struct timeval tv;
 368
 369         do_gettimeofday(&tv);
 370         *time = cpu_to_le64(tv.tv_sec);
 371 }
 372
 373 static struct status_msg *stex_get_status(struct st_hba *hba)
 374 {
 375         struct status_msg *status = hba->status_buffer + hba->status_tail;
 376
 377         ++hba->status_tail;
 378         hba->status_tail %= hba->sts_count+1;
 379
 380         return status;
 381 }
 382
 383 static void stex_invalid_field(struct scsi_cmnd *cmd,
 384                                void (*done)(struct scsi_cmnd *))
 385 {
 386         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 387
 388         /* "Invalid field in cdb" */
 389         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 390                                 0x0);
 391         done(cmd);
 392 }
 393
 394 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 395 {
 396         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 397
 398         ++hba->req_head;
 399         hba->req_head %= hba->rq_count+1;
 400
 401         return req;
 402 }
 403
 404 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 405 {
 406         return (struct req_msg *)(hba->dma_mem +
 407                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 408 }
 409
 410 static int stex_map_sg(struct st_hba *hba,
 411         struct req_msg *req, struct st_ccb *ccb)
 412 {
 413         struct scsi_cmnd *cmd;
 414         struct scatterlist *sg;
 415         struct st_sgtable *dst;
 416         struct st_sgitem *table;
 417         int i, nseg;
 418
 419         cmd = ccb->cmd;
 420         nseg = scsi_dma_map(cmd);
 421         BUG_ON(nseg < 0);
 422         if (nseg) {
 423                 dst = (struct st_sgtable *)req->variable;
 424
 425                 ccb->sg_count = nseg;
 426                 dst->sg_count = cpu_to_le16((u16)nseg);
 427                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 428                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 429
 430                 table = (struct st_sgitem *)(dst + 1);
 431                 scsi_for_each_sg(cmd, sg, nseg, i) {
 432                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 433                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 434                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 435                 }
 436                 table[--i].ctrl |= SG_CF_EOT;
 437         }
 438
 439         return nseg;
 440 }
 441
 442 static int stex_ss_map_sg(struct st_hba *hba,
 443         struct req_msg *req, struct st_ccb *ccb)
 444 {
 445         struct scsi_cmnd *cmd;
 446         struct scatterlist *sg;
 447         struct st_sgtable *dst;
 448         struct st_ss_sgitem *table;
 449         int i, nseg;
 450
 451         cmd = ccb->cmd;
 452         nseg = scsi_dma_map(cmd);
 453         BUG_ON(nseg < 0);
 454         if (nseg) {
 455                 dst = (struct st_sgtable *)req->variable;
 456
 457                 ccb->sg_count = nseg;
 458                 dst->sg_count = cpu_to_le16((u16)nseg);
 459                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 460                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 461
 462                 table = (struct st_ss_sgitem *)(dst + 1);
 463                 scsi_for_each_sg(cmd, sg, nseg, i) {
 464                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 465                         table[i].addr =
 466                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 467                         table[i].addr_hi =
 468                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 469                 }
 470         }
 471
 472         return nseg;
 473 }
 474
 475 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 476 {
 477         struct st_frame *p;
 478         size_t count = sizeof(struct st_frame);
 479
 480         p = hba->copy_buffer;
 481         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 482         memset(p->base, 0, sizeof(u32)*6);
 483         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 484         p->rom_addr = 0;
 485
 486         p->drv_ver.major = ST_VER_MAJOR;
 487         p->drv_ver.minor = ST_VER_MINOR;
 488         p->drv_ver.oem = ST_OEM;
 489         p->drv_ver.build = ST_BUILD_VER;
 490
 491         p->bus = hba->pdev->bus->number;
 492         p->slot = hba->pdev->devfn;
 493         p->irq_level = 0;
 494         p->irq_vec = hba->pdev->irq;
 495         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 496         p->subid =
 497                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 498
 499         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 500 }
 501
 502 static void
 503 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 504 {
 505         req->tag = cpu_to_le16(tag);
 506
 507         hba->ccb[tag].req = req;
 508         hba->out_req_cnt++;
 509
 510         writel(hba->req_head, hba->mmio_base + IMR0);
 511         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 512         readl(hba->mmio_base + IDBL); /* flush */
 513 }
 514
 515 static void
 516 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 517 {
 518         struct scsi_cmnd *cmd;
 519         struct st_msg_header *msg_h;
 520         dma_addr_t addr;
 521
 522         req->tag = cpu_to_le16(tag);
 523
 524         hba->ccb[tag].req = req;
 525         hba->out_req_cnt++;
 526
 527         cmd = hba->ccb[tag].cmd;
 528         msg_h = (struct st_msg_header *)req - 1;
 529         if (likely(cmd)) {
 530                 msg_h->channel = (u8)cmd->device->channel;
 531                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 532         }
 533         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 534         addr += (hba->ccb[tag].sg_count+4)/11;
 535         msg_h->handle = cpu_to_le64(addr);
 536
 537         ++hba->req_head;
 538         hba->req_head %= hba->rq_count+1;
 539
 540         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 541         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 542         writel(addr, hba->mmio_base + YH2I_REQ);
 543         readl(hba->mmio_base + YH2I_REQ); /* flush */
 544 }
 545
 546 static int
 547 stex_slave_alloc(struct scsi_device *sdev)
 548 {
 549         /* Cheat: usually extracted from Inquiry data */
 550         sdev->tagged_supported = 1;
 551
 552         scsi_activate_tcq(sdev, sdev->host->can_queue);
 553
 554         return 0;
 555 }
 556
 557 static int
 558 stex_slave_config(struct scsi_device *sdev)
 559 {
 560         sdev->use_10_for_rw = 1;
 561         sdev->use_10_for_ms = 1;
 562         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 563         sdev->tagged_supported = 1;
 564
 565         return 0;
 566 }
 567
 568 static void
 569 stex_slave_destroy(struct scsi_device *sdev)
 570 {
 571         scsi_deactivate_tcq(sdev, 1);
 572 }
 573
 574 static int
 575 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
 576 {
 577         struct st_hba *hba;
 578         struct Scsi_Host *host;
 579         unsigned int id, lun;
 580         struct req_msg *req;
 581         u16 tag;
 582
 583         host = cmd->device->host;
 584         id = cmd->device->id;
 585         lun = cmd->device->lun;
 586         hba = (struct st_hba *) &host->hostdata[0];
 587
 588         if (unlikely(hba->mu_status == MU_STATE_RESETTING))
 589                 return SCSI_MLQUEUE_HOST_BUSY;
 590
 591         switch (cmd->cmnd[0]) {
 592         case MODE_SENSE_10:
 593         {
 594                 static char ms10_caching_page[12] =
 595                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 596                 unsigned char page;
 597
 598                 page = cmd->cmnd[2] & 0x3f;
 599                 if (page == 0x8 || page == 0x3f) {
 600                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 601                                                  sizeof(ms10_caching_page));
 602                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 603                         done(cmd);
 604                 } else
 605                         stex_invalid_field(cmd, done);
 606                 return 0;
 607         }
 608         case REPORT_LUNS:
 609                 /*
 610                  * The shasta firmware does not report actual luns in the
 611                  * target, so fail the command to force sequential lun scan.
 612                  * Also, the console device does not support this command.
 613                  */
 614                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 615                         stex_invalid_field(cmd, done);
 616                         return 0;
 617                 }
 618                 break;
 619         case TEST_UNIT_READY:
 620                 if (id == host->max_id - 1) {
 621                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 622                         done(cmd);
 623                         return 0;
 624                 }
 625                 break;
 626         case INQUIRY:
 627                 if (lun >= host->max_lun) {
 628                         cmd->result = DID_NO_CONNECT << 16;
 629                         done(cmd);
 630                         return 0;
 631                 }
 632                 if (id != host->max_id - 1)
 633                         break;
 634                 if (!lun && !cmd->device->channel &&
 635                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 636                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 637                                                  sizeof(console_inq_page));
 638                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 639                         done(cmd);
 640                 } else
 641                         stex_invalid_field(cmd, done);
 642                 return 0;
 643         case PASSTHRU_CMD:
 644                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 645                         struct st_drvver ver;
 646                         size_t cp_len = sizeof(ver);
 647
 648                         ver.major = ST_VER_MAJOR;
 649                         ver.minor = ST_VER_MINOR;
 650                         ver.oem = ST_OEM;
 651                         ver.build = ST_BUILD_VER;
 652                         ver.signature[0] = PASSTHRU_SIGNATURE;
 653                         ver.console_id = host->max_id - 1;
 654                         ver.host_no = hba->host->host_no;
 655                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 656                         cmd->result = sizeof(ver) == cp_len ?
 657                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 658                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 659                         done(cmd);
 660                         return 0;
 661                 }
 662         default:
 663                 break;
 664         }
 665
 666         cmd->scsi_done = done;
 667
 668         tag = cmd->request->tag;
 669
 670         if (unlikely(tag >= host->can_queue))
 671                 return SCSI_MLQUEUE_HOST_BUSY;
 672
 673         req = hba->alloc_rq(hba);
 674
 675         req->lun = lun;
 676         req->target = id;
 677
 678         /* cdb */
 679         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 680
 681         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 682                 req->data_dir = MSG_DATA_DIR_IN;
 683         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 684                 req->data_dir = MSG_DATA_DIR_OUT;
 685         else
 686                 req->data_dir = MSG_DATA_DIR_ND;
 687
 688         hba->ccb[tag].cmd = cmd;
 689         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 690         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 691
 692         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 693                 hba->ccb[tag].sg_count = 0;
 694                 memset(&req->variable[0], 0, 8);
 695         }
 696
 697         hba->send(hba, req, tag);
 698         return 0;
 699 }
 700
 701 static void stex_scsi_done(struct st_ccb *ccb)
 702 {
 703         struct scsi_cmnd *cmd = ccb->cmd;
 704         int result;
 705
 706         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 707                 result = ccb->scsi_status;
 708                 switch (ccb->scsi_status) {
 709                 case SAM_STAT_GOOD:
 710                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 711                         break;
 712                 case SAM_STAT_CHECK_CONDITION:
 713                         result |= DRIVER_SENSE << 24;
 714                         break;
 715                 case SAM_STAT_BUSY:
 716                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 717                         break;
 718                 default:
 719                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 720                         break;
 721                 }
 722         }
 723         else if (ccb->srb_status & SRB_SEE_SENSE)
 724                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 725         else switch (ccb->srb_status) {
 726                 case SRB_STATUS_SELECTION_TIMEOUT:
 727                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 728                         break;
 729                 case SRB_STATUS_BUSY:
 730                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 731                         break;
 732                 case SRB_STATUS_INVALID_REQUEST:
 733                 case SRB_STATUS_ERROR:
 734                 default:
 735                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 736                         break;
 737         }
 738
 739         cmd->result = result;
 740         cmd->scsi_done(cmd);
 741 }
 742
 743 static void stex_copy_data(struct st_ccb *ccb,
 744         struct status_msg *resp, unsigned int variable)
 745 {
 746         if (resp->scsi_status != SAM_STAT_GOOD) {
 747                 if (ccb->sense_buffer != NULL)
 748                         memcpy(ccb->sense_buffer, resp->variable,
 749                                 min(variable, ccb->sense_bufflen));
 750                 return;
 751         }
 752
 753         if (ccb->cmd == NULL)
 754                 return;
 755         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 756 }
 757
 758 static void stex_check_cmd(struct st_hba *hba,
 759         struct st_ccb *ccb, struct status_msg *resp)
 760 {
 761         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 762                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 763                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 764                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 765 }
 766
 767 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 768 {
 769         void __iomem *base = hba->mmio_base;
 770         struct status_msg *resp;
 771         struct st_ccb *ccb;
 772         unsigned int size;
 773         u16 tag;
 774
 775         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 776                 return;
 777
 778         /* status payloads */
 779         hba->status_head = readl(base + OMR1);
 780         if (unlikely(hba->status_head > hba->sts_count)) {
 781                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 782                         pci_name(hba->pdev));
 783                 return;
 784         }
 785
 786         /*
 787          * it's not a valid status payload if:
 788          * 1. there are no pending requests(e.g. during init stage)
 789          * 2. there are some pending requests, but the controller is in
 790          *     reset status, and its type is not st_yosemite
 791          * firmware of st_yosemite in reset status will return pending requests
 792          * to driver, so we allow it to pass
 793          */
 794         if (unlikely(hba->out_req_cnt <= 0 ||
 795                         (hba->mu_status == MU_STATE_RESETTING &&
 796                          hba->cardtype != st_yosemite))) {
 797                 hba->status_tail = hba->status_head;
 798                 goto update_status;
 799         }
 800
 801         while (hba->status_tail != hba->status_head) {
 802                 resp = stex_get_status(hba);
 803                 tag = le16_to_cpu(resp->tag);
 804                 if (unlikely(tag >= hba->host->can_queue)) {
 805                         printk(KERN_WARNING DRV_NAME
 806                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 807                         continue;
 808                 }
 809
 810                 hba->out_req_cnt--;
 811                 ccb = &hba->ccb[tag];
 812                 if (unlikely(hba->wait_ccb == ccb))
 813                         hba->wait_ccb = NULL;
 814                 if (unlikely(ccb->req == NULL)) {
 815                         printk(KERN_WARNING DRV_NAME
 816                                 "(%s): lagging req\n", pci_name(hba->pdev));
 817                         continue;
 818                 }
 819
 820                 size = resp->payload_sz * sizeof(u32); /* payload size */
 821                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 822                         size > sizeof(*resp))) {
 823                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 824                                 pci_name(hba->pdev));
 825                 } else {
 826                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 827                         if (size)
 828                                 stex_copy_data(ccb, resp, size);
 829                 }
 830
 831                 ccb->req = NULL;
 832                 ccb->srb_status = resp->srb_status;
 833                 ccb->scsi_status = resp->scsi_status;
 834
 835                 if (likely(ccb->cmd != NULL)) {
 836                         if (hba->cardtype == st_yosemite)
 837                                 stex_check_cmd(hba, ccb, resp);
 838
 839                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 840                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 841                                 stex_controller_info(hba, ccb);
 842
 843                         scsi_dma_unmap(ccb->cmd);
 844                         stex_scsi_done(ccb);
 845                 } else
 846                         ccb->req_type = 0;
 847         }
 848
 849 update_status:
 850         writel(hba->status_head, base + IMR1);
 851         readl(base + IMR1); /* flush */
 852 }
 853
 854 static irqreturn_t stex_intr(int irq, void *__hba)
 855 {
 856         struct st_hba *hba = __hba;
 857         void __iomem *base = hba->mmio_base;
 858         u32 data;
 859         unsigned long flags;
 860
 861         spin_lock_irqsave(hba->host->host_lock, flags);
 862
 863         data = readl(base + ODBL);
 864
 865         if (data && data != 0xffffffff) {
 866                 /* clear the interrupt */
 867                 writel(data, base + ODBL);
 868                 readl(base + ODBL); /* flush */
 869                 stex_mu_intr(hba, data);
 870                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 871                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 872                         hba->cardtype == st_shasta))
 873                         queue_work(hba->work_q, &hba->reset_work);
 874                 return IRQ_HANDLED;
 875         }
 876
 877         spin_unlock_irqrestore(hba->host->host_lock, flags);
 878
 879         return IRQ_NONE;
 880 }
 881
 882 static void stex_ss_mu_intr(struct st_hba *hba)
 883 {
 884         struct status_msg *resp;
 885         struct st_ccb *ccb;
 886         __le32 *scratch;
 887         unsigned int size;
 888         int count = 0;
 889         u32 value;
 890         u16 tag;
 891
 892         if (unlikely(hba->out_req_cnt <= 0 ||
 893                         hba->mu_status == MU_STATE_RESETTING))
 894                 return;
 895
 896         while (count < hba->sts_count) {
 897                 scratch = hba->scratch + hba->status_tail;
 898                 value = le32_to_cpu(*scratch);
 899                 if (unlikely(!(value & SS_STS_NORMAL)))
 900                         return;
 901
 902                 resp = hba->status_buffer + hba->status_tail;
 903                 *scratch = 0;
 904                 ++count;
 905                 ++hba->status_tail;
 906                 hba->status_tail %= hba->sts_count+1;
 907
 908                 tag = (u16)value;
 909                 if (unlikely(tag >= hba->host->can_queue)) {
 910                         printk(KERN_WARNING DRV_NAME
 911                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 912                         continue;
 913                 }
 914
 915                 hba->out_req_cnt--;
 916                 ccb = &hba->ccb[tag];
 917                 if (unlikely(hba->wait_ccb == ccb))
 918                         hba->wait_ccb = NULL;
 919                 if (unlikely(ccb->req == NULL)) {
 920                         printk(KERN_WARNING DRV_NAME
 921                                 "(%s): lagging req\n", pci_name(hba->pdev));
 922                         continue;
 923                 }
 924
 925                 ccb->req = NULL;
 926                 if (likely(value & SS_STS_DONE)) { /* normal case */
 927                         ccb->srb_status = SRB_STATUS_SUCCESS;
 928                         ccb->scsi_status = SAM_STAT_GOOD;
 929                 } else {
 930                         ccb->srb_status = resp->srb_status;
 931                         ccb->scsi_status = resp->scsi_status;
 932                         size = resp->payload_sz * sizeof(u32);
 933                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 934                                 size > sizeof(*resp))) {
 935                                 printk(KERN_WARNING DRV_NAME
 936                                         "(%s): bad status size\n",
 937                                         pci_name(hba->pdev));
 938                         } else {
 939                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 940                                 if (size)
 941                                         stex_copy_data(ccb, resp, size);
 942                         }
 943                         if (likely(ccb->cmd != NULL))
 944                                 stex_check_cmd(hba, ccb, resp);
 945                 }
 946
 947                 if (likely(ccb->cmd != NULL)) {
 948                         scsi_dma_unmap(ccb->cmd);
 949                         stex_scsi_done(ccb);
 950                 } else
 951                         ccb->req_type = 0;
 952         }
 953 }
 954
 955 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 956 {
 957         struct st_hba *hba = __hba;
 958         void __iomem *base = hba->mmio_base;
 959         u32 data;
 960         unsigned long flags;
 961
 962         spin_lock_irqsave(hba->host->host_lock, flags);
 963
 964         data = readl(base + YI2H_INT);
 965         if (data && data != 0xffffffff) {
 966                 /* clear the interrupt */
 967                 writel(data, base + YI2H_INT_C);
 968                 stex_ss_mu_intr(hba);
 969                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 970                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 971                         queue_work(hba->work_q, &hba->reset_work);
 972                 return IRQ_HANDLED;
 973         }
 974
 975         spin_unlock_irqrestore(hba->host->host_lock, flags);
 976
 977         return IRQ_NONE;
 978 }
 979
 980 static int stex_common_handshake(struct st_hba *hba)
 981 {
 982         void __iomem *base = hba->mmio_base;
 983         struct handshake_frame *h;
 984         dma_addr_t status_phys;
 985         u32 data;
 986         unsigned long before;
 987
 988         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 989                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 990                 readl(base + IDBL);
 991                 before = jiffies;
 992                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 993                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 994                                 printk(KERN_ERR DRV_NAME
 995                                         "(%s): no handshake signature\n",
 996                                         pci_name(hba->pdev));
 997                                 return -1;
 998                         }
 999                         rmb();
1000                         msleep(1);
1001                 }
1002         }
1003
1004         udelay(10);
1005
1006         data = readl(base + OMR1);
1007         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1008                 data &= 0x0000ffff;
1009                 if (hba->host->can_queue > data) {
1010                         hba->host->can_queue = data;
1011                         hba->host->cmd_per_lun = data;
1012                 }
1013         }
1014
1015         h = (struct handshake_frame *)hba->status_buffer;
1016         h->rb_phy = cpu_to_le64(hba->dma_handle);
1017         h->req_sz = cpu_to_le16(hba->rq_size);
1018         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1019         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1020         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1021         stex_gettime(&h->hosttime);
1022         h->partner_type = HMU_PARTNER_TYPE;
1023         if (hba->extra_offset) {
1024                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1025                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1026         } else
1027                 h->extra_offset = h->extra_size = 0;
1028
1029         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1030         writel(status_phys, base + IMR0);
1031         readl(base + IMR0);
1032         writel((status_phys >> 16) >> 16, base + IMR1);
1033         readl(base + IMR1);
1034
1035         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1036         readl(base + OMR0);
1037         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1038         readl(base + IDBL); /* flush */
1039
1040         udelay(10);
1041         before = jiffies;
1042         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1043                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1044                         printk(KERN_ERR DRV_NAME
1045                                 "(%s): no signature after handshake frame\n",
1046                                 pci_name(hba->pdev));
1047                         return -1;
1048                 }
1049                 rmb();
1050                 msleep(1);
1051         }
1052
1053         writel(0, base + IMR0);
1054         readl(base + IMR0);
1055         writel(0, base + OMR0);
1056         readl(base + OMR0);
1057         writel(0, base + IMR1);
1058         readl(base + IMR1);
1059         writel(0, base + OMR1);
1060         readl(base + OMR1); /* flush */
1061         return 0;
1062 }
1063
1064 static int stex_ss_handshake(struct st_hba *hba)
1065 {
1066         void __iomem *base = hba->mmio_base;
1067         struct st_msg_header *msg_h;
1068         struct handshake_frame *h;
1069         __le32 *scratch;
1070         u32 data, scratch_size;
1071         unsigned long before;
1072         int ret = 0;
1073
1074         before = jiffies;
1075         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1076                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1077                         printk(KERN_ERR DRV_NAME
1078                                 "(%s): firmware not operational\n",
1079                                 pci_name(hba->pdev));
1080                         return -1;
1081                 }
1082                 msleep(1);
1083         }
1084
1085         msg_h = (struct st_msg_header *)hba->dma_mem;
1086         msg_h->handle = cpu_to_le64(hba->dma_handle);
1087         msg_h->flag = SS_HEAD_HANDSHAKE;
1088
1089         h = (struct handshake_frame *)(msg_h + 1);
1090         h->rb_phy = cpu_to_le64(hba->dma_handle);
1091         h->req_sz = cpu_to_le16(hba->rq_size);
1092         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1093         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1094         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1095         stex_gettime(&h->hosttime);
1096         h->partner_type = HMU_PARTNER_TYPE;
1097         h->extra_offset = h->extra_size = 0;
1098         scratch_size = (hba->sts_count+1)*sizeof(u32);
1099         h->scratch_size = cpu_to_le32(scratch_size);
1100
1101         data = readl(base + YINT_EN);
1102         data &= ~4;
1103         writel(data, base + YINT_EN);
1104         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1105         readl(base + YH2I_REQ_HI);
1106         writel(hba->dma_handle, base + YH2I_REQ);
1107         readl(base + YH2I_REQ); /* flush */
1108
1109         scratch = hba->scratch;
1110         before = jiffies;
1111         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1112                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1113                         printk(KERN_ERR DRV_NAME
1114                                 "(%s): no signature after handshake frame\n",
1115                                 pci_name(hba->pdev));
1116                         ret = -1;
1117                         break;
1118                 }
1119                 rmb();
1120                 msleep(1);
1121         }
1122
1123         memset(scratch, 0, scratch_size);
1124         msg_h->flag = 0;
1125         return ret;
1126 }
1127
1128 static int stex_handshake(struct st_hba *hba)
1129 {
1130         int err;
1131         unsigned long flags;
1132         unsigned int mu_status;
1133
1134         err = (hba->cardtype == st_yel) ?
1135                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1136         spin_lock_irqsave(hba->host->host_lock, flags);
1137         mu_status = hba->mu_status;
1138         if (err == 0) {
1139                 hba->req_head = 0;
1140                 hba->req_tail = 0;
1141                 hba->status_head = 0;
1142                 hba->status_tail = 0;
1143                 hba->out_req_cnt = 0;
1144                 hba->mu_status = MU_STATE_STARTED;
1145         } else
1146                 hba->mu_status = MU_STATE_FAILED;
1147         if (mu_status == MU_STATE_RESETTING)
1148                 wake_up_all(&hba->reset_waitq);
1149         spin_unlock_irqrestore(hba->host->host_lock, flags);
1150         return err;
1151 }
1152
1153 static int stex_abort(struct scsi_cmnd *cmd)
1154 {
1155         struct Scsi_Host *host = cmd->device->host;
1156         struct st_hba *hba = (struct st_hba *)host->hostdata;
1157         u16 tag = cmd->request->tag;
1158         void __iomem *base;
1159         u32 data;
1160         int result = SUCCESS;
1161         unsigned long flags;
1162
1163         printk(KERN_INFO DRV_NAME
1164                 "(%s): aborting command\n", pci_name(hba->pdev));
1165         scsi_print_command(cmd);
1166
1167         base = hba->mmio_base;
1168         spin_lock_irqsave(host->host_lock, flags);
1169         if (tag < host->can_queue &&
1170                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1171                 hba->wait_ccb = &hba->ccb[tag];
1172         else
1173                 goto out;
1174
1175         if (hba->cardtype == st_yel) {
1176                 data = readl(base + YI2H_INT);
1177                 if (data == 0 || data == 0xffffffff)
1178                         goto fail_out;
1179
1180                 writel(data, base + YI2H_INT_C);
1181                 stex_ss_mu_intr(hba);
1182         } else {
1183                 data = readl(base + ODBL);
1184                 if (data == 0 || data == 0xffffffff)
1185                         goto fail_out;
1186
1187                 writel(data, base + ODBL);
1188                 readl(base + ODBL); /* flush */
1189
1190                 stex_mu_intr(hba, data);
1191         }
1192         if (hba->wait_ccb == NULL) {
1193                 printk(KERN_WARNING DRV_NAME
1194                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1195                 goto out;
1196         }
1197
1198 fail_out:
1199         scsi_dma_unmap(cmd);
1200         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1201         hba->wait_ccb = NULL;
1202         result = FAILED;
1203 out:
1204         spin_unlock_irqrestore(host->host_lock, flags);
1205         return result;
1206 }
1207
1208 static void stex_hard_reset(struct st_hba *hba)
1209 {
1210         struct pci_bus *bus;
1211         int i;
1212         u16 pci_cmd;
1213         u8 pci_bctl;
1214
1215         for (i = 0; i < 16; i++)
1216                 pci_read_config_dword(hba->pdev, i * 4,
1217                         &hba->pdev->saved_config_space[i]);
1218
1219         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1220            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1221         bus = hba->pdev->bus;
1222         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1223         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1224         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1225
1226         /*
1227          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1228          * require more time to finish bus reset. Use 100 ms here for safety
1229          */
1230         msleep(100);
1231         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1232         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1233
1234         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1235                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1236                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1237                         break;
1238                 msleep(1);
1239         }
1240
1241         ssleep(5);
1242         for (i = 0; i < 16; i++)
1243                 pci_write_config_dword(hba->pdev, i * 4,
1244                         hba->pdev->saved_config_space[i]);
1245 }
1246
1247 static int stex_yos_reset(struct st_hba *hba)
1248 {
1249         void __iomem *base;
1250         unsigned long flags, before;
1251         int ret = 0;
1252
1253         base = hba->mmio_base;
1254         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1255         readl(base + IDBL); /* flush */
1256         before = jiffies;
1257         while (hba->out_req_cnt > 0) {
1258                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1259                         printk(KERN_WARNING DRV_NAME
1260                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1261                         ret = -1;
1262                         break;
1263                 }
1264                 msleep(1);
1265         }
1266
1267         spin_lock_irqsave(hba->host->host_lock, flags);
1268         if (ret == -1)
1269                 hba->mu_status = MU_STATE_FAILED;
1270         else
1271                 hba->mu_status = MU_STATE_STARTED;
1272         wake_up_all(&hba->reset_waitq);
1273         spin_unlock_irqrestore(hba->host->host_lock, flags);
1274
1275         return ret;
1276 }
1277
1278 static void stex_ss_reset(struct st_hba *hba)
1279 {
1280         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1281         readl(hba->mmio_base + YH2I_INT);
1282         ssleep(5);
1283 }
1284
1285 static int stex_do_reset(struct st_hba *hba)
1286 {
1287         struct st_ccb *ccb;
1288         unsigned long flags;
1289         unsigned int mu_status = MU_STATE_RESETTING;
1290         u16 tag;
1291
1292         spin_lock_irqsave(hba->host->host_lock, flags);
1293         if (hba->mu_status == MU_STATE_STARTING) {
1294                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1295                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1296                         pci_name(hba->pdev));
1297                 return 0;
1298         }
1299         while (hba->mu_status == MU_STATE_RESETTING) {
1300                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1301                 wait_event_timeout(hba->reset_waitq,
1302                                    hba->mu_status != MU_STATE_RESETTING,
1303                                    MU_MAX_DELAY * HZ);
1304                 spin_lock_irqsave(hba->host->host_lock, flags);
1305                 mu_status = hba->mu_status;
1306         }
1307
1308         if (mu_status != MU_STATE_RESETTING) {
1309                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1310                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1311         }
1312
1313         hba->mu_status = MU_STATE_RESETTING;
1314         spin_unlock_irqrestore(hba->host->host_lock, flags);
1315
1316         if (hba->cardtype == st_yosemite)
1317                 return stex_yos_reset(hba);
1318
1319         if (hba->cardtype == st_shasta)
1320                 stex_hard_reset(hba);
1321         else if (hba->cardtype == st_yel)
1322                 stex_ss_reset(hba);
1323
1324         spin_lock_irqsave(hba->host->host_lock, flags);
1325         for (tag = 0; tag < hba->host->can_queue; tag++) {
1326                 ccb = &hba->ccb[tag];
1327                 if (ccb->req == NULL)
1328                         continue;
1329                 ccb->req = NULL;
1330                 if (ccb->cmd) {
1331                         scsi_dma_unmap(ccb->cmd);
1332                         ccb->cmd->result = DID_RESET << 16;
1333                         ccb->cmd->scsi_done(ccb->cmd);
1334                         ccb->cmd = NULL;
1335                 }
1336         }
1337         spin_unlock_irqrestore(hba->host->host_lock, flags);
1338
1339         if (stex_handshake(hba) == 0)
1340                 return 0;
1341
1342         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1343                 pci_name(hba->pdev));
1344         return -1;
1345 }
1346
1347 static int stex_reset(struct scsi_cmnd *cmd)
1348 {
1349         struct st_hba *hba;
1350
1351         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1352
1353         printk(KERN_INFO DRV_NAME
1354                 "(%s): resetting host\n", pci_name(hba->pdev));
1355         scsi_print_command(cmd);
1356
1357         return stex_do_reset(hba) ? FAILED : SUCCESS;
1358 }
1359
1360 static void stex_reset_work(struct work_struct *work)
1361 {
1362         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1363
1364         stex_do_reset(hba);
1365 }
1366
1367 static int stex_biosparam(struct scsi_device *sdev,
1368         struct block_device *bdev, sector_t capacity, int geom[])
1369 {
1370         int heads = 255, sectors = 63;
1371
1372         if (capacity < 0x200000) {
1373                 heads = 64;
1374                 sectors = 32;
1375         }
1376
1377         sector_div(capacity, heads * sectors);
1378
1379         geom[0] = heads;
1380         geom[1] = sectors;
1381         geom[2] = capacity;
1382
1383         return 0;
1384 }
1385
1386 static struct scsi_host_template driver_template = {
1387         .module                         = THIS_MODULE,
1388         .name                           = DRV_NAME,
1389         .proc_name                      = DRV_NAME,
1390         .bios_param                     = stex_biosparam,
1391         .queuecommand                   = stex_queuecommand,
1392         .slave_alloc                    = stex_slave_alloc,
1393         .slave_configure                = stex_slave_config,
1394         .slave_destroy                  = stex_slave_destroy,
1395         .eh_abort_handler               = stex_abort,
1396         .eh_host_reset_handler          = stex_reset,
1397         .this_id                        = -1,
1398 };
1399
1400 static struct pci_device_id stex_pci_tbl[] = {
1401         /* st_shasta */
1402         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1403                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1404         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1405                 st_shasta }, /* SuperTrak EX12350 */
1406         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1407                 st_shasta }, /* SuperTrak EX4350 */
1408         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1409                 st_shasta }, /* SuperTrak EX24350 */
1410
1411         /* st_vsc */
1412         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1413
1414         /* st_yosemite */
1415         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1416
1417         /* st_seq */
1418         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1419
1420         /* st_yel */
1421         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1422         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1423         { }     /* terminate list */
1424 };
1425
1426 static struct st_card_info stex_card_info[] = {
1427         /* st_shasta */
1428         {
1429                 .max_id         = 17,
1430                 .max_lun        = 8,
1431                 .max_channel    = 0,
1432                 .rq_count       = 32,
1433                 .rq_size        = 1048,
1434                 .sts_count      = 32,
1435                 .alloc_rq       = stex_alloc_req,
1436                 .map_sg         = stex_map_sg,
1437                 .send           = stex_send_cmd,
1438         },
1439
1440         /* st_vsc */
1441         {
1442                 .max_id         = 129,
1443                 .max_lun        = 1,
1444                 .max_channel    = 0,
1445                 .rq_count       = 32,
1446                 .rq_size        = 1048,
1447                 .sts_count      = 32,
1448                 .alloc_rq       = stex_alloc_req,
1449                 .map_sg         = stex_map_sg,
1450                 .send           = stex_send_cmd,
1451         },
1452
1453         /* st_yosemite */
1454         {
1455                 .max_id         = 2,
1456                 .max_lun        = 256,
1457                 .max_channel    = 0,
1458                 .rq_count       = 256,
1459                 .rq_size        = 1048,
1460                 .sts_count      = 256,
1461                 .alloc_rq       = stex_alloc_req,
1462                 .map_sg         = stex_map_sg,
1463                 .send           = stex_send_cmd,
1464         },
1465
1466         /* st_seq */
1467         {
1468                 .max_id         = 129,
1469                 .max_lun        = 1,
1470                 .max_channel    = 0,
1471                 .rq_count       = 32,
1472                 .rq_size        = 1048,
1473                 .sts_count      = 32,
1474                 .alloc_rq       = stex_alloc_req,
1475                 .map_sg         = stex_map_sg,
1476                 .send           = stex_send_cmd,
1477         },
1478
1479         /* st_yel */
1480         {
1481                 .max_id         = 129,
1482                 .max_lun        = 256,
1483                 .max_channel    = 3,
1484                 .rq_count       = 801,
1485                 .rq_size        = 512,
1486                 .sts_count      = 801,
1487                 .alloc_rq       = stex_ss_alloc_req,
1488                 .map_sg         = stex_ss_map_sg,
1489                 .send           = stex_ss_send_cmd,
1490         },
1491 };
1492
1493 static int stex_set_dma_mask(struct pci_dev * pdev)
1494 {
1495         int ret;
1496
1497         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1498                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1499                 return 0;
1500         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1501         if (!ret)
1502                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1503         return ret;
1504 }
1505
1506 static int stex_request_irq(struct st_hba *hba)
1507 {
1508         struct pci_dev *pdev = hba->pdev;
1509         int status;
1510
1511         if (msi) {
1512                 status = pci_enable_msi(pdev);
1513                 if (status != 0)
1514                         printk(KERN_ERR DRV_NAME
1515                                 "(%s): error %d setting up MSI\n",
1516                                 pci_name(pdev), status);
1517                 else
1518                         hba->msi_enabled = 1;
1519         } else
1520                 hba->msi_enabled = 0;
1521
1522         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1523                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1524
1525         if (status != 0) {
1526                 if (hba->msi_enabled)
1527                         pci_disable_msi(pdev);
1528         }
1529         return status;
1530 }
1531
1532 static void stex_free_irq(struct st_hba *hba)
1533 {
1534         struct pci_dev *pdev = hba->pdev;
1535
1536         free_irq(pdev->irq, hba);
1537         if (hba->msi_enabled)
1538                 pci_disable_msi(pdev);
1539 }
1540
1541 static int __devinit
1542 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1543 {
1544         struct st_hba *hba;
1545         struct Scsi_Host *host;
1546         const struct st_card_info *ci = NULL;
1547         u32 sts_offset, cp_offset, scratch_offset;
1548         int err;
1549
1550         err = pci_enable_device(pdev);
1551         if (err)
1552                 return err;
1553
1554         pci_set_master(pdev);
1555
1556         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1557
1558         if (!host) {
1559                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1560                         pci_name(pdev));
1561                 err = -ENOMEM;
1562                 goto out_disable;
1563         }
1564
1565         hba = (struct st_hba *)host->hostdata;
1566         memset(hba, 0, sizeof(struct st_hba));
1567
1568         err = pci_request_regions(pdev, DRV_NAME);
1569         if (err < 0) {
1570                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1571                         pci_name(pdev));
1572                 goto out_scsi_host_put;
1573         }
1574
1575         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1576         if ( !hba->mmio_base) {
1577                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1578                         pci_name(pdev));
1579                 err = -ENOMEM;
1580                 goto out_release_regions;
1581         }
1582
1583         err = stex_set_dma_mask(pdev);
1584         if (err) {
1585                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1586                         pci_name(pdev));
1587                 goto out_iounmap;
1588         }
1589
1590         hba->cardtype = (unsigned int) id->driver_data;
1591         ci = &stex_card_info[hba->cardtype];
1592         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1593         if (hba->cardtype == st_yel)
1594                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1595         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1596         hba->dma_size = cp_offset + sizeof(struct st_frame);
1597         if (hba->cardtype == st_seq ||
1598                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1599                 hba->extra_offset = hba->dma_size;
1600                 hba->dma_size += ST_ADDITIONAL_MEM;
1601         }
1602         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1603                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1604         if (!hba->dma_mem) {
1605                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1606                 if (hba->cardtype == st_seq ||
1607                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1608                         printk(KERN_WARNING DRV_NAME
1609                                 "(%s): allocating min buffer for controller\n",
1610                                 pci_name(pdev));
1611                         hba->dma_size = hba->extra_offset
1612                                 + ST_ADDITIONAL_MEM_MIN;
1613                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1614                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1615                 }
1616
1617                 if (!hba->dma_mem) {
1618                         err = -ENOMEM;
1619                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1620                                 pci_name(pdev));
1621                         goto out_iounmap;
1622                 }
1623         }
1624
1625         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1626         if (!hba->ccb) {
1627                 err = -ENOMEM;
1628                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1629                         pci_name(pdev));
1630                 goto out_pci_free;
1631         }
1632
1633         if (hba->cardtype == st_yel)
1634                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1635         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1636         hba->copy_buffer = hba->dma_mem + cp_offset;
1637         hba->rq_count = ci->rq_count;
1638         hba->rq_size = ci->rq_size;
1639         hba->sts_count = ci->sts_count;
1640         hba->alloc_rq = ci->alloc_rq;
1641         hba->map_sg = ci->map_sg;
1642         hba->send = ci->send;
1643         hba->mu_status = MU_STATE_STARTING;
1644
1645         if (hba->cardtype == st_yel)
1646                 host->sg_tablesize = 38;
1647         else
1648                 host->sg_tablesize = 32;
1649         host->can_queue = ci->rq_count;
1650         host->cmd_per_lun = ci->rq_count;
1651         host->max_id = ci->max_id;
1652         host->max_lun = ci->max_lun;
1653         host->max_channel = ci->max_channel;
1654         host->unique_id = host->host_no;
1655         host->max_cmd_len = STEX_CDB_LENGTH;
1656
1657         hba->host = host;
1658         hba->pdev = pdev;
1659         init_waitqueue_head(&hba->reset_waitq);
1660
1661         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1662                  "stex_wq_%d", host->host_no);
1663         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1664         if (!hba->work_q) {
1665                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1666                         pci_name(pdev));
1667                 err = -ENOMEM;
1668                 goto out_ccb_free;
1669         }
1670         INIT_WORK(&hba->reset_work, stex_reset_work);
1671
1672         err = stex_request_irq(hba);
1673         if (err) {
1674                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1675                         pci_name(pdev));
1676                 goto out_free_wq;
1677         }
1678
1679         err = stex_handshake(hba);
1680         if (err)
1681                 goto out_free_irq;
1682
1683         err = scsi_init_shared_tag_map(host, host->can_queue);
1684         if (err) {
1685                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1686                         pci_name(pdev));
1687                 goto out_free_irq;
1688         }
1689
1690         pci_set_drvdata(pdev, hba);
1691
1692         err = scsi_add_host(host, &pdev->dev);
1693         if (err) {
1694                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1695                         pci_name(pdev));
1696                 goto out_free_irq;
1697         }
1698
1699         scsi_scan_host(host);
1700
1701         return 0;
1702
1703 out_free_irq:
1704         stex_free_irq(hba);
1705 out_free_wq:
1706         destroy_workqueue(hba->work_q);
1707 out_ccb_free:
1708         kfree(hba->ccb);
1709 out_pci_free:
1710         dma_free_coherent(&pdev->dev, hba->dma_size,
1711                           hba->dma_mem, hba->dma_handle);
1712 out_iounmap:
1713         iounmap(hba->mmio_base);
1714 out_release_regions:
1715         pci_release_regions(pdev);
1716 out_scsi_host_put:
1717         scsi_host_put(host);
1718 out_disable:
1719         pci_disable_device(pdev);
1720
1721         return err;
1722 }
1723
1724 static void stex_hba_stop(struct st_hba *hba)
1725 {
1726         struct req_msg *req;
1727         struct st_msg_header *msg_h;
1728         unsigned long flags;
1729         unsigned long before;
1730         u16 tag = 0;
1731
1732         spin_lock_irqsave(hba->host->host_lock, flags);
1733         req = hba->alloc_rq(hba);
1734         if (hba->cardtype == st_yel) {
1735                 msg_h = (struct st_msg_header *)req - 1;
1736                 memset(msg_h, 0, hba->rq_size);
1737         } else
1738                 memset(req, 0, hba->rq_size);
1739
1740         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1741                 req->cdb[0] = MGT_CMD;
1742                 req->cdb[1] = MGT_CMD_SIGNATURE;
1743                 req->cdb[2] = CTLR_CONFIG_CMD;
1744                 req->cdb[3] = CTLR_SHUTDOWN;
1745         } else {
1746                 req->cdb[0] = CONTROLLER_CMD;
1747                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1748                 req->cdb[2] = CTLR_POWER_SAVING;
1749         }
1750
1751         hba->ccb[tag].cmd = NULL;
1752         hba->ccb[tag].sg_count = 0;
1753         hba->ccb[tag].sense_bufflen = 0;
1754         hba->ccb[tag].sense_buffer = NULL;
1755         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1756
1757         hba->send(hba, req, tag);
1758         spin_unlock_irqrestore(hba->host->host_lock, flags);
1759
1760         before = jiffies;
1761         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1762                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1763                         hba->ccb[tag].req_type = 0;
1764                         return;
1765                 }
1766                 msleep(1);
1767         }
1768 }
1769
1770 static void stex_hba_free(struct st_hba *hba)
1771 {
1772         stex_free_irq(hba);
1773
1774         destroy_workqueue(hba->work_q);
1775
1776         iounmap(hba->mmio_base);
1777
1778         pci_release_regions(hba->pdev);
1779
1780         kfree(hba->ccb);
1781
1782         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1783                           hba->dma_mem, hba->dma_handle);
1784 }
1785
1786 static void stex_remove(struct pci_dev *pdev)
1787 {
1788         struct st_hba *hba = pci_get_drvdata(pdev);
1789
1790         scsi_remove_host(hba->host);
1791
1792         pci_set_drvdata(pdev, NULL);
1793
1794         stex_hba_stop(hba);
1795
1796         stex_hba_free(hba);
1797
1798         scsi_host_put(hba->host);
1799
1800         pci_disable_device(pdev);
1801 }
1802
1803 static void stex_shutdown(struct pci_dev *pdev)
1804 {
1805         struct st_hba *hba = pci_get_drvdata(pdev);
1806
1807         stex_hba_stop(hba);
1808 }
1809
1810 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1811
1812 static struct pci_driver stex_pci_driver = {
1813         .name           = DRV_NAME,
1814         .id_table       = stex_pci_tbl,
1815         .probe          = stex_probe,
1816         .remove         = __devexit_p(stex_remove),
1817         .shutdown       = stex_shutdown,
1818 };
1819
1820 static int __init stex_init(void)
1821 {
1822         printk(KERN_INFO DRV_NAME
1823                 ": Promise SuperTrak EX Driver version: %s\n",
1824                  ST_DRIVER_VERSION);
1825
1826         return pci_register_driver(&stex_pci_driver);
1827 }
1828
1829 static void __exit stex_exit(void)
1830 {
1831         pci_unregister_driver(&stex_pci_driver);
1832 }
1833
1834 module_init(stex_init);
1835 module_exit(stex_exit);