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   1 /*
   2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40  #include "pm8001_sas.h"
  41  #include "pm8001_hwi.h"
  42  #include "pm8001_chips.h"
  43  #include "pm8001_ctl.h"
  44
  45 /**
  46  * read_main_config_table - read the configure table and save it.
  47  * @pm8001_ha: our hba card information
  48  */
  49 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  50 {
  51         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  52         pm8001_ha->main_cfg_tbl.signature       = pm8001_mr32(address, 0x00);
  53         pm8001_ha->main_cfg_tbl.interface_rev   = pm8001_mr32(address, 0x04);
  54         pm8001_ha->main_cfg_tbl.firmware_rev    = pm8001_mr32(address, 0x08);
  55         pm8001_ha->main_cfg_tbl.max_out_io      = pm8001_mr32(address, 0x0C);
  56         pm8001_ha->main_cfg_tbl.max_sgl         = pm8001_mr32(address, 0x10);
  57         pm8001_ha->main_cfg_tbl.ctrl_cap_flag   = pm8001_mr32(address, 0x14);
  58         pm8001_ha->main_cfg_tbl.gst_offset      = pm8001_mr32(address, 0x18);
  59         pm8001_ha->main_cfg_tbl.inbound_queue_offset =
  60                 pm8001_mr32(address, MAIN_IBQ_OFFSET);
  61         pm8001_ha->main_cfg_tbl.outbound_queue_offset =
  62                 pm8001_mr32(address, MAIN_OBQ_OFFSET);
  63         pm8001_ha->main_cfg_tbl.hda_mode_flag   =
  64                 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  65
  66         /* read analog Setting offset from the configuration table */
  67         pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
  68                 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  69
  70         /* read Error Dump Offset and Length */
  71         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
  72                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  73         pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
  74                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  75         pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
  76                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  77         pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
  78                 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  79 }
  80
  81 /**
  82  * read_general_status_table - read the general status table and save it.
  83  * @pm8001_ha: our hba card information
  84  */
  85 static void __devinit
  86 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  87 {
  88         void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  89         pm8001_ha->gs_tbl.gst_len_mpistate      = pm8001_mr32(address, 0x00);
  90         pm8001_ha->gs_tbl.iq_freeze_state0      = pm8001_mr32(address, 0x04);
  91         pm8001_ha->gs_tbl.iq_freeze_state1      = pm8001_mr32(address, 0x08);
  92         pm8001_ha->gs_tbl.msgu_tcnt             = pm8001_mr32(address, 0x0C);
  93         pm8001_ha->gs_tbl.iop_tcnt              = pm8001_mr32(address, 0x10);
  94         pm8001_ha->gs_tbl.reserved              = pm8001_mr32(address, 0x14);
  95         pm8001_ha->gs_tbl.phy_state[0]  = pm8001_mr32(address, 0x18);
  96         pm8001_ha->gs_tbl.phy_state[1]  = pm8001_mr32(address, 0x1C);
  97         pm8001_ha->gs_tbl.phy_state[2]  = pm8001_mr32(address, 0x20);
  98         pm8001_ha->gs_tbl.phy_state[3]  = pm8001_mr32(address, 0x24);
  99         pm8001_ha->gs_tbl.phy_state[4]  = pm8001_mr32(address, 0x28);
 100         pm8001_ha->gs_tbl.phy_state[5]  = pm8001_mr32(address, 0x2C);
 101         pm8001_ha->gs_tbl.phy_state[6]  = pm8001_mr32(address, 0x30);
 102         pm8001_ha->gs_tbl.phy_state[7]  = pm8001_mr32(address, 0x34);
 103         pm8001_ha->gs_tbl.reserved1             = pm8001_mr32(address, 0x38);
 104         pm8001_ha->gs_tbl.reserved2             = pm8001_mr32(address, 0x3C);
 105         pm8001_ha->gs_tbl.reserved3             = pm8001_mr32(address, 0x40);
 106         pm8001_ha->gs_tbl.recover_err_info[0]   = pm8001_mr32(address, 0x44);
 107         pm8001_ha->gs_tbl.recover_err_info[1]   = pm8001_mr32(address, 0x48);
 108         pm8001_ha->gs_tbl.recover_err_info[2]   = pm8001_mr32(address, 0x4C);
 109         pm8001_ha->gs_tbl.recover_err_info[3]   = pm8001_mr32(address, 0x50);
 110         pm8001_ha->gs_tbl.recover_err_info[4]   = pm8001_mr32(address, 0x54);
 111         pm8001_ha->gs_tbl.recover_err_info[5]   = pm8001_mr32(address, 0x58);
 112         pm8001_ha->gs_tbl.recover_err_info[6]   = pm8001_mr32(address, 0x5C);
 113         pm8001_ha->gs_tbl.recover_err_info[7]   = pm8001_mr32(address, 0x60);
 114 }
 115
 116 /**
 117  * read_inbnd_queue_table - read the inbound queue table and save it.
 118  * @pm8001_ha: our hba card information
 119  */
 120 static void __devinit
 121 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 122 {
 123         int inbQ_num = 1;
 124         int i;
 125         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 126         for (i = 0; i < inbQ_num; i++) {
 127                 u32 offset = i * 0x20;
 128                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 129                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 130                 pm8001_ha->inbnd_q_tbl[i].pi_offset =
 131                         pm8001_mr32(address, (offset + 0x18));
 132         }
 133 }
 134
 135 /**
 136  * read_outbnd_queue_table - read the outbound queue table and save it.
 137  * @pm8001_ha: our hba card information
 138  */
 139 static void __devinit
 140 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 141 {
 142         int outbQ_num = 1;
 143         int i;
 144         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 145         for (i = 0; i < outbQ_num; i++) {
 146                 u32 offset = i * 0x24;
 147                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 148                       get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 149                 pm8001_ha->outbnd_q_tbl[i].ci_offset =
 150                         pm8001_mr32(address, (offset + 0x18));
 151         }
 152 }
 153
 154 /**
 155  * init_default_table_values - init the default table.
 156  * @pm8001_ha: our hba card information
 157  */
 158 static void __devinit
 159 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 160 {
 161         int qn = 1;
 162         int i;
 163         u32 offsetib, offsetob;
 164         void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 165         void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 166
 167         pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd                     = 0;
 168         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3                = 0;
 169         pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7                = 0;
 170         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3               = 0;
 171         pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7               = 0;
 172         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3       = 0;
 173         pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7       = 0;
 174         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3   = 0;
 175         pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7   = 0;
 176         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3   = 0;
 177         pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7   = 0;
 178
 179         pm8001_ha->main_cfg_tbl.upper_event_log_addr            =
 180                 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 181         pm8001_ha->main_cfg_tbl.lower_event_log_addr            =
 182                 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 183         pm8001_ha->main_cfg_tbl.event_log_size  = PM8001_EVENT_LOG_SIZE;
 184         pm8001_ha->main_cfg_tbl.event_log_option                = 0x01;
 185         pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr        =
 186                 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 187         pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr        =
 188                 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 189         pm8001_ha->main_cfg_tbl.iop_event_log_size      = PM8001_EVENT_LOG_SIZE;
 190         pm8001_ha->main_cfg_tbl.iop_event_log_option            = 0x01;
 191         pm8001_ha->main_cfg_tbl.fatal_err_interrupt             = 0x01;
 192         for (i = 0; i < qn; i++) {
 193                 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 194                         0x00000100 | (0x00000040 << 16) | (0x00<<30);
 195                 pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 196                         pm8001_ha->memoryMap.region[IB].phys_addr_hi;
 197                 pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 198                 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
 199                 pm8001_ha->inbnd_q_tbl[i].base_virt             =
 200                         (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
 201                 pm8001_ha->inbnd_q_tbl[i].total_length          =
 202                         pm8001_ha->memoryMap.region[IB].total_len;
 203                 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 204                         pm8001_ha->memoryMap.region[CI].phys_addr_hi;
 205                 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 206                         pm8001_ha->memoryMap.region[CI].phys_addr_lo;
 207                 pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 208                         pm8001_ha->memoryMap.region[CI].virt_ptr;
 209                 offsetib = i * 0x20;
 210                 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 211                         get_pci_bar_index(pm8001_mr32(addressib,
 212                                 (offsetib + 0x14)));
 213                 pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 214                         pm8001_mr32(addressib, (offsetib + 0x18));
 215                 pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 216                 pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 217         }
 218         for (i = 0; i < qn; i++) {
 219                 pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 220                         256 | (64 << 16) | (1<<30);
 221                 pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 222                         pm8001_ha->memoryMap.region[OB].phys_addr_hi;
 223                 pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 224                         pm8001_ha->memoryMap.region[OB].phys_addr_lo;
 225                 pm8001_ha->outbnd_q_tbl[i].base_virt            =
 226                         (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
 227                 pm8001_ha->outbnd_q_tbl[i].total_length         =
 228                         pm8001_ha->memoryMap.region[OB].total_len;
 229                 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 230                         pm8001_ha->memoryMap.region[PI].phys_addr_hi;
 231                 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 232                         pm8001_ha->memoryMap.region[PI].phys_addr_lo;
 233                 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 234                         0 | (10 << 16) | (0 << 24);
 235                 pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 236                         pm8001_ha->memoryMap.region[PI].virt_ptr;
 237                 offsetob = i * 0x24;
 238                 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 239                         get_pci_bar_index(pm8001_mr32(addressob,
 240                         offsetob + 0x14));
 241                 pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 242                         pm8001_mr32(addressob, (offsetob + 0x18));
 243                 pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 244                 pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 245         }
 246 }
 247
 248 /**
 249  * update_main_config_table - update the main default table to the HBA.
 250  * @pm8001_ha: our hba card information
 251  */
 252 static void __devinit
 253 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 254 {
 255         void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 256         pm8001_mw32(address, 0x24,
 257                 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
 258         pm8001_mw32(address, 0x28,
 259                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
 260         pm8001_mw32(address, 0x2C,
 261                 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
 262         pm8001_mw32(address, 0x30,
 263                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
 264         pm8001_mw32(address, 0x34,
 265                 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
 266         pm8001_mw32(address, 0x38,
 267                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
 268         pm8001_mw32(address, 0x3C,
 269                 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
 270         pm8001_mw32(address, 0x40,
 271                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
 272         pm8001_mw32(address, 0x44,
 273                 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
 274         pm8001_mw32(address, 0x48,
 275                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
 276         pm8001_mw32(address, 0x4C,
 277                 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
 278         pm8001_mw32(address, 0x50,
 279                 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
 280         pm8001_mw32(address, 0x54,
 281                 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
 282         pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
 283         pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
 284         pm8001_mw32(address, 0x60,
 285                 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
 286         pm8001_mw32(address, 0x64,
 287                 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
 288         pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
 289         pm8001_mw32(address, 0x6C,
 290                 pm8001_ha->main_cfg_tbl.iop_event_log_option);
 291         pm8001_mw32(address, 0x70,
 292                 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
 293 }
 294
 295 /**
 296  * update_inbnd_queue_table - update the inbound queue table to the HBA.
 297  * @pm8001_ha: our hba card information
 298  */
 299 static void __devinit
 300 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 301 {
 302         void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 303         u16 offset = number * 0x20;
 304         pm8001_mw32(address, offset + 0x00,
 305                 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 306         pm8001_mw32(address, offset + 0x04,
 307                 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 308         pm8001_mw32(address, offset + 0x08,
 309                 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 310         pm8001_mw32(address, offset + 0x0C,
 311                 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 312         pm8001_mw32(address, offset + 0x10,
 313                 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 314 }
 315
 316 /**
 317  * update_outbnd_queue_table - update the outbound queue table to the HBA.
 318  * @pm8001_ha: our hba card information
 319  */
 320 static void __devinit
 321 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
 322 {
 323         void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 324         u16 offset = number * 0x24;
 325         pm8001_mw32(address, offset + 0x00,
 326                 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 327         pm8001_mw32(address, offset + 0x04,
 328                 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 329         pm8001_mw32(address, offset + 0x08,
 330                 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 331         pm8001_mw32(address, offset + 0x0C,
 332                 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 333         pm8001_mw32(address, offset + 0x10,
 334                 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 335         pm8001_mw32(address, offset + 0x1C,
 336                 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 337 }
 338
 339 /**
 340  * bar4_shift - function is called to shift BAR base address
 341  * @pm8001_ha : our hba card infomation
 342  * @shiftValue : shifting value in memory bar.
 343  */
 344 static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 345 {
 346         u32 regVal;
 347         u32 max_wait_count;
 348
 349         /* program the inbound AXI translation Lower Address */
 350         pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 351
 352         /* confirm the setting is written */
 353         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 354         do {
 355                 udelay(1);
 356                 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 357         } while ((regVal != shiftValue) && (--max_wait_count));
 358
 359         if (!max_wait_count) {
 360                 PM8001_INIT_DBG(pm8001_ha,
 361                         pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
 362                         " = 0x%x\n", regVal));
 363                 return -1;
 364         }
 365         return 0;
 366 }
 367
 368 /**
 369  * mpi_set_phys_g3_with_ssc
 370  * @pm8001_ha: our hba card information
 371  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 372  */
 373 static void __devinit
 374 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
 375 {
 376         u32 value, offset, i;
 377
 378 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 379 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 380 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 381 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 382 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 383 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
 384 #define SNW3_PHY_CAPABILITIES_PARITY 31
 385
 386    /*
 387     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 388     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 389     */
 390         if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
 391                 return;
 392
 393         for (i = 0; i < 4; i++) {
 394                 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 395                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 396         }
 397         /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 398         if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
 399                 return;
 400         for (i = 4; i < 8; i++) {
 401                 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 402                 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 403         }
 404         /*************************************************************
 405         Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 406         Device MABC SMOD0 Controls
 407         Address: (via MEMBASE-III):
 408         Using shifted destination address 0x0_0000: with Offset 0xD8
 409
 410         31:28 R/W Reserved Do not change
 411         27:24 R/W SAS_SMOD_SPRDUP 0000
 412         23:20 R/W SAS_SMOD_SPRDDN 0000
 413         19:0  R/W  Reserved Do not change
 414         Upon power-up this register will read as 0x8990c016,
 415         and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 416         so that the written value will be 0x8090c016.
 417         This will ensure only down-spreading SSC is enabled on the SPC.
 418         *************************************************************/
 419         value = pm8001_cr32(pm8001_ha, 2, 0xd8);
 420         pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 421
 422         /*set the shifted destination address to 0x0 to avoid error operation */
 423         bar4_shift(pm8001_ha, 0x0);
 424         return;
 425 }
 426
 427 /**
 428  * mpi_set_open_retry_interval_reg
 429  * @pm8001_ha: our hba card information
 430  * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 431  */
 432 static void __devinit
 433 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 434                                 u32 interval)
 435 {
 436         u32 offset;
 437         u32 value;
 438         u32 i;
 439
 440 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 441 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 442 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 443 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 444 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 445
 446         value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 447         /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 448         if (-1 == bar4_shift(pm8001_ha,
 449                              OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
 450                 return;
 451         for (i = 0; i < 4; i++) {
 452                 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 453                 pm8001_cw32(pm8001_ha, 2, offset, value);
 454         }
 455
 456         if (-1 == bar4_shift(pm8001_ha,
 457                              OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
 458                 return;
 459         for (i = 4; i < 8; i++) {
 460                 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 461                 pm8001_cw32(pm8001_ha, 2, offset, value);
 462         }
 463         /*set the shifted destination address to 0x0 to avoid error operation */
 464         bar4_shift(pm8001_ha, 0x0);
 465         return;
 466 }
 467
 468 /**
 469  * mpi_init_check - check firmware initialization status.
 470  * @pm8001_ha: our hba card information
 471  */
 472 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 473 {
 474         u32 max_wait_count;
 475         u32 value;
 476         u32 gst_len_mpistate;
 477         /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 478         table is updated */
 479         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 480         /* wait until Inbound DoorBell Clear Register toggled */
 481         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 482         do {
 483                 udelay(1);
 484                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 485                 value &= SPC_MSGU_CFG_TABLE_UPDATE;
 486         } while ((value != 0) && (--max_wait_count));
 487
 488         if (!max_wait_count)
 489                 return -1;
 490         /* check the MPI-State for initialization */
 491         gst_len_mpistate =
 492                 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 493                 GST_GSTLEN_MPIS_OFFSET);
 494         if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 495                 return -1;
 496         /* check MPI Initialization error */
 497         gst_len_mpistate = gst_len_mpistate >> 16;
 498         if (0x0000 != gst_len_mpistate)
 499                 return -1;
 500         return 0;
 501 }
 502
 503 /**
 504  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 505  * @pm8001_ha: our hba card information
 506  */
 507 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 508 {
 509         u32 value, value1;
 510         u32 max_wait_count;
 511         /* check error state */
 512         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 513         value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 514         /* check AAP error */
 515         if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 516                 /* error state */
 517                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 518                 return -1;
 519         }
 520
 521         /* check IOP error */
 522         if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 523                 /* error state */
 524                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 525                 return -1;
 526         }
 527
 528         /* bit 4-31 of scratch pad1 should be zeros if it is not
 529         in error state*/
 530         if (value & SCRATCH_PAD1_STATE_MASK) {
 531                 /* error case */
 532                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 533                 return -1;
 534         }
 535
 536         /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 537         in error state */
 538         if (value1 & SCRATCH_PAD2_STATE_MASK) {
 539                 /* error case */
 540                 return -1;
 541         }
 542
 543         max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 544
 545         /* wait until scratch pad 1 and 2 registers in ready state  */
 546         do {
 547                 udelay(1);
 548                 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 549                         & SCRATCH_PAD1_RDY;
 550                 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 551                         & SCRATCH_PAD2_RDY;
 552                 if ((--max_wait_count) == 0)
 553                         return -1;
 554         } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 555         return 0;
 556 }
 557
 558 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 559 {
 560         void __iomem *base_addr;
 561         u32     value;
 562         u32     offset;
 563         u32     pcibar;
 564         u32     pcilogic;
 565
 566         value = pm8001_cr32(pm8001_ha, 0, 0x44);
 567         offset = value & 0x03FFFFFF;
 568         PM8001_INIT_DBG(pm8001_ha,
 569                 pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
 570         pcilogic = (value & 0xFC000000) >> 26;
 571         pcibar = get_pci_bar_index(pcilogic);
 572         PM8001_INIT_DBG(pm8001_ha,
 573                 pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
 574         pm8001_ha->main_cfg_tbl_addr = base_addr =
 575                 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 576         pm8001_ha->general_stat_tbl_addr =
 577                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 578         pm8001_ha->inbnd_q_tbl_addr =
 579                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 580         pm8001_ha->outbnd_q_tbl_addr =
 581                 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 582 }
 583
 584 /**
 585  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 586  * @pm8001_ha: our hba card information
 587  */
 588 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 589 {
 590         /* check the firmware status */
 591         if (-1 == check_fw_ready(pm8001_ha)) {
 592                 PM8001_FAIL_DBG(pm8001_ha,
 593                         pm8001_printk("Firmware is not ready!\n"));
 594                 return -EBUSY;
 595         }
 596
 597         /* Initialize pci space address eg: mpi offset */
 598         init_pci_device_addresses(pm8001_ha);
 599         init_default_table_values(pm8001_ha);
 600         read_main_config_table(pm8001_ha);
 601         read_general_status_table(pm8001_ha);
 602         read_inbnd_queue_table(pm8001_ha);
 603         read_outbnd_queue_table(pm8001_ha);
 604         /* update main config table ,inbound table and outbound table */
 605         update_main_config_table(pm8001_ha);
 606         update_inbnd_queue_table(pm8001_ha, 0);
 607         update_outbnd_queue_table(pm8001_ha, 0);
 608         mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 609         mpi_set_open_retry_interval_reg(pm8001_ha, 7);
 610         /* notify firmware update finished and check initialization status */
 611         if (0 == mpi_init_check(pm8001_ha)) {
 612                 PM8001_INIT_DBG(pm8001_ha,
 613                         pm8001_printk("MPI initialize successful!\n"));
 614         } else
 615                 return -EBUSY;
 616         /*This register is a 16-bit timer with a resolution of 1us. This is the
 617         timer used for interrupt delay/coalescing in the PCIe Application Layer.
 618         Zero is not a valid value. A value of 1 in the register will cause the
 619         interrupts to be normal. A value greater than 1 will cause coalescing
 620         delays.*/
 621         pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 622         pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 623         return 0;
 624 }
 625
 626 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 627 {
 628         u32 max_wait_count;
 629         u32 value;
 630         u32 gst_len_mpistate;
 631         init_pci_device_addresses(pm8001_ha);
 632         /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 633         table is stop */
 634         pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 635
 636         /* wait until Inbound DoorBell Clear Register toggled */
 637         max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 638         do {
 639                 udelay(1);
 640                 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 641                 value &= SPC_MSGU_CFG_TABLE_RESET;
 642         } while ((value != 0) && (--max_wait_count));
 643
 644         if (!max_wait_count) {
 645                 PM8001_FAIL_DBG(pm8001_ha,
 646                         pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
 647                 return -1;
 648         }
 649
 650         /* check the MPI-State for termination in progress */
 651         /* wait until Inbound DoorBell Clear Register toggled */
 652         max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 653         do {
 654                 udelay(1);
 655                 gst_len_mpistate =
 656                         pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 657                         GST_GSTLEN_MPIS_OFFSET);
 658                 if (GST_MPI_STATE_UNINIT ==
 659                         (gst_len_mpistate & GST_MPI_STATE_MASK))
 660                         break;
 661         } while (--max_wait_count);
 662         if (!max_wait_count) {
 663                 PM8001_FAIL_DBG(pm8001_ha,
 664                         pm8001_printk(" TIME OUT MPI State = 0x%x\n",
 665                                 gst_len_mpistate & GST_MPI_STATE_MASK));
 666                 return -1;
 667         }
 668         return 0;
 669 }
 670
 671 /**
 672  * soft_reset_ready_check - Function to check FW is ready for soft reset.
 673  * @pm8001_ha: our hba card information
 674  */
 675 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 676 {
 677         u32 regVal, regVal1, regVal2;
 678         if (mpi_uninit_check(pm8001_ha) != 0) {
 679                 PM8001_FAIL_DBG(pm8001_ha,
 680                         pm8001_printk("MPI state is not ready\n"));
 681                 return -1;
 682         }
 683         /* read the scratch pad 2 register bit 2 */
 684         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 685                 & SCRATCH_PAD2_FWRDY_RST;
 686         if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 687                 PM8001_INIT_DBG(pm8001_ha,
 688                         pm8001_printk("Firmware is ready for reset .\n"));
 689         } else {
 690         /* Trigger NMI twice via RB6 */
 691                 if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 692                         PM8001_FAIL_DBG(pm8001_ha,
 693                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 694                                         RB6_ACCESS_REG));
 695                         return -1;
 696                 }
 697                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 698                         RB6_MAGIC_NUMBER_RST);
 699                 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 700                 /* wait for 100 ms */
 701                 mdelay(100);
 702                 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 703                         SCRATCH_PAD2_FWRDY_RST;
 704                 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 705                         regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 706                         regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 707                         PM8001_FAIL_DBG(pm8001_ha,
 708                                 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
 709                                 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 710                                 regVal1, regVal2));
 711                         PM8001_FAIL_DBG(pm8001_ha,
 712                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
 713                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
 714                         PM8001_FAIL_DBG(pm8001_ha,
 715                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
 716                                 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
 717                         return -1;
 718                 }
 719         }
 720         return 0;
 721 }
 722
 723 /**
 724  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 725  * the FW register status to the originated status.
 726  * @pm8001_ha: our hba card information
 727  * @signature: signature in host scratch pad0 register.
 728  */
 729 static int
 730 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
 731 {
 732         u32     regVal, toggleVal;
 733         u32     max_wait_count;
 734         u32     regVal1, regVal2, regVal3;
 735
 736         /* step1: Check FW is ready for soft reset */
 737         if (soft_reset_ready_check(pm8001_ha) != 0) {
 738                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
 739                 return -1;
 740         }
 741
 742         /* step 2: clear NMI status register on AAP1 and IOP, write the same
 743         value to clear */
 744         /* map 0x60000 to BAR4(0x20), BAR2(win) */
 745         if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 746                 PM8001_FAIL_DBG(pm8001_ha,
 747                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 748                         MBIC_AAP1_ADDR_BASE));
 749                 return -1;
 750         }
 751         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 752         PM8001_INIT_DBG(pm8001_ha,
 753                 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
 754         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 755         /* map 0x70000 to BAR4(0x20), BAR2(win) */
 756         if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 757                 PM8001_FAIL_DBG(pm8001_ha,
 758                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 759                         MBIC_IOP_ADDR_BASE));
 760                 return -1;
 761         }
 762         regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 763         PM8001_INIT_DBG(pm8001_ha,
 764                 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
 765         pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 766
 767         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 768         PM8001_INIT_DBG(pm8001_ha,
 769                 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
 770         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 771
 772         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 773         PM8001_INIT_DBG(pm8001_ha,
 774                 pm8001_printk("PCIE - Event Interrupt  = 0x%x\n", regVal));
 775         pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 776
 777         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 778         PM8001_INIT_DBG(pm8001_ha,
 779                 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
 780         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 781
 782         regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 783         PM8001_INIT_DBG(pm8001_ha,
 784                 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
 785         pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 786
 787         /* read the scratch pad 1 register bit 2 */
 788         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 789                 & SCRATCH_PAD1_RST;
 790         toggleVal = regVal ^ SCRATCH_PAD1_RST;
 791
 792         /* set signature in host scratch pad0 register to tell SPC that the
 793         host performs the soft reset */
 794         pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 795
 796         /* read required registers for confirmming */
 797         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 798         if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 799                 PM8001_FAIL_DBG(pm8001_ha,
 800                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 801                         GSM_ADDR_BASE));
 802                 return -1;
 803         }
 804         PM8001_INIT_DBG(pm8001_ha,
 805                 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
 806                 " Reset = 0x%x\n",
 807                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 808
 809         /* step 3: host read GSM Configuration and Reset register */
 810         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 811         /* Put those bits to low */
 812         /* GSM XCBI offset = 0x70 0000
 813         0x00 Bit 13 COM_SLV_SW_RSTB 1
 814         0x00 Bit 12 QSSP_SW_RSTB 1
 815         0x00 Bit 11 RAAE_SW_RSTB 1
 816         0x00 Bit 9 RB_1_SW_RSTB 1
 817         0x00 Bit 8 SM_SW_RSTB 1
 818         */
 819         regVal &= ~(0x00003b00);
 820         /* host write GSM Configuration and Reset register */
 821         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 822         PM8001_INIT_DBG(pm8001_ha,
 823                 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
 824                 "Configuration and Reset is set to = 0x%x\n",
 825                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 826
 827         /* step 4: */
 828         /* disable GSM - Read Address Parity Check */
 829         regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 830         PM8001_INIT_DBG(pm8001_ha,
 831                 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
 832                 "Enable = 0x%x\n", regVal1));
 833         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 834         PM8001_INIT_DBG(pm8001_ha,
 835                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 836                 "is set to = 0x%x\n",
 837                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 838
 839         /* disable GSM - Write Address Parity Check */
 840         regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 841         PM8001_INIT_DBG(pm8001_ha,
 842                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 843                 " Enable = 0x%x\n", regVal2));
 844         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 845         PM8001_INIT_DBG(pm8001_ha,
 846                 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
 847                 "Enable is set to = 0x%x\n",
 848                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 849
 850         /* disable GSM - Write Data Parity Check */
 851         regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 852         PM8001_INIT_DBG(pm8001_ha,
 853                 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
 854                 " Enable = 0x%x\n", regVal3));
 855         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 856         PM8001_INIT_DBG(pm8001_ha,
 857                 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
 858                 "is set to = 0x%x\n",
 859         pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 860
 861         /* step 5: delay 10 usec */
 862         udelay(10);
 863         /* step 5-b: set GPIO-0 output control to tristate anyway */
 864         if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 865                 PM8001_INIT_DBG(pm8001_ha,
 866                                 pm8001_printk("Shift Bar4 to 0x%x failed\n",
 867                                 GPIO_ADDR_BASE));
 868                 return -1;
 869         }
 870         regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 871                 PM8001_INIT_DBG(pm8001_ha,
 872                                 pm8001_printk("GPIO Output Control Register:"
 873                                 " = 0x%x\n", regVal));
 874         /* set GPIO-0 output control to tri-state */
 875         regVal &= 0xFFFFFFFC;
 876         pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 877
 878         /* Step 6: Reset the IOP and AAP1 */
 879         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 880         if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 881                 PM8001_FAIL_DBG(pm8001_ha,
 882                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 883                         SPC_TOP_LEVEL_ADDR_BASE));
 884                 return -1;
 885         }
 886         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 887         PM8001_INIT_DBG(pm8001_ha,
 888                 pm8001_printk("Top Register before resetting IOP/AAP1"
 889                 ":= 0x%x\n", regVal));
 890         regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 891         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 892
 893         /* step 7: Reset the BDMA/OSSP */
 894         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 895         PM8001_INIT_DBG(pm8001_ha,
 896                 pm8001_printk("Top Register before resetting BDMA/OSSP"
 897                 ": = 0x%x\n", regVal));
 898         regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 899         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 900
 901         /* step 8: delay 10 usec */
 902         udelay(10);
 903
 904         /* step 9: bring the BDMA and OSSP out of reset */
 905         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 906         PM8001_INIT_DBG(pm8001_ha,
 907                 pm8001_printk("Top Register before bringing up BDMA/OSSP"
 908                 ":= 0x%x\n", regVal));
 909         regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 910         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 911
 912         /* step 10: delay 10 usec */
 913         udelay(10);
 914
 915         /* step 11: reads and sets the GSM Configuration and Reset Register */
 916         /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 917         if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 918                 PM8001_FAIL_DBG(pm8001_ha,
 919                         pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
 920                         GSM_ADDR_BASE));
 921                 return -1;
 922         }
 923         PM8001_INIT_DBG(pm8001_ha,
 924                 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
 925                 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 926         regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 927         /* Put those bits to high */
 928         /* GSM XCBI offset = 0x70 0000
 929         0x00 Bit 13 COM_SLV_SW_RSTB 1
 930         0x00 Bit 12 QSSP_SW_RSTB 1
 931         0x00 Bit 11 RAAE_SW_RSTB 1
 932         0x00 Bit 9   RB_1_SW_RSTB 1
 933         0x00 Bit 8   SM_SW_RSTB 1
 934         */
 935         regVal |= (GSM_CONFIG_RESET_VALUE);
 936         pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 937         PM8001_INIT_DBG(pm8001_ha,
 938                 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
 939                 " Configuration and Reset is set to = 0x%x\n",
 940                 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
 941
 942         /* step 12: Restore GSM - Read Address Parity Check */
 943         regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 944         /* just for debugging */
 945         PM8001_INIT_DBG(pm8001_ha,
 946                 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
 947                 " = 0x%x\n", regVal));
 948         pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
 949         PM8001_INIT_DBG(pm8001_ha,
 950                 pm8001_printk("GSM 0x700038 - Read Address Parity"
 951                 " Check Enable is set to = 0x%x\n",
 952                 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
 953         /* Restore GSM - Write Address Parity Check */
 954         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 955         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
 956         PM8001_INIT_DBG(pm8001_ha,
 957                 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
 958                 " Enable is set to = 0x%x\n",
 959                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
 960         /* Restore GSM - Write Data Parity Check */
 961         regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 962         pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
 963         PM8001_INIT_DBG(pm8001_ha,
 964                 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
 965                 "is set to = 0x%x\n",
 966                 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
 967
 968         /* step 13: bring the IOP and AAP1 out of reset */
 969         /* map 0x00000 to BAR4(0x20), BAR2(win) */
 970         if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 971                 PM8001_FAIL_DBG(pm8001_ha,
 972                         pm8001_printk("Shift Bar4 to 0x%x failed\n",
 973                         SPC_TOP_LEVEL_ADDR_BASE));
 974                 return -1;
 975         }
 976         regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 977         regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 978         pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 979
 980         /* step 14: delay 10 usec - Normal Mode */
 981         udelay(10);
 982         /* check Soft Reset Normal mode or Soft Reset HDA mode */
 983         if (signature == SPC_SOFT_RESET_SIGNATURE) {
 984                 /* step 15 (Normal Mode): wait until scratch pad1 register
 985                 bit 2 toggled */
 986                 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
 987                 do {
 988                         udelay(1);
 989                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
 990                                 SCRATCH_PAD1_RST;
 991                 } while ((regVal != toggleVal) && (--max_wait_count));
 992
 993                 if (!max_wait_count) {
 994                         regVal = pm8001_cr32(pm8001_ha, 0,
 995                                 MSGU_SCRATCH_PAD_1);
 996                         PM8001_FAIL_DBG(pm8001_ha,
 997                                 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
 998                                 "MSGU_SCRATCH_PAD1 = 0x%x\n",
 999                                 toggleVal, regVal));
1000                         PM8001_FAIL_DBG(pm8001_ha,
1001                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1002                                 pm8001_cr32(pm8001_ha, 0,
1003                                 MSGU_SCRATCH_PAD_0)));
1004                         PM8001_FAIL_DBG(pm8001_ha,
1005                                 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1006                                 pm8001_cr32(pm8001_ha, 0,
1007                                 MSGU_SCRATCH_PAD_2)));
1008                         PM8001_FAIL_DBG(pm8001_ha,
1009                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1010                                 pm8001_cr32(pm8001_ha, 0,
1011                                 MSGU_SCRATCH_PAD_3)));
1012                         return -1;
1013                 }
1014
1015                 /* step 16 (Normal) - Clear ODMR and ODCR */
1016                 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1017                 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1018
1019                 /* step 17 (Normal Mode): wait for the FW and IOP to get
1020                 ready - 1 sec timeout */
1021                 /* Wait for the SPC Configuration Table to be ready */
1022                 if (check_fw_ready(pm8001_ha) == -1) {
1023                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1024                         /* return error if MPI Configuration Table not ready */
1025                         PM8001_INIT_DBG(pm8001_ha,
1026                                 pm8001_printk("FW not ready SCRATCH_PAD1"
1027                                 " = 0x%x\n", regVal));
1028                         regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1029                         /* return error if MPI Configuration Table not ready */
1030                         PM8001_INIT_DBG(pm8001_ha,
1031                                 pm8001_printk("FW not ready SCRATCH_PAD2"
1032                                 " = 0x%x\n", regVal));
1033                         PM8001_INIT_DBG(pm8001_ha,
1034                                 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1035                                 pm8001_cr32(pm8001_ha, 0,
1036                                 MSGU_SCRATCH_PAD_0)));
1037                         PM8001_INIT_DBG(pm8001_ha,
1038                                 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1039                                 pm8001_cr32(pm8001_ha, 0,
1040                                 MSGU_SCRATCH_PAD_3)));
1041                         return -1;
1042                 }
1043         }
1044
1045         PM8001_INIT_DBG(pm8001_ha,
1046                 pm8001_printk("SPC soft reset Complete\n"));
1047         return 0;
1048 }
1049
1050 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1051 {
1052         u32 i;
1053         u32 regVal;
1054         PM8001_INIT_DBG(pm8001_ha,
1055                 pm8001_printk("chip reset start\n"));
1056
1057         /* do SPC chip reset. */
1058         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1059         regVal &= ~(SPC_REG_RESET_DEVICE);
1060         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1061
1062         /* delay 10 usec */
1063         udelay(10);
1064
1065         /* bring chip reset out of reset */
1066         regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1067         regVal |= SPC_REG_RESET_DEVICE;
1068         pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1069
1070         /* delay 10 usec */
1071         udelay(10);
1072
1073         /* wait for 20 msec until the firmware gets reloaded */
1074         i = 20;
1075         do {
1076                 mdelay(1);
1077         } while ((--i) != 0);
1078
1079         PM8001_INIT_DBG(pm8001_ha,
1080                 pm8001_printk("chip reset finished\n"));
1081 }
1082
1083 /**
1084  * pm8001_chip_iounmap - which maped when initilized.
1085  * @pm8001_ha: our hba card information
1086  */
1087 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1088 {
1089         s8 bar, logical = 0;
1090         for (bar = 0; bar < 6; bar++) {
1091                 /*
1092                 ** logical BARs for SPC:
1093                 ** bar 0 and 1 - logical BAR0
1094                 ** bar 2 and 3 - logical BAR1
1095                 ** bar4 - logical BAR2
1096                 ** bar5 - logical BAR3
1097                 ** Skip the appropriate assignments:
1098                 */
1099                 if ((bar == 1) || (bar == 3))
1100                         continue;
1101                 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1102                         iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1103                         logical++;
1104                 }
1105         }
1106 }
1107
1108 /**
1109  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1110  * @pm8001_ha: our hba card information
1111  */
1112 static void
1113 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1114 {
1115         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1116         pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1117 }
1118
1119  /**
1120   * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1121   * @pm8001_ha: our hba card information
1122   */
1123 static void
1124 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1125 {
1126         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1127 }
1128
1129 /**
1130  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1131  * @pm8001_ha: our hba card information
1132  */
1133 static void
1134 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1135         u32 int_vec_idx)
1136 {
1137         u32 msi_index;
1138         u32 value;
1139         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1140         msi_index += MSIX_TABLE_BASE;
1141         pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1142         value = (1 << int_vec_idx);
1143         pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1144
1145 }
1146
1147 /**
1148  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1149  * @pm8001_ha: our hba card information
1150  */
1151 static void
1152 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1153         u32 int_vec_idx)
1154 {
1155         u32 msi_index;
1156         msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1157         msi_index += MSIX_TABLE_BASE;
1158         pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1159
1160 }
1161 /**
1162  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1163  * @pm8001_ha: our hba card information
1164  */
1165 static void
1166 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1167 {
1168 #ifdef PM8001_USE_MSIX
1169         pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1170         return;
1171 #endif
1172         pm8001_chip_intx_interrupt_enable(pm8001_ha);
1173
1174 }
1175
1176 /**
1177  * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1178  * @pm8001_ha: our hba card information
1179  */
1180 static void
1181 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1182 {
1183 #ifdef PM8001_USE_MSIX
1184         pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1185         return;
1186 #endif
1187         pm8001_chip_intx_interrupt_disable(pm8001_ha);
1188
1189 }
1190
1191 /**
1192  * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1193  * @circularQ: the inbound queue  we want to transfer to HBA.
1194  * @messageSize: the message size of this transfer, normally it is 64 bytes
1195  * @messagePtr: the pointer to message.
1196  */
1197 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1198                             u16 messageSize, void **messagePtr)
1199 {
1200         u32 offset, consumer_index;
1201         struct mpi_msg_hdr *msgHeader;
1202         u8 bcCount = 1; /* only support single buffer */
1203
1204         /* Checks is the requested message size can be allocated in this queue*/
1205         if (messageSize > 64) {
1206                 *messagePtr = NULL;
1207                 return -1;
1208         }
1209
1210         /* Stores the new consumer index */
1211         consumer_index = pm8001_read_32(circularQ->ci_virt);
1212         circularQ->consumer_index = cpu_to_le32(consumer_index);
1213         if (((circularQ->producer_idx + bcCount) % 256) ==
1214                 circularQ->consumer_index) {
1215                 *messagePtr = NULL;
1216                 return -1;
1217         }
1218         /* get memory IOMB buffer address */
1219         offset = circularQ->producer_idx * 64;
1220         /* increment to next bcCount element */
1221         circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1222         /* Adds that distance to the base of the region virtual address plus
1223         the message header size*/
1224         msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1225         *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1226         return 0;
1227 }
1228
1229 /**
1230  * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1231  * to tell the fw to get this message from IOMB.
1232  * @pm8001_ha: our hba card information
1233  * @circularQ: the inbound queue we want to transfer to HBA.
1234  * @opCode: the operation code represents commands which LLDD and fw recognized.
1235  * @payload: the command payload of each operation command.
1236  */
1237 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1238                          struct inbound_queue_table *circularQ,
1239                          u32 opCode, void *payload)
1240 {
1241         u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1242         u32 responseQueue = 0;
1243         void *pMessage;
1244
1245         if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1246                 PM8001_IO_DBG(pm8001_ha,
1247                         pm8001_printk("No free mpi buffer \n"));
1248                 return -1;
1249         }
1250         BUG_ON(!payload);
1251         /*Copy to the payload*/
1252         memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1253
1254         /*Build the header*/
1255         Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1256                 | ((responseQueue & 0x3F) << 16)
1257                 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1258
1259         pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1260         /*Update the PI to the firmware*/
1261         pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1262                 circularQ->pi_offset, circularQ->producer_idx);
1263         PM8001_IO_DBG(pm8001_ha,
1264                 pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
1265                 circularQ->consumer_index));
1266         return 0;
1267 }
1268
1269 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1270                             struct outbound_queue_table *circularQ, u8 bc)
1271 {
1272         u32 producer_index;
1273         struct mpi_msg_hdr *msgHeader;
1274         struct mpi_msg_hdr *pOutBoundMsgHeader;
1275
1276         msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1277         pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1278                                 circularQ->consumer_idx * 64);
1279         if (pOutBoundMsgHeader != msgHeader) {
1280                 PM8001_FAIL_DBG(pm8001_ha,
1281                         pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1282                         circularQ->consumer_idx, msgHeader));
1283
1284                 /* Update the producer index from SPC */
1285                 producer_index = pm8001_read_32(circularQ->pi_virt);
1286                 circularQ->producer_index = cpu_to_le32(producer_index);
1287                 PM8001_FAIL_DBG(pm8001_ha,
1288                         pm8001_printk("consumer_idx = %d producer_index = %d"
1289                         "msgHeader = %p\n", circularQ->consumer_idx,
1290                         circularQ->producer_index, msgHeader));
1291                 return 0;
1292         }
1293         /* free the circular queue buffer elements associated with the message*/
1294         circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1295         /* update the CI of outbound queue */
1296         pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1297                 circularQ->consumer_idx);
1298         /* Update the producer index from SPC*/
1299         producer_index = pm8001_read_32(circularQ->pi_virt);
1300         circularQ->producer_index = cpu_to_le32(producer_index);
1301         PM8001_IO_DBG(pm8001_ha,
1302                 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1303                 circularQ->producer_index));
1304         return 0;
1305 }
1306
1307 /**
1308  * mpi_msg_consume- get the MPI message from  outbound queue message table.
1309  * @pm8001_ha: our hba card information
1310  * @circularQ: the outbound queue  table.
1311  * @messagePtr1: the message contents of this outbound message.
1312  * @pBC: the message size.
1313  */
1314 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1315                            struct outbound_queue_table *circularQ,
1316                            void **messagePtr1, u8 *pBC)
1317 {
1318         struct mpi_msg_hdr      *msgHeader;
1319         __le32  msgHeader_tmp;
1320         u32 header_tmp;
1321         do {
1322                 /* If there are not-yet-delivered messages ... */
1323                 if (circularQ->producer_index != circularQ->consumer_idx) {
1324                         /*Get the pointer to the circular queue buffer element*/
1325                         msgHeader = (struct mpi_msg_hdr *)
1326                                 (circularQ->base_virt +
1327                                 circularQ->consumer_idx * 64);
1328                         /* read header */
1329                         header_tmp = pm8001_read_32(msgHeader);
1330                         msgHeader_tmp = cpu_to_le32(header_tmp);
1331                         if (0 != (msgHeader_tmp & 0x80000000)) {
1332                                 if (OPC_OUB_SKIP_ENTRY !=
1333                                         (msgHeader_tmp & 0xfff)) {
1334                                         *messagePtr1 =
1335                                                 ((u8 *)msgHeader) +
1336                                                 sizeof(struct mpi_msg_hdr);
1337                                         *pBC = (u8)((msgHeader_tmp >> 24) &
1338                                                 0x1f);
1339                                         PM8001_IO_DBG(pm8001_ha,
1340                                                 pm8001_printk(": CI=%d PI=%d "
1341                                                 "msgHeader=%x\n",
1342                                                 circularQ->consumer_idx,
1343                                                 circularQ->producer_index,
1344                                                 msgHeader_tmp));
1345                                         return MPI_IO_STATUS_SUCCESS;
1346                                 } else {
1347                                         circularQ->consumer_idx =
1348                                                 (circularQ->consumer_idx +
1349                                                 ((msgHeader_tmp >> 24) & 0x1f))
1350                                                 % 256;
1351                                         msgHeader_tmp = 0;
1352                                         pm8001_write_32(msgHeader, 0, 0);
1353                                         /* update the CI of outbound queue */
1354                                         pm8001_cw32(pm8001_ha,
1355                                                 circularQ->ci_pci_bar,
1356                                                 circularQ->ci_offset,
1357                                                 circularQ->consumer_idx);
1358                                 }
1359                         } else {
1360                                 circularQ->consumer_idx =
1361                                         (circularQ->consumer_idx +
1362                                         ((msgHeader_tmp >> 24) & 0x1f)) % 256;
1363                                 msgHeader_tmp = 0;
1364                                 pm8001_write_32(msgHeader, 0, 0);
1365                                 /* update the CI of outbound queue */
1366                                 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1367                                         circularQ->ci_offset,
1368                                         circularQ->consumer_idx);
1369                                 return MPI_IO_STATUS_FAIL;
1370                         }
1371                 } else {
1372                         u32 producer_index;
1373                         void *pi_virt = circularQ->pi_virt;
1374                         /* Update the producer index from SPC */
1375                         producer_index = pm8001_read_32(pi_virt);
1376                         circularQ->producer_index = cpu_to_le32(producer_index);
1377                 }
1378         } while (circularQ->producer_index != circularQ->consumer_idx);
1379         /* while we don't have any more not-yet-delivered message */
1380         /* report empty */
1381         return MPI_IO_STATUS_BUSY;
1382 }
1383
1384 static void pm8001_work_queue(struct work_struct *work)
1385 {
1386         struct delayed_work *dw = container_of(work, struct delayed_work, work);
1387         struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
1388         struct pm8001_device *pm8001_dev;
1389         struct domain_device    *dev;
1390
1391         switch (wq->handler) {
1392         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1393                 pm8001_dev = wq->data;
1394                 dev = pm8001_dev->sas_device;
1395                 pm8001_I_T_nexus_reset(dev);
1396                 break;
1397         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1398                 pm8001_dev = wq->data;
1399                 dev = pm8001_dev->sas_device;
1400                 pm8001_I_T_nexus_reset(dev);
1401                 break;
1402         case IO_DS_IN_ERROR:
1403                 pm8001_dev = wq->data;
1404                 dev = pm8001_dev->sas_device;
1405                 pm8001_I_T_nexus_reset(dev);
1406                 break;
1407         case IO_DS_NON_OPERATIONAL:
1408                 pm8001_dev = wq->data;
1409                 dev = pm8001_dev->sas_device;
1410                 pm8001_I_T_nexus_reset(dev);
1411                 break;
1412         }
1413         list_del(&wq->entry);
1414         kfree(wq);
1415 }
1416
1417 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1418                                int handler)
1419 {
1420         struct pm8001_wq *wq;
1421         int ret = 0;
1422
1423         wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
1424         if (wq) {
1425                 wq->pm8001_ha = pm8001_ha;
1426                 wq->data = data;
1427                 wq->handler = handler;
1428                 INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
1429                 list_add_tail(&wq->entry, &pm8001_ha->wq_list);
1430                 schedule_delayed_work(&wq->work_q, 0);
1431         } else
1432                 ret = -ENOMEM;
1433
1434         return ret;
1435 }
1436
1437 /**
1438  * mpi_ssp_completion- process the event that FW response to the SSP request.
1439  * @pm8001_ha: our hba card information
1440  * @piomb: the message contents of this outbound message.
1441  *
1442  * When FW has completed a ssp request for example a IO request, after it has
1443  * filled the SG data with the data, it will trigger this event represent
1444  * that he has finished the job,please check the coresponding buffer.
1445  * So we will tell the caller who maybe waiting the result to tell upper layer
1446  * that the task has been finished.
1447  */
1448 static void
1449 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1450 {
1451         struct sas_task *t;
1452         struct pm8001_ccb_info *ccb;
1453         unsigned long flags;
1454         u32 status;
1455         u32 param;
1456         u32 tag;
1457         struct ssp_completion_resp *psspPayload;
1458         struct task_status_struct *ts;
1459         struct ssp_response_iu *iu;
1460         struct pm8001_device *pm8001_dev;
1461         psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1462         status = le32_to_cpu(psspPayload->status);
1463         tag = le32_to_cpu(psspPayload->tag);
1464         ccb = &pm8001_ha->ccb_info[tag];
1465         pm8001_dev = ccb->device;
1466         param = le32_to_cpu(psspPayload->param);
1467
1468         t = ccb->task;
1469
1470         if (status && status != IO_UNDERFLOW)
1471                 PM8001_FAIL_DBG(pm8001_ha,
1472                         pm8001_printk("sas IO status 0x%x\n", status));
1473         if (unlikely(!t || !t->lldd_task || !t->dev))
1474                 return;
1475         ts = &t->task_status;
1476         switch (status) {
1477         case IO_SUCCESS:
1478                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1479                         ",param = %d \n", param));
1480                 if (param == 0) {
1481                         ts->resp = SAS_TASK_COMPLETE;
1482                         ts->stat = SAM_GOOD;
1483                 } else {
1484                         ts->resp = SAS_TASK_COMPLETE;
1485                         ts->stat = SAS_PROTO_RESPONSE;
1486                         ts->residual = param;
1487                         iu = &psspPayload->ssp_resp_iu;
1488                         sas_ssp_task_response(pm8001_ha->dev, t, iu);
1489                 }
1490                 if (pm8001_dev)
1491                         pm8001_dev->running_req--;
1492                 break;
1493         case IO_ABORTED:
1494                 PM8001_IO_DBG(pm8001_ha,
1495                         pm8001_printk("IO_ABORTED IOMB Tag \n"));
1496                 ts->resp = SAS_TASK_COMPLETE;
1497                 ts->stat = SAS_ABORTED_TASK;
1498                 break;
1499         case IO_UNDERFLOW:
1500                 /* SSP Completion with error */
1501                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1502                         ",param = %d \n", param));
1503                 ts->resp = SAS_TASK_COMPLETE;
1504                 ts->stat = SAS_DATA_UNDERRUN;
1505                 ts->residual = param;
1506                 if (pm8001_dev)
1507                         pm8001_dev->running_req--;
1508                 break;
1509         case IO_NO_DEVICE:
1510                 PM8001_IO_DBG(pm8001_ha,
1511                         pm8001_printk("IO_NO_DEVICE\n"));
1512                 ts->resp = SAS_TASK_UNDELIVERED;
1513                 ts->stat = SAS_PHY_DOWN;
1514                 break;
1515         case IO_XFER_ERROR_BREAK:
1516                 PM8001_IO_DBG(pm8001_ha,
1517                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1518                 ts->resp = SAS_TASK_COMPLETE;
1519                 ts->stat = SAS_OPEN_REJECT;
1520                 break;
1521         case IO_XFER_ERROR_PHY_NOT_READY:
1522                 PM8001_IO_DBG(pm8001_ha,
1523                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1524                 ts->resp = SAS_TASK_COMPLETE;
1525                 ts->stat = SAS_OPEN_REJECT;
1526                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1527                 break;
1528         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1529                 PM8001_IO_DBG(pm8001_ha,
1530                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1531                 ts->resp = SAS_TASK_COMPLETE;
1532                 ts->stat = SAS_OPEN_REJECT;
1533                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1534                 break;
1535         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1536                 PM8001_IO_DBG(pm8001_ha,
1537                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1538                 ts->resp = SAS_TASK_COMPLETE;
1539                 ts->stat = SAS_OPEN_REJECT;
1540                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1541                 break;
1542         case IO_OPEN_CNX_ERROR_BREAK:
1543                 PM8001_IO_DBG(pm8001_ha,
1544                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1545                 ts->resp = SAS_TASK_COMPLETE;
1546                 ts->stat = SAS_OPEN_REJECT;
1547                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1548                 break;
1549         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1550                 PM8001_IO_DBG(pm8001_ha,
1551                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1552                 ts->resp = SAS_TASK_COMPLETE;
1553                 ts->stat = SAS_OPEN_REJECT;
1554                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1555                 if (!t->uldd_task)
1556                         pm8001_handle_event(pm8001_ha,
1557                                 pm8001_dev,
1558                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1559                 break;
1560         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1561                 PM8001_IO_DBG(pm8001_ha,
1562                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1563                 ts->resp = SAS_TASK_COMPLETE;
1564                 ts->stat = SAS_OPEN_REJECT;
1565                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1566                 break;
1567         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1568                 PM8001_IO_DBG(pm8001_ha,
1569                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1570                         "NOT_SUPPORTED\n"));
1571                 ts->resp = SAS_TASK_COMPLETE;
1572                 ts->stat = SAS_OPEN_REJECT;
1573                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1574                 break;
1575         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1576                 PM8001_IO_DBG(pm8001_ha,
1577                         pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1578                 ts->resp = SAS_TASK_UNDELIVERED;
1579                 ts->stat = SAS_OPEN_REJECT;
1580                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1581                 break;
1582         case IO_XFER_ERROR_NAK_RECEIVED:
1583                 PM8001_IO_DBG(pm8001_ha,
1584                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1585                 ts->resp = SAS_TASK_COMPLETE;
1586                 ts->stat = SAS_OPEN_REJECT;
1587                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1588                 break;
1589         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1590                 PM8001_IO_DBG(pm8001_ha,
1591                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1592                 ts->resp = SAS_TASK_COMPLETE;
1593                 ts->stat = SAS_NAK_R_ERR;
1594                 break;
1595         case IO_XFER_ERROR_DMA:
1596                 PM8001_IO_DBG(pm8001_ha,
1597                 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1598                 ts->resp = SAS_TASK_COMPLETE;
1599                 ts->stat = SAS_OPEN_REJECT;
1600                 break;
1601         case IO_XFER_OPEN_RETRY_TIMEOUT:
1602                 PM8001_IO_DBG(pm8001_ha,
1603                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1604                 ts->resp = SAS_TASK_COMPLETE;
1605                 ts->stat = SAS_OPEN_REJECT;
1606                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1607                 break;
1608         case IO_XFER_ERROR_OFFSET_MISMATCH:
1609                 PM8001_IO_DBG(pm8001_ha,
1610                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1611                 ts->resp = SAS_TASK_COMPLETE;
1612                 ts->stat = SAS_OPEN_REJECT;
1613                 break;
1614         case IO_PORT_IN_RESET:
1615                 PM8001_IO_DBG(pm8001_ha,
1616                         pm8001_printk("IO_PORT_IN_RESET\n"));
1617                 ts->resp = SAS_TASK_COMPLETE;
1618                 ts->stat = SAS_OPEN_REJECT;
1619                 break;
1620         case IO_DS_NON_OPERATIONAL:
1621                 PM8001_IO_DBG(pm8001_ha,
1622                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1623                 ts->resp = SAS_TASK_COMPLETE;
1624                 ts->stat = SAS_OPEN_REJECT;
1625                 if (!t->uldd_task)
1626                         pm8001_handle_event(pm8001_ha,
1627                                 pm8001_dev,
1628                                 IO_DS_NON_OPERATIONAL);
1629                 break;
1630         case IO_DS_IN_RECOVERY:
1631                 PM8001_IO_DBG(pm8001_ha,
1632                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
1633                 ts->resp = SAS_TASK_COMPLETE;
1634                 ts->stat = SAS_OPEN_REJECT;
1635                 break;
1636         case IO_TM_TAG_NOT_FOUND:
1637                 PM8001_IO_DBG(pm8001_ha,
1638                         pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1639                 ts->resp = SAS_TASK_COMPLETE;
1640                 ts->stat = SAS_OPEN_REJECT;
1641                 break;
1642         case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1643                 PM8001_IO_DBG(pm8001_ha,
1644                         pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1645                 ts->resp = SAS_TASK_COMPLETE;
1646                 ts->stat = SAS_OPEN_REJECT;
1647                 break;
1648         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1649                 PM8001_IO_DBG(pm8001_ha,
1650                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1651                 ts->resp = SAS_TASK_COMPLETE;
1652                 ts->stat = SAS_OPEN_REJECT;
1653                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1654         default:
1655                 PM8001_IO_DBG(pm8001_ha,
1656                         pm8001_printk("Unknown status 0x%x\n", status));
1657                 /* not allowed case. Therefore, return failed status */
1658                 ts->resp = SAS_TASK_COMPLETE;
1659                 ts->stat = SAS_OPEN_REJECT;
1660                 break;
1661         }
1662         PM8001_IO_DBG(pm8001_ha,
1663                 pm8001_printk("scsi_status = %x \n ",
1664                 psspPayload->ssp_resp_iu.status));
1665         spin_lock_irqsave(&t->task_state_lock, flags);
1666         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1667         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1668         t->task_state_flags |= SAS_TASK_STATE_DONE;
1669         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1670                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1671                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1672                         " io_status 0x%x resp 0x%x "
1673                         "stat 0x%x but aborted by upper layer!\n",
1674                         t, status, ts->resp, ts->stat));
1675                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1676         } else {
1677                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1678                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1679                 mb();/* in order to force CPU ordering */
1680                 t->task_done(t);
1681         }
1682 }
1683
1684 /*See the comments for mpi_ssp_completion */
1685 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1686 {
1687         struct sas_task *t;
1688         unsigned long flags;
1689         struct task_status_struct *ts;
1690         struct pm8001_ccb_info *ccb;
1691         struct pm8001_device *pm8001_dev;
1692         struct ssp_event_resp *psspPayload =
1693                 (struct ssp_event_resp *)(piomb + 4);
1694         u32 event = le32_to_cpu(psspPayload->event);
1695         u32 tag = le32_to_cpu(psspPayload->tag);
1696         u32 port_id = le32_to_cpu(psspPayload->port_id);
1697         u32 dev_id = le32_to_cpu(psspPayload->device_id);
1698
1699         ccb = &pm8001_ha->ccb_info[tag];
1700         t = ccb->task;
1701         pm8001_dev = ccb->device;
1702         if (event)
1703                 PM8001_FAIL_DBG(pm8001_ha,
1704                         pm8001_printk("sas IO status 0x%x\n", event));
1705         if (unlikely(!t || !t->lldd_task || !t->dev))
1706                 return;
1707         ts = &t->task_status;
1708         PM8001_IO_DBG(pm8001_ha,
1709                 pm8001_printk("port_id = %x,device_id = %x\n",
1710                 port_id, dev_id));
1711         switch (event) {
1712         case IO_OVERFLOW:
1713                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1714                 ts->resp = SAS_TASK_COMPLETE;
1715                 ts->stat = SAS_DATA_OVERRUN;
1716                 ts->residual = 0;
1717                 if (pm8001_dev)
1718                         pm8001_dev->running_req--;
1719                 break;
1720         case IO_XFER_ERROR_BREAK:
1721                 PM8001_IO_DBG(pm8001_ha,
1722                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1723                 ts->resp = SAS_TASK_COMPLETE;
1724                 ts->stat = SAS_INTERRUPTED;
1725                 break;
1726         case IO_XFER_ERROR_PHY_NOT_READY:
1727                 PM8001_IO_DBG(pm8001_ha,
1728                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1729                 ts->resp = SAS_TASK_COMPLETE;
1730                 ts->stat = SAS_OPEN_REJECT;
1731                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1732                 break;
1733         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1734                 PM8001_IO_DBG(pm8001_ha,
1735                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1736                         "_SUPPORTED\n"));
1737                 ts->resp = SAS_TASK_COMPLETE;
1738                 ts->stat = SAS_OPEN_REJECT;
1739                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1740                 break;
1741         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1742                 PM8001_IO_DBG(pm8001_ha,
1743                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1744                 ts->resp = SAS_TASK_COMPLETE;
1745                 ts->stat = SAS_OPEN_REJECT;
1746                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1747                 break;
1748         case IO_OPEN_CNX_ERROR_BREAK:
1749                 PM8001_IO_DBG(pm8001_ha,
1750                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1751                 ts->resp = SAS_TASK_COMPLETE;
1752                 ts->stat = SAS_OPEN_REJECT;
1753                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1754                 break;
1755         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1756                 PM8001_IO_DBG(pm8001_ha,
1757                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1758                 ts->resp = SAS_TASK_COMPLETE;
1759                 ts->stat = SAS_OPEN_REJECT;
1760                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1761                 if (!t->uldd_task)
1762                         pm8001_handle_event(pm8001_ha,
1763                                 pm8001_dev,
1764                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1765                 break;
1766         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1767                 PM8001_IO_DBG(pm8001_ha,
1768                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1769                 ts->resp = SAS_TASK_COMPLETE;
1770                 ts->stat = SAS_OPEN_REJECT;
1771                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1772                 break;
1773         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1774                 PM8001_IO_DBG(pm8001_ha,
1775                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1776                         "NOT_SUPPORTED\n"));
1777                 ts->resp = SAS_TASK_COMPLETE;
1778                 ts->stat = SAS_OPEN_REJECT;
1779                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1780                 break;
1781         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1782                 PM8001_IO_DBG(pm8001_ha,
1783                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1784                 ts->resp = SAS_TASK_COMPLETE;
1785                 ts->stat = SAS_OPEN_REJECT;
1786                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1787                 break;
1788         case IO_XFER_ERROR_NAK_RECEIVED:
1789                 PM8001_IO_DBG(pm8001_ha,
1790                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1791                 ts->resp = SAS_TASK_COMPLETE;
1792                 ts->stat = SAS_OPEN_REJECT;
1793                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1794                 break;
1795         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1796                 PM8001_IO_DBG(pm8001_ha,
1797                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1798                 ts->resp = SAS_TASK_COMPLETE;
1799                 ts->stat = SAS_NAK_R_ERR;
1800                 break;
1801         case IO_XFER_OPEN_RETRY_TIMEOUT:
1802                 PM8001_IO_DBG(pm8001_ha,
1803                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1804                 ts->resp = SAS_TASK_COMPLETE;
1805                 ts->stat = SAS_OPEN_REJECT;
1806                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1807                 break;
1808         case IO_XFER_ERROR_UNEXPECTED_PHASE:
1809                 PM8001_IO_DBG(pm8001_ha,
1810                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1811                 ts->resp = SAS_TASK_COMPLETE;
1812                 ts->stat = SAS_DATA_OVERRUN;
1813                 break;
1814         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1815                 PM8001_IO_DBG(pm8001_ha,
1816                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1817                 ts->resp = SAS_TASK_COMPLETE;
1818                 ts->stat = SAS_DATA_OVERRUN;
1819                 break;
1820         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1821                 PM8001_IO_DBG(pm8001_ha,
1822                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1823                 ts->resp = SAS_TASK_COMPLETE;
1824                 ts->stat = SAS_DATA_OVERRUN;
1825                 break;
1826         case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1827                 PM8001_IO_DBG(pm8001_ha,
1828                 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1829                 ts->resp = SAS_TASK_COMPLETE;
1830                 ts->stat = SAS_DATA_OVERRUN;
1831                 break;
1832         case IO_XFER_ERROR_OFFSET_MISMATCH:
1833                 PM8001_IO_DBG(pm8001_ha,
1834                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1835                 ts->resp = SAS_TASK_COMPLETE;
1836                 ts->stat = SAS_DATA_OVERRUN;
1837                 break;
1838         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1839                 PM8001_IO_DBG(pm8001_ha,
1840                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1841                 ts->resp = SAS_TASK_COMPLETE;
1842                 ts->stat = SAS_DATA_OVERRUN;
1843                 break;
1844         case IO_XFER_CMD_FRAME_ISSUED:
1845                 PM8001_IO_DBG(pm8001_ha,
1846                         pm8001_printk("  IO_XFER_CMD_FRAME_ISSUED\n"));
1847                 return;
1848         default:
1849                 PM8001_IO_DBG(pm8001_ha,
1850                         pm8001_printk("Unknown status 0x%x\n", event));
1851                 /* not allowed case. Therefore, return failed status */
1852                 ts->resp = SAS_TASK_COMPLETE;
1853                 ts->stat = SAS_DATA_OVERRUN;
1854                 break;
1855         }
1856         spin_lock_irqsave(&t->task_state_lock, flags);
1857         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1858         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1859         t->task_state_flags |= SAS_TASK_STATE_DONE;
1860         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1861                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1862                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1863                         " event 0x%x resp 0x%x "
1864                         "stat 0x%x but aborted by upper layer!\n",
1865                         t, event, ts->resp, ts->stat));
1866                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1867         } else {
1868                 spin_unlock_irqrestore(&t->task_state_lock, flags);
1869                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1870                 mb();/* in order to force CPU ordering */
1871                 t->task_done(t);
1872         }
1873 }
1874
1875 /*See the comments for mpi_ssp_completion */
1876 static void
1877 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1878 {
1879         struct sas_task *t;
1880         struct pm8001_ccb_info *ccb;
1881         unsigned long flags = 0;
1882         u32 param;
1883         u32 status;
1884         u32 tag;
1885         struct sata_completion_resp *psataPayload;
1886         struct task_status_struct *ts;
1887         struct ata_task_resp *resp ;
1888         u32 *sata_resp;
1889         struct pm8001_device *pm8001_dev;
1890
1891         psataPayload = (struct sata_completion_resp *)(piomb + 4);
1892         status = le32_to_cpu(psataPayload->status);
1893         tag = le32_to_cpu(psataPayload->tag);
1894
1895         ccb = &pm8001_ha->ccb_info[tag];
1896         param = le32_to_cpu(psataPayload->param);
1897         t = ccb->task;
1898         ts = &t->task_status;
1899         pm8001_dev = ccb->device;
1900         if (status)
1901                 PM8001_FAIL_DBG(pm8001_ha,
1902                         pm8001_printk("sata IO status 0x%x\n", status));
1903         if (unlikely(!t || !t->lldd_task || !t->dev))
1904                 return;
1905
1906         switch (status) {
1907         case IO_SUCCESS:
1908                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
1909                 if (param == 0) {
1910                         ts->resp = SAS_TASK_COMPLETE;
1911                         ts->stat = SAM_GOOD;
1912                 } else {
1913                         u8 len;
1914                         ts->resp = SAS_TASK_COMPLETE;
1915                         ts->stat = SAS_PROTO_RESPONSE;
1916                         ts->residual = param;
1917                         PM8001_IO_DBG(pm8001_ha,
1918                                 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
1919                                 param));
1920                         sata_resp = &psataPayload->sata_resp[0];
1921                         resp = (struct ata_task_resp *)ts->buf;
1922                         if (t->ata_task.dma_xfer == 0 &&
1923                         t->data_dir == PCI_DMA_FROMDEVICE) {
1924                                 len = sizeof(struct pio_setup_fis);
1925                                 PM8001_IO_DBG(pm8001_ha,
1926                                 pm8001_printk("PIO read len = %d\n", len));
1927                         } else if (t->ata_task.use_ncq) {
1928                                 len = sizeof(struct set_dev_bits_fis);
1929                                 PM8001_IO_DBG(pm8001_ha,
1930                                         pm8001_printk("FPDMA len = %d\n", len));
1931                         } else {
1932                                 len = sizeof(struct dev_to_host_fis);
1933                                 PM8001_IO_DBG(pm8001_ha,
1934                                 pm8001_printk("other len = %d\n", len));
1935                         }
1936                         if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
1937                                 resp->frame_len = len;
1938                                 memcpy(&resp->ending_fis[0], sata_resp, len);
1939                                 ts->buf_valid_size = sizeof(*resp);
1940                         } else
1941                                 PM8001_IO_DBG(pm8001_ha,
1942                                         pm8001_printk("response to large \n"));
1943                 }
1944                 if (pm8001_dev)
1945                         pm8001_dev->running_req--;
1946                 break;
1947         case IO_ABORTED:
1948                 PM8001_IO_DBG(pm8001_ha,
1949                         pm8001_printk("IO_ABORTED IOMB Tag \n"));
1950                 ts->resp = SAS_TASK_COMPLETE;
1951                 ts->stat = SAS_ABORTED_TASK;
1952                 if (pm8001_dev)
1953                         pm8001_dev->running_req--;
1954                 break;
1955                 /* following cases are to do cases */
1956         case IO_UNDERFLOW:
1957                 /* SATA Completion with error */
1958                 PM8001_IO_DBG(pm8001_ha,
1959                         pm8001_printk("IO_UNDERFLOW param = %d\n", param));
1960                 ts->resp = SAS_TASK_COMPLETE;
1961                 ts->stat = SAS_DATA_UNDERRUN;
1962                 ts->residual =  param;
1963                 if (pm8001_dev)
1964                         pm8001_dev->running_req--;
1965                 break;
1966         case IO_NO_DEVICE:
1967                 PM8001_IO_DBG(pm8001_ha,
1968                         pm8001_printk("IO_NO_DEVICE\n"));
1969                 ts->resp = SAS_TASK_UNDELIVERED;
1970                 ts->stat = SAS_PHY_DOWN;
1971                 break;
1972         case IO_XFER_ERROR_BREAK:
1973                 PM8001_IO_DBG(pm8001_ha,
1974                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1975                 ts->resp = SAS_TASK_COMPLETE;
1976                 ts->stat = SAS_INTERRUPTED;
1977                 break;
1978         case IO_XFER_ERROR_PHY_NOT_READY:
1979                 PM8001_IO_DBG(pm8001_ha,
1980                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1981                 ts->resp = SAS_TASK_COMPLETE;
1982                 ts->stat = SAS_OPEN_REJECT;
1983                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1984                 break;
1985         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1986                 PM8001_IO_DBG(pm8001_ha,
1987                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1988                         "_SUPPORTED\n"));
1989                 ts->resp = SAS_TASK_COMPLETE;
1990                 ts->stat = SAS_OPEN_REJECT;
1991                 ts->open_rej_reason = SAS_OREJ_EPROTO;
1992                 break;
1993         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1994                 PM8001_IO_DBG(pm8001_ha,
1995                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1996                 ts->resp = SAS_TASK_COMPLETE;
1997                 ts->stat = SAS_OPEN_REJECT;
1998                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1999                 break;
2000         case IO_OPEN_CNX_ERROR_BREAK:
2001                 PM8001_IO_DBG(pm8001_ha,
2002                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2003                 ts->resp = SAS_TASK_COMPLETE;
2004                 ts->stat = SAS_OPEN_REJECT;
2005                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2006                 break;
2007         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2008                 PM8001_IO_DBG(pm8001_ha,
2009                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2010                 ts->resp = SAS_TASK_COMPLETE;
2011                 ts->stat = SAS_DEV_NO_RESPONSE;
2012                 if (!t->uldd_task) {
2013                         pm8001_handle_event(pm8001_ha,
2014                                 pm8001_dev,
2015                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2016                         ts->resp = SAS_TASK_UNDELIVERED;
2017                         ts->stat = SAS_QUEUE_FULL;
2018                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2019                         mb();/*in order to force CPU ordering*/
2020                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2021                         t->task_done(t);
2022                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2023                         return;
2024                 }
2025                 break;
2026         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2027                 PM8001_IO_DBG(pm8001_ha,
2028                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2029                 ts->resp = SAS_TASK_UNDELIVERED;
2030                 ts->stat = SAS_OPEN_REJECT;
2031                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2032                 if (!t->uldd_task) {
2033                         pm8001_handle_event(pm8001_ha,
2034                                 pm8001_dev,
2035                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2036                         ts->resp = SAS_TASK_UNDELIVERED;
2037                         ts->stat = SAS_QUEUE_FULL;
2038                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2039                         mb();/*ditto*/
2040                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2041                         t->task_done(t);
2042                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2043                         return;
2044                 }
2045                 break;
2046         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2047                 PM8001_IO_DBG(pm8001_ha,
2048                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2049                         "NOT_SUPPORTED\n"));
2050                 ts->resp = SAS_TASK_COMPLETE;
2051                 ts->stat = SAS_OPEN_REJECT;
2052                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2053                 break;
2054         case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2055                 PM8001_IO_DBG(pm8001_ha,
2056                         pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2057                         "_BUSY\n"));
2058                 ts->resp = SAS_TASK_COMPLETE;
2059                 ts->stat = SAS_DEV_NO_RESPONSE;
2060                 if (!t->uldd_task) {
2061                         pm8001_handle_event(pm8001_ha,
2062                                 pm8001_dev,
2063                                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2064                         ts->resp = SAS_TASK_UNDELIVERED;
2065                         ts->stat = SAS_QUEUE_FULL;
2066                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2067                         mb();/* ditto*/
2068                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2069                         t->task_done(t);
2070                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2071                         return;
2072                 }
2073                 break;
2074         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2075                 PM8001_IO_DBG(pm8001_ha,
2076                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2077                 ts->resp = SAS_TASK_COMPLETE;
2078                 ts->stat = SAS_OPEN_REJECT;
2079                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2080                 break;
2081         case IO_XFER_ERROR_NAK_RECEIVED:
2082                 PM8001_IO_DBG(pm8001_ha,
2083                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2084                 ts->resp = SAS_TASK_COMPLETE;
2085                 ts->stat = SAS_NAK_R_ERR;
2086                 break;
2087         case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2088                 PM8001_IO_DBG(pm8001_ha,
2089                         pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2090                 ts->resp = SAS_TASK_COMPLETE;
2091                 ts->stat = SAS_NAK_R_ERR;
2092                 break;
2093         case IO_XFER_ERROR_DMA:
2094                 PM8001_IO_DBG(pm8001_ha,
2095                         pm8001_printk("IO_XFER_ERROR_DMA\n"));
2096                 ts->resp = SAS_TASK_COMPLETE;
2097                 ts->stat = SAS_ABORTED_TASK;
2098                 break;
2099         case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2100                 PM8001_IO_DBG(pm8001_ha,
2101                         pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2102                 ts->resp = SAS_TASK_UNDELIVERED;
2103                 ts->stat = SAS_DEV_NO_RESPONSE;
2104                 break;
2105         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2106                 PM8001_IO_DBG(pm8001_ha,
2107                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2108                 ts->resp = SAS_TASK_COMPLETE;
2109                 ts->stat = SAS_DATA_UNDERRUN;
2110                 break;
2111         case IO_XFER_OPEN_RETRY_TIMEOUT:
2112                 PM8001_IO_DBG(pm8001_ha,
2113                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2114                 ts->resp = SAS_TASK_COMPLETE;
2115                 ts->stat = SAS_OPEN_TO;
2116                 break;
2117         case IO_PORT_IN_RESET:
2118                 PM8001_IO_DBG(pm8001_ha,
2119                         pm8001_printk("IO_PORT_IN_RESET\n"));
2120                 ts->resp = SAS_TASK_COMPLETE;
2121                 ts->stat = SAS_DEV_NO_RESPONSE;
2122                 break;
2123         case IO_DS_NON_OPERATIONAL:
2124                 PM8001_IO_DBG(pm8001_ha,
2125                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2126                 ts->resp = SAS_TASK_COMPLETE;
2127                 ts->stat = SAS_DEV_NO_RESPONSE;
2128                 if (!t->uldd_task) {
2129                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2130                                     IO_DS_NON_OPERATIONAL);
2131                         ts->resp = SAS_TASK_UNDELIVERED;
2132                         ts->stat = SAS_QUEUE_FULL;
2133                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2134                         mb();/*ditto*/
2135                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2136                         t->task_done(t);
2137                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2138                         return;
2139                 }
2140                 break;
2141         case IO_DS_IN_RECOVERY:
2142                 PM8001_IO_DBG(pm8001_ha,
2143                         pm8001_printk("  IO_DS_IN_RECOVERY\n"));
2144                 ts->resp = SAS_TASK_COMPLETE;
2145                 ts->stat = SAS_DEV_NO_RESPONSE;
2146                 break;
2147         case IO_DS_IN_ERROR:
2148                 PM8001_IO_DBG(pm8001_ha,
2149                         pm8001_printk("IO_DS_IN_ERROR\n"));
2150                 ts->resp = SAS_TASK_COMPLETE;
2151                 ts->stat = SAS_DEV_NO_RESPONSE;
2152                 if (!t->uldd_task) {
2153                         pm8001_handle_event(pm8001_ha, pm8001_dev,
2154                                     IO_DS_IN_ERROR);
2155                         ts->resp = SAS_TASK_UNDELIVERED;
2156                         ts->stat = SAS_QUEUE_FULL;
2157                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2158                         mb();/*ditto*/
2159                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2160                         t->task_done(t);
2161                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2162                         return;
2163                 }
2164                 break;
2165         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2166                 PM8001_IO_DBG(pm8001_ha,
2167                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2168                 ts->resp = SAS_TASK_COMPLETE;
2169                 ts->stat = SAS_OPEN_REJECT;
2170                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2171         default:
2172                 PM8001_IO_DBG(pm8001_ha,
2173                         pm8001_printk("Unknown status 0x%x\n", status));
2174                 /* not allowed case. Therefore, return failed status */
2175                 ts->resp = SAS_TASK_COMPLETE;
2176                 ts->stat = SAS_DEV_NO_RESPONSE;
2177                 break;
2178         }
2179         spin_lock_irqsave(&t->task_state_lock, flags);
2180         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2181         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2182         t->task_state_flags |= SAS_TASK_STATE_DONE;
2183         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2184                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2185                 PM8001_FAIL_DBG(pm8001_ha,
2186                         pm8001_printk("task 0x%p done with io_status 0x%x"
2187                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2188                         t, status, ts->resp, ts->stat));
2189                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2190         } else if (t->uldd_task) {
2191                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2192                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2193                 mb();/* ditto */
2194                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2195                 t->task_done(t);
2196                 spin_lock_irqsave(&pm8001_ha->lock, flags);
2197         } else if (!t->uldd_task) {
2198                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2199                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2200                 mb();/*ditto*/
2201                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2202                 t->task_done(t);
2203                 spin_lock_irqsave(&pm8001_ha->lock, flags);
2204         }
2205 }
2206
2207 /*See the comments for mpi_ssp_completion */
2208 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2209 {
2210         struct sas_task *t;
2211         unsigned long flags = 0;
2212         struct task_status_struct *ts;
2213         struct pm8001_ccb_info *ccb;
2214         struct pm8001_device *pm8001_dev;
2215         struct sata_event_resp *psataPayload =
2216                 (struct sata_event_resp *)(piomb + 4);
2217         u32 event = le32_to_cpu(psataPayload->event);
2218         u32 tag = le32_to_cpu(psataPayload->tag);
2219         u32 port_id = le32_to_cpu(psataPayload->port_id);
2220         u32 dev_id = le32_to_cpu(psataPayload->device_id);
2221
2222         ccb = &pm8001_ha->ccb_info[tag];
2223         t = ccb->task;
2224         pm8001_dev = ccb->device;
2225         if (event)
2226                 PM8001_FAIL_DBG(pm8001_ha,
2227                         pm8001_printk("sata IO status 0x%x\n", event));
2228         if (unlikely(!t || !t->lldd_task || !t->dev))
2229                 return;
2230         ts = &t->task_status;
2231         PM8001_IO_DBG(pm8001_ha,
2232                 pm8001_printk("port_id = %x,device_id = %x\n",
2233                 port_id, dev_id));
2234         switch (event) {
2235         case IO_OVERFLOW:
2236                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2237                 ts->resp = SAS_TASK_COMPLETE;
2238                 ts->stat = SAS_DATA_OVERRUN;
2239                 ts->residual = 0;
2240                 if (pm8001_dev)
2241                         pm8001_dev->running_req--;
2242                 break;
2243         case IO_XFER_ERROR_BREAK:
2244                 PM8001_IO_DBG(pm8001_ha,
2245                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2246                 ts->resp = SAS_TASK_COMPLETE;
2247                 ts->stat = SAS_INTERRUPTED;
2248                 break;
2249         case IO_XFER_ERROR_PHY_NOT_READY:
2250                 PM8001_IO_DBG(pm8001_ha,
2251                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2252                 ts->resp = SAS_TASK_COMPLETE;
2253                 ts->stat = SAS_OPEN_REJECT;
2254                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2255                 break;
2256         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2257                 PM8001_IO_DBG(pm8001_ha,
2258                         pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2259                         "_SUPPORTED\n"));
2260                 ts->resp = SAS_TASK_COMPLETE;
2261                 ts->stat = SAS_OPEN_REJECT;
2262                 ts->open_rej_reason = SAS_OREJ_EPROTO;
2263                 break;
2264         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2265                 PM8001_IO_DBG(pm8001_ha,
2266                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2267                 ts->resp = SAS_TASK_COMPLETE;
2268                 ts->stat = SAS_OPEN_REJECT;
2269                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2270                 break;
2271         case IO_OPEN_CNX_ERROR_BREAK:
2272                 PM8001_IO_DBG(pm8001_ha,
2273                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2274                 ts->resp = SAS_TASK_COMPLETE;
2275                 ts->stat = SAS_OPEN_REJECT;
2276                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2277                 break;
2278         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2279                 PM8001_IO_DBG(pm8001_ha,
2280                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2281                 ts->resp = SAS_TASK_UNDELIVERED;
2282                 ts->stat = SAS_DEV_NO_RESPONSE;
2283                 if (!t->uldd_task) {
2284                         pm8001_handle_event(pm8001_ha,
2285                                 pm8001_dev,
2286                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2287                         ts->resp = SAS_TASK_COMPLETE;
2288                         ts->stat = SAS_QUEUE_FULL;
2289                         pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2290                         mb();/*ditto*/
2291                         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2292                         t->task_done(t);
2293                         spin_lock_irqsave(&pm8001_ha->lock, flags);
2294                         return;
2295                 }
2296                 break;
2297         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2298                 PM8001_IO_DBG(pm8001_ha,
2299                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2300                 ts->resp = SAS_TASK_UNDELIVERED;
2301                 ts->stat = SAS_OPEN_REJECT;
2302                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2303                 break;
2304         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2305                 PM8001_IO_DBG(pm8001_ha,
2306                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2307                         "NOT_SUPPORTED\n"));
2308                 ts->resp = SAS_TASK_COMPLETE;
2309                 ts->stat = SAS_OPEN_REJECT;
2310                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2311                 break;
2312         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2313                 PM8001_IO_DBG(pm8001_ha,
2314                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2315                 ts->resp = SAS_TASK_COMPLETE;
2316                 ts->stat = SAS_OPEN_REJECT;
2317                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2318                 break;
2319         case IO_XFER_ERROR_NAK_RECEIVED:
2320                 PM8001_IO_DBG(pm8001_ha,
2321                         pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2322                 ts->resp = SAS_TASK_COMPLETE;
2323                 ts->stat = SAS_NAK_R_ERR;
2324                 break;
2325         case IO_XFER_ERROR_PEER_ABORTED:
2326                 PM8001_IO_DBG(pm8001_ha,
2327                         pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2328                 ts->resp = SAS_TASK_COMPLETE;
2329                 ts->stat = SAS_NAK_R_ERR;
2330                 break;
2331         case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2332                 PM8001_IO_DBG(pm8001_ha,
2333                         pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2334                 ts->resp = SAS_TASK_COMPLETE;
2335                 ts->stat = SAS_DATA_UNDERRUN;
2336                 break;
2337         case IO_XFER_OPEN_RETRY_TIMEOUT:
2338                 PM8001_IO_DBG(pm8001_ha,
2339                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2340                 ts->resp = SAS_TASK_COMPLETE;
2341                 ts->stat = SAS_OPEN_TO;
2342                 break;
2343         case IO_XFER_ERROR_UNEXPECTED_PHASE:
2344                 PM8001_IO_DBG(pm8001_ha,
2345                         pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2346                 ts->resp = SAS_TASK_COMPLETE;
2347                 ts->stat = SAS_OPEN_TO;
2348                 break;
2349         case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2350                 PM8001_IO_DBG(pm8001_ha,
2351                         pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2352                 ts->resp = SAS_TASK_COMPLETE;
2353                 ts->stat = SAS_OPEN_TO;
2354                 break;
2355         case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2356                 PM8001_IO_DBG(pm8001_ha,
2357                        pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2358                 ts->resp = SAS_TASK_COMPLETE;
2359                 ts->stat = SAS_OPEN_TO;
2360                 break;
2361         case IO_XFER_ERROR_OFFSET_MISMATCH:
2362                 PM8001_IO_DBG(pm8001_ha,
2363                         pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2364                 ts->resp = SAS_TASK_COMPLETE;
2365                 ts->stat = SAS_OPEN_TO;
2366                 break;
2367         case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2368                 PM8001_IO_DBG(pm8001_ha,
2369                         pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2370                 ts->resp = SAS_TASK_COMPLETE;
2371                 ts->stat = SAS_OPEN_TO;
2372                 break;
2373         case IO_XFER_CMD_FRAME_ISSUED:
2374                 PM8001_IO_DBG(pm8001_ha,
2375                         pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2376                 break;
2377         case IO_XFER_PIO_SETUP_ERROR:
2378                 PM8001_IO_DBG(pm8001_ha,
2379                         pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2380                 ts->resp = SAS_TASK_COMPLETE;
2381                 ts->stat = SAS_OPEN_TO;
2382                 break;
2383         default:
2384                 PM8001_IO_DBG(pm8001_ha,
2385                         pm8001_printk("Unknown status 0x%x\n", event));
2386                 /* not allowed case. Therefore, return failed status */
2387                 ts->resp = SAS_TASK_COMPLETE;
2388                 ts->stat = SAS_OPEN_TO;
2389                 break;
2390         }
2391         spin_lock_irqsave(&t->task_state_lock, flags);
2392         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2393         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2394         t->task_state_flags |= SAS_TASK_STATE_DONE;
2395         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2396                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2397                 PM8001_FAIL_DBG(pm8001_ha,
2398                         pm8001_printk("task 0x%p done with io_status 0x%x"
2399                         " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2400                         t, event, ts->resp, ts->stat));
2401                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2402         } else if (t->uldd_task) {
2403                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2404                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2405                 mb();/* ditto */
2406                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2407                 t->task_done(t);
2408                 spin_lock_irqsave(&pm8001_ha->lock, flags);
2409         } else if (!t->uldd_task) {
2410                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2411                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2412                 mb();/*ditto*/
2413                 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
2414                 t->task_done(t);
2415                 spin_lock_irqsave(&pm8001_ha->lock, flags);
2416         }
2417 }
2418
2419 /*See the comments for mpi_ssp_completion */
2420 static void
2421 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2422 {
2423         u32 param;
2424         struct sas_task *t;
2425         struct pm8001_ccb_info *ccb;
2426         unsigned long flags;
2427         u32 status;
2428         u32 tag;
2429         struct smp_completion_resp *psmpPayload;
2430         struct task_status_struct *ts;
2431         struct pm8001_device *pm8001_dev;
2432
2433         psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2434         status = le32_to_cpu(psmpPayload->status);
2435         tag = le32_to_cpu(psmpPayload->tag);
2436
2437         ccb = &pm8001_ha->ccb_info[tag];
2438         param = le32_to_cpu(psmpPayload->param);
2439         t = ccb->task;
2440         ts = &t->task_status;
2441         pm8001_dev = ccb->device;
2442         if (status)
2443                 PM8001_FAIL_DBG(pm8001_ha,
2444                         pm8001_printk("smp IO status 0x%x\n", status));
2445         if (unlikely(!t || !t->lldd_task || !t->dev))
2446                 return;
2447
2448         switch (status) {
2449         case IO_SUCCESS:
2450                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2451                 ts->resp = SAS_TASK_COMPLETE;
2452                 ts->stat = SAM_GOOD;
2453         if (pm8001_dev)
2454                         pm8001_dev->running_req--;
2455                 break;
2456         case IO_ABORTED:
2457                 PM8001_IO_DBG(pm8001_ha,
2458                         pm8001_printk("IO_ABORTED IOMB\n"));
2459                 ts->resp = SAS_TASK_COMPLETE;
2460                 ts->stat = SAS_ABORTED_TASK;
2461                 if (pm8001_dev)
2462                         pm8001_dev->running_req--;
2463                 break;
2464         case IO_OVERFLOW:
2465                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2466                 ts->resp = SAS_TASK_COMPLETE;
2467                 ts->stat = SAS_DATA_OVERRUN;
2468                 ts->residual = 0;
2469                 if (pm8001_dev)
2470                         pm8001_dev->running_req--;
2471                 break;
2472         case IO_NO_DEVICE:
2473                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2474                 ts->resp = SAS_TASK_COMPLETE;
2475                 ts->stat = SAS_PHY_DOWN;
2476                 break;
2477         case IO_ERROR_HW_TIMEOUT:
2478                 PM8001_IO_DBG(pm8001_ha,
2479                         pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2480                 ts->resp = SAS_TASK_COMPLETE;
2481                 ts->stat = SAM_BUSY;
2482                 break;
2483         case IO_XFER_ERROR_BREAK:
2484                 PM8001_IO_DBG(pm8001_ha,
2485                         pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2486                 ts->resp = SAS_TASK_COMPLETE;
2487                 ts->stat = SAM_BUSY;
2488                 break;
2489         case IO_XFER_ERROR_PHY_NOT_READY:
2490                 PM8001_IO_DBG(pm8001_ha,
2491                         pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2492                 ts->resp = SAS_TASK_COMPLETE;
2493                 ts->stat = SAM_BUSY;
2494                 break;
2495         case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2496                 PM8001_IO_DBG(pm8001_ha,
2497                 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2498                 ts->resp = SAS_TASK_COMPLETE;
2499                 ts->stat = SAS_OPEN_REJECT;
2500                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2501                 break;
2502         case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2503                 PM8001_IO_DBG(pm8001_ha,
2504                         pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2505                 ts->resp = SAS_TASK_COMPLETE;
2506                 ts->stat = SAS_OPEN_REJECT;
2507                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2508                 break;
2509         case IO_OPEN_CNX_ERROR_BREAK:
2510                 PM8001_IO_DBG(pm8001_ha,
2511                         pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2512                 ts->resp = SAS_TASK_COMPLETE;
2513                 ts->stat = SAS_OPEN_REJECT;
2514                 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2515                 break;
2516         case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2517                 PM8001_IO_DBG(pm8001_ha,
2518                         pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2519                 ts->resp = SAS_TASK_COMPLETE;
2520                 ts->stat = SAS_OPEN_REJECT;
2521                 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2522                 pm8001_handle_event(pm8001_ha,
2523                                 pm8001_dev,
2524                                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2525                 break;
2526         case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2527                 PM8001_IO_DBG(pm8001_ha,
2528                         pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2529                 ts->resp = SAS_TASK_COMPLETE;
2530                 ts->stat = SAS_OPEN_REJECT;
2531                 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2532                 break;
2533         case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2534                 PM8001_IO_DBG(pm8001_ha,
2535                         pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2536                         "NOT_SUPPORTED\n"));
2537                 ts->resp = SAS_TASK_COMPLETE;
2538                 ts->stat = SAS_OPEN_REJECT;
2539                 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2540                 break;
2541         case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2542                 PM8001_IO_DBG(pm8001_ha,
2543                        pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2544                 ts->resp = SAS_TASK_COMPLETE;
2545                 ts->stat = SAS_OPEN_REJECT;
2546                 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2547                 break;
2548         case IO_XFER_ERROR_RX_FRAME:
2549                 PM8001_IO_DBG(pm8001_ha,
2550                         pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2551                 ts->resp = SAS_TASK_COMPLETE;
2552                 ts->stat = SAS_DEV_NO_RESPONSE;
2553                 break;
2554         case IO_XFER_OPEN_RETRY_TIMEOUT:
2555                 PM8001_IO_DBG(pm8001_ha,
2556                         pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2557                 ts->resp = SAS_TASK_COMPLETE;
2558                 ts->stat = SAS_OPEN_REJECT;
2559                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2560                 break;
2561         case IO_ERROR_INTERNAL_SMP_RESOURCE:
2562                 PM8001_IO_DBG(pm8001_ha,
2563                         pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2564                 ts->resp = SAS_TASK_COMPLETE;
2565                 ts->stat = SAS_QUEUE_FULL;
2566                 break;
2567         case IO_PORT_IN_RESET:
2568                 PM8001_IO_DBG(pm8001_ha,
2569                         pm8001_printk("IO_PORT_IN_RESET\n"));
2570                 ts->resp = SAS_TASK_COMPLETE;
2571                 ts->stat = SAS_OPEN_REJECT;
2572                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2573                 break;
2574         case IO_DS_NON_OPERATIONAL:
2575                 PM8001_IO_DBG(pm8001_ha,
2576                         pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2577                 ts->resp = SAS_TASK_COMPLETE;
2578                 ts->stat = SAS_DEV_NO_RESPONSE;
2579                 break;
2580         case IO_DS_IN_RECOVERY:
2581                 PM8001_IO_DBG(pm8001_ha,
2582                         pm8001_printk("IO_DS_IN_RECOVERY\n"));
2583                 ts->resp = SAS_TASK_COMPLETE;
2584                 ts->stat = SAS_OPEN_REJECT;
2585                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2586                 break;
2587         case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2588                 PM8001_IO_DBG(pm8001_ha,
2589                         pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2590                 ts->resp = SAS_TASK_COMPLETE;
2591                 ts->stat = SAS_OPEN_REJECT;
2592                 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2593                 break;
2594         default:
2595                 PM8001_IO_DBG(pm8001_ha,
2596                         pm8001_printk("Unknown status 0x%x\n", status));
2597                 ts->resp = SAS_TASK_COMPLETE;
2598                 ts->stat = SAS_DEV_NO_RESPONSE;
2599                 /* not allowed case. Therefore, return failed status */
2600                 break;
2601         }
2602         spin_lock_irqsave(&t->task_state_lock, flags);
2603         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2604         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2605         t->task_state_flags |= SAS_TASK_STATE_DONE;
2606         if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2607                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2608                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2609                         " io_status 0x%x resp 0x%x "
2610                         "stat 0x%x but aborted by upper layer!\n",
2611                         t, status, ts->resp, ts->stat));
2612                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2613         } else {
2614                 spin_unlock_irqrestore(&t->task_state_lock, flags);
2615                 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2616                 mb();/* in order to force CPU ordering */
2617                 t->task_done(t);
2618         }
2619 }
2620
2621 static void
2622 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2623 {
2624         struct set_dev_state_resp *pPayload =
2625                 (struct set_dev_state_resp *)(piomb + 4);
2626         u32 tag = le32_to_cpu(pPayload->tag);
2627         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2628         struct pm8001_device *pm8001_dev = ccb->device;
2629         u32 status = le32_to_cpu(pPayload->status);
2630         u32 device_id = le32_to_cpu(pPayload->device_id);
2631         u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2632         u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2633         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2634                 "from 0x%x to 0x%x status = 0x%x!\n",
2635                 device_id, pds, nds, status));
2636         complete(pm8001_dev->setds_completion);
2637         ccb->task = NULL;
2638         ccb->ccb_tag = 0xFFFFFFFF;
2639         pm8001_ccb_free(pm8001_ha, tag);
2640 }
2641
2642 static void
2643 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2644 {
2645         struct get_nvm_data_resp *pPayload =
2646                 (struct get_nvm_data_resp *)(piomb + 4);
2647         u32 tag = le32_to_cpu(pPayload->tag);
2648         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2649         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2650         complete(pm8001_ha->nvmd_completion);
2651         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2652         if ((dlen_status & NVMD_STAT) != 0) {
2653                 PM8001_FAIL_DBG(pm8001_ha,
2654                         pm8001_printk("Set nvm data error!\n"));
2655                 return;
2656         }
2657         ccb->task = NULL;
2658         ccb->ccb_tag = 0xFFFFFFFF;
2659         pm8001_ccb_free(pm8001_ha, tag);
2660 }
2661
2662 static void
2663 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2664 {
2665         struct fw_control_ex    *fw_control_context;
2666         struct get_nvm_data_resp *pPayload =
2667                 (struct get_nvm_data_resp *)(piomb + 4);
2668         u32 tag = le32_to_cpu(pPayload->tag);
2669         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2670         u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2671         u32 ir_tds_bn_dps_das_nvm =
2672                 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2673         void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2674         fw_control_context = ccb->fw_control_context;
2675
2676         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2677         if ((dlen_status & NVMD_STAT) != 0) {
2678                 PM8001_FAIL_DBG(pm8001_ha,
2679                         pm8001_printk("Get nvm data error!\n"));
2680                 complete(pm8001_ha->nvmd_completion);
2681                 return;
2682         }
2683
2684         if (ir_tds_bn_dps_das_nvm & IPMode) {
2685                 /* indirect mode - IR bit set */
2686                 PM8001_MSG_DBG(pm8001_ha,
2687                         pm8001_printk("Get NVMD success, IR=1\n"));
2688                 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2689                         if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2690                                 memcpy(pm8001_ha->sas_addr,
2691                                       ((u8 *)virt_addr + 4),
2692                                        SAS_ADDR_SIZE);
2693                                 PM8001_MSG_DBG(pm8001_ha,
2694                                         pm8001_printk("Get SAS address"
2695                                         " from VPD successfully!\n"));
2696                         }
2697                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2698                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2699                         ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2700                                 ;
2701                 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2702                         || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2703                         ;
2704                 } else {
2705                         /* Should not be happened*/
2706                         PM8001_MSG_DBG(pm8001_ha,
2707                                 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2708                                 ir_tds_bn_dps_das_nvm));
2709                 }
2710         } else /* direct mode */{
2711                 PM8001_MSG_DBG(pm8001_ha,
2712                         pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2713                         (dlen_status & NVMD_LEN) >> 24));
2714         }
2715         memcpy(fw_control_context->usrAddr,
2716                 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2717                 fw_control_context->len);
2718         complete(pm8001_ha->nvmd_completion);
2719         ccb->task = NULL;
2720         ccb->ccb_tag = 0xFFFFFFFF;
2721         pm8001_ccb_free(pm8001_ha, tag);
2722 }
2723
2724 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2725 {
2726         struct local_phy_ctl_resp *pPayload =
2727                 (struct local_phy_ctl_resp *)(piomb + 4);
2728         u32 status = le32_to_cpu(pPayload->status);
2729         u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2730         u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2731         if (status != 0) {
2732                 PM8001_MSG_DBG(pm8001_ha,
2733                         pm8001_printk("%x phy execute %x phy op failed! \n",
2734                         phy_id, phy_op));
2735         } else
2736                 PM8001_MSG_DBG(pm8001_ha,
2737                         pm8001_printk("%x phy execute %x phy op success! \n",
2738                         phy_id, phy_op));
2739         return 0;
2740 }
2741
2742 /**
2743  * pm8001_bytes_dmaed - one of the interface function communication with libsas
2744  * @pm8001_ha: our hba card information
2745  * @i: which phy that received the event.
2746  *
2747  * when HBA driver received the identify done event or initiate FIS received
2748  * event(for SATA), it will invoke this function to notify the sas layer that
2749  * the sas toplogy has formed, please discover the the whole sas domain,
2750  * while receive a broadcast(change) primitive just tell the sas
2751  * layer to discover the changed domain rather than the whole domain.
2752  */
2753 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2754 {
2755         struct pm8001_phy *phy = &pm8001_ha->phy[i];
2756         struct asd_sas_phy *sas_phy = &phy->sas_phy;
2757         struct sas_ha_struct *sas_ha;
2758         if (!phy->phy_attached)
2759                 return;
2760
2761         sas_ha = pm8001_ha->sas;
2762         if (sas_phy->phy) {
2763                 struct sas_phy *sphy = sas_phy->phy;
2764                 sphy->negotiated_linkrate = sas_phy->linkrate;
2765                 sphy->minimum_linkrate = phy->minimum_linkrate;
2766                 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2767                 sphy->maximum_linkrate = phy->maximum_linkrate;
2768                 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2769         }
2770
2771         if (phy->phy_type & PORT_TYPE_SAS) {
2772                 struct sas_identify_frame *id;
2773                 id = (struct sas_identify_frame *)phy->frame_rcvd;
2774                 id->dev_type = phy->identify.device_type;
2775                 id->initiator_bits = SAS_PROTOCOL_ALL;
2776                 id->target_bits = phy->identify.target_port_protocols;
2777         } else if (phy->phy_type & PORT_TYPE_SATA) {
2778                 /*Nothing*/
2779         }
2780         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2781
2782         sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2783         pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2784 }
2785
2786 /* Get the link rate speed  */
2787 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2788 {
2789         struct sas_phy *sas_phy = phy->sas_phy.phy;
2790
2791         switch (link_rate) {
2792         case PHY_SPEED_60:
2793                 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2794                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2795                 break;
2796         case PHY_SPEED_30:
2797                 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
2798                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
2799                 break;
2800         case PHY_SPEED_15:
2801                 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
2802                 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
2803                 break;
2804         }
2805         sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
2806         sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
2807         sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2808         sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
2809         sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
2810 }
2811
2812 /**
2813  * asd_get_attached_sas_addr -- extract/generate attached SAS address
2814  * @phy: pointer to asd_phy
2815  * @sas_addr: pointer to buffer where the SAS address is to be written
2816  *
2817  * This function extracts the SAS address from an IDENTIFY frame
2818  * received.  If OOB is SATA, then a SAS address is generated from the
2819  * HA tables.
2820  *
2821  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
2822  * buffer.
2823  */
2824 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
2825         u8 *sas_addr)
2826 {
2827         if (phy->sas_phy.frame_rcvd[0] == 0x34
2828                 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
2829                 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
2830                 /* FIS device-to-host */
2831                 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
2832                 addr += phy->sas_phy.id;
2833                 *(__be64 *)sas_addr = cpu_to_be64(addr);
2834         } else {
2835                 struct sas_identify_frame *idframe =
2836                         (void *) phy->sas_phy.frame_rcvd;
2837                 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
2838         }
2839 }
2840
2841 /**
2842  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2843  * @pm8001_ha: our hba card information
2844  * @Qnum: the outbound queue message number.
2845  * @SEA: source of event to ack
2846  * @port_id: port id.
2847  * @phyId: phy id.
2848  * @param0: parameter 0.
2849  * @param1: parameter 1.
2850  */
2851 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2852         u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2853 {
2854         struct hw_event_ack_req  payload;
2855         u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2856
2857         struct inbound_queue_table *circularQ;
2858
2859         memset((u8 *)&payload, 0, sizeof(payload));
2860         circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2861         payload.tag = 1;
2862         payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2863                 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
2864         payload.param0 = cpu_to_le32(param0);
2865         payload.param1 = cpu_to_le32(param1);
2866         mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
2867 }
2868
2869 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2870         u32 phyId, u32 phy_op);
2871
2872 /**
2873  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2874  * @pm8001_ha: our hba card information
2875  * @piomb: IO message buffer
2876  */
2877 static void
2878 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2879 {
2880         struct hw_event_resp *pPayload =
2881                 (struct hw_event_resp *)(piomb + 4);
2882         u32 lr_evt_status_phyid_portid =
2883                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2884         u8 link_rate =
2885                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2886         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2887         u8 phy_id =
2888                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2889         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2890         u8 portstate = (u8)(npip_portstate & 0x0000000F);
2891         struct pm8001_port *port = &pm8001_ha->port[port_id];
2892         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2893         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2894         unsigned long flags;
2895         u8 deviceType = pPayload->sas_identify.dev_type;
2896         port->port_state =  portstate;
2897         PM8001_MSG_DBG(pm8001_ha,
2898                 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
2899                 port_id, phy_id));
2900
2901         switch (deviceType) {
2902         case SAS_PHY_UNUSED:
2903                 PM8001_MSG_DBG(pm8001_ha,
2904                         pm8001_printk("device type no device.\n"));
2905                 break;
2906         case SAS_END_DEVICE:
2907                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2908                 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
2909                         PHY_NOTIFY_ENABLE_SPINUP);
2910                 port->port_attached = 1;
2911                 get_lrate_mode(phy, link_rate);
2912                 break;
2913         case SAS_EDGE_EXPANDER_DEVICE:
2914                 PM8001_MSG_DBG(pm8001_ha,
2915                         pm8001_printk("expander device.\n"));
2916                 port->port_attached = 1;
2917                 get_lrate_mode(phy, link_rate);
2918                 break;
2919         case SAS_FANOUT_EXPANDER_DEVICE:
2920                 PM8001_MSG_DBG(pm8001_ha,
2921                         pm8001_printk("fanout expander device.\n"));
2922                 port->port_attached = 1;
2923                 get_lrate_mode(phy, link_rate);
2924                 break;
2925         default:
2926                 PM8001_MSG_DBG(pm8001_ha,
2927                         pm8001_printk("unkown device type(%x)\n", deviceType));
2928                 break;
2929         }
2930         phy->phy_type |= PORT_TYPE_SAS;
2931         phy->identify.device_type = deviceType;
2932         phy->phy_attached = 1;
2933         if (phy->identify.device_type == SAS_END_DEV)
2934                 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2935         else if (phy->identify.device_type != NO_DEVICE)
2936                 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2937         phy->sas_phy.oob_mode = SAS_OOB_MODE;
2938         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2939         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2940         memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2941                 sizeof(struct sas_identify_frame)-4);
2942         phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2943         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2944         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2945         if (pm8001_ha->flags == PM8001F_RUN_TIME)
2946                 mdelay(200);/*delay a moment to wait disk to spinup*/
2947         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2948 }
2949
2950 /**
2951  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2952  * @pm8001_ha: our hba card information
2953  * @piomb: IO message buffer
2954  */
2955 static void
2956 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2957 {
2958         struct hw_event_resp *pPayload =
2959                 (struct hw_event_resp *)(piomb + 4);
2960         u32 lr_evt_status_phyid_portid =
2961                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
2962         u8 link_rate =
2963                 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
2964         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
2965         u8 phy_id =
2966                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
2967         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
2968         u8 portstate = (u8)(npip_portstate & 0x0000000F);
2969         struct pm8001_port *port = &pm8001_ha->port[port_id];
2970         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2971         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2972         unsigned long flags;
2973         PM8001_MSG_DBG(pm8001_ha,
2974                 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
2975                 " phy id = %d\n", port_id, phy_id));
2976         port->port_state =  portstate;
2977         port->port_attached = 1;
2978         get_lrate_mode(phy, link_rate);
2979         phy->phy_type |= PORT_TYPE_SATA;
2980         phy->phy_attached = 1;
2981         phy->sas_phy.oob_mode = SATA_OOB_MODE;
2982         sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2983         spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2984         memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2985                 sizeof(struct dev_to_host_fis));
2986         phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2987         phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2988         phy->identify.device_type = SATA_DEV;
2989         pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2990         spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2991         pm8001_bytes_dmaed(pm8001_ha, phy_id);
2992 }
2993
2994 /**
2995  * hw_event_phy_down -we should notify the libsas the phy is down.
2996  * @pm8001_ha: our hba card information
2997  * @piomb: IO message buffer
2998  */
2999 static void
3000 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3001 {
3002         struct hw_event_resp *pPayload =
3003                 (struct hw_event_resp *)(piomb + 4);
3004         u32 lr_evt_status_phyid_portid =
3005                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3006         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3007         u8 phy_id =
3008                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3009         u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3010         u8 portstate = (u8)(npip_portstate & 0x0000000F);
3011         struct pm8001_port *port = &pm8001_ha->port[port_id];
3012         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3013         port->port_state =  portstate;
3014         phy->phy_type = 0;
3015         phy->identify.device_type = 0;
3016         phy->phy_attached = 0;
3017         memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3018         switch (portstate) {
3019         case PORT_VALID:
3020                 break;
3021         case PORT_INVALID:
3022                 PM8001_MSG_DBG(pm8001_ha,
3023                         pm8001_printk(" PortInvalid portID %d \n", port_id));
3024                 PM8001_MSG_DBG(pm8001_ha,
3025                         pm8001_printk(" Last phy Down and port invalid\n"));
3026                 port->port_attached = 0;
3027                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3028                         port_id, phy_id, 0, 0);
3029                 break;
3030         case PORT_IN_RESET:
3031                 PM8001_MSG_DBG(pm8001_ha,
3032                         pm8001_printk(" Port In Reset portID %d \n", port_id));
3033                 break;
3034         case PORT_NOT_ESTABLISHED:
3035                 PM8001_MSG_DBG(pm8001_ha,
3036                         pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3037                 port->port_attached = 0;
3038                 break;
3039         case PORT_LOSTCOMM:
3040                 PM8001_MSG_DBG(pm8001_ha,
3041                         pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3042                 PM8001_MSG_DBG(pm8001_ha,
3043                         pm8001_printk(" Last phy Down and port invalid\n"));
3044                 port->port_attached = 0;
3045                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3046                         port_id, phy_id, 0, 0);
3047                 break;
3048         default:
3049                 port->port_attached = 0;
3050                 PM8001_MSG_DBG(pm8001_ha,
3051                         pm8001_printk(" phy Down and(default) = %x\n",
3052                         portstate));
3053                 break;
3054
3055         }
3056 }
3057
3058 /**
3059  * mpi_reg_resp -process register device ID response.
3060  * @pm8001_ha: our hba card information
3061  * @piomb: IO message buffer
3062  *
3063  * when sas layer find a device it will notify LLDD, then the driver register
3064  * the domain device to FW, this event is the return device ID which the FW
3065  * has assigned, from now,inter-communication with FW is no longer using the
3066  * SAS address, use device ID which FW assigned.
3067  */
3068 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3069 {
3070         u32 status;
3071         u32 device_id;
3072         u32 htag;
3073         struct pm8001_ccb_info *ccb;
3074         struct pm8001_device *pm8001_dev;
3075         struct dev_reg_resp *registerRespPayload =
3076                 (struct dev_reg_resp *)(piomb + 4);
3077
3078         htag = le32_to_cpu(registerRespPayload->tag);
3079         ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3080         pm8001_dev = ccb->device;
3081         status = le32_to_cpu(registerRespPayload->status);
3082         device_id = le32_to_cpu(registerRespPayload->device_id);
3083         PM8001_MSG_DBG(pm8001_ha,
3084                 pm8001_printk(" register device is status = %d\n", status));
3085         switch (status) {
3086         case DEVREG_SUCCESS:
3087                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3088                 pm8001_dev->device_id = device_id;
3089                 break;
3090         case DEVREG_FAILURE_OUT_OF_RESOURCE:
3091                 PM8001_MSG_DBG(pm8001_ha,
3092                         pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3093                 break;
3094         case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3095                 PM8001_MSG_DBG(pm8001_ha,
3096                    pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3097                 break;
3098         case DEVREG_FAILURE_INVALID_PHY_ID:
3099                 PM8001_MSG_DBG(pm8001_ha,
3100                         pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3101                 break;
3102         case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3103                 PM8001_MSG_DBG(pm8001_ha,
3104                    pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3105                 break;
3106         case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3107                 PM8001_MSG_DBG(pm8001_ha,
3108                         pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3109                 break;
3110         case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3111                 PM8001_MSG_DBG(pm8001_ha,
3112                         pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3113                 break;
3114         case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3115                 PM8001_MSG_DBG(pm8001_ha,
3116                        pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3117                 break;
3118         default:
3119                 PM8001_MSG_DBG(pm8001_ha,
3120                  pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3121                 break;
3122         }
3123         complete(pm8001_dev->dcompletion);
3124         ccb->task = NULL;
3125         ccb->ccb_tag = 0xFFFFFFFF;
3126         pm8001_ccb_free(pm8001_ha, htag);
3127         return 0;
3128 }
3129
3130 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3131 {
3132         u32 status;
3133         u32 device_id;
3134         struct dev_reg_resp *registerRespPayload =
3135                 (struct dev_reg_resp *)(piomb + 4);
3136
3137         status = le32_to_cpu(registerRespPayload->status);
3138         device_id = le32_to_cpu(registerRespPayload->device_id);
3139         if (status != 0)
3140                 PM8001_MSG_DBG(pm8001_ha,
3141                         pm8001_printk(" deregister device failed ,status = %x"
3142                         ", device_id = %x\n", status, device_id));
3143         return 0;
3144 }
3145
3146 static int
3147 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3148 {
3149         u32 status;
3150         struct fw_control_ex    fw_control_context;
3151         struct fw_flash_Update_resp *ppayload =
3152                 (struct fw_flash_Update_resp *)(piomb + 4);
3153         u32 tag = le32_to_cpu(ppayload->tag);
3154         struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3155         status = le32_to_cpu(ppayload->status);
3156         memcpy(&fw_control_context,
3157                 ccb->fw_control_context,
3158                 sizeof(fw_control_context));
3159         switch (status) {
3160         case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3161                 PM8001_MSG_DBG(pm8001_ha,
3162                 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3163                 break;
3164         case FLASH_UPDATE_IN_PROGRESS:
3165                 PM8001_MSG_DBG(pm8001_ha,
3166                         pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3167                 break;
3168         case FLASH_UPDATE_HDR_ERR:
3169                 PM8001_MSG_DBG(pm8001_ha,
3170                         pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3171                 break;
3172         case FLASH_UPDATE_OFFSET_ERR:
3173                 PM8001_MSG_DBG(pm8001_ha,
3174                         pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3175                 break;
3176         case FLASH_UPDATE_CRC_ERR:
3177                 PM8001_MSG_DBG(pm8001_ha,
3178                         pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3179                 break;
3180         case FLASH_UPDATE_LENGTH_ERR:
3181                 PM8001_MSG_DBG(pm8001_ha,
3182                         pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3183                 break;
3184         case FLASH_UPDATE_HW_ERR:
3185                 PM8001_MSG_DBG(pm8001_ha,
3186                         pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3187                 break;
3188         case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3189                 PM8001_MSG_DBG(pm8001_ha,
3190                         pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3191                 break;
3192         case FLASH_UPDATE_DISABLED:
3193                 PM8001_MSG_DBG(pm8001_ha,
3194                         pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3195                 break;
3196         default:
3197                 PM8001_MSG_DBG(pm8001_ha,
3198                         pm8001_printk("No matched status = %d\n", status));
3199                 break;
3200         }
3201         ccb->fw_control_context->fw_control->retcode = status;
3202         pci_free_consistent(pm8001_ha->pdev,
3203                         fw_control_context.len,
3204                         fw_control_context.virtAddr,
3205                         fw_control_context.phys_addr);
3206         complete(pm8001_ha->nvmd_completion);
3207         ccb->task = NULL;
3208         ccb->ccb_tag = 0xFFFFFFFF;
3209         pm8001_ccb_free(pm8001_ha, tag);
3210         return 0;
3211 }
3212
3213 static int
3214 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3215 {
3216         u32 status;
3217         int i;
3218         struct general_event_resp *pPayload =
3219                 (struct general_event_resp *)(piomb + 4);
3220         status = le32_to_cpu(pPayload->status);
3221         PM8001_MSG_DBG(pm8001_ha,
3222                 pm8001_printk(" status = 0x%x\n", status));
3223         for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3224                 PM8001_MSG_DBG(pm8001_ha,
3225                         pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
3226                         pPayload->inb_IOMB_payload[i]));
3227         return 0;
3228 }
3229
3230 static int
3231 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3232 {
3233         struct sas_task *t;
3234         struct pm8001_ccb_info *ccb;
3235         unsigned long flags;
3236         u32 status ;
3237         u32 tag, scp;
3238         struct task_status_struct *ts;
3239
3240         struct task_abort_resp *pPayload =
3241                 (struct task_abort_resp *)(piomb + 4);
3242         ccb = &pm8001_ha->ccb_info[pPayload->tag];
3243         t = ccb->task;
3244
3245
3246         status = le32_to_cpu(pPayload->status);
3247         tag = le32_to_cpu(pPayload->tag);
3248         scp = le32_to_cpu(pPayload->scp);
3249         PM8001_IO_DBG(pm8001_ha,
3250                 pm8001_printk(" status = 0x%x\n", status));
3251         if (t == NULL)
3252                 return -1;
3253         ts = &t->task_status;
3254         if (status != 0)
3255                 PM8001_FAIL_DBG(pm8001_ha,
3256                         pm8001_printk("task abort failed status 0x%x ,"
3257                         "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3258         switch (status) {
3259         case IO_SUCCESS:
3260                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3261                 ts->resp = SAS_TASK_COMPLETE;
3262                 ts->stat = SAM_GOOD;
3263                 break;
3264         case IO_NOT_VALID:
3265                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3266                 ts->resp = TMF_RESP_FUNC_FAILED;
3267                 break;
3268         }
3269         spin_lock_irqsave(&t->task_state_lock, flags);
3270         t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3271         t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3272         t->task_state_flags |= SAS_TASK_STATE_DONE;
3273         spin_unlock_irqrestore(&t->task_state_lock, flags);
3274         pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3275         mb();
3276         t->task_done(t);
3277         return 0;
3278 }
3279
3280 /**
3281  * mpi_hw_event -The hw event has come.
3282  * @pm8001_ha: our hba card information
3283  * @piomb: IO message buffer
3284  */
3285 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3286 {
3287         unsigned long flags;
3288         struct hw_event_resp *pPayload =
3289                 (struct hw_event_resp *)(piomb + 4);
3290         u32 lr_evt_status_phyid_portid =
3291                 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3292         u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3293         u8 phy_id =
3294                 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3295         u16 eventType =
3296                 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3297         u8 status =
3298                 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3299         struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3300         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3301         struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3302         PM8001_MSG_DBG(pm8001_ha,
3303                 pm8001_printk("outbound queue HW event & event type : "));
3304         switch (eventType) {
3305         case HW_EVENT_PHY_START_STATUS:
3306                 PM8001_MSG_DBG(pm8001_ha,
3307                 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3308                         " status = %x\n", status));
3309                 if (status == 0) {
3310                         phy->phy_state = 1;
3311                         if (pm8001_ha->flags == PM8001F_RUN_TIME)
3312                                 complete(phy->enable_completion);
3313                 }
3314                 break;
3315         case HW_EVENT_SAS_PHY_UP:
3316                 PM8001_MSG_DBG(pm8001_ha,
3317                         pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
3318                 hw_event_sas_phy_up(pm8001_ha, piomb);
3319                 break;
3320         case HW_EVENT_SATA_PHY_UP:
3321                 PM8001_MSG_DBG(pm8001_ha,
3322                         pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
3323                 hw_event_sata_phy_up(pm8001_ha, piomb);
3324                 break;
3325         case HW_EVENT_PHY_STOP_STATUS:
3326                 PM8001_MSG_DBG(pm8001_ha,
3327                         pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3328                         "status = %x\n", status));
3329                 if (status == 0)
3330                         phy->phy_state = 0;
3331                 break;
3332         case HW_EVENT_SATA_SPINUP_HOLD:
3333                 PM8001_MSG_DBG(pm8001_ha,
3334                         pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
3335                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3336                 break;
3337         case HW_EVENT_PHY_DOWN:
3338                 PM8001_MSG_DBG(pm8001_ha,
3339                         pm8001_printk("HW_EVENT_PHY_DOWN \n"));
3340                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3341                 phy->phy_attached = 0;
3342                 phy->phy_state = 0;
3343                 hw_event_phy_down(pm8001_ha, piomb);
3344                 break;
3345         case HW_EVENT_PORT_INVALID:
3346                 PM8001_MSG_DBG(pm8001_ha,
3347                         pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3348                 sas_phy_disconnected(sas_phy);
3349                 phy->phy_attached = 0;
3350                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3351                 break;
3352         /* the broadcast change primitive received, tell the LIBSAS this event
3353         to revalidate the sas domain*/
3354         case HW_EVENT_BROADCAST_CHANGE:
3355                 PM8001_MSG_DBG(pm8001_ha,
3356                         pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3357                 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3358                         port_id, phy_id, 1, 0);
3359                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3360                 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3361                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3362                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3363                 break;
3364         case HW_EVENT_PHY_ERROR:
3365                 PM8001_MSG_DBG(pm8001_ha,
3366                         pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3367                 sas_phy_disconnected(&phy->sas_phy);
3368                 phy->phy_attached = 0;
3369                 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3370                 break;
3371         case HW_EVENT_BROADCAST_EXP:
3372                 PM8001_MSG_DBG(pm8001_ha,
3373                         pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3374                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3375                 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3376                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3377                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3378                 break;
3379         case HW_EVENT_LINK_ERR_INVALID_DWORD:
3380                 PM8001_MSG_DBG(pm8001_ha,
3381                         pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3382                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3383                         HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3384                 sas_phy_disconnected(sas_phy);
3385                 phy->phy_attached = 0;
3386                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3387                 break;
3388         case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3389                 PM8001_MSG_DBG(pm8001_ha,
3390                         pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3391                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3392                         HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3393                         port_id, phy_id, 0, 0);
3394                 sas_phy_disconnected(sas_phy);
3395                 phy->phy_attached = 0;
3396                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3397                 break;
3398         case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3399                 PM8001_MSG_DBG(pm8001_ha,
3400                         pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3401                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3402                         HW_EVENT_LINK_ERR_CODE_VIOLATION,
3403                         port_id, phy_id, 0, 0);
3404                 sas_phy_disconnected(sas_phy);
3405                 phy->phy_attached = 0;
3406                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3407                 break;
3408         case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3409                 PM8001_MSG_DBG(pm8001_ha,
3410                       pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3411                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3412                         HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3413                         port_id, phy_id, 0, 0);
3414                 sas_phy_disconnected(sas_phy);
3415                 phy->phy_attached = 0;
3416                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3417                 break;
3418         case HW_EVENT_MALFUNCTION:
3419                 PM8001_MSG_DBG(pm8001_ha,
3420                         pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3421                 break;
3422         case HW_EVENT_BROADCAST_SES:
3423                 PM8001_MSG_DBG(pm8001_ha,
3424                         pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3425                 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3426                 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3427                 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3428                 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3429                 break;
3430         case HW_EVENT_INBOUND_CRC_ERROR:
3431                 PM8001_MSG_DBG(pm8001_ha,
3432                         pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3433                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3434                         HW_EVENT_INBOUND_CRC_ERROR,
3435                         port_id, phy_id, 0, 0);
3436                 break;
3437         case HW_EVENT_HARD_RESET_RECEIVED:
3438                 PM8001_MSG_DBG(pm8001_ha,
3439                         pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3440                 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3441                 break;
3442         case HW_EVENT_ID_FRAME_TIMEOUT:
3443                 PM8001_MSG_DBG(pm8001_ha,
3444                         pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3445                 sas_phy_disconnected(sas_phy);
3446                 phy->phy_attached = 0;
3447                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3448                 break;
3449         case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3450                 PM8001_MSG_DBG(pm8001_ha,
3451                         pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
3452                 pm8001_hw_event_ack_req(pm8001_ha, 0,
3453                         HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3454                         port_id, phy_id, 0, 0);
3455                 sas_phy_disconnected(sas_phy);
3456                 phy->phy_attached = 0;
3457                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3458                 break;
3459         case HW_EVENT_PORT_RESET_TIMER_TMO:
3460                 PM8001_MSG_DBG(pm8001_ha,
3461                         pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
3462                 sas_phy_disconnected(sas_phy);
3463                 phy->phy_attached = 0;
3464                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3465                 break;
3466         case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3467                 PM8001_MSG_DBG(pm8001_ha,
3468                         pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
3469                 sas_phy_disconnected(sas_phy);
3470                 phy->phy_attached = 0;
3471                 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3472                 break;
3473         case HW_EVENT_PORT_RECOVER:
3474                 PM8001_MSG_DBG(pm8001_ha,
3475                         pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
3476                 break;
3477         case HW_EVENT_PORT_RESET_COMPLETE:
3478                 PM8001_MSG_DBG(pm8001_ha,
3479                         pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
3480                 break;
3481         case EVENT_BROADCAST_ASYNCH_EVENT:
3482                 PM8001_MSG_DBG(pm8001_ha,
3483                         pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3484                 break;
3485         default:
3486                 PM8001_MSG_DBG(pm8001_ha,
3487                         pm8001_printk("Unknown event type = %x\n", eventType));
3488                 break;
3489         }
3490         return 0;
3491 }
3492
3493 /**
3494  * process_one_iomb - process one outbound Queue memory block
3495  * @pm8001_ha: our hba card information
3496  * @piomb: IO message buffer
3497  */
3498 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3499 {
3500         u32 pHeader = (u32)*(u32 *)piomb;
3501         u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3502
3503         PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3504
3505         switch (opc) {
3506         case OPC_OUB_ECHO:
3507                 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
3508                 break;
3509         case OPC_OUB_HW_EVENT:
3510                 PM8001_MSG_DBG(pm8001_ha,
3511                         pm8001_printk("OPC_OUB_HW_EVENT \n"));
3512                 mpi_hw_event(pm8001_ha, piomb);
3513                 break;
3514         case OPC_OUB_SSP_COMP:
3515                 PM8001_MSG_DBG(pm8001_ha,
3516                         pm8001_printk("OPC_OUB_SSP_COMP \n"));
3517                 mpi_ssp_completion(pm8001_ha, piomb);
3518                 break;
3519         case OPC_OUB_SMP_COMP:
3520                 PM8001_MSG_DBG(pm8001_ha,
3521                         pm8001_printk("OPC_OUB_SMP_COMP \n"));
3522                 mpi_smp_completion(pm8001_ha, piomb);
3523                 break;
3524         case OPC_OUB_LOCAL_PHY_CNTRL:
3525                 PM8001_MSG_DBG(pm8001_ha,
3526                         pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3527                 mpi_local_phy_ctl(pm8001_ha, piomb);
3528                 break;
3529         case OPC_OUB_DEV_REGIST:
3530                 PM8001_MSG_DBG(pm8001_ha,
3531                         pm8001_printk("OPC_OUB_DEV_REGIST \n"));
3532                 mpi_reg_resp(pm8001_ha, piomb);
3533                 break;
3534         case OPC_OUB_DEREG_DEV:
3535                 PM8001_MSG_DBG(pm8001_ha,
3536                         pm8001_printk("unresgister the deviece \n"));
3537                 mpi_dereg_resp(pm8001_ha, piomb);
3538                 break;
3539         case OPC_OUB_GET_DEV_HANDLE:
3540                 PM8001_MSG_DBG(pm8001_ha,
3541                         pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
3542                 break;
3543         case OPC_OUB_SATA_COMP:
3544                 PM8001_MSG_DBG(pm8001_ha,
3545                         pm8001_printk("OPC_OUB_SATA_COMP \n"));
3546                 mpi_sata_completion(pm8001_ha, piomb);
3547                 break;
3548         case OPC_OUB_SATA_EVENT:
3549                 PM8001_MSG_DBG(pm8001_ha,
3550                         pm8001_printk("OPC_OUB_SATA_EVENT \n"));
3551                 mpi_sata_event(pm8001_ha, piomb);
3552                 break;
3553         case OPC_OUB_SSP_EVENT:
3554                 PM8001_MSG_DBG(pm8001_ha,
3555                         pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3556                 mpi_ssp_event(pm8001_ha, piomb);
3557                 break;
3558         case OPC_OUB_DEV_HANDLE_ARRIV:
3559                 PM8001_MSG_DBG(pm8001_ha,
3560                         pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3561                 /*This is for target*/
3562                 break;
3563         case OPC_OUB_SSP_RECV_EVENT:
3564                 PM8001_MSG_DBG(pm8001_ha,
3565                         pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3566                 /*This is for target*/
3567                 break;
3568         case OPC_OUB_DEV_INFO:
3569                 PM8001_MSG_DBG(pm8001_ha,
3570                         pm8001_printk("OPC_OUB_DEV_INFO\n"));
3571                 break;
3572         case OPC_OUB_FW_FLASH_UPDATE:
3573                 PM8001_MSG_DBG(pm8001_ha,
3574                         pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3575                 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3576                 break;
3577         case OPC_OUB_GPIO_RESPONSE:
3578                 PM8001_MSG_DBG(pm8001_ha,
3579                         pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3580                 break;
3581         case OPC_OUB_GPIO_EVENT:
3582                 PM8001_MSG_DBG(pm8001_ha,
3583                         pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3584                 break;
3585         case OPC_OUB_GENERAL_EVENT:
3586                 PM8001_MSG_DBG(pm8001_ha,
3587                         pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3588                 mpi_general_event(pm8001_ha, piomb);
3589                 break;
3590         case OPC_OUB_SSP_ABORT_RSP:
3591                 PM8001_MSG_DBG(pm8001_ha,
3592                         pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3593                 mpi_task_abort_resp(pm8001_ha, piomb);
3594                 break;
3595         case OPC_OUB_SATA_ABORT_RSP:
3596                 PM8001_MSG_DBG(pm8001_ha,
3597                         pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3598                 mpi_task_abort_resp(pm8001_ha, piomb);
3599                 break;
3600         case OPC_OUB_SAS_DIAG_MODE_START_END:
3601                 PM8001_MSG_DBG(pm8001_ha,
3602                         pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3603                 break;
3604         case OPC_OUB_SAS_DIAG_EXECUTE:
3605                 PM8001_MSG_DBG(pm8001_ha,
3606                         pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3607                 break;
3608         case OPC_OUB_GET_TIME_STAMP:
3609                 PM8001_MSG_DBG(pm8001_ha,
3610                         pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3611                 break;
3612         case OPC_OUB_SAS_HW_EVENT_ACK:
3613                 PM8001_MSG_DBG(pm8001_ha,
3614                         pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3615                 break;
3616         case OPC_OUB_PORT_CONTROL:
3617                 PM8001_MSG_DBG(pm8001_ha,
3618                         pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3619                 break;
3620         case OPC_OUB_SMP_ABORT_RSP:
3621                 PM8001_MSG_DBG(pm8001_ha,
3622                         pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3623                 mpi_task_abort_resp(pm8001_ha, piomb);
3624                 break;
3625         case OPC_OUB_GET_NVMD_DATA:
3626                 PM8001_MSG_DBG(pm8001_ha,
3627                         pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3628                 mpi_get_nvmd_resp(pm8001_ha, piomb);
3629                 break;
3630         case OPC_OUB_SET_NVMD_DATA:
3631                 PM8001_MSG_DBG(pm8001_ha,
3632                         pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3633                 mpi_set_nvmd_resp(pm8001_ha, piomb);
3634                 break;
3635         case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3636                 PM8001_MSG_DBG(pm8001_ha,
3637                         pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3638                 break;
3639         case OPC_OUB_SET_DEVICE_STATE:
3640                 PM8001_MSG_DBG(pm8001_ha,
3641                         pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3642                 mpi_set_dev_state_resp(pm8001_ha, piomb);
3643                 break;
3644         case OPC_OUB_GET_DEVICE_STATE:
3645                 PM8001_MSG_DBG(pm8001_ha,
3646                         pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3647                 break;
3648         case OPC_OUB_SET_DEV_INFO:
3649                 PM8001_MSG_DBG(pm8001_ha,
3650                         pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3651                 break;
3652         case OPC_OUB_SAS_RE_INITIALIZE:
3653                 PM8001_MSG_DBG(pm8001_ha,
3654                         pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3655                 break;
3656         default:
3657                 PM8001_MSG_DBG(pm8001_ha,
3658                         pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3659                         opc));
3660                 break;
3661         }
3662 }
3663
3664 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3665 {
3666         struct outbound_queue_table *circularQ;
3667         void *pMsg1 = NULL;
3668         u8 bc = 0;
3669         u32 ret = MPI_IO_STATUS_FAIL;
3670
3671         circularQ = &pm8001_ha->outbnd_q_tbl[0];
3672         do {
3673                 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3674                 if (MPI_IO_STATUS_SUCCESS == ret) {
3675                         /* process the outbound message */
3676                         process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3677                         /* free the message from the outbound circular buffer */
3678                         mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3679                 }
3680                 if (MPI_IO_STATUS_BUSY == ret) {
3681                         u32 producer_idx;
3682                         /* Update the producer index from SPC */
3683                         producer_idx = pm8001_read_32(circularQ->pi_virt);
3684                         circularQ->producer_index = cpu_to_le32(producer_idx);
3685                         if (circularQ->producer_index ==
3686                                 circularQ->consumer_idx)
3687                                 /* OQ is empty */
3688                                 break;
3689                 }
3690         } while (1);
3691         return ret;
3692 }
3693
3694 /* PCI_DMA_... to our direction translation. */
3695 static const u8 data_dir_flags[] = {
3696         [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3697         [PCI_DMA_TODEVICE]      = DATA_DIR_OUT,/* OUTBOUND */
3698         [PCI_DMA_FROMDEVICE]    = DATA_DIR_IN,/* INBOUND */
3699         [PCI_DMA_NONE]          = DATA_DIR_NONE,/* NO TRANSFER */
3700 };
3701 static void
3702 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3703 {
3704         int i;
3705         struct scatterlist *sg;
3706         struct pm8001_prd *buf_prd = prd;
3707
3708         for_each_sg(scatter, sg, nr, i) {
3709                 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3710                 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3711                 buf_prd->im_len.e = 0;
3712                 buf_prd++;
3713         }
3714 }
3715
3716 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3717 {
3718         psmp_cmd->tag = cpu_to_le32(hTag);
3719         psmp_cmd->device_id = cpu_to_le32(deviceID);
3720         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3721 }
3722
3723 /**
3724  * pm8001_chip_smp_req - send a SMP task to FW
3725  * @pm8001_ha: our hba card information.
3726  * @ccb: the ccb information this request used.
3727  */
3728 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3729         struct pm8001_ccb_info *ccb)
3730 {
3731         int elem, rc;
3732         struct sas_task *task = ccb->task;
3733         struct domain_device *dev = task->dev;
3734         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3735         struct scatterlist *sg_req, *sg_resp;
3736         u32 req_len, resp_len;
3737         struct smp_req smp_cmd;
3738         u32 opc;
3739         struct inbound_queue_table *circularQ;
3740
3741         memset(&smp_cmd, 0, sizeof(smp_cmd));
3742         /*
3743          * DMA-map SMP request, response buffers
3744          */
3745         sg_req = &task->smp_task.smp_req;
3746         elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3747         if (!elem)
3748                 return -ENOMEM;
3749         req_len = sg_dma_len(sg_req);
3750
3751         sg_resp = &task->smp_task.smp_resp;
3752         elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3753         if (!elem) {
3754                 rc = -ENOMEM;
3755                 goto err_out;
3756         }
3757         resp_len = sg_dma_len(sg_resp);
3758         /* must be in dwords */
3759         if ((req_len & 0x3) || (resp_len & 0x3)) {
3760                 rc = -EINVAL;
3761                 goto err_out_2;
3762         }
3763
3764         opc = OPC_INB_SMP_REQUEST;
3765         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3766         smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3767         smp_cmd.long_smp_req.long_req_addr =
3768                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3769         smp_cmd.long_smp_req.long_req_size =
3770                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3771         smp_cmd.long_smp_req.long_resp_addr =
3772                 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3773         smp_cmd.long_smp_req.long_resp_size =
3774                 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3775         build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3776         mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3777         return 0;
3778
3779 err_out_2:
3780         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3781                         PCI_DMA_FROMDEVICE);
3782 err_out:
3783         dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3784                         PCI_DMA_TODEVICE);
3785         return rc;
3786 }
3787
3788 /**
3789  * pm8001_chip_ssp_io_req - send a SSP task to FW
3790  * @pm8001_ha: our hba card information.
3791  * @ccb: the ccb information this request used.
3792  */
3793 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3794         struct pm8001_ccb_info *ccb)
3795 {
3796         struct sas_task *task = ccb->task;
3797         struct domain_device *dev = task->dev;
3798         struct pm8001_device *pm8001_dev = dev->lldd_dev;
3799         struct ssp_ini_io_start_req ssp_cmd;
3800         u32 tag = ccb->ccb_tag;
3801         int ret;
3802         __le64 phys_addr;
3803         struct inbound_queue_table *circularQ;
3804         u32 opc = OPC_INB_SSPINIIOSTART;
3805         memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3806         memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3807         ssp_cmd.dir_m_tlr =
3808                 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
3809         SAS 1.1 compatible TLR*/
3810         ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3811         ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3812         ssp_cmd.tag = cpu_to_le32(tag);
3813         if (task->ssp_task.enable_first_burst)
3814                 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3815         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3816         ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3817         memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
3818         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3819
3820         /* fill in PRD (scatter/gather) table, if any */
3821         if (task->num_scatter > 1) {
3822                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3823                 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3824                                 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3825                 ssp_cmd.addr_low = lower_32_bits(phys_addr);
3826                 ssp_cmd.addr_high = upper_32_bits(phys_addr);
3827                 ssp_cmd.esgl = cpu_to_le32(1<<31);
3828         } else if (task->num_scatter == 1) {
3829                 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3830                 ssp_cmd.addr_low = lower_32_bits(dma_addr);
3831                 ssp_cmd.addr_high = upper_32_bits(dma_addr);
3832                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3833                 ssp_cmd.esgl = 0;
3834         } else if (task->num_scatter == 0) {
3835                 ssp_cmd.addr_low = 0;
3836                 ssp_cmd.addr_high = 0;
3837                 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
3838                 ssp_cmd.esgl = 0;
3839         }
3840         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
3841         return ret;
3842 }
3843
3844 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
3845         struct pm8001_ccb_info *ccb)
3846 {
3847         struct sas_task *task = ccb->task;
3848         struct domain_device *dev = task->dev;
3849         struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
3850         u32 tag = ccb->ccb_tag;
3851         int ret;
3852         struct sata_start_req sata_cmd;
3853         u32 hdr_tag, ncg_tag = 0;
3854         __le64 phys_addr;
3855         u32 ATAP = 0x0;
3856         u32 dir;
3857         struct inbound_queue_table *circularQ;
3858         u32  opc = OPC_INB_SATA_HOST_OPSTART;
3859         memset(&sata_cmd, 0, sizeof(sata_cmd));
3860         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3861         if (task->data_dir == PCI_DMA_NONE) {
3862                 ATAP = 0x04;  /* no data*/
3863                 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
3864         } else if (likely(!task->ata_task.device_control_reg_update)) {
3865                 if (task->ata_task.dma_xfer) {
3866                         ATAP = 0x06; /* DMA */
3867                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
3868                 } else {
3869                         ATAP = 0x05; /* PIO*/
3870                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
3871                 }
3872                 if (task->ata_task.use_ncq &&
3873                         dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
3874                         ATAP = 0x07; /* FPDMA */
3875                         PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
3876                 }
3877         }
3878         if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
3879                 ncg_tag = hdr_tag;
3880         dir = data_dir_flags[task->data_dir] << 8;
3881         sata_cmd.tag = cpu_to_le32(tag);
3882         sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
3883         sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3884         sata_cmd.ncqtag_atap_dir_m =
3885                 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
3886         sata_cmd.sata_fis = task->ata_task.fis;
3887         if (likely(!task->ata_task.device_control_reg_update))
3888                 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
3889         sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
3890         /* fill in PRD (scatter/gather) table, if any */
3891         if (task->num_scatter > 1) {
3892                 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
3893                 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
3894                                 offsetof(struct pm8001_ccb_info, buf_prd[0]));
3895                 sata_cmd.addr_low = lower_32_bits(phys_addr);
3896                 sata_cmd.addr_high = upper_32_bits(phys_addr);
3897                 sata_cmd.esgl = cpu_to_le32(1 << 31);
3898         } else if (task->num_scatter == 1) {
3899                 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
3900                 sata_cmd.addr_low = lower_32_bits(dma_addr);
3901                 sata_cmd.addr_high = upper_32_bits(dma_addr);
3902                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3903                 sata_cmd.esgl = 0;
3904         } else if (task->num_scatter == 0) {
3905                 sata_cmd.addr_low = 0;
3906                 sata_cmd.addr_high = 0;
3907                 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
3908                 sata_cmd.esgl = 0;
3909         }
3910         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
3911         return ret;
3912 }
3913
3914 /**
3915  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
3916  * @pm8001_ha: our hba card information.
3917  * @num: the inbound queue number
3918  * @phy_id: the phy id which we wanted to start up.
3919  */
3920 static int
3921 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
3922 {
3923         struct phy_start_req payload;
3924         struct inbound_queue_table *circularQ;
3925         int ret;
3926         u32 tag = 0x01;
3927         u32 opcode = OPC_INB_PHYSTART;
3928         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3929         memset(&payload, 0, sizeof(payload));
3930         payload.tag = cpu_to_le32(tag);
3931         /*
3932          ** [0:7]   PHY Identifier
3933          ** [8:11]  link rate 1.5G, 3G, 6G
3934          ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
3935          ** [14]    0b disable spin up hold; 1b enable spin up hold
3936          */
3937         payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
3938                 LINKMODE_AUTO | LINKRATE_15 |
3939                 LINKRATE_30 | LINKRATE_60 | phy_id);
3940         payload.sas_identify.dev_type = SAS_END_DEV;
3941         payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
3942         memcpy(payload.sas_identify.sas_addr,
3943                 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
3944         payload.sas_identify.phy_id = phy_id;
3945         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3946         return ret;
3947 }
3948
3949 /**
3950  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
3951  * @pm8001_ha: our hba card information.
3952  * @num: the inbound queue number
3953  * @phy_id: the phy id which we wanted to start up.
3954  */
3955 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
3956         u8 phy_id)
3957 {
3958         struct phy_stop_req payload;
3959         struct inbound_queue_table *circularQ;
3960         int ret;
3961         u32 tag = 0x01;
3962         u32 opcode = OPC_INB_PHYSTOP;
3963         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3964         memset(&payload, 0, sizeof(payload));
3965         payload.tag = cpu_to_le32(tag);
3966         payload.phy_id = cpu_to_le32(phy_id);
3967         ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
3968         return ret;
3969 }
3970
3971 /**
3972  * see comments on mpi_reg_resp.
3973  */
3974 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
3975         struct pm8001_device *pm8001_dev, u32 flag)
3976 {
3977         struct reg_dev_req payload;
3978         u32     opc;
3979         u32 stp_sspsmp_sata = 0x4;
3980         struct inbound_queue_table *circularQ;
3981         u32 linkrate, phy_id;
3982         int rc, tag = 0xdeadbeef;
3983         struct pm8001_ccb_info *ccb;
3984         u8 retryFlag = 0x1;
3985         u16 firstBurstSize = 0;
3986         u16 ITNT = 2000;
3987         struct domain_device *dev = pm8001_dev->sas_device;
3988         struct domain_device *parent_dev = dev->parent;
3989         circularQ = &pm8001_ha->inbnd_q_tbl[0];
3990
3991         memset(&payload, 0, sizeof(payload));
3992         rc = pm8001_tag_alloc(pm8001_ha, &tag);
3993         if (rc)
3994                 return rc;
3995         ccb = &pm8001_ha->ccb_info[tag];
3996         ccb->device = pm8001_dev;
3997         ccb->ccb_tag = tag;
3998         payload.tag = cpu_to_le32(tag);
3999         if (flag == 1)
4000                 stp_sspsmp_sata = 0x02; /*direct attached sata */
4001         else {
4002                 if (pm8001_dev->dev_type == SATA_DEV)
4003                         stp_sspsmp_sata = 0x00; /* stp*/
4004                 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4005                         pm8001_dev->dev_type == EDGE_DEV ||
4006                         pm8001_dev->dev_type == FANOUT_DEV)
4007                         stp_sspsmp_sata = 0x01; /*ssp or smp*/
4008         }
4009         if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4010                 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4011         else
4012                 phy_id = pm8001_dev->attached_phy;
4013         opc = OPC_INB_REG_DEV;
4014         linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4015                         pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4016         payload.phyid_portid =
4017                 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4018                 ((phy_id & 0x0F) << 4));
4019         payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4020                 ((linkrate & 0x0F) * 0x1000000) |
4021                 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4022         payload.firstburstsize_ITNexustimeout =
4023                 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4024         memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4025                 SAS_ADDR_SIZE);
4026         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4027         return rc;
4028 }
4029
4030 /**
4031  * see comments on mpi_reg_resp.
4032  */
4033 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4034         u32 device_id)
4035 {
4036         struct dereg_dev_req payload;
4037         u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4038         int ret;
4039         struct inbound_queue_table *circularQ;
4040
4041         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4042         memset(&payload, 0, sizeof(payload));
4043         payload.tag = 1;
4044         payload.device_id = cpu_to_le32(device_id);
4045         PM8001_MSG_DBG(pm8001_ha,
4046                 pm8001_printk("unregister device device_id = %d\n", device_id));
4047         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4048         return ret;
4049 }
4050
4051 /**
4052  * pm8001_chip_phy_ctl_req - support the local phy operation
4053  * @pm8001_ha: our hba card information.
4054  * @num: the inbound queue number
4055  * @phy_id: the phy id which we wanted to operate
4056  * @phy_op:
4057  */
4058 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4059         u32 phyId, u32 phy_op)
4060 {
4061         struct local_phy_ctl_req payload;
4062         struct inbound_queue_table *circularQ;
4063         int ret;
4064         u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4065         memset(&payload, 0, sizeof(payload));
4066         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4067         payload.tag = 1;
4068         payload.phyop_phyid =
4069                 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4070         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4071         return ret;
4072 }
4073
4074 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4075 {
4076         u32 value;
4077 #ifdef PM8001_USE_MSIX
4078         return 1;
4079 #endif
4080         value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4081         if (value)
4082                 return 1;
4083         return 0;
4084
4085 }
4086
4087 /**
4088  * pm8001_chip_isr - PM8001 isr handler.
4089  * @pm8001_ha: our hba card information.
4090  * @irq: irq number.
4091  * @stat: stat.
4092  */
4093 static irqreturn_t
4094 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4095 {
4096         unsigned long flags;
4097         spin_lock_irqsave(&pm8001_ha->lock, flags);
4098         pm8001_chip_interrupt_disable(pm8001_ha);
4099         process_oq(pm8001_ha);
4100         pm8001_chip_interrupt_enable(pm8001_ha);
4101         spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4102         return IRQ_HANDLED;
4103 }
4104
4105 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4106         u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4107 {
4108         struct task_abort_req task_abort;
4109         struct inbound_queue_table *circularQ;
4110         int ret;
4111         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4112         memset(&task_abort, 0, sizeof(task_abort));
4113         if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4114                 task_abort.abort_all = 0;
4115                 task_abort.device_id = cpu_to_le32(dev_id);
4116                 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4117                 task_abort.tag = cpu_to_le32(cmd_tag);
4118         } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4119                 task_abort.abort_all = cpu_to_le32(1);
4120                 task_abort.device_id = cpu_to_le32(dev_id);
4121                 task_abort.tag = cpu_to_le32(cmd_tag);
4122         }
4123         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4124         return ret;
4125 }
4126
4127 /**
4128  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4129  * @task: the task we wanted to aborted.
4130  * @flag: the abort flag.
4131  */
4132 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4133         struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4134 {
4135         u32 opc, device_id;
4136         int rc = TMF_RESP_FUNC_FAILED;
4137         PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4138                 " = %x", cmd_tag, task_tag));
4139         if (pm8001_dev->dev_type == SAS_END_DEV)
4140                 opc = OPC_INB_SSP_ABORT;
4141         else if (pm8001_dev->dev_type == SATA_DEV)
4142                 opc = OPC_INB_SATA_ABORT;
4143         else
4144                 opc = OPC_INB_SMP_ABORT;/* SMP */
4145         device_id = pm8001_dev->device_id;
4146         rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4147                 task_tag, cmd_tag);
4148         if (rc != TMF_RESP_FUNC_COMPLETE)
4149                 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4150         return rc;
4151 }
4152
4153 /**
4154  * pm8001_chip_ssp_tm_req - built the task managment command.
4155  * @pm8001_ha: our hba card information.
4156  * @ccb: the ccb information.
4157  * @tmf: task management function.
4158  */
4159 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4160         struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4161 {
4162         struct sas_task *task = ccb->task;
4163         struct domain_device *dev = task->dev;
4164         struct pm8001_device *pm8001_dev = dev->lldd_dev;
4165         u32 opc = OPC_INB_SSPINITMSTART;
4166         struct inbound_queue_table *circularQ;
4167         struct ssp_ini_tm_start_req sspTMCmd;
4168         int ret;
4169
4170         memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4171         sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4172         sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4173         sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4174         memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4175         sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4176         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4177         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4178         return ret;
4179 }
4180
4181 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4182         void *payload)
4183 {
4184         u32 opc = OPC_INB_GET_NVMD_DATA;
4185         u32 nvmd_type;
4186         int rc;
4187         u32 tag;
4188         struct pm8001_ccb_info *ccb;
4189         struct inbound_queue_table *circularQ;
4190         struct get_nvm_data_req nvmd_req;
4191         struct fw_control_ex *fw_control_context;
4192         struct pm8001_ioctl_payload *ioctl_payload = payload;
4193
4194         nvmd_type = ioctl_payload->minor_function;
4195         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4196         fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4197         fw_control_context->len = ioctl_payload->length;
4198         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4199         memset(&nvmd_req, 0, sizeof(nvmd_req));
4200         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4201         if (rc)
4202                 return rc;
4203         ccb = &pm8001_ha->ccb_info[tag];
4204         ccb->ccb_tag = tag;
4205         ccb->fw_control_context = fw_control_context;
4206         nvmd_req.tag = cpu_to_le32(tag);
4207
4208         switch (nvmd_type) {
4209         case TWI_DEVICE: {
4210                 u32 twi_addr, twi_page_size;
4211                 twi_addr = 0xa8;
4212                 twi_page_size = 2;
4213
4214                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4215                         twi_page_size << 8 | TWI_DEVICE);
4216                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4217                 nvmd_req.resp_addr_hi =
4218                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4219                 nvmd_req.resp_addr_lo =
4220                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4221                 break;
4222         }
4223         case C_SEEPROM: {
4224                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4225                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4226                 nvmd_req.resp_addr_hi =
4227                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4228                 nvmd_req.resp_addr_lo =
4229                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4230                 break;
4231         }
4232         case VPD_FLASH: {
4233                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4234                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4235                 nvmd_req.resp_addr_hi =
4236                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4237                 nvmd_req.resp_addr_lo =
4238                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4239                 break;
4240         }
4241         case EXPAN_ROM: {
4242                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4243                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4244                 nvmd_req.resp_addr_hi =
4245                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4246                 nvmd_req.resp_addr_lo =
4247                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4248                 break;
4249         }
4250         default:
4251                 break;
4252         }
4253         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4254         return rc;
4255 }
4256
4257 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4258         void *payload)
4259 {
4260         u32 opc = OPC_INB_SET_NVMD_DATA;
4261         u32 nvmd_type;
4262         int rc;
4263         u32 tag;
4264         struct pm8001_ccb_info *ccb;
4265         struct inbound_queue_table *circularQ;
4266         struct set_nvm_data_req nvmd_req;
4267         struct fw_control_ex *fw_control_context;
4268         struct pm8001_ioctl_payload *ioctl_payload = payload;
4269
4270         nvmd_type = ioctl_payload->minor_function;
4271         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4272         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4273         memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4274                 ioctl_payload->func_specific,
4275                 ioctl_payload->length);
4276         memset(&nvmd_req, 0, sizeof(nvmd_req));
4277         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4278         if (rc)
4279                 return rc;
4280         ccb = &pm8001_ha->ccb_info[tag];
4281         ccb->fw_control_context = fw_control_context;
4282         ccb->ccb_tag = tag;
4283         nvmd_req.tag = cpu_to_le32(tag);
4284         switch (nvmd_type) {
4285         case TWI_DEVICE: {
4286                 u32 twi_addr, twi_page_size;
4287                 twi_addr = 0xa8;
4288                 twi_page_size = 2;
4289                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4290                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4291                         twi_page_size << 8 | TWI_DEVICE);
4292                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4293                 nvmd_req.resp_addr_hi =
4294                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4295                 nvmd_req.resp_addr_lo =
4296                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4297                 break;
4298         }
4299         case C_SEEPROM:
4300                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4301                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4302                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4303                 nvmd_req.resp_addr_hi =
4304                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4305                 nvmd_req.resp_addr_lo =
4306                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4307                 break;
4308         case VPD_FLASH:
4309                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4310                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4311                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4312                 nvmd_req.resp_addr_hi =
4313                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4314                 nvmd_req.resp_addr_lo =
4315                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4316                 break;
4317         case EXPAN_ROM:
4318                 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4319                 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4320                 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4321                 nvmd_req.resp_addr_hi =
4322                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4323                 nvmd_req.resp_addr_lo =
4324                     cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4325                 break;
4326         default:
4327                 break;
4328         }
4329         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4330         return rc;
4331 }
4332
4333 /**
4334  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4335  * @pm8001_ha: our hba card information.
4336  * @fw_flash_updata_info: firmware flash update param
4337  */
4338 static int
4339 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4340         void *fw_flash_updata_info, u32 tag)
4341 {
4342         struct fw_flash_Update_req payload;
4343         struct fw_flash_updata_info *info;
4344         struct inbound_queue_table *circularQ;
4345         int ret;
4346         u32 opc = OPC_INB_FW_FLASH_UPDATE;
4347
4348         memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4349         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4350         info = fw_flash_updata_info;
4351         payload.tag = cpu_to_le32(tag);
4352         payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4353         payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4354         payload.total_image_len = cpu_to_le32(info->total_image_len);
4355         payload.len = info->sgl.im_len.len ;
4356         payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4357         payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4358         ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4359         return ret;
4360 }
4361
4362 static int
4363 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4364         void *payload)
4365 {
4366         struct fw_flash_updata_info flash_update_info;
4367         struct fw_control_info *fw_control;
4368         struct fw_control_ex *fw_control_context;
4369         int rc;
4370         u32 tag;
4371         struct pm8001_ccb_info *ccb;
4372         void *buffer = NULL;
4373         dma_addr_t phys_addr;
4374         u32 phys_addr_hi;
4375         u32 phys_addr_lo;
4376         struct pm8001_ioctl_payload *ioctl_payload = payload;
4377
4378         fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4379         fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4380         if (fw_control->len != 0) {
4381                 if (pm8001_mem_alloc(pm8001_ha->pdev,
4382                         (void **)&buffer,
4383                         &phys_addr,
4384                         &phys_addr_hi,
4385                         &phys_addr_lo,
4386                         fw_control->len, 0) != 0) {
4387                                 PM8001_FAIL_DBG(pm8001_ha,
4388                                         pm8001_printk("Mem alloc failure\n"));
4389                                 return -ENOMEM;
4390                 }
4391         }
4392         memset(buffer, 0, fw_control->len);
4393         memcpy(buffer, fw_control->buffer, fw_control->len);
4394         flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4395         flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4396         flash_update_info.sgl.im_len.e = 0;
4397         flash_update_info.cur_image_offset = fw_control->offset;
4398         flash_update_info.cur_image_len = fw_control->len;
4399         flash_update_info.total_image_len = fw_control->size;
4400         fw_control_context->fw_control = fw_control;
4401         fw_control_context->virtAddr = buffer;
4402         fw_control_context->len = fw_control->len;
4403         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4404         if (rc)
4405                 return rc;
4406         ccb = &pm8001_ha->ccb_info[tag];
4407         ccb->fw_control_context = fw_control_context;
4408         ccb->ccb_tag = tag;
4409         rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4410                 tag);
4411         return rc;
4412 }
4413
4414 static int
4415 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4416         struct pm8001_device *pm8001_dev, u32 state)
4417 {
4418         struct set_dev_state_req payload;
4419         struct inbound_queue_table *circularQ;
4420         struct pm8001_ccb_info *ccb;
4421         int rc;
4422         u32 tag;
4423         u32 opc = OPC_INB_SET_DEVICE_STATE;
4424         memset(&payload, 0, sizeof(payload));
4425         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4426         if (rc)
4427                 return -1;
4428         ccb = &pm8001_ha->ccb_info[tag];
4429         ccb->ccb_tag = tag;
4430         ccb->device = pm8001_dev;
4431         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4432         payload.tag = cpu_to_le32(tag);
4433         payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4434         payload.nds = cpu_to_le32(state);
4435         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4436         return rc;
4437
4438 }
4439
4440 static int
4441 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4442 {
4443         struct sas_re_initialization_req payload;
4444         struct inbound_queue_table *circularQ;
4445         struct pm8001_ccb_info *ccb;
4446         int rc;
4447         u32 tag;
4448         u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4449         memset(&payload, 0, sizeof(payload));
4450         rc = pm8001_tag_alloc(pm8001_ha, &tag);
4451         if (rc)
4452                 return -1;
4453         ccb = &pm8001_ha->ccb_info[tag];
4454         ccb->ccb_tag = tag;
4455         circularQ = &pm8001_ha->inbnd_q_tbl[0];
4456         payload.tag = cpu_to_le32(tag);
4457         payload.SSAHOLT = cpu_to_le32(0xd << 25);
4458         payload.sata_hol_tmo = cpu_to_le32(80);
4459         payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4460         rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4461         return rc;
4462
4463 }
4464
4465 const struct pm8001_dispatch pm8001_8001_dispatch = {
4466         .name                   = "pmc8001",
4467         .chip_init              = pm8001_chip_init,
4468         .chip_soft_rst          = pm8001_chip_soft_rst,
4469         .chip_rst               = pm8001_hw_chip_rst,
4470         .chip_iounmap           = pm8001_chip_iounmap,
4471         .isr                    = pm8001_chip_isr,
4472         .is_our_interupt        = pm8001_chip_is_our_interupt,
4473         .isr_process_oq         = process_oq,
4474         .interrupt_enable       = pm8001_chip_interrupt_enable,
4475         .interrupt_disable      = pm8001_chip_interrupt_disable,
4476         .make_prd               = pm8001_chip_make_sg,
4477         .smp_req                = pm8001_chip_smp_req,
4478         .ssp_io_req             = pm8001_chip_ssp_io_req,
4479         .sata_req               = pm8001_chip_sata_req,
4480         .phy_start_req          = pm8001_chip_phy_start_req,
4481         .phy_stop_req           = pm8001_chip_phy_stop_req,
4482         .reg_dev_req            = pm8001_chip_reg_dev_req,
4483         .dereg_dev_req          = pm8001_chip_dereg_dev_req,
4484         .phy_ctl_req            = pm8001_chip_phy_ctl_req,
4485         .task_abort             = pm8001_chip_abort_task,
4486         .ssp_tm_req             = pm8001_chip_ssp_tm_req,
4487         .get_nvmd_req           = pm8001_chip_get_nvmd_req,
4488         .set_nvmd_req           = pm8001_chip_set_nvmd_req,
4489         .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
4490         .set_dev_state_req      = pm8001_chip_set_dev_state_req,
4491         .sas_re_init_req        = pm8001_chip_sas_re_initialization,
4492 };
4493