SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/scsi/aic7xxx/aic7xxx_core.c

   1 /*
   2  * Core routines and tables shareable across OS platforms.
   3  *
   4  * Copyright (c) 1994-2002 Justin T. Gibbs.
   5  * Copyright (c) 2000-2002 Adaptec Inc.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions, and the following disclaimer,
  13  *    without modification.
  14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15  *    substantially similar to the "NO WARRANTY" disclaimer below
  16  *    ("Disclaimer") and any redistribution must be conditioned upon
  17  *    including a substantially similar Disclaimer requirement for further
  18  *    binary redistribution.
  19  * 3. Neither the names of the above-listed copyright holders nor the names
  20  *    of any contributors may be used to endorse or promote products derived
  21  *    from this software without specific prior written permission.
  22  *
  23  * Alternatively, this software may be distributed under the terms of the
  24  * GNU General Public License ("GPL") version 2 as published by the Free
  25  * Software Foundation.
  26  *
  27  * NO WARRANTY
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38  * POSSIBILITY OF SUCH DAMAGES.
  39  *
  40  * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
  41  */
  42
  43 #ifdef __linux__
  44 #include "aic7xxx_osm.h"
  45 #include "aic7xxx_inline.h"
  46 #include "aicasm/aicasm_insformat.h"
  47 #else
  48 #include <dev/aic7xxx/aic7xxx_osm.h>
  49 #include <dev/aic7xxx/aic7xxx_inline.h>
  50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
  51 #endif
  52
  53 /***************************** Lookup Tables **********************************/
  54 static const char *const ahc_chip_names[] = {
  55         "NONE",
  56         "aic7770",
  57         "aic7850",
  58         "aic7855",
  59         "aic7859",
  60         "aic7860",
  61         "aic7870",
  62         "aic7880",
  63         "aic7895",
  64         "aic7895C",
  65         "aic7890/91",
  66         "aic7896/97",
  67         "aic7892",
  68         "aic7899"
  69 };
  70 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names);
  71
  72 /*
  73  * Hardware error codes.
  74  */
  75 struct ahc_hard_error_entry {
  76         uint8_t errno;
  77         const char *errmesg;
  78 };
  79
  80 static const struct ahc_hard_error_entry ahc_hard_errors[] = {
  81         { ILLHADDR,     "Illegal Host Access" },
  82         { ILLSADDR,     "Illegal Sequencer Address referrenced" },
  83         { ILLOPCODE,    "Illegal Opcode in sequencer program" },
  84         { SQPARERR,     "Sequencer Parity Error" },
  85         { DPARERR,      "Data-path Parity Error" },
  86         { MPARERR,      "Scratch or SCB Memory Parity Error" },
  87         { PCIERRSTAT,   "PCI Error detected" },
  88         { CIOPARERR,    "CIOBUS Parity Error" },
  89 };
  90 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors);
  91
  92 static const struct ahc_phase_table_entry ahc_phase_table[] =
  93 {
  94         { P_DATAOUT,    MSG_NOOP,               "in Data-out phase"     },
  95         { P_DATAIN,     MSG_INITIATOR_DET_ERR,  "in Data-in phase"      },
  96         { P_DATAOUT_DT, MSG_NOOP,               "in DT Data-out phase"  },
  97         { P_DATAIN_DT,  MSG_INITIATOR_DET_ERR,  "in DT Data-in phase"   },
  98         { P_COMMAND,    MSG_NOOP,               "in Command phase"      },
  99         { P_MESGOUT,    MSG_NOOP,               "in Message-out phase"  },
 100         { P_STATUS,     MSG_INITIATOR_DET_ERR,  "in Status phase"       },
 101         { P_MESGIN,     MSG_PARITY_ERROR,       "in Message-in phase"   },
 102         { P_BUSFREE,    MSG_NOOP,               "while idle"            },
 103         { 0,            MSG_NOOP,               "in unknown phase"      }
 104 };
 105
 106 /*
 107  * In most cases we only wish to itterate over real phases, so
 108  * exclude the last element from the count.
 109  */
 110 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1;
 111
 112 /*
 113  * Valid SCSIRATE values.  (p. 3-17)
 114  * Provides a mapping of tranfer periods in ns to the proper value to
 115  * stick in the scsixfer reg.
 116  */
 117 static const struct ahc_syncrate ahc_syncrates[] =
 118 {
 119       /* ultra2    fast/ultra  period     rate */
 120         { 0x42,      0x000,      9,      "80.0" },
 121         { 0x03,      0x000,     10,      "40.0" },
 122         { 0x04,      0x000,     11,      "33.0" },
 123         { 0x05,      0x100,     12,      "20.0" },
 124         { 0x06,      0x110,     15,      "16.0" },
 125         { 0x07,      0x120,     18,      "13.4" },
 126         { 0x08,      0x000,     25,      "10.0" },
 127         { 0x19,      0x010,     31,      "8.0"  },
 128         { 0x1a,      0x020,     37,      "6.67" },
 129         { 0x1b,      0x030,     43,      "5.7"  },
 130         { 0x1c,      0x040,     50,      "5.0"  },
 131         { 0x00,      0x050,     56,      "4.4"  },
 132         { 0x00,      0x060,     62,      "4.0"  },
 133         { 0x00,      0x070,     68,      "3.6"  },
 134         { 0x00,      0x000,      0,      NULL   }
 135 };
 136
 137 /* Our Sequencer Program */
 138 #include "aic7xxx_seq.h"
 139
 140 /**************************** Function Declarations ***************************/
 141 static void             ahc_force_renegotiation(struct ahc_softc *ahc,
 142                                                 struct ahc_devinfo *devinfo);
 143 static struct ahc_tmode_tstate*
 144                         ahc_alloc_tstate(struct ahc_softc *ahc,
 145                                          u_int scsi_id, char channel);
 146 #ifdef AHC_TARGET_MODE
 147 static void             ahc_free_tstate(struct ahc_softc *ahc,
 148                                         u_int scsi_id, char channel, int force);
 149 #endif
 150 static const struct ahc_syncrate*
 151                         ahc_devlimited_syncrate(struct ahc_softc *ahc,
 152                                                 struct ahc_initiator_tinfo *,
 153                                                 u_int *period,
 154                                                 u_int *ppr_options,
 155                                                 role_t role);
 156 static void             ahc_update_pending_scbs(struct ahc_softc *ahc);
 157 static void             ahc_fetch_devinfo(struct ahc_softc *ahc,
 158                                           struct ahc_devinfo *devinfo);
 159 static void             ahc_scb_devinfo(struct ahc_softc *ahc,
 160                                         struct ahc_devinfo *devinfo,
 161                                         struct scb *scb);
 162 static void             ahc_assert_atn(struct ahc_softc *ahc);
 163 static void             ahc_setup_initiator_msgout(struct ahc_softc *ahc,
 164                                                    struct ahc_devinfo *devinfo,
 165                                                    struct scb *scb);
 166 static void             ahc_build_transfer_msg(struct ahc_softc *ahc,
 167                                                struct ahc_devinfo *devinfo);
 168 static void             ahc_construct_sdtr(struct ahc_softc *ahc,
 169                                            struct ahc_devinfo *devinfo,
 170                                            u_int period, u_int offset);
 171 static void             ahc_construct_wdtr(struct ahc_softc *ahc,
 172                                            struct ahc_devinfo *devinfo,
 173                                            u_int bus_width);
 174 static void             ahc_construct_ppr(struct ahc_softc *ahc,
 175                                           struct ahc_devinfo *devinfo,
 176                                           u_int period, u_int offset,
 177                                           u_int bus_width, u_int ppr_options);
 178 static void             ahc_clear_msg_state(struct ahc_softc *ahc);
 179 static void             ahc_handle_proto_violation(struct ahc_softc *ahc);
 180 static void             ahc_handle_message_phase(struct ahc_softc *ahc);
 181 typedef enum {
 182         AHCMSG_1B,
 183         AHCMSG_2B,
 184         AHCMSG_EXT
 185 } ahc_msgtype;
 186 static int              ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
 187                                      u_int msgval, int full);
 188 static int              ahc_parse_msg(struct ahc_softc *ahc,
 189                                       struct ahc_devinfo *devinfo);
 190 static int              ahc_handle_msg_reject(struct ahc_softc *ahc,
 191                                               struct ahc_devinfo *devinfo);
 192 static void             ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
 193                                                 struct ahc_devinfo *devinfo);
 194 static void             ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
 195 static void             ahc_handle_devreset(struct ahc_softc *ahc,
 196                                             struct ahc_devinfo *devinfo,
 197                                             cam_status status, char *message,
 198                                             int verbose_level);
 199 #ifdef AHC_TARGET_MODE
 200 static void             ahc_setup_target_msgin(struct ahc_softc *ahc,
 201                                                struct ahc_devinfo *devinfo,
 202                                                struct scb *scb);
 203 #endif
 204
 205 static bus_dmamap_callback_t    ahc_dmamap_cb;
 206 static void             ahc_build_free_scb_list(struct ahc_softc *ahc);
 207 static int              ahc_init_scbdata(struct ahc_softc *ahc);
 208 static void             ahc_fini_scbdata(struct ahc_softc *ahc);
 209 static void             ahc_qinfifo_requeue(struct ahc_softc *ahc,
 210                                             struct scb *prev_scb,
 211                                             struct scb *scb);
 212 static int              ahc_qinfifo_count(struct ahc_softc *ahc);
 213 static u_int            ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
 214                                                    u_int prev, u_int scbptr);
 215 static void             ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
 216 static u_int            ahc_rem_wscb(struct ahc_softc *ahc,
 217                                      u_int scbpos, u_int prev);
 218 static void             ahc_reset_current_bus(struct ahc_softc *ahc);
 219 #ifdef AHC_DUMP_SEQ
 220 static void             ahc_dumpseq(struct ahc_softc *ahc);
 221 #endif
 222 static int              ahc_loadseq(struct ahc_softc *ahc);
 223 static int              ahc_check_patch(struct ahc_softc *ahc,
 224                                         struct patch **start_patch,
 225                                         u_int start_instr, u_int *skip_addr);
 226 static void             ahc_download_instr(struct ahc_softc *ahc,
 227                                            u_int instrptr, uint8_t *dconsts);
 228 #ifdef AHC_TARGET_MODE
 229 static void             ahc_queue_lstate_event(struct ahc_softc *ahc,
 230                                                struct ahc_tmode_lstate *lstate,
 231                                                u_int initiator_id,
 232                                                u_int event_type,
 233                                                u_int event_arg);
 234 static void             ahc_update_scsiid(struct ahc_softc *ahc,
 235                                           u_int targid_mask);
 236 static int              ahc_handle_target_cmd(struct ahc_softc *ahc,
 237                                               struct target_cmd *cmd);
 238 #endif
 239
 240 static u_int            ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
 241 static void             ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
 242 static void             ahc_busy_tcl(struct ahc_softc *ahc,
 243                                      u_int tcl, u_int busyid);
 244
 245 /************************** SCB and SCB queue management **********************/
 246 static void             ahc_run_untagged_queues(struct ahc_softc *ahc);
 247 static void             ahc_run_untagged_queue(struct ahc_softc *ahc,
 248                                                struct scb_tailq *queue);
 249
 250 /****************************** Initialization ********************************/
 251 static void              ahc_alloc_scbs(struct ahc_softc *ahc);
 252 static void              ahc_shutdown(void *arg);
 253
 254 /*************************** Interrupt Services *******************************/
 255 static void             ahc_clear_intstat(struct ahc_softc *ahc);
 256 static void             ahc_run_qoutfifo(struct ahc_softc *ahc);
 257 #ifdef AHC_TARGET_MODE
 258 static void             ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
 259 #endif
 260 static void             ahc_handle_brkadrint(struct ahc_softc *ahc);
 261 static void             ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
 262 static void             ahc_handle_scsiint(struct ahc_softc *ahc,
 263                                            u_int intstat);
 264 static void             ahc_clear_critical_section(struct ahc_softc *ahc);
 265
 266 /***************************** Error Recovery *********************************/
 267 static void             ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
 268 static int              ahc_abort_scbs(struct ahc_softc *ahc, int target,
 269                                        char channel, int lun, u_int tag,
 270                                        role_t role, uint32_t status);
 271 static void             ahc_calc_residual(struct ahc_softc *ahc,
 272                                           struct scb *scb);
 273
 274 /*********************** Untagged Transaction Routines ************************/
 275 static inline void      ahc_freeze_untagged_queues(struct ahc_softc *ahc);
 276 static inline void      ahc_release_untagged_queues(struct ahc_softc *ahc);
 277
 278 /*
 279  * Block our completion routine from starting the next untagged
 280  * transaction for this target or target lun.
 281  */
 282 static inline void
 283 ahc_freeze_untagged_queues(struct ahc_softc *ahc)
 284 {
 285         if ((ahc->flags & AHC_SCB_BTT) == 0)
 286                 ahc->untagged_queue_lock++;
 287 }
 288
 289 /*
 290  * Allow the next untagged transaction for this target or target lun
 291  * to be executed.  We use a counting semaphore to allow the lock
 292  * to be acquired recursively.  Once the count drops to zero, the
 293  * transaction queues will be run.
 294  */
 295 static inline void
 296 ahc_release_untagged_queues(struct ahc_softc *ahc)
 297 {
 298         if ((ahc->flags & AHC_SCB_BTT) == 0) {
 299                 ahc->untagged_queue_lock--;
 300                 if (ahc->untagged_queue_lock == 0)
 301                         ahc_run_untagged_queues(ahc);
 302         }
 303 }
 304
 305 /************************* Sequencer Execution Control ************************/
 306 /*
 307  * Work around any chip bugs related to halting sequencer execution.
 308  * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
 309  * reading a register that will set this signal and deassert it.
 310  * Without this workaround, if the chip is paused, by an interrupt or
 311  * manual pause while accessing scb ram, accesses to certain registers
 312  * will hang the system (infinite pci retries).
 313  */
 314 static void
 315 ahc_pause_bug_fix(struct ahc_softc *ahc)
 316 {
 317         if ((ahc->features & AHC_ULTRA2) != 0)
 318                 (void)ahc_inb(ahc, CCSCBCTL);
 319 }
 320
 321 /*
 322  * Determine whether the sequencer has halted code execution.
 323  * Returns non-zero status if the sequencer is stopped.
 324  */
 325 int
 326 ahc_is_paused(struct ahc_softc *ahc)
 327 {
 328         return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
 329 }
 330
 331 /*
 332  * Request that the sequencer stop and wait, indefinitely, for it
 333  * to stop.  The sequencer will only acknowledge that it is paused
 334  * once it has reached an instruction boundary and PAUSEDIS is
 335  * cleared in the SEQCTL register.  The sequencer may use PAUSEDIS
 336  * for critical sections.
 337  */
 338 void
 339 ahc_pause(struct ahc_softc *ahc)
 340 {
 341         ahc_outb(ahc, HCNTRL, ahc->pause);
 342
 343         /*
 344          * Since the sequencer can disable pausing in a critical section, we
 345          * must loop until it actually stops.
 346          */
 347         while (ahc_is_paused(ahc) == 0)
 348                 ;
 349
 350         ahc_pause_bug_fix(ahc);
 351 }
 352
 353 /*
 354  * Allow the sequencer to continue program execution.
 355  * We check here to ensure that no additional interrupt
 356  * sources that would cause the sequencer to halt have been
 357  * asserted.  If, for example, a SCSI bus reset is detected
 358  * while we are fielding a different, pausing, interrupt type,
 359  * we don't want to release the sequencer before going back
 360  * into our interrupt handler and dealing with this new
 361  * condition.
 362  */
 363 void
 364 ahc_unpause(struct ahc_softc *ahc)
 365 {
 366         if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
 367                 ahc_outb(ahc, HCNTRL, ahc->unpause);
 368 }
 369
 370 /************************** Memory mapping routines ***************************/
 371 static struct ahc_dma_seg *
 372 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
 373 {
 374         int sg_index;
 375
 376         sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
 377         /* sg_list_phys points to entry 1, not 0 */
 378         sg_index++;
 379
 380         return (&scb->sg_list[sg_index]);
 381 }
 382
 383 static uint32_t
 384 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
 385 {
 386         int sg_index;
 387
 388         /* sg_list_phys points to entry 1, not 0 */
 389         sg_index = sg - &scb->sg_list[1];
 390
 391         return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
 392 }
 393
 394 static uint32_t
 395 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
 396 {
 397         return (ahc->scb_data->hscb_busaddr
 398                 + (sizeof(struct hardware_scb) * index));
 399 }
 400
 401 static void
 402 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
 403 {
 404         ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat,
 405                         ahc->scb_data->hscb_dmamap,
 406                         /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb),
 407                         /*len*/sizeof(*scb->hscb), op);
 408 }
 409
 410 void
 411 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
 412 {
 413         if (scb->sg_count == 0)
 414                 return;
 415
 416         ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap,
 417                         /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
 418                                 * sizeof(struct ahc_dma_seg),
 419                         /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
 420 }
 421
 422 #ifdef AHC_TARGET_MODE
 423 static uint32_t
 424 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
 425 {
 426         return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
 427 }
 428 #endif
 429
 430 /*********************** Miscelaneous Support Functions ***********************/
 431 /*
 432  * Determine whether the sequencer reported a residual
 433  * for this SCB/transaction.
 434  */
 435 static void
 436 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
 437 {
 438         uint32_t sgptr;
 439
 440         sgptr = ahc_le32toh(scb->hscb->sgptr);
 441         if ((sgptr & SG_RESID_VALID) != 0)
 442                 ahc_calc_residual(ahc, scb);
 443 }
 444
 445 /*
 446  * Return pointers to the transfer negotiation information
 447  * for the specified our_id/remote_id pair.
 448  */
 449 struct ahc_initiator_tinfo *
 450 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
 451                     u_int remote_id, struct ahc_tmode_tstate **tstate)
 452 {
 453         /*
 454          * Transfer data structures are stored from the perspective
 455          * of the target role.  Since the parameters for a connection
 456          * in the initiator role to a given target are the same as
 457          * when the roles are reversed, we pretend we are the target.
 458          */
 459         if (channel == 'B')
 460                 our_id += 8;
 461         *tstate = ahc->enabled_targets[our_id];
 462         return (&(*tstate)->transinfo[remote_id]);
 463 }
 464
 465 uint16_t
 466 ahc_inw(struct ahc_softc *ahc, u_int port)
 467 {
 468         uint16_t r = ahc_inb(ahc, port+1) << 8;
 469         return r | ahc_inb(ahc, port);
 470 }
 471
 472 void
 473 ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
 474 {
 475         ahc_outb(ahc, port, value & 0xFF);
 476         ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
 477 }
 478
 479 uint32_t
 480 ahc_inl(struct ahc_softc *ahc, u_int port)
 481 {
 482         return ((ahc_inb(ahc, port))
 483               | (ahc_inb(ahc, port+1) << 8)
 484               | (ahc_inb(ahc, port+2) << 16)
 485               | (ahc_inb(ahc, port+3) << 24));
 486 }
 487
 488 void
 489 ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
 490 {
 491         ahc_outb(ahc, port, (value) & 0xFF);
 492         ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
 493         ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
 494         ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
 495 }
 496
 497 uint64_t
 498 ahc_inq(struct ahc_softc *ahc, u_int port)
 499 {
 500         return ((ahc_inb(ahc, port))
 501               | (ahc_inb(ahc, port+1) << 8)
 502               | (ahc_inb(ahc, port+2) << 16)
 503               | (ahc_inb(ahc, port+3) << 24)
 504               | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
 505               | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
 506               | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
 507               | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
 508 }
 509
 510 void
 511 ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
 512 {
 513         ahc_outb(ahc, port, value & 0xFF);
 514         ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
 515         ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
 516         ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
 517         ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
 518         ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
 519         ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
 520         ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
 521 }
 522
 523 /*
 524  * Get a free scb. If there are none, see if we can allocate a new SCB.
 525  */
 526 struct scb *
 527 ahc_get_scb(struct ahc_softc *ahc)
 528 {
 529         struct scb *scb;
 530
 531         if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) {
 532                 ahc_alloc_scbs(ahc);
 533                 scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
 534                 if (scb == NULL)
 535                         return (NULL);
 536         }
 537         SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
 538         return (scb);
 539 }
 540
 541 /*
 542  * Return an SCB resource to the free list.
 543  */
 544 void
 545 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
 546 {
 547         struct hardware_scb *hscb;
 548
 549         hscb = scb->hscb;
 550         /* Clean up for the next user */
 551         ahc->scb_data->scbindex[hscb->tag] = NULL;
 552         scb->flags = SCB_FREE;
 553         hscb->control = 0;
 554
 555         SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
 556
 557         /* Notify the OSM that a resource is now available. */
 558         ahc_platform_scb_free(ahc, scb);
 559 }
 560
 561 struct scb *
 562 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
 563 {
 564         struct scb* scb;
 565
 566         scb = ahc->scb_data->scbindex[tag];
 567         if (scb != NULL)
 568                 ahc_sync_scb(ahc, scb,
 569                              BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 570         return (scb);
 571 }
 572
 573 static void
 574 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
 575 {
 576         struct hardware_scb *q_hscb;
 577         u_int  saved_tag;
 578
 579         /*
 580          * Our queuing method is a bit tricky.  The card
 581          * knows in advance which HSCB to download, and we
 582          * can't disappoint it.  To achieve this, the next
 583          * SCB to download is saved off in ahc->next_queued_scb.
 584          * When we are called to queue "an arbitrary scb",
 585          * we copy the contents of the incoming HSCB to the one
 586          * the sequencer knows about, swap HSCB pointers and
 587          * finally assign the SCB to the tag indexed location
 588          * in the scb_array.  This makes sure that we can still
 589          * locate the correct SCB by SCB_TAG.
 590          */
 591         q_hscb = ahc->next_queued_scb->hscb;
 592         saved_tag = q_hscb->tag;
 593         memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
 594         if ((scb->flags & SCB_CDB32_PTR) != 0) {
 595                 q_hscb->shared_data.cdb_ptr =
 596                     ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
 597                               + offsetof(struct hardware_scb, cdb32));
 598         }
 599         q_hscb->tag = saved_tag;
 600         q_hscb->next = scb->hscb->tag;
 601
 602         /* Now swap HSCB pointers. */
 603         ahc->next_queued_scb->hscb = scb->hscb;
 604         scb->hscb = q_hscb;
 605
 606         /* Now define the mapping from tag to SCB in the scbindex */
 607         ahc->scb_data->scbindex[scb->hscb->tag] = scb;
 608 }
 609
 610 /*
 611  * Tell the sequencer about a new transaction to execute.
 612  */
 613 void
 614 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
 615 {
 616         ahc_swap_with_next_hscb(ahc, scb);
 617
 618         if (scb->hscb->tag == SCB_LIST_NULL
 619          || scb->hscb->next == SCB_LIST_NULL)
 620                 panic("Attempt to queue invalid SCB tag %x:%x\n",
 621                       scb->hscb->tag, scb->hscb->next);
 622
 623         /*
 624          * Setup data "oddness".
 625          */
 626         scb->hscb->lun &= LID;
 627         if (ahc_get_transfer_length(scb) & 0x1)
 628                 scb->hscb->lun |= SCB_XFERLEN_ODD;
 629
 630         /*
 631          * Keep a history of SCBs we've downloaded in the qinfifo.
 632          */
 633         ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
 634
 635         /*
 636          * Make sure our data is consistent from the
 637          * perspective of the adapter.
 638          */
 639         ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 640
 641         /* Tell the adapter about the newly queued SCB */
 642         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
 643                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
 644         } else {
 645                 if ((ahc->features & AHC_AUTOPAUSE) == 0)
 646                         ahc_pause(ahc);
 647                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
 648                 if ((ahc->features & AHC_AUTOPAUSE) == 0)
 649                         ahc_unpause(ahc);
 650         }
 651 }
 652
 653 struct scsi_sense_data *
 654 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
 655 {
 656         int offset;
 657
 658         offset = scb - ahc->scb_data->scbarray;
 659         return (&ahc->scb_data->sense[offset]);
 660 }
 661
 662 static uint32_t
 663 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
 664 {
 665         int offset;
 666
 667         offset = scb - ahc->scb_data->scbarray;
 668         return (ahc->scb_data->sense_busaddr
 669               + (offset * sizeof(struct scsi_sense_data)));
 670 }
 671
 672 /************************** Interrupt Processing ******************************/
 673 static void
 674 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
 675 {
 676         ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
 677                         /*offset*/0, /*len*/256, op);
 678 }
 679
 680 static void
 681 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
 682 {
 683 #ifdef AHC_TARGET_MODE
 684         if ((ahc->flags & AHC_TARGETROLE) != 0) {
 685                 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
 686                                 ahc->shared_data_dmamap,
 687                                 ahc_targetcmd_offset(ahc, 0),
 688                                 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
 689                                 op);
 690         }
 691 #endif
 692 }
 693
 694 /*
 695  * See if the firmware has posted any completed commands
 696  * into our in-core command complete fifos.
 697  */
 698 #define AHC_RUN_QOUTFIFO 0x1
 699 #define AHC_RUN_TQINFIFO 0x2
 700 static u_int
 701 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
 702 {
 703         u_int retval;
 704
 705         retval = 0;
 706         ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
 707                         /*offset*/ahc->qoutfifonext, /*len*/1,
 708                         BUS_DMASYNC_POSTREAD);
 709         if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
 710                 retval |= AHC_RUN_QOUTFIFO;
 711 #ifdef AHC_TARGET_MODE
 712         if ((ahc->flags & AHC_TARGETROLE) != 0
 713          && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
 714                 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
 715                                 ahc->shared_data_dmamap,
 716                                 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext),
 717                                 /*len*/sizeof(struct target_cmd),
 718                                 BUS_DMASYNC_POSTREAD);
 719                 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
 720                         retval |= AHC_RUN_TQINFIFO;
 721         }
 722 #endif
 723         return (retval);
 724 }
 725
 726 /*
 727  * Catch an interrupt from the adapter
 728  */
 729 int
 730 ahc_intr(struct ahc_softc *ahc)
 731 {
 732         u_int   intstat;
 733
 734         if ((ahc->pause & INTEN) == 0) {
 735                 /*
 736                  * Our interrupt is not enabled on the chip
 737                  * and may be disabled for re-entrancy reasons,
 738                  * so just return.  This is likely just a shared
 739                  * interrupt.
 740                  */
 741                 return (0);
 742         }
 743         /*
 744          * Instead of directly reading the interrupt status register,
 745          * infer the cause of the interrupt by checking our in-core
 746          * completion queues.  This avoids a costly PCI bus read in
 747          * most cases.
 748          */
 749         if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
 750          && (ahc_check_cmdcmpltqueues(ahc) != 0))
 751                 intstat = CMDCMPLT;
 752         else {
 753                 intstat = ahc_inb(ahc, INTSTAT);
 754         }
 755
 756         if ((intstat & INT_PEND) == 0) {
 757 #if AHC_PCI_CONFIG > 0
 758                 if (ahc->unsolicited_ints > 500) {
 759                         ahc->unsolicited_ints = 0;
 760                         if ((ahc->chip & AHC_PCI) != 0
 761                          && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
 762                                 ahc->bus_intr(ahc);
 763                 }
 764 #endif
 765                 ahc->unsolicited_ints++;
 766                 return (0);
 767         }
 768         ahc->unsolicited_ints = 0;
 769
 770         if (intstat & CMDCMPLT) {
 771                 ahc_outb(ahc, CLRINT, CLRCMDINT);
 772
 773                 /*
 774                  * Ensure that the chip sees that we've cleared
 775                  * this interrupt before we walk the output fifo.
 776                  * Otherwise, we may, due to posted bus writes,
 777                  * clear the interrupt after we finish the scan,
 778                  * and after the sequencer has added new entries
 779                  * and asserted the interrupt again.
 780                  */
 781                 ahc_flush_device_writes(ahc);
 782                 ahc_run_qoutfifo(ahc);
 783 #ifdef AHC_TARGET_MODE
 784                 if ((ahc->flags & AHC_TARGETROLE) != 0)
 785                         ahc_run_tqinfifo(ahc, /*paused*/FALSE);
 786 #endif
 787         }
 788
 789         /*
 790          * Handle statuses that may invalidate our cached
 791          * copy of INTSTAT separately.
 792          */
 793         if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) {
 794                 /* Hot eject.  Do nothing */
 795         } else if (intstat & BRKADRINT) {
 796                 ahc_handle_brkadrint(ahc);
 797         } else if ((intstat & (SEQINT|SCSIINT)) != 0) {
 798
 799                 ahc_pause_bug_fix(ahc);
 800
 801                 if ((intstat & SEQINT) != 0)
 802                         ahc_handle_seqint(ahc, intstat);
 803
 804                 if ((intstat & SCSIINT) != 0)
 805                         ahc_handle_scsiint(ahc, intstat);
 806         }
 807         return (1);
 808 }
 809
 810 /************************* Sequencer Execution Control ************************/
 811 /*
 812  * Restart the sequencer program from address zero
 813  */
 814 static void
 815 ahc_restart(struct ahc_softc *ahc)
 816 {
 817
 818         ahc_pause(ahc);
 819
 820         /* No more pending messages. */
 821         ahc_clear_msg_state(ahc);
 822
 823         ahc_outb(ahc, SCSISIGO, 0);             /* De-assert BSY */
 824         ahc_outb(ahc, MSG_OUT, MSG_NOOP);       /* No message to send */
 825         ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
 826         ahc_outb(ahc, LASTPHASE, P_BUSFREE);
 827         ahc_outb(ahc, SAVED_SCSIID, 0xFF);
 828         ahc_outb(ahc, SAVED_LUN, 0xFF);
 829
 830         /*
 831          * Ensure that the sequencer's idea of TQINPOS
 832          * matches our own.  The sequencer increments TQINPOS
 833          * only after it sees a DMA complete and a reset could
 834          * occur before the increment leaving the kernel to believe
 835          * the command arrived but the sequencer to not.
 836          */
 837         ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
 838
 839         /* Always allow reselection */
 840         ahc_outb(ahc, SCSISEQ,
 841                  ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
 842         if ((ahc->features & AHC_CMD_CHAN) != 0) {
 843                 /* Ensure that no DMA operations are in progress */
 844                 ahc_outb(ahc, CCSCBCNT, 0);
 845                 ahc_outb(ahc, CCSGCTL, 0);
 846                 ahc_outb(ahc, CCSCBCTL, 0);
 847         }
 848         /*
 849          * If we were in the process of DMA'ing SCB data into
 850          * an SCB, replace that SCB on the free list.  This prevents
 851          * an SCB leak.
 852          */
 853         if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
 854                 ahc_add_curscb_to_free_list(ahc);
 855                 ahc_outb(ahc, SEQ_FLAGS2,
 856                          ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
 857         }
 858
 859         /*
 860          * Clear any pending sequencer interrupt.  It is no
 861          * longer relevant since we're resetting the Program
 862          * Counter.
 863          */
 864         ahc_outb(ahc, CLRINT, CLRSEQINT);
 865
 866         ahc_outb(ahc, MWI_RESIDUAL, 0);
 867         ahc_outb(ahc, SEQCTL, ahc->seqctl);
 868         ahc_outb(ahc, SEQADDR0, 0);
 869         ahc_outb(ahc, SEQADDR1, 0);
 870
 871         ahc_unpause(ahc);
 872 }
 873
 874 /************************* Input/Output Queues ********************************/
 875 static void
 876 ahc_run_qoutfifo(struct ahc_softc *ahc)
 877 {
 878         struct scb *scb;
 879         u_int  scb_index;
 880
 881         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
 882         while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
 883
 884                 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
 885                 if ((ahc->qoutfifonext & 0x03) == 0x03) {
 886                         u_int modnext;
 887
 888                         /*
 889                          * Clear 32bits of QOUTFIFO at a time
 890                          * so that we don't clobber an incoming
 891                          * byte DMA to the array on architectures
 892                          * that only support 32bit load and store
 893                          * operations.
 894                          */
 895                         modnext = ahc->qoutfifonext & ~0x3;
 896                         *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
 897                         ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
 898                                         ahc->shared_data_dmamap,
 899                                         /*offset*/modnext, /*len*/4,
 900                                         BUS_DMASYNC_PREREAD);
 901                 }
 902                 ahc->qoutfifonext++;
 903
 904                 scb = ahc_lookup_scb(ahc, scb_index);
 905                 if (scb == NULL) {
 906                         printf("%s: WARNING no command for scb %d "
 907                                "(cmdcmplt)\nQOUTPOS = %d\n",
 908                                ahc_name(ahc), scb_index,
 909                                (ahc->qoutfifonext - 1) & 0xFF);
 910                         continue;
 911                 }
 912
 913                 /*
 914                  * Save off the residual
 915                  * if there is one.
 916                  */
 917                 ahc_update_residual(ahc, scb);
 918                 ahc_done(ahc, scb);
 919         }
 920 }
 921
 922 static void
 923 ahc_run_untagged_queues(struct ahc_softc *ahc)
 924 {
 925         int i;
 926
 927         for (i = 0; i < 16; i++)
 928                 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
 929 }
 930
 931 static void
 932 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
 933 {
 934         struct scb *scb;
 935
 936         if (ahc->untagged_queue_lock != 0)
 937                 return;
 938
 939         if ((scb = TAILQ_FIRST(queue)) != NULL
 940          && (scb->flags & SCB_ACTIVE) == 0) {
 941                 scb->flags |= SCB_ACTIVE;
 942                 ahc_queue_scb(ahc, scb);
 943         }
 944 }
 945
 946 /************************* Interrupt Handling *********************************/
 947 static void
 948 ahc_handle_brkadrint(struct ahc_softc *ahc)
 949 {
 950         /*
 951          * We upset the sequencer :-(
 952          * Lookup the error message
 953          */
 954         int i;
 955         int error;
 956
 957         error = ahc_inb(ahc, ERROR);
 958         for (i = 0; error != 1 && i < num_errors; i++)
 959                 error >>= 1;
 960         printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
 961                ahc_name(ahc), ahc_hard_errors[i].errmesg,
 962                ahc_inb(ahc, SEQADDR0) |
 963                (ahc_inb(ahc, SEQADDR1) << 8));
 964
 965         ahc_dump_card_state(ahc);
 966
 967         /* Tell everyone that this HBA is no longer available */
 968         ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
 969                        CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
 970                        CAM_NO_HBA);
 971
 972         /* Disable all interrupt sources by resetting the controller */
 973         ahc_shutdown(ahc);
 974 }
 975
 976 static void
 977 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
 978 {
 979         struct scb *scb;
 980         struct ahc_devinfo devinfo;
 981
 982         ahc_fetch_devinfo(ahc, &devinfo);
 983
 984         /*
 985          * Clear the upper byte that holds SEQINT status
 986          * codes and clear the SEQINT bit. We will unpause
 987          * the sequencer, if appropriate, after servicing
 988          * the request.
 989          */
 990         ahc_outb(ahc, CLRINT, CLRSEQINT);
 991         switch (intstat & SEQINT_MASK) {
 992         case BAD_STATUS:
 993         {
 994                 u_int  scb_index;
 995                 struct hardware_scb *hscb;
 996
 997                 /*
 998                  * Set the default return value to 0 (don't
 999                  * send sense).  The sense code will change
1000                  * this if needed.
1001                  */
1002                 ahc_outb(ahc, RETURN_1, 0);
1003
1004                 /*
1005                  * The sequencer will notify us when a command
1006                  * has an error that would be of interest to
1007                  * the kernel.  This allows us to leave the sequencer
1008                  * running in the common case of command completes
1009                  * without error.  The sequencer will already have
1010                  * dma'd the SCB back up to us, so we can reference
1011                  * the in kernel copy directly.
1012                  */
1013                 scb_index = ahc_inb(ahc, SCB_TAG);
1014                 scb = ahc_lookup_scb(ahc, scb_index);
1015                 if (scb == NULL) {
1016                         ahc_print_devinfo(ahc, &devinfo);
1017                         printf("ahc_intr - referenced scb "
1018                                "not valid during seqint 0x%x scb(%d)\n",
1019                                intstat, scb_index);
1020                         ahc_dump_card_state(ahc);
1021                         panic("for safety");
1022                         goto unpause;
1023                 }
1024
1025                 hscb = scb->hscb;
1026
1027                 /* Don't want to clobber the original sense code */
1028                 if ((scb->flags & SCB_SENSE) != 0) {
1029                         /*
1030                          * Clear the SCB_SENSE Flag and have
1031                          * the sequencer do a normal command
1032                          * complete.
1033                          */
1034                         scb->flags &= ~SCB_SENSE;
1035                         ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1036                         break;
1037                 }
1038                 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
1039                 /* Freeze the queue until the client sees the error. */
1040                 ahc_freeze_devq(ahc, scb);
1041                 ahc_freeze_scb(scb);
1042                 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
1043                 switch (hscb->shared_data.status.scsi_status) {
1044                 case SCSI_STATUS_OK:
1045                         printf("%s: Interrupted for staus of 0???\n",
1046                                ahc_name(ahc));
1047                         break;
1048                 case SCSI_STATUS_CMD_TERMINATED:
1049                 case SCSI_STATUS_CHECK_COND:
1050                 {
1051                         struct ahc_dma_seg *sg;
1052                         struct scsi_sense *sc;
1053                         struct ahc_initiator_tinfo *targ_info;
1054                         struct ahc_tmode_tstate *tstate;
1055                         struct ahc_transinfo *tinfo;
1056 #ifdef AHC_DEBUG
1057                         if (ahc_debug & AHC_SHOW_SENSE) {
1058                                 ahc_print_path(ahc, scb);
1059                                 printf("SCB %d: requests Check Status\n",
1060                                        scb->hscb->tag);
1061                         }
1062 #endif
1063
1064                         if (ahc_perform_autosense(scb) == 0)
1065                                 break;
1066
1067                         targ_info = ahc_fetch_transinfo(ahc,
1068                                                         devinfo.channel,
1069                                                         devinfo.our_scsiid,
1070                                                         devinfo.target,
1071                                                         &tstate);
1072                         tinfo = &targ_info->curr;
1073                         sg = scb->sg_list;
1074                         sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
1075                         /*
1076                          * Save off the residual if there is one.
1077                          */
1078                         ahc_update_residual(ahc, scb);
1079 #ifdef AHC_DEBUG
1080                         if (ahc_debug & AHC_SHOW_SENSE) {
1081                                 ahc_print_path(ahc, scb);
1082                                 printf("Sending Sense\n");
1083                         }
1084 #endif
1085                         sg->addr = ahc_get_sense_bufaddr(ahc, scb);
1086                         sg->len = ahc_get_sense_bufsize(ahc, scb);
1087                         sg->len |= AHC_DMA_LAST_SEG;
1088
1089                         /* Fixup byte order */
1090                         sg->addr = ahc_htole32(sg->addr);
1091                         sg->len = ahc_htole32(sg->len);
1092
1093                         sc->opcode = REQUEST_SENSE;
1094                         sc->byte2 = 0;
1095                         if (tinfo->protocol_version <= SCSI_REV_2
1096                          && SCB_GET_LUN(scb) < 8)
1097                                 sc->byte2 = SCB_GET_LUN(scb) << 5;
1098                         sc->unused[0] = 0;
1099                         sc->unused[1] = 0;
1100                         sc->length = sg->len;
1101                         sc->control = 0;
1102
1103                         /*
1104                          * We can't allow the target to disconnect.
1105                          * This will be an untagged transaction and
1106                          * having the target disconnect will make this
1107                          * transaction indestinguishable from outstanding
1108                          * tagged transactions.
1109                          */
1110                         hscb->control = 0;
1111
1112                         /*
1113                          * This request sense could be because the
1114                          * the device lost power or in some other
1115                          * way has lost our transfer negotiations.
1116                          * Renegotiate if appropriate.  Unit attention
1117                          * errors will be reported before any data
1118                          * phases occur.
1119                          */
1120                         if (ahc_get_residual(scb)
1121                          == ahc_get_transfer_length(scb)) {
1122                                 ahc_update_neg_request(ahc, &devinfo,
1123                                                        tstate, targ_info,
1124                                                        AHC_NEG_IF_NON_ASYNC);
1125                         }
1126                         if (tstate->auto_negotiate & devinfo.target_mask) {
1127                                 hscb->control |= MK_MESSAGE;
1128                                 scb->flags &= ~SCB_NEGOTIATE;
1129                                 scb->flags |= SCB_AUTO_NEGOTIATE;
1130                         }
1131                         hscb->cdb_len = sizeof(*sc);
1132                         hscb->dataptr = sg->addr;
1133                         hscb->datacnt = sg->len;
1134                         hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
1135                         hscb->sgptr = ahc_htole32(hscb->sgptr);
1136                         scb->sg_count = 1;
1137                         scb->flags |= SCB_SENSE;
1138                         ahc_qinfifo_requeue_tail(ahc, scb);
1139                         ahc_outb(ahc, RETURN_1, SEND_SENSE);
1140                         /*
1141                          * Ensure we have enough time to actually
1142                          * retrieve the sense.
1143                          */
1144                         ahc_scb_timer_reset(scb, 5 * 1000000);
1145                         break;
1146                 }
1147                 default:
1148                         break;
1149                 }
1150                 break;
1151         }
1152         case NO_MATCH:
1153         {
1154                 /* Ensure we don't leave the selection hardware on */
1155                 ahc_outb(ahc, SCSISEQ,
1156                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1157
1158                 printf("%s:%c:%d: no active SCB for reconnecting "
1159                        "target - issuing BUS DEVICE RESET\n",
1160                        ahc_name(ahc), devinfo.channel, devinfo.target);
1161                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1162                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
1163                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1164                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1165                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1166                        "SINDEX == 0x%x\n",
1167                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1168                        ahc_index_busy_tcl(ahc,
1169                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1170                                       ahc_inb(ahc, SAVED_LUN))),
1171                        ahc_inb(ahc, SINDEX));
1172                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1173                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1174                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1175                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1176                        ahc_inb(ahc, SCB_CONTROL));
1177                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1178                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1179                 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
1180                 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
1181                 ahc_dump_card_state(ahc);
1182                 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
1183                 ahc->msgout_len = 1;
1184                 ahc->msgout_index = 0;
1185                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1186                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
1187                 ahc_assert_atn(ahc);
1188                 break;
1189         }
1190         case SEND_REJECT:
1191         {
1192                 u_int rejbyte = ahc_inb(ahc, ACCUM);
1193                 printf("%s:%c:%d: Warning - unknown message received from "
1194                        "target (0x%x).  Rejecting\n",
1195                        ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
1196                 break;
1197         }
1198         case PROTO_VIOLATION:
1199         {
1200                 ahc_handle_proto_violation(ahc);
1201                 break;
1202         }
1203         case IGN_WIDE_RES:
1204                 ahc_handle_ign_wide_residue(ahc, &devinfo);
1205                 break;
1206         case PDATA_REINIT:
1207                 ahc_reinitialize_dataptrs(ahc);
1208                 break;
1209         case BAD_PHASE:
1210         {
1211                 u_int lastphase;
1212
1213                 lastphase = ahc_inb(ahc, LASTPHASE);
1214                 printf("%s:%c:%d: unknown scsi bus phase %x, "
1215                        "lastphase = 0x%x.  Attempting to continue\n",
1216                        ahc_name(ahc), devinfo.channel, devinfo.target,
1217                        lastphase, ahc_inb(ahc, SCSISIGI));
1218                 break;
1219         }
1220         case MISSED_BUSFREE:
1221         {
1222                 u_int lastphase;
1223
1224                 lastphase = ahc_inb(ahc, LASTPHASE);
1225                 printf("%s:%c:%d: Missed busfree. "
1226                        "Lastphase = 0x%x, Curphase = 0x%x\n",
1227                        ahc_name(ahc), devinfo.channel, devinfo.target,
1228                        lastphase, ahc_inb(ahc, SCSISIGI));
1229                 ahc_restart(ahc);
1230                 return;
1231         }
1232         case HOST_MSG_LOOP:
1233         {
1234                 /*
1235                  * The sequencer has encountered a message phase
1236                  * that requires host assistance for completion.
1237                  * While handling the message phase(s), we will be
1238                  * notified by the sequencer after each byte is
1239                  * transfered so we can track bus phase changes.
1240                  *
1241                  * If this is the first time we've seen a HOST_MSG_LOOP
1242                  * interrupt, initialize the state of the host message
1243                  * loop.
1244                  */
1245                 if (ahc->msg_type == MSG_TYPE_NONE) {
1246                         struct scb *scb;
1247                         u_int scb_index;
1248                         u_int bus_phase;
1249
1250                         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1251                         if (bus_phase != P_MESGIN
1252                          && bus_phase != P_MESGOUT) {
1253                                 printf("ahc_intr: HOST_MSG_LOOP bad "
1254                                        "phase 0x%x\n",
1255                                       bus_phase);
1256                                 /*
1257                                  * Probably transitioned to bus free before
1258                                  * we got here.  Just punt the message.
1259                                  */
1260                                 ahc_clear_intstat(ahc);
1261                                 ahc_restart(ahc);
1262                                 return;
1263                         }
1264
1265                         scb_index = ahc_inb(ahc, SCB_TAG);
1266                         scb = ahc_lookup_scb(ahc, scb_index);
1267                         if (devinfo.role == ROLE_INITIATOR) {
1268                                 if (bus_phase == P_MESGOUT) {
1269                                         if (scb == NULL)
1270                                                 panic("HOST_MSG_LOOP with "
1271                                                       "invalid SCB %x\n",
1272                                                       scb_index);
1273
1274                                         ahc_setup_initiator_msgout(ahc,
1275                                                                    &devinfo,
1276                                                                    scb);
1277                                 } else {
1278                                         ahc->msg_type =
1279                                             MSG_TYPE_INITIATOR_MSGIN;
1280                                         ahc->msgin_index = 0;
1281                                 }
1282                         }
1283 #ifdef AHC_TARGET_MODE
1284                         else {
1285                                 if (bus_phase == P_MESGOUT) {
1286                                         ahc->msg_type =
1287                                             MSG_TYPE_TARGET_MSGOUT;
1288                                         ahc->msgin_index = 0;
1289                                 }
1290                                 else
1291                                         ahc_setup_target_msgin(ahc,
1292                                                                &devinfo,
1293                                                                scb);
1294                         }
1295 #endif
1296                 }
1297
1298                 ahc_handle_message_phase(ahc);
1299                 break;
1300         }
1301         case PERR_DETECTED:
1302         {
1303                 /*
1304                  * If we've cleared the parity error interrupt
1305                  * but the sequencer still believes that SCSIPERR
1306                  * is true, it must be that the parity error is
1307                  * for the currently presented byte on the bus,
1308                  * and we are not in a phase (data-in) where we will
1309                  * eventually ack this byte.  Ack the byte and
1310                  * throw it away in the hope that the target will
1311                  * take us to message out to deliver the appropriate
1312                  * error message.
1313                  */
1314                 if ((intstat & SCSIINT) == 0
1315                  && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
1316
1317                         if ((ahc->features & AHC_DT) == 0) {
1318                                 u_int curphase;
1319
1320                                 /*
1321                                  * The hardware will only let you ack bytes
1322                                  * if the expected phase in SCSISIGO matches
1323                                  * the current phase.  Make sure this is
1324                                  * currently the case.
1325                                  */
1326                                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1327                                 ahc_outb(ahc, LASTPHASE, curphase);
1328                                 ahc_outb(ahc, SCSISIGO, curphase);
1329                         }
1330                         if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
1331                                 int wait;
1332
1333                                 /*
1334                                  * In a data phase.  Faster to bitbucket
1335                                  * the data than to individually ack each
1336                                  * byte.  This is also the only strategy
1337                                  * that will work with AUTOACK enabled.
1338                                  */
1339                                 ahc_outb(ahc, SXFRCTL1,
1340                                          ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
1341                                 wait = 5000;
1342                                 while (--wait != 0) {
1343                                         if ((ahc_inb(ahc, SCSISIGI)
1344                                           & (CDI|MSGI)) != 0)
1345                                                 break;
1346                                         ahc_delay(100);
1347                                 }
1348                                 ahc_outb(ahc, SXFRCTL1,
1349                                          ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
1350                                 if (wait == 0) {
1351                                         struct  scb *scb;
1352                                         u_int   scb_index;
1353
1354                                         ahc_print_devinfo(ahc, &devinfo);
1355                                         printf("Unable to clear parity error.  "
1356                                                "Resetting bus.\n");
1357                                         scb_index = ahc_inb(ahc, SCB_TAG);
1358                                         scb = ahc_lookup_scb(ahc, scb_index);
1359                                         if (scb != NULL)
1360                                                 ahc_set_transaction_status(scb,
1361                                                     CAM_UNCOR_PARITY);
1362                                         ahc_reset_channel(ahc, devinfo.channel,
1363                                                           /*init reset*/TRUE);
1364                                 }
1365                         } else {
1366                                 ahc_inb(ahc, SCSIDATL);
1367                         }
1368                 }
1369                 break;
1370         }
1371         case DATA_OVERRUN:
1372         {
1373                 /*
1374                  * When the sequencer detects an overrun, it
1375                  * places the controller in "BITBUCKET" mode
1376                  * and allows the target to complete its transfer.
1377                  * Unfortunately, none of the counters get updated
1378                  * when the controller is in this mode, so we have
1379                  * no way of knowing how large the overrun was.
1380                  */
1381                 u_int scbindex = ahc_inb(ahc, SCB_TAG);
1382                 u_int lastphase = ahc_inb(ahc, LASTPHASE);
1383                 u_int i;
1384
1385                 scb = ahc_lookup_scb(ahc, scbindex);
1386                 for (i = 0; i < num_phases; i++) {
1387                         if (lastphase == ahc_phase_table[i].phase)
1388                                 break;
1389                 }
1390                 ahc_print_path(ahc, scb);
1391                 printf("data overrun detected %s."
1392                        "  Tag == 0x%x.\n",
1393                        ahc_phase_table[i].phasemsg,
1394                        scb->hscb->tag);
1395                 ahc_print_path(ahc, scb);
1396                 printf("%s seen Data Phase.  Length = %ld.  NumSGs = %d.\n",
1397                        ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
1398                        ahc_get_transfer_length(scb), scb->sg_count);
1399                 if (scb->sg_count > 0) {
1400                         for (i = 0; i < scb->sg_count; i++) {
1401
1402                                 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1403                                        i,
1404                                        (ahc_le32toh(scb->sg_list[i].len) >> 24
1405                                         & SG_HIGH_ADDR_BITS),
1406                                        ahc_le32toh(scb->sg_list[i].addr),
1407                                        ahc_le32toh(scb->sg_list[i].len)
1408                                        & AHC_SG_LEN_MASK);
1409                         }
1410                 }
1411                 /*
1412                  * Set this and it will take effect when the
1413                  * target does a command complete.
1414                  */
1415                 ahc_freeze_devq(ahc, scb);
1416                 if ((scb->flags & SCB_SENSE) == 0) {
1417                         ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1418                 } else {
1419                         scb->flags &= ~SCB_SENSE;
1420                         ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
1421                 }
1422                 ahc_freeze_scb(scb);
1423
1424                 if ((ahc->features & AHC_ULTRA2) != 0) {
1425                         /*
1426                          * Clear the channel in case we return
1427                          * to data phase later.
1428                          */
1429                         ahc_outb(ahc, SXFRCTL0,
1430                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1431                         ahc_outb(ahc, SXFRCTL0,
1432                                  ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
1433                 }
1434                 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
1435                         u_int dscommand1;
1436
1437                         /* Ensure HHADDR is 0 for future DMA operations. */
1438                         dscommand1 = ahc_inb(ahc, DSCOMMAND1);
1439                         ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
1440                         ahc_outb(ahc, HADDR, 0);
1441                         ahc_outb(ahc, DSCOMMAND1, dscommand1);
1442                 }
1443                 break;
1444         }
1445         case MKMSG_FAILED:
1446         {
1447                 u_int scbindex;
1448
1449                 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1450                        ahc_name(ahc), devinfo.channel, devinfo.target,
1451                        devinfo.lun);
1452                 scbindex = ahc_inb(ahc, SCB_TAG);
1453                 scb = ahc_lookup_scb(ahc, scbindex);
1454                 if (scb != NULL
1455                  && (scb->flags & SCB_RECOVERY_SCB) != 0)
1456                         /*
1457                          * Ensure that we didn't put a second instance of this
1458                          * SCB into the QINFIFO.
1459                          */
1460                         ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
1461                                            SCB_GET_CHANNEL(ahc, scb),
1462                                            SCB_GET_LUN(scb), scb->hscb->tag,
1463                                            ROLE_INITIATOR, /*status*/0,
1464                                            SEARCH_REMOVE);
1465                 break;
1466         }
1467         case NO_FREE_SCB:
1468         {
1469                 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
1470                 ahc_dump_card_state(ahc);
1471                 panic("for safety");
1472                 break;
1473         }
1474         case SCB_MISMATCH:
1475         {
1476                 u_int scbptr;
1477
1478                 scbptr = ahc_inb(ahc, SCBPTR);
1479                 printf("Bogus TAG after DMA.  SCBPTR %d, tag %d, our tag %d\n",
1480                        scbptr, ahc_inb(ahc, ARG_1),
1481                        ahc->scb_data->hscbs[scbptr].tag);
1482                 ahc_dump_card_state(ahc);
1483                 panic("for saftey");
1484                 break;
1485         }
1486         case OUT_OF_RANGE:
1487         {
1488                 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
1489                 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1490                        "ARG_1 == 0x%x ACCUM = 0x%x\n",
1491                        ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
1492                        ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
1493                 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1494                        "SINDEX == 0x%x\n, A == 0x%x\n",
1495                        ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
1496                        ahc_index_busy_tcl(ahc,
1497                             BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
1498                                       ahc_inb(ahc, SAVED_LUN))),
1499                        ahc_inb(ahc, SINDEX),
1500                        ahc_inb(ahc, ACCUM));
1501                 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1502                        "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
1503                        ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
1504                        ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
1505                        ahc_inb(ahc, SCB_CONTROL));
1506                 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
1507                        ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
1508                 ahc_dump_card_state(ahc);
1509                 panic("for safety");
1510                 break;
1511         }
1512         default:
1513                 printf("ahc_intr: seqint, "
1514                        "intstat == 0x%x, scsisigi = 0x%x\n",
1515                        intstat, ahc_inb(ahc, SCSISIGI));
1516                 break;
1517         }
1518 unpause:
1519         /*
1520          *  The sequencer is paused immediately on
1521          *  a SEQINT, so we should restart it when
1522          *  we're done.
1523          */
1524         ahc_unpause(ahc);
1525 }
1526
1527 static void
1528 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
1529 {
1530         u_int   scb_index;
1531         u_int   status0;
1532         u_int   status;
1533         struct  scb *scb;
1534         char    cur_channel;
1535         char    intr_channel;
1536
1537         if ((ahc->features & AHC_TWIN) != 0
1538          && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
1539                 cur_channel = 'B';
1540         else
1541                 cur_channel = 'A';
1542         intr_channel = cur_channel;
1543
1544         if ((ahc->features & AHC_ULTRA2) != 0)
1545                 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
1546         else
1547                 status0 = 0;
1548         status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1549         if (status == 0 && status0 == 0) {
1550                 if ((ahc->features & AHC_TWIN) != 0) {
1551                         /* Try the other channel */
1552                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1553                         status = ahc_inb(ahc, SSTAT1)
1554                                & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1555                         intr_channel = (cur_channel == 'A') ? 'B' : 'A';
1556                 }
1557                 if (status == 0) {
1558                         printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
1559                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
1560                         ahc_unpause(ahc);
1561                         return;
1562                 }
1563         }
1564
1565         /* Make sure the sequencer is in a safe location. */
1566         ahc_clear_critical_section(ahc);
1567
1568         scb_index = ahc_inb(ahc, SCB_TAG);
1569         scb = ahc_lookup_scb(ahc, scb_index);
1570         if (scb != NULL
1571          && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1572                 scb = NULL;
1573
1574         if ((ahc->features & AHC_ULTRA2) != 0
1575          && (status0 & IOERR) != 0) {
1576                 int now_lvd;
1577
1578                 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1579                 printf("%s: Transceiver State Has Changed to %s mode\n",
1580                        ahc_name(ahc), now_lvd ? "LVD" : "SE");
1581                 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1582                 /*
1583                  * When transitioning to SE mode, the reset line
1584                  * glitches, triggering an arbitration bug in some
1585                  * Ultra2 controllers.  This bug is cleared when we
1586                  * assert the reset line.  Since a reset glitch has
1587                  * already occurred with this transition and a
1588                  * transceiver state change is handled just like
1589                  * a bus reset anyway, asserting the reset line
1590                  * ourselves is safe.
1591                  */
1592                 ahc_reset_channel(ahc, intr_channel,
1593                                  /*Initiate Reset*/now_lvd == 0);
1594         } else if ((status & SCSIRSTI) != 0) {
1595                 printf("%s: Someone reset channel %c\n",
1596                         ahc_name(ahc), intr_channel);
1597                 if (intr_channel != cur_channel)
1598                         ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1599                 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1600         } else if ((status & SCSIPERR) != 0) {
1601                 /*
1602                  * Determine the bus phase and queue an appropriate message.
1603                  * SCSIPERR is latched true as soon as a parity error
1604                  * occurs.  If the sequencer acked the transfer that
1605                  * caused the parity error and the currently presented
1606                  * transfer on the bus has correct parity, SCSIPERR will
1607                  * be cleared by CLRSCSIPERR.  Use this to determine if
1608                  * we should look at the last phase the sequencer recorded,
1609                  * or the current phase presented on the bus.
1610                  */
1611                 struct  ahc_devinfo devinfo;
1612                 u_int   mesg_out;
1613                 u_int   curphase;
1614                 u_int   errorphase;
1615                 u_int   lastphase;
1616                 u_int   scsirate;
1617                 u_int   i;
1618                 u_int   sstat2;
1619                 int     silent;
1620
1621                 lastphase = ahc_inb(ahc, LASTPHASE);
1622                 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1623                 sstat2 = ahc_inb(ahc, SSTAT2);
1624                 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1625                 /*
1626                  * For all phases save DATA, the sequencer won't
1627                  * automatically ack a byte that has a parity error
1628                  * in it.  So the only way that the current phase
1629                  * could be 'data-in' is if the parity error is for
1630                  * an already acked byte in the data phase.  During
1631                  * synchronous data-in transfers, we may actually
1632                  * ack bytes before latching the current phase in
1633                  * LASTPHASE, leading to the discrepancy between
1634                  * curphase and lastphase.
1635                  */
1636                 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1637                  || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1638                         errorphase = curphase;
1639                 else
1640                         errorphase = lastphase;
1641
1642                 for (i = 0; i < num_phases; i++) {
1643                         if (errorphase == ahc_phase_table[i].phase)
1644                                 break;
1645                 }
1646                 mesg_out = ahc_phase_table[i].mesg_out;
1647                 silent = FALSE;
1648                 if (scb != NULL) {
1649                         if (SCB_IS_SILENT(scb))
1650                                 silent = TRUE;
1651                         else
1652                                 ahc_print_path(ahc, scb);
1653                         scb->flags |= SCB_TRANSMISSION_ERROR;
1654                 } else
1655                         printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1656                                SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1657                 scsirate = ahc_inb(ahc, SCSIRATE);
1658                 if (silent == FALSE) {
1659                         printf("parity error detected %s. "
1660                                "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1661                                ahc_phase_table[i].phasemsg,
1662                                ahc_inw(ahc, SEQADDR0),
1663                                scsirate);
1664                         if ((ahc->features & AHC_DT) != 0) {
1665                                 if ((sstat2 & CRCVALERR) != 0)
1666                                         printf("\tCRC Value Mismatch\n");
1667                                 if ((sstat2 & CRCENDERR) != 0)
1668                                         printf("\tNo terminal CRC packet "
1669                                                "recevied\n");
1670                                 if ((sstat2 & CRCREQERR) != 0)
1671                                         printf("\tIllegal CRC packet "
1672                                                "request\n");
1673                                 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1674                                         printf("\tUnexpected %sDT Data Phase\n",
1675                                                (scsirate & SINGLE_EDGE)
1676                                              ? "" : "non-");
1677                         }
1678                 }
1679
1680                 if ((ahc->features & AHC_DT) != 0
1681                  && (sstat2 & DUAL_EDGE_ERR) != 0) {
1682                         /*
1683                          * This error applies regardless of
1684                          * data direction, so ignore the value
1685                          * in the phase table.
1686                          */
1687                         mesg_out = MSG_INITIATOR_DET_ERR;
1688                 }
1689
1690                 /*
1691                  * We've set the hardware to assert ATN if we
1692                  * get a parity error on "in" phases, so all we
1693                  * need to do is stuff the message buffer with
1694                  * the appropriate message.  "In" phases have set
1695                  * mesg_out to something other than MSG_NOP.
1696                  */
1697                 if (mesg_out != MSG_NOOP) {
1698                         if (ahc->msg_type != MSG_TYPE_NONE)
1699                                 ahc->send_msg_perror = TRUE;
1700                         else
1701                                 ahc_outb(ahc, MSG_OUT, mesg_out);
1702                 }
1703                 /*
1704                  * Force a renegotiation with this target just in
1705                  * case we are out of sync for some external reason
1706                  * unknown (or unreported) by the target.
1707                  */
1708                 ahc_fetch_devinfo(ahc, &devinfo);
1709                 ahc_force_renegotiation(ahc, &devinfo);
1710
1711                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1712                 ahc_unpause(ahc);
1713         } else if ((status & SELTO) != 0) {
1714                 u_int   scbptr;
1715
1716                 /* Stop the selection */
1717                 ahc_outb(ahc, SCSISEQ, 0);
1718
1719                 /* No more pending messages */
1720                 ahc_clear_msg_state(ahc);
1721
1722                 /* Clear interrupt state */
1723                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1724                 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1725
1726                 /*
1727                  * Although the driver does not care about the
1728                  * 'Selection in Progress' status bit, the busy
1729                  * LED does.  SELINGO is only cleared by a sucessfull
1730                  * selection, so we must manually clear it to insure
1731                  * the LED turns off just incase no future successful
1732                  * selections occur (e.g. no devices on the bus).
1733                  */
1734                 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1735
1736                 scbptr = ahc_inb(ahc, WAITING_SCBH);
1737                 ahc_outb(ahc, SCBPTR, scbptr);
1738                 scb_index = ahc_inb(ahc, SCB_TAG);
1739
1740                 scb = ahc_lookup_scb(ahc, scb_index);
1741                 if (scb == NULL) {
1742                         printf("%s: ahc_intr - referenced scb not "
1743                                "valid during SELTO scb(%d, %d)\n",
1744                                ahc_name(ahc), scbptr, scb_index);
1745                         ahc_dump_card_state(ahc);
1746                 } else {
1747                         struct ahc_devinfo devinfo;
1748 #ifdef AHC_DEBUG
1749                         if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1750                                 ahc_print_path(ahc, scb);
1751                                 printf("Saw Selection Timeout for SCB 0x%x\n",
1752                                        scb_index);
1753                         }
1754 #endif
1755                         ahc_scb_devinfo(ahc, &devinfo, scb);
1756                         ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1757                         ahc_freeze_devq(ahc, scb);
1758
1759                         /*
1760                          * Cancel any pending transactions on the device
1761                          * now that it seems to be missing.  This will
1762                          * also revert us to async/narrow transfers until
1763                          * we can renegotiate with the device.
1764                          */
1765                         ahc_handle_devreset(ahc, &devinfo,
1766                                             CAM_SEL_TIMEOUT,
1767                                             "Selection Timeout",
1768                                             /*verbose_level*/1);
1769                 }
1770                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1771                 ahc_restart(ahc);
1772         } else if ((status & BUSFREE) != 0
1773                 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1774                 struct  ahc_devinfo devinfo;
1775                 u_int   lastphase;
1776                 u_int   saved_scsiid;
1777                 u_int   saved_lun;
1778                 u_int   target;
1779                 u_int   initiator_role_id;
1780                 char    channel;
1781                 int     printerror;
1782
1783                 /*
1784                  * Clear our selection hardware as soon as possible.
1785                  * We may have an entry in the waiting Q for this target,
1786                  * that is affected by this busfree and we don't want to
1787                  * go about selecting the target while we handle the event.
1788                  */
1789                 ahc_outb(ahc, SCSISEQ,
1790                          ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1791
1792                 /*
1793                  * Disable busfree interrupts and clear the busfree
1794                  * interrupt status.  We do this here so that several
1795                  * bus transactions occur prior to clearing the SCSIINT
1796                  * latch.  It can take a bit for the clearing to take effect.
1797                  */
1798                 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1799                 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1800
1801                 /*
1802                  * Look at what phase we were last in.
1803                  * If its message out, chances are pretty good
1804                  * that the busfree was in response to one of
1805                  * our abort requests.
1806                  */
1807                 lastphase = ahc_inb(ahc, LASTPHASE);
1808                 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1809                 saved_lun = ahc_inb(ahc, SAVED_LUN);
1810                 target = SCSIID_TARGET(ahc, saved_scsiid);
1811                 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1812                 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1813                 ahc_compile_devinfo(&devinfo, initiator_role_id,
1814                                     target, saved_lun, channel, ROLE_INITIATOR);
1815                 printerror = 1;
1816
1817                 if (lastphase == P_MESGOUT) {
1818                         u_int tag;
1819
1820                         tag = SCB_LIST_NULL;
1821                         if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1822                          || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1823                                 if (ahc->msgout_buf[ahc->msgout_index - 1]
1824                                  == MSG_ABORT_TAG)
1825                                         tag = scb->hscb->tag;
1826                                 ahc_print_path(ahc, scb);
1827                                 printf("SCB %d - Abort%s Completed.\n",
1828                                        scb->hscb->tag, tag == SCB_LIST_NULL ?
1829                                        "" : " Tag");
1830                                 ahc_abort_scbs(ahc, target, channel,
1831                                                saved_lun, tag,
1832                                                ROLE_INITIATOR,
1833                                                CAM_REQ_ABORTED);
1834                                 printerror = 0;
1835                         } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1836                                                 MSG_BUS_DEV_RESET, TRUE)) {
1837 #ifdef __FreeBSD__
1838                                 /*
1839                                  * Don't mark the user's request for this BDR
1840                                  * as completing with CAM_BDR_SENT.  CAM3
1841                                  * specifies CAM_REQ_CMP.
1842                                  */
1843                                 if (scb != NULL
1844                                  && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1845                                  && ahc_match_scb(ahc, scb, target, channel,
1846                                                   CAM_LUN_WILDCARD,
1847                                                   SCB_LIST_NULL,
1848                                                   ROLE_INITIATOR)) {
1849                                         ahc_set_transaction_status(scb, CAM_REQ_CMP);
1850                                 }
1851 #endif
1852                                 ahc_compile_devinfo(&devinfo,
1853                                                     initiator_role_id,
1854                                                     target,
1855                                                     CAM_LUN_WILDCARD,
1856                                                     channel,
1857                                                     ROLE_INITIATOR);
1858                                 ahc_handle_devreset(ahc, &devinfo,
1859                                                     CAM_BDR_SENT,
1860                                                     "Bus Device Reset",
1861                                                     /*verbose_level*/0);
1862                                 printerror = 0;
1863                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1864                                                 MSG_EXT_PPR, FALSE)) {
1865                                 struct ahc_initiator_tinfo *tinfo;
1866                                 struct ahc_tmode_tstate *tstate;
1867
1868                                 /*
1869                                  * PPR Rejected.  Try non-ppr negotiation
1870                                  * and retry command.
1871                                  */
1872                                 tinfo = ahc_fetch_transinfo(ahc,
1873                                                             devinfo.channel,
1874                                                             devinfo.our_scsiid,
1875                                                             devinfo.target,
1876                                                             &tstate);
1877                                 tinfo->curr.transport_version = 2;
1878                                 tinfo->goal.transport_version = 2;
1879                                 tinfo->goal.ppr_options = 0;
1880                                 ahc_qinfifo_requeue_tail(ahc, scb);
1881                                 printerror = 0;
1882                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1883                                                 MSG_EXT_WDTR, FALSE)) {
1884                                 /*
1885                                  * Negotiation Rejected.  Go-narrow and
1886                                  * retry command.
1887                                  */
1888                                 ahc_set_width(ahc, &devinfo,
1889                                               MSG_EXT_WDTR_BUS_8_BIT,
1890                                               AHC_TRANS_CUR|AHC_TRANS_GOAL,
1891                                               /*paused*/TRUE);
1892                                 ahc_qinfifo_requeue_tail(ahc, scb);
1893                                 printerror = 0;
1894                         } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1895                                                 MSG_EXT_SDTR, FALSE)) {
1896                                 /*
1897                                  * Negotiation Rejected.  Go-async and
1898                                  * retry command.
1899                                  */
1900                                 ahc_set_syncrate(ahc, &devinfo,
1901                                                 /*syncrate*/NULL,
1902                                                 /*period*/0, /*offset*/0,
1903                                                 /*ppr_options*/0,
1904                                                 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1905                                                 /*paused*/TRUE);
1906                                 ahc_qinfifo_requeue_tail(ahc, scb);
1907                                 printerror = 0;
1908                         }
1909                 }
1910                 if (printerror != 0) {
1911                         u_int i;
1912
1913                         if (scb != NULL) {
1914                                 u_int tag;
1915
1916                                 if ((scb->hscb->control & TAG_ENB) != 0)
1917                                         tag = scb->hscb->tag;
1918                                 else
1919                                         tag = SCB_LIST_NULL;
1920                                 ahc_print_path(ahc, scb);
1921                                 ahc_abort_scbs(ahc, target, channel,
1922                                                SCB_GET_LUN(scb), tag,
1923                                                ROLE_INITIATOR,
1924                                                CAM_UNEXP_BUSFREE);
1925                         } else {
1926                                 /*
1927                                  * We had not fully identified this connection,
1928                                  * so we cannot abort anything.
1929                                  */
1930                                 printf("%s: ", ahc_name(ahc));
1931                         }
1932                         for (i = 0; i < num_phases; i++) {
1933                                 if (lastphase == ahc_phase_table[i].phase)
1934                                         break;
1935                         }
1936                         if (lastphase != P_BUSFREE) {
1937                                 /*
1938                                  * Renegotiate with this device at the
1939                                  * next oportunity just in case this busfree
1940                                  * is due to a negotiation mismatch with the
1941                                  * device.
1942                                  */
1943                                 ahc_force_renegotiation(ahc, &devinfo);
1944                         }
1945                         printf("Unexpected busfree %s\n"
1946                                "SEQADDR == 0x%x\n",
1947                                ahc_phase_table[i].phasemsg,
1948                                ahc_inb(ahc, SEQADDR0)
1949                                 | (ahc_inb(ahc, SEQADDR1) << 8));
1950                 }
1951                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1952                 ahc_restart(ahc);
1953         } else {
1954                 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1955                        ahc_name(ahc), status);
1956                 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1957         }
1958 }
1959
1960 /*
1961  * Force renegotiation to occur the next time we initiate
1962  * a command to the current device.
1963  */
1964 static void
1965 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1966 {
1967         struct  ahc_initiator_tinfo *targ_info;
1968         struct  ahc_tmode_tstate *tstate;
1969
1970         targ_info = ahc_fetch_transinfo(ahc,
1971                                         devinfo->channel,
1972                                         devinfo->our_scsiid,
1973                                         devinfo->target,
1974                                         &tstate);
1975         ahc_update_neg_request(ahc, devinfo, tstate,
1976                                targ_info, AHC_NEG_IF_NON_ASYNC);
1977 }
1978
1979 #define AHC_MAX_STEPS 2000
1980 static void
1981 ahc_clear_critical_section(struct ahc_softc *ahc)
1982 {
1983         int     stepping;
1984         int     steps;
1985         u_int   simode0;
1986         u_int   simode1;
1987
1988         if (ahc->num_critical_sections == 0)
1989                 return;
1990
1991         stepping = FALSE;
1992         steps = 0;
1993         simode0 = 0;
1994         simode1 = 0;
1995         for (;;) {
1996                 struct  cs *cs;
1997                 u_int   seqaddr;
1998                 u_int   i;
1999
2000                 seqaddr = ahc_inb(ahc, SEQADDR0)
2001                         | (ahc_inb(ahc, SEQADDR1) << 8);
2002
2003                 /*
2004                  * Seqaddr represents the next instruction to execute,
2005                  * so we are really executing the instruction just
2006                  * before it.
2007                  */
2008                 if (seqaddr != 0)
2009                         seqaddr -= 1;
2010                 cs = ahc->critical_sections;
2011                 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
2012
2013                         if (cs->begin < seqaddr && cs->end >= seqaddr)
2014                                 break;
2015                 }
2016
2017                 if (i == ahc->num_critical_sections)
2018                         break;
2019
2020                 if (steps > AHC_MAX_STEPS) {
2021                         printf("%s: Infinite loop in critical section\n",
2022                                ahc_name(ahc));
2023                         ahc_dump_card_state(ahc);
2024                         panic("critical section loop");
2025                 }
2026
2027                 steps++;
2028                 if (stepping == FALSE) {
2029
2030                         /*
2031                          * Disable all interrupt sources so that the
2032                          * sequencer will not be stuck by a pausing
2033                          * interrupt condition while we attempt to
2034                          * leave a critical section.
2035                          */
2036                         simode0 = ahc_inb(ahc, SIMODE0);
2037                         ahc_outb(ahc, SIMODE0, 0);
2038                         simode1 = ahc_inb(ahc, SIMODE1);
2039                         if ((ahc->features & AHC_DT) != 0)
2040                                 /*
2041                                  * On DT class controllers, we
2042                                  * use the enhanced busfree logic.
2043                                  * Unfortunately we cannot re-enable
2044                                  * busfree detection within the
2045                                  * current connection, so we must
2046                                  * leave it on while single stepping.
2047                                  */
2048                                 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
2049                         else
2050                                 ahc_outb(ahc, SIMODE1, 0);
2051                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
2052                         ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
2053                         stepping = TRUE;
2054                 }
2055                 if ((ahc->features & AHC_DT) != 0) {
2056                         ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
2057                         ahc_outb(ahc, CLRINT, CLRSCSIINT);
2058                 }
2059                 ahc_outb(ahc, HCNTRL, ahc->unpause);
2060                 while (!ahc_is_paused(ahc))
2061                         ahc_delay(200);
2062         }
2063         if (stepping) {
2064                 ahc_outb(ahc, SIMODE0, simode0);
2065                 ahc_outb(ahc, SIMODE1, simode1);
2066                 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2067         }
2068 }
2069
2070 /*
2071  * Clear any pending interrupt status.
2072  */
2073 static void
2074 ahc_clear_intstat(struct ahc_softc *ahc)
2075 {
2076         /* Clear any interrupt conditions this may have caused */
2077         ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2078                                 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
2079                                 CLRREQINIT);
2080         ahc_flush_device_writes(ahc);
2081         ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
2082         ahc_flush_device_writes(ahc);
2083         ahc_outb(ahc, CLRINT, CLRSCSIINT);
2084         ahc_flush_device_writes(ahc);
2085 }
2086
2087 /**************************** Debugging Routines ******************************/
2088 #ifdef AHC_DEBUG
2089 uint32_t ahc_debug = AHC_DEBUG_OPTS;
2090 #endif
2091
2092 #if 0 /* unused */
2093 static void
2094 ahc_print_scb(struct scb *scb)
2095 {
2096         int i;
2097
2098         struct hardware_scb *hscb = scb->hscb;
2099
2100         printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2101                (void *)scb,
2102                hscb->control,
2103                hscb->scsiid,
2104                hscb->lun,
2105                hscb->cdb_len);
2106         printf("Shared Data: ");
2107         for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
2108                 printf("%#02x", hscb->shared_data.cdb[i]);
2109         printf("        dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
2110                 ahc_le32toh(hscb->dataptr),
2111                 ahc_le32toh(hscb->datacnt),
2112                 ahc_le32toh(hscb->sgptr),
2113                 hscb->tag);
2114         if (scb->sg_count > 0) {
2115                 for (i = 0; i < scb->sg_count; i++) {
2116                         printf("sg[%d] - Addr 0x%x%x : Length %d\n",
2117                                i,
2118                                (ahc_le32toh(scb->sg_list[i].len) >> 24
2119                                 & SG_HIGH_ADDR_BITS),
2120                                ahc_le32toh(scb->sg_list[i].addr),
2121                                ahc_le32toh(scb->sg_list[i].len));
2122                 }
2123         }
2124 }
2125 #endif
2126
2127 /************************* Transfer Negotiation *******************************/
2128 /*
2129  * Allocate per target mode instance (ID we respond to as a target)
2130  * transfer negotiation data structures.
2131  */
2132 static struct ahc_tmode_tstate *
2133 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
2134 {
2135         struct ahc_tmode_tstate *master_tstate;
2136         struct ahc_tmode_tstate *tstate;
2137         int i;
2138
2139         master_tstate = ahc->enabled_targets[ahc->our_id];
2140         if (channel == 'B') {
2141                 scsi_id += 8;
2142                 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
2143         }
2144         if (ahc->enabled_targets[scsi_id] != NULL
2145          && ahc->enabled_targets[scsi_id] != master_tstate)
2146                 panic("%s: ahc_alloc_tstate - Target already allocated",
2147                       ahc_name(ahc));
2148         tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
2149                                                    M_DEVBUF, M_NOWAIT);
2150         if (tstate == NULL)
2151                 return (NULL);
2152
2153         /*
2154          * If we have allocated a master tstate, copy user settings from
2155          * the master tstate (taken from SRAM or the EEPROM) for this
2156          * channel, but reset our current and goal settings to async/narrow
2157          * until an initiator talks to us.
2158          */
2159         if (master_tstate != NULL) {
2160                 memcpy(tstate, master_tstate, sizeof(*tstate));
2161                 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2162                 tstate->ultraenb = 0;
2163                 for (i = 0; i < AHC_NUM_TARGETS; i++) {
2164                         memset(&tstate->transinfo[i].curr, 0,
2165                               sizeof(tstate->transinfo[i].curr));
2166                         memset(&tstate->transinfo[i].goal, 0,
2167                               sizeof(tstate->transinfo[i].goal));
2168                 }
2169         } else
2170                 memset(tstate, 0, sizeof(*tstate));
2171         ahc->enabled_targets[scsi_id] = tstate;
2172         return (tstate);
2173 }
2174
2175 #ifdef AHC_TARGET_MODE
2176 /*
2177  * Free per target mode instance (ID we respond to as a target)
2178  * transfer negotiation data structures.
2179  */
2180 static void
2181 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
2182 {
2183         struct ahc_tmode_tstate *tstate;
2184
2185         /*
2186          * Don't clean up our "master" tstate.
2187          * It has our default user settings.
2188          */
2189         if (((channel == 'B' && scsi_id == ahc->our_id_b)
2190           || (channel == 'A' && scsi_id == ahc->our_id))
2191          && force == FALSE)
2192                 return;
2193
2194         if (channel == 'B')
2195                 scsi_id += 8;
2196         tstate = ahc->enabled_targets[scsi_id];
2197         if (tstate != NULL)
2198                 free(tstate, M_DEVBUF);
2199         ahc->enabled_targets[scsi_id] = NULL;
2200 }
2201 #endif
2202
2203 /*
2204  * Called when we have an active connection to a target on the bus,
2205  * this function finds the nearest syncrate to the input period limited
2206  * by the capabilities of the bus connectivity of and sync settings for
2207  * the target.
2208  */
2209 const struct ahc_syncrate *
2210 ahc_devlimited_syncrate(struct ahc_softc *ahc,
2211                         struct ahc_initiator_tinfo *tinfo,
2212                         u_int *period, u_int *ppr_options, role_t role)
2213 {
2214         struct  ahc_transinfo *transinfo;
2215         u_int   maxsync;
2216
2217         if ((ahc->features & AHC_ULTRA2) != 0) {
2218                 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
2219                  && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
2220                         maxsync = AHC_SYNCRATE_DT;
2221                 } else {
2222                         maxsync = AHC_SYNCRATE_ULTRA;
2223                         /* Can't do DT on an SE bus */
2224                         *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2225                 }
2226         } else if ((ahc->features & AHC_ULTRA) != 0) {
2227                 maxsync = AHC_SYNCRATE_ULTRA;
2228         } else {
2229                 maxsync = AHC_SYNCRATE_FAST;
2230         }
2231         /*
2232          * Never allow a value higher than our current goal
2233          * period otherwise we may allow a target initiated
2234          * negotiation to go above the limit as set by the
2235          * user.  In the case of an initiator initiated
2236          * sync negotiation, we limit based on the user
2237          * setting.  This allows the system to still accept
2238          * incoming negotiations even if target initiated
2239          * negotiation is not performed.
2240          */
2241         if (role == ROLE_TARGET)
2242                 transinfo = &tinfo->user;
2243         else
2244                 transinfo = &tinfo->goal;
2245         *ppr_options &= transinfo->ppr_options;
2246         if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2247                 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2);
2248                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2249         }
2250         if (transinfo->period == 0) {
2251                 *period = 0;
2252                 *ppr_options = 0;
2253                 return (NULL);
2254         }
2255         *period = max(*period, (u_int)transinfo->period);
2256         return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
2257 }
2258
2259 /*
2260  * Look up the valid period to SCSIRATE conversion in our table.
2261  * Return the period and offset that should be sent to the target
2262  * if this was the beginning of an SDTR.
2263  */
2264 const struct ahc_syncrate *
2265 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
2266                   u_int *ppr_options, u_int maxsync)
2267 {
2268         const struct ahc_syncrate *syncrate;
2269
2270         if ((ahc->features & AHC_DT) == 0)
2271                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2272
2273         /* Skip all DT only entries if DT is not available */
2274         if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2275          && maxsync < AHC_SYNCRATE_ULTRA2)
2276                 maxsync = AHC_SYNCRATE_ULTRA2;
2277
2278         /* Now set the maxsync based on the card capabilities
2279          * DT is already done above */
2280         if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2281             && maxsync < AHC_SYNCRATE_ULTRA)
2282                 maxsync = AHC_SYNCRATE_ULTRA;
2283         if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2284             && maxsync < AHC_SYNCRATE_FAST)
2285                 maxsync = AHC_SYNCRATE_FAST;
2286
2287         for (syncrate = &ahc_syncrates[maxsync];
2288              syncrate->rate != NULL;
2289              syncrate++) {
2290
2291                 /*
2292                  * The Ultra2 table doesn't go as low
2293                  * as for the Fast/Ultra cards.
2294                  */
2295                 if ((ahc->features & AHC_ULTRA2) != 0
2296                  && (syncrate->sxfr_u2 == 0))
2297                         break;
2298
2299                 if (*period <= syncrate->period) {
2300                         /*
2301                          * When responding to a target that requests
2302                          * sync, the requested rate may fall between
2303                          * two rates that we can output, but still be
2304                          * a rate that we can receive.  Because of this,
2305                          * we want to respond to the target with
2306                          * the same rate that it sent to us even
2307                          * if the period we use to send data to it
2308                          * is lower.  Only lower the response period
2309                          * if we must.
2310                          */
2311                         if (syncrate == &ahc_syncrates[maxsync])
2312                                 *period = syncrate->period;
2313
2314                         /*
2315                          * At some speeds, we only support
2316                          * ST transfers.
2317                          */
2318                         if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
2319                                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2320                         break;
2321                 }
2322         }
2323
2324         if ((*period == 0)
2325          || (syncrate->rate == NULL)
2326          || ((ahc->features & AHC_ULTRA2) != 0
2327           && (syncrate->sxfr_u2 == 0))) {
2328                 /* Use asynchronous transfers. */
2329                 *period = 0;
2330                 syncrate = NULL;
2331                 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2332         }
2333         return (syncrate);
2334 }
2335
2336 /*
2337  * Convert from an entry in our syncrate table to the SCSI equivalent
2338  * sync "period" factor.
2339  */
2340 u_int
2341 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
2342 {
2343         const struct ahc_syncrate *syncrate;
2344
2345         if ((ahc->features & AHC_ULTRA2) != 0)
2346                 scsirate &= SXFR_ULTRA2;
2347         else
2348                 scsirate &= SXFR;
2349
2350         /* now set maxsync based on card capabilities */
2351         if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2)
2352                 maxsync = AHC_SYNCRATE_ULTRA2;
2353         if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0
2354             && maxsync < AHC_SYNCRATE_ULTRA)
2355                 maxsync = AHC_SYNCRATE_ULTRA;
2356         if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0
2357             && maxsync < AHC_SYNCRATE_FAST)
2358                 maxsync = AHC_SYNCRATE_FAST;
2359
2360
2361         syncrate = &ahc_syncrates[maxsync];
2362         while (syncrate->rate != NULL) {
2363
2364                 if ((ahc->features & AHC_ULTRA2) != 0) {
2365                         if (syncrate->sxfr_u2 == 0)
2366                                 break;
2367                         else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
2368                                 return (syncrate->period);
2369                 } else if (scsirate == (syncrate->sxfr & SXFR)) {
2370                                 return (syncrate->period);
2371                 }
2372                 syncrate++;
2373         }
2374         return (0); /* async */
2375 }
2376
2377 /*
2378  * Truncate the given synchronous offset to a value the
2379  * current adapter type and syncrate are capable of.
2380  */
2381 static void
2382 ahc_validate_offset(struct ahc_softc *ahc,
2383                     struct ahc_initiator_tinfo *tinfo,
2384                     const struct ahc_syncrate *syncrate,
2385                     u_int *offset, int wide, role_t role)
2386 {
2387         u_int maxoffset;
2388
2389         /* Limit offset to what we can do */
2390         if (syncrate == NULL) {
2391                 maxoffset = 0;
2392         } else if ((ahc->features & AHC_ULTRA2) != 0) {
2393                 maxoffset = MAX_OFFSET_ULTRA2;
2394         } else {
2395                 if (wide)
2396                         maxoffset = MAX_OFFSET_16BIT;
2397                 else
2398                         maxoffset = MAX_OFFSET_8BIT;
2399         }
2400         *offset = min(*offset, maxoffset);
2401         if (tinfo != NULL) {
2402                 if (role == ROLE_TARGET)
2403                         *offset = min(*offset, (u_int)tinfo->user.offset);
2404                 else
2405                         *offset = min(*offset, (u_int)tinfo->goal.offset);
2406         }
2407 }
2408
2409 /*
2410  * Truncate the given transfer width parameter to a value the
2411  * current adapter type is capable of.
2412  */
2413 static void
2414 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
2415                    u_int *bus_width, role_t role)
2416 {
2417         switch (*bus_width) {
2418         default:
2419                 if (ahc->features & AHC_WIDE) {
2420                         /* Respond Wide */
2421                         *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2422                         break;
2423                 }
2424                 /* FALLTHROUGH */
2425         case MSG_EXT_WDTR_BUS_8_BIT:
2426                 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2427                 break;
2428         }
2429         if (tinfo != NULL) {
2430                 if (role == ROLE_TARGET)
2431                         *bus_width = min((u_int)tinfo->user.width, *bus_width);
2432                 else
2433                         *bus_width = min((u_int)tinfo->goal.width, *bus_width);
2434         }
2435 }
2436
2437 /*
2438  * Update the bitmask of targets for which the controller should
2439  * negotiate with at the next convenient oportunity.  This currently
2440  * means the next time we send the initial identify messages for
2441  * a new transaction.
2442  */
2443 int
2444 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2445                        struct ahc_tmode_tstate *tstate,
2446                        struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
2447 {
2448         u_int auto_negotiate_orig;
2449
2450         auto_negotiate_orig = tstate->auto_negotiate;
2451         if (neg_type == AHC_NEG_ALWAYS) {
2452                 /*
2453                  * Force our "current" settings to be
2454                  * unknown so that unless a bus reset
2455                  * occurs the need to renegotiate is
2456                  * recorded persistently.
2457                  */
2458                 if ((ahc->features & AHC_WIDE) != 0)
2459                         tinfo->curr.width = AHC_WIDTH_UNKNOWN;
2460                 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
2461                 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
2462         }
2463         if (tinfo->curr.period != tinfo->goal.period
2464          || tinfo->curr.width != tinfo->goal.width
2465          || tinfo->curr.offset != tinfo->goal.offset
2466          || tinfo->curr.ppr_options != tinfo->goal.ppr_options
2467          || (neg_type == AHC_NEG_IF_NON_ASYNC
2468           && (tinfo->goal.offset != 0
2469            || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
2470            || tinfo->goal.ppr_options != 0)))
2471                 tstate->auto_negotiate |= devinfo->target_mask;
2472         else
2473                 tstate->auto_negotiate &= ~devinfo->target_mask;
2474
2475         return (auto_negotiate_orig != tstate->auto_negotiate);
2476 }
2477
2478 /*
2479  * Update the user/goal/curr tables of synchronous negotiation
2480  * parameters as well as, in the case of a current or active update,
2481  * any data structures on the host controller.  In the case of an
2482  * active update, the specified target is currently talking to us on
2483  * the bus, so the transfer parameter update must take effect
2484  * immediately.
2485  */
2486 void
2487 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2488                  const struct ahc_syncrate *syncrate, u_int period,
2489                  u_int offset, u_int ppr_options, u_int type, int paused)
2490 {
2491         struct  ahc_initiator_tinfo *tinfo;
2492         struct  ahc_tmode_tstate *tstate;
2493         u_int   old_period;
2494         u_int   old_offset;
2495         u_int   old_ppr;
2496         int     active;
2497         int     update_needed;
2498
2499         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2500         update_needed = 0;
2501
2502         if (syncrate == NULL) {
2503                 period = 0;
2504                 offset = 0;
2505         }
2506
2507         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2508                                     devinfo->target, &tstate);
2509
2510         if ((type & AHC_TRANS_USER) != 0) {
2511                 tinfo->user.period = period;
2512                 tinfo->user.offset = offset;
2513                 tinfo->user.ppr_options = ppr_options;
2514         }
2515
2516         if ((type & AHC_TRANS_GOAL) != 0) {
2517                 tinfo->goal.period = period;
2518                 tinfo->goal.offset = offset;
2519                 tinfo->goal.ppr_options = ppr_options;
2520         }
2521
2522         old_period = tinfo->curr.period;
2523         old_offset = tinfo->curr.offset;
2524         old_ppr    = tinfo->curr.ppr_options;
2525
2526         if ((type & AHC_TRANS_CUR) != 0
2527          && (old_period != period
2528           || old_offset != offset
2529           || old_ppr != ppr_options)) {
2530                 u_int   scsirate;
2531
2532                 update_needed++;
2533                 scsirate = tinfo->scsirate;
2534                 if ((ahc->features & AHC_ULTRA2) != 0) {
2535
2536                         scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
2537                         if (syncrate != NULL) {
2538                                 scsirate |= syncrate->sxfr_u2;
2539                                 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
2540                                         scsirate |= ENABLE_CRC;
2541                                 else
2542                                         scsirate |= SINGLE_EDGE;
2543                         }
2544                 } else {
2545
2546                         scsirate &= ~(SXFR|SOFS);
2547                         /*
2548                          * Ensure Ultra mode is set properly for
2549                          * this target.
2550                          */
2551                         tstate->ultraenb &= ~devinfo->target_mask;
2552                         if (syncrate != NULL) {
2553                                 if (syncrate->sxfr & ULTRA_SXFR) {
2554                                         tstate->ultraenb |=
2555                                                 devinfo->target_mask;
2556                                 }
2557                                 scsirate |= syncrate->sxfr & SXFR;
2558                                 scsirate |= offset & SOFS;
2559                         }
2560                         if (active) {
2561                                 u_int sxfrctl0;
2562
2563                                 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
2564                                 sxfrctl0 &= ~FAST20;
2565                                 if (tstate->ultraenb & devinfo->target_mask)
2566                                         sxfrctl0 |= FAST20;
2567                                 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
2568                         }
2569                 }
2570                 if (active) {
2571                         ahc_outb(ahc, SCSIRATE, scsirate);
2572                         if ((ahc->features & AHC_ULTRA2) != 0)
2573                                 ahc_outb(ahc, SCSIOFFSET, offset);
2574                 }
2575
2576                 tinfo->scsirate = scsirate;
2577                 tinfo->curr.period = period;
2578                 tinfo->curr.offset = offset;
2579                 tinfo->curr.ppr_options = ppr_options;
2580
2581                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2582                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2583                 if (bootverbose) {
2584                         if (offset != 0) {
2585                                 printf("%s: target %d synchronous at %sMHz%s, "
2586                                        "offset = 0x%x\n", ahc_name(ahc),
2587                                        devinfo->target, syncrate->rate,
2588                                        (ppr_options & MSG_EXT_PPR_DT_REQ)
2589                                        ? " DT" : "", offset);
2590                         } else {
2591                                 printf("%s: target %d using "
2592                                        "asynchronous transfers\n",
2593                                        ahc_name(ahc), devinfo->target);
2594                         }
2595                 }
2596         }
2597
2598         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2599                                                 tinfo, AHC_NEG_TO_GOAL);
2600
2601         if (update_needed)
2602                 ahc_update_pending_scbs(ahc);
2603 }
2604
2605 /*
2606  * Update the user/goal/curr tables of wide negotiation
2607  * parameters as well as, in the case of a current or active update,
2608  * any data structures on the host controller.  In the case of an
2609  * active update, the specified target is currently talking to us on
2610  * the bus, so the transfer parameter update must take effect
2611  * immediately.
2612  */
2613 void
2614 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2615               u_int width, u_int type, int paused)
2616 {
2617         struct  ahc_initiator_tinfo *tinfo;
2618         struct  ahc_tmode_tstate *tstate;
2619         u_int   oldwidth;
2620         int     active;
2621         int     update_needed;
2622
2623         active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2624         update_needed = 0;
2625         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2626                                     devinfo->target, &tstate);
2627
2628         if ((type & AHC_TRANS_USER) != 0)
2629                 tinfo->user.width = width;
2630
2631         if ((type & AHC_TRANS_GOAL) != 0)
2632                 tinfo->goal.width = width;
2633
2634         oldwidth = tinfo->curr.width;
2635         if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2636                 u_int   scsirate;
2637
2638                 update_needed++;
2639                 scsirate =  tinfo->scsirate;
2640                 scsirate &= ~WIDEXFER;
2641                 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2642                         scsirate |= WIDEXFER;
2643
2644                 tinfo->scsirate = scsirate;
2645
2646                 if (active)
2647                         ahc_outb(ahc, SCSIRATE, scsirate);
2648
2649                 tinfo->curr.width = width;
2650
2651                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2652                                CAM_LUN_WILDCARD, AC_TRANSFER_NEG);
2653                 if (bootverbose) {
2654                         printf("%s: target %d using %dbit transfers\n",
2655                                ahc_name(ahc), devinfo->target,
2656                                8 * (0x01 << width));
2657                 }
2658         }
2659
2660         update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2661                                                 tinfo, AHC_NEG_TO_GOAL);
2662         if (update_needed)
2663                 ahc_update_pending_scbs(ahc);
2664 }
2665
2666 /*
2667  * Update the current state of tagged queuing for a given target.
2668  */
2669 static void
2670 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd,
2671              struct ahc_devinfo *devinfo, ahc_queue_alg alg)
2672 {
2673         struct scsi_device *sdev = cmd->device;
2674
2675         ahc_platform_set_tags(ahc, sdev, devinfo, alg);
2676         ahc_send_async(ahc, devinfo->channel, devinfo->target,
2677                        devinfo->lun, AC_TRANSFER_NEG);
2678 }
2679
2680 /*
2681  * When the transfer settings for a connection change, update any
2682  * in-transit SCBs to contain the new data so the hardware will
2683  * be set correctly during future (re)selections.
2684  */
2685 static void
2686 ahc_update_pending_scbs(struct ahc_softc *ahc)
2687 {
2688         struct  scb *pending_scb;
2689         int     pending_scb_count;
2690         int     i;
2691         int     paused;
2692         u_int   saved_scbptr;
2693
2694         /*
2695          * Traverse the pending SCB list and ensure that all of the
2696          * SCBs there have the proper settings.
2697          */
2698         pending_scb_count = 0;
2699         LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2700                 struct ahc_devinfo devinfo;
2701                 struct hardware_scb *pending_hscb;
2702                 struct ahc_initiator_tinfo *tinfo;
2703                 struct ahc_tmode_tstate *tstate;
2704
2705                 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2706                 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2707                                             devinfo.our_scsiid,
2708                                             devinfo.target, &tstate);
2709                 pending_hscb = pending_scb->hscb;
2710                 pending_hscb->control &= ~ULTRAENB;
2711                 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2712                         pending_hscb->control |= ULTRAENB;
2713                 pending_hscb->scsirate = tinfo->scsirate;
2714                 pending_hscb->scsioffset = tinfo->curr.offset;
2715                 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2716                  && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2717                         pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2718                         pending_hscb->control &= ~MK_MESSAGE;
2719                 }
2720                 ahc_sync_scb(ahc, pending_scb,
2721                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2722                 pending_scb_count++;
2723         }
2724
2725         if (pending_scb_count == 0)
2726                 return;
2727
2728         if (ahc_is_paused(ahc)) {
2729                 paused = 1;
2730         } else {
2731                 paused = 0;
2732                 ahc_pause(ahc);
2733         }
2734
2735         saved_scbptr = ahc_inb(ahc, SCBPTR);
2736         /* Ensure that the hscbs down on the card match the new information */
2737         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2738                 struct  hardware_scb *pending_hscb;
2739                 u_int   control;
2740                 u_int   scb_tag;
2741
2742                 ahc_outb(ahc, SCBPTR, i);
2743                 scb_tag = ahc_inb(ahc, SCB_TAG);
2744                 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2745                 if (pending_scb == NULL)
2746                         continue;
2747
2748                 pending_hscb = pending_scb->hscb;
2749                 control = ahc_inb(ahc, SCB_CONTROL);
2750                 control &= ~(ULTRAENB|MK_MESSAGE);
2751                 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2752                 ahc_outb(ahc, SCB_CONTROL, control);
2753                 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2754                 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2755         }
2756         ahc_outb(ahc, SCBPTR, saved_scbptr);
2757
2758         if (paused == 0)
2759                 ahc_unpause(ahc);
2760 }
2761
2762 /**************************** Pathing Information *****************************/
2763 static void
2764 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2765 {
2766         u_int   saved_scsiid;
2767         role_t  role;
2768         int     our_id;
2769
2770         if (ahc_inb(ahc, SSTAT0) & TARGET)
2771                 role = ROLE_TARGET;
2772         else
2773                 role = ROLE_INITIATOR;
2774
2775         if (role == ROLE_TARGET
2776          && (ahc->features & AHC_MULTI_TID) != 0
2777          && (ahc_inb(ahc, SEQ_FLAGS)
2778            & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2779                 /* We were selected, so pull our id from TARGIDIN */
2780                 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2781         } else if ((ahc->features & AHC_ULTRA2) != 0)
2782                 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2783         else
2784                 our_id = ahc_inb(ahc, SCSIID) & OID;
2785
2786         saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2787         ahc_compile_devinfo(devinfo,
2788                             our_id,
2789                             SCSIID_TARGET(ahc, saved_scsiid),
2790                             ahc_inb(ahc, SAVED_LUN),
2791                             SCSIID_CHANNEL(ahc, saved_scsiid),
2792                             role);
2793 }
2794
2795 static const struct ahc_phase_table_entry*
2796 ahc_lookup_phase_entry(int phase)
2797 {
2798         const struct ahc_phase_table_entry *entry;
2799         const struct ahc_phase_table_entry *last_entry;
2800
2801         /*
2802          * num_phases doesn't include the default entry which
2803          * will be returned if the phase doesn't match.
2804          */
2805         last_entry = &ahc_phase_table[num_phases];
2806         for (entry = ahc_phase_table; entry < last_entry; entry++) {
2807                 if (phase == entry->phase)
2808                         break;
2809         }
2810         return (entry);
2811 }
2812
2813 void
2814 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2815                     u_int lun, char channel, role_t role)
2816 {
2817         devinfo->our_scsiid = our_id;
2818         devinfo->target = target;
2819         devinfo->lun = lun;
2820         devinfo->target_offset = target;
2821         devinfo->channel = channel;
2822         devinfo->role = role;
2823         if (channel == 'B')
2824                 devinfo->target_offset += 8;
2825         devinfo->target_mask = (0x01 << devinfo->target_offset);
2826 }
2827
2828 void
2829 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2830 {
2831         printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2832                devinfo->target, devinfo->lun);
2833 }
2834
2835 static void
2836 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2837                 struct scb *scb)
2838 {
2839         role_t  role;
2840         int     our_id;
2841
2842         our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2843         role = ROLE_INITIATOR;
2844         if ((scb->flags & SCB_TARGET_SCB) != 0)
2845                 role = ROLE_TARGET;
2846         ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2847                             SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2848 }
2849
2850
2851 /************************ Message Phase Processing ****************************/
2852 static void
2853 ahc_assert_atn(struct ahc_softc *ahc)
2854 {
2855         u_int scsisigo;
2856
2857         scsisigo = ATNO;
2858         if ((ahc->features & AHC_DT) == 0)
2859                 scsisigo |= ahc_inb(ahc, SCSISIGI);
2860         ahc_outb(ahc, SCSISIGO, scsisigo);
2861 }
2862
2863 /*
2864  * When an initiator transaction with the MK_MESSAGE flag either reconnects
2865  * or enters the initial message out phase, we are interrupted.  Fill our
2866  * outgoing message buffer with the appropriate message and beging handing
2867  * the message phase(s) manually.
2868  */
2869 static void
2870 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2871                            struct scb *scb)
2872 {
2873         /*
2874          * To facilitate adding multiple messages together,
2875          * each routine should increment the index and len
2876          * variables instead of setting them explicitly.
2877          */
2878         ahc->msgout_index = 0;
2879         ahc->msgout_len = 0;
2880
2881         if ((scb->flags & SCB_DEVICE_RESET) == 0
2882          && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2883                 u_int identify_msg;
2884
2885                 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2886                 if ((scb->hscb->control & DISCENB) != 0)
2887                         identify_msg |= MSG_IDENTIFY_DISCFLAG;
2888                 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2889                 ahc->msgout_len++;
2890
2891                 if ((scb->hscb->control & TAG_ENB) != 0) {
2892                         ahc->msgout_buf[ahc->msgout_index++] =
2893                             scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2894                         ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2895                         ahc->msgout_len += 2;
2896                 }
2897         }
2898
2899         if (scb->flags & SCB_DEVICE_RESET) {
2900                 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2901                 ahc->msgout_len++;
2902                 ahc_print_path(ahc, scb);
2903                 printf("Bus Device Reset Message Sent\n");
2904                 /*
2905                  * Clear our selection hardware in advance of
2906                  * the busfree.  We may have an entry in the waiting
2907                  * Q for this target, and we don't want to go about
2908                  * selecting while we handle the busfree and blow it
2909                  * away.
2910                  */
2911                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2912         } else if ((scb->flags & SCB_ABORT) != 0) {
2913                 if ((scb->hscb->control & TAG_ENB) != 0)
2914                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2915                 else
2916                         ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2917                 ahc->msgout_len++;
2918                 ahc_print_path(ahc, scb);
2919                 printf("Abort%s Message Sent\n",
2920                        (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2921                 /*
2922                  * Clear our selection hardware in advance of
2923                  * the busfree.  We may have an entry in the waiting
2924                  * Q for this target, and we don't want to go about
2925                  * selecting while we handle the busfree and blow it
2926                  * away.
2927                  */
2928                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2929         } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2930                 ahc_build_transfer_msg(ahc, devinfo);
2931         } else {
2932                 printf("ahc_intr: AWAITING_MSG for an SCB that "
2933                        "does not have a waiting message\n");
2934                 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2935                        devinfo->target_mask);
2936                 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2937                       "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2938                       ahc_inb(ahc, MSG_OUT), scb->flags);
2939         }
2940
2941         /*
2942          * Clear the MK_MESSAGE flag from the SCB so we aren't
2943          * asked to send this message again.
2944          */
2945         ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2946         scb->hscb->control &= ~MK_MESSAGE;
2947         ahc->msgout_index = 0;
2948         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2949 }
2950
2951 /*
2952  * Build an appropriate transfer negotiation message for the
2953  * currently active target.
2954  */
2955 static void
2956 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2957 {
2958         /*
2959          * We need to initiate transfer negotiations.
2960          * If our current and goal settings are identical,
2961          * we want to renegotiate due to a check condition.
2962          */
2963         struct  ahc_initiator_tinfo *tinfo;
2964         struct  ahc_tmode_tstate *tstate;
2965         const struct ahc_syncrate *rate;
2966         int     dowide;
2967         int     dosync;
2968         int     doppr;
2969         u_int   period;
2970         u_int   ppr_options;
2971         u_int   offset;
2972
2973         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2974                                     devinfo->target, &tstate);
2975         /*
2976          * Filter our period based on the current connection.
2977          * If we can't perform DT transfers on this segment (not in LVD
2978          * mode for instance), then our decision to issue a PPR message
2979          * may change.
2980          */
2981         period = tinfo->goal.period;
2982         offset = tinfo->goal.offset;
2983         ppr_options = tinfo->goal.ppr_options;
2984         /* Target initiated PPR is not allowed in the SCSI spec */
2985         if (devinfo->role == ROLE_TARGET)
2986                 ppr_options = 0;
2987         rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2988                                        &ppr_options, devinfo->role);
2989         dowide = tinfo->curr.width != tinfo->goal.width;
2990         dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2991         /*
2992          * Only use PPR if we have options that need it, even if the device
2993          * claims to support it.  There might be an expander in the way
2994          * that doesn't.
2995          */
2996         doppr = ppr_options != 0;
2997
2998         if (!dowide && !dosync && !doppr) {
2999                 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3000                 dosync = tinfo->goal.offset != 0;
3001         }
3002
3003         if (!dowide && !dosync && !doppr) {
3004                 /*
3005                  * Force async with a WDTR message if we have a wide bus,
3006                  * or just issue an SDTR with a 0 offset.
3007                  */
3008                 if ((ahc->features & AHC_WIDE) != 0)
3009                         dowide = 1;
3010                 else
3011                         dosync = 1;
3012
3013                 if (bootverbose) {
3014                         ahc_print_devinfo(ahc, devinfo);
3015                         printf("Ensuring async\n");
3016                 }
3017         }
3018
3019         /* Target initiated PPR is not allowed in the SCSI spec */
3020         if (devinfo->role == ROLE_TARGET)
3021                 doppr = 0;
3022
3023         /*
3024          * Both the PPR message and SDTR message require the
3025          * goal syncrate to be limited to what the target device
3026          * is capable of handling (based on whether an LVD->SE
3027          * expander is on the bus), so combine these two cases.
3028          * Regardless, guarantee that if we are using WDTR and SDTR
3029          * messages that WDTR comes first.
3030          */
3031         if (doppr || (dosync && !dowide)) {
3032
3033                 offset = tinfo->goal.offset;
3034                 ahc_validate_offset(ahc, tinfo, rate, &offset,
3035                                     doppr ? tinfo->goal.width
3036                                           : tinfo->curr.width,
3037                                     devinfo->role);
3038                 if (doppr) {
3039                         ahc_construct_ppr(ahc, devinfo, period, offset,
3040                                           tinfo->goal.width, ppr_options);
3041                 } else {
3042                         ahc_construct_sdtr(ahc, devinfo, period, offset);
3043                 }
3044         } else {
3045                 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
3046         }
3047 }
3048
3049 /*
3050  * Build a synchronous negotiation message in our message
3051  * buffer based on the input parameters.
3052  */
3053 static void
3054 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3055                    u_int period, u_int offset)
3056 {
3057         if (offset == 0)
3058                 period = AHC_ASYNC_XFER_PERIOD;
3059         ahc->msgout_index += spi_populate_sync_msg(
3060                         ahc->msgout_buf + ahc->msgout_index, period, offset);
3061         ahc->msgout_len += 5;
3062         if (bootverbose) {
3063                 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3064                        ahc_name(ahc), devinfo->channel, devinfo->target,
3065                        devinfo->lun, period, offset);
3066         }
3067 }
3068
3069 /*
3070  * Build a wide negotiation message in our message
3071  * buffer based on the input parameters.
3072  */
3073 static void
3074 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3075                    u_int bus_width)
3076 {
3077         ahc->msgout_index += spi_populate_width_msg(
3078                         ahc->msgout_buf + ahc->msgout_index, bus_width);
3079         ahc->msgout_len += 4;
3080         if (bootverbose) {
3081                 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3082                        ahc_name(ahc), devinfo->channel, devinfo->target,
3083                        devinfo->lun, bus_width);
3084         }
3085 }
3086
3087 /*
3088  * Build a parallel protocol request message in our message
3089  * buffer based on the input parameters.
3090  */
3091 static void
3092 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3093                   u_int period, u_int offset, u_int bus_width,
3094                   u_int ppr_options)
3095 {
3096         if (offset == 0)
3097                 period = AHC_ASYNC_XFER_PERIOD;
3098         ahc->msgout_index += spi_populate_ppr_msg(
3099                         ahc->msgout_buf + ahc->msgout_index, period, offset,
3100                         bus_width, ppr_options);
3101         ahc->msgout_len += 8;
3102         if (bootverbose) {
3103                 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3104                        "offset %x, ppr_options %x\n", ahc_name(ahc),
3105                        devinfo->channel, devinfo->target, devinfo->lun,
3106                        bus_width, period, offset, ppr_options);
3107         }
3108 }
3109
3110 /*
3111  * Clear any active message state.
3112  */
3113 static void
3114 ahc_clear_msg_state(struct ahc_softc *ahc)
3115 {
3116         ahc->msgout_len = 0;
3117         ahc->msgin_index = 0;
3118         ahc->msg_type = MSG_TYPE_NONE;
3119         if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
3120                 /*
3121                  * The target didn't care to respond to our
3122                  * message request, so clear ATN.
3123                  */
3124                 ahc_outb(ahc, CLRSINT1, CLRATNO);
3125         }
3126         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
3127         ahc_outb(ahc, SEQ_FLAGS2,
3128                  ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3129 }
3130
3131 static void
3132 ahc_handle_proto_violation(struct ahc_softc *ahc)
3133 {
3134         struct  ahc_devinfo devinfo;
3135         struct  scb *scb;
3136         u_int   scbid;
3137         u_int   seq_flags;
3138         u_int   curphase;
3139         u_int   lastphase;
3140         int     found;
3141
3142         ahc_fetch_devinfo(ahc, &devinfo);
3143         scbid = ahc_inb(ahc, SCB_TAG);
3144         scb = ahc_lookup_scb(ahc, scbid);
3145         seq_flags = ahc_inb(ahc, SEQ_FLAGS);
3146         curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3147         lastphase = ahc_inb(ahc, LASTPHASE);
3148         if ((seq_flags & NOT_IDENTIFIED) != 0) {
3149
3150                 /*
3151                  * The reconnecting target either did not send an
3152                  * identify message, or did, but we didn't find an SCB
3153                  * to match.
3154                  */
3155                 ahc_print_devinfo(ahc, &devinfo);
3156                 printf("Target did not send an IDENTIFY message. "
3157                        "LASTPHASE = 0x%x.\n", lastphase);
3158                 scb = NULL;
3159         } else if (scb == NULL) {
3160                 /*
3161                  * We don't seem to have an SCB active for this
3162                  * transaction.  Print an error and reset the bus.
3163                  */
3164                 ahc_print_devinfo(ahc, &devinfo);
3165                 printf("No SCB found during protocol violation\n");
3166                 goto proto_violation_reset;
3167         } else {
3168                 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
3169                 if ((seq_flags & NO_CDB_SENT) != 0) {
3170                         ahc_print_path(ahc, scb);
3171                         printf("No or incomplete CDB sent to device.\n");
3172                 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
3173                         /*
3174                          * The target never bothered to provide status to
3175                          * us prior to completing the command.  Since we don't
3176                          * know the disposition of this command, we must attempt
3177                          * to abort it.  Assert ATN and prepare to send an abort
3178                          * message.
3179                          */
3180                         ahc_print_path(ahc, scb);
3181                         printf("Completed command without status.\n");
3182                 } else {
3183                         ahc_print_path(ahc, scb);
3184                         printf("Unknown protocol violation.\n");
3185                         ahc_dump_card_state(ahc);
3186                 }
3187         }
3188         if ((lastphase & ~P_DATAIN_DT) == 0
3189          || lastphase == P_COMMAND) {
3190 proto_violation_reset:
3191                 /*
3192                  * Target either went directly to data/command
3193                  * phase or didn't respond to our ATN.
3194                  * The only safe thing to do is to blow
3195                  * it away with a bus reset.
3196                  */
3197                 found = ahc_reset_channel(ahc, 'A', TRUE);
3198                 printf("%s: Issued Channel %c Bus Reset. "
3199                        "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
3200         } else {
3201                 /*
3202                  * Leave the selection hardware off in case
3203                  * this abort attempt will affect yet to
3204                  * be sent commands.
3205                  */
3206                 ahc_outb(ahc, SCSISEQ,
3207                          ahc_inb(ahc, SCSISEQ) & ~ENSELO);
3208                 ahc_assert_atn(ahc);
3209                 ahc_outb(ahc, MSG_OUT, HOST_MSG);
3210                 if (scb == NULL) {
3211                         ahc_print_devinfo(ahc, &devinfo);
3212                         ahc->msgout_buf[0] = MSG_ABORT_TASK;
3213                         ahc->msgout_len = 1;
3214                         ahc->msgout_index = 0;
3215                         ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3216                 } else {
3217                         ahc_print_path(ahc, scb);
3218                         scb->flags |= SCB_ABORT;
3219                 }
3220                 printf("Protocol violation %s.  Attempting to abort.\n",
3221                        ahc_lookup_phase_entry(curphase)->phasemsg);
3222         }
3223 }
3224
3225 /*
3226  * Manual message loop handler.
3227  */
3228 static void
3229 ahc_handle_message_phase(struct ahc_softc *ahc)
3230 {
3231         struct  ahc_devinfo devinfo;
3232         u_int   bus_phase;
3233         int     end_session;
3234
3235         ahc_fetch_devinfo(ahc, &devinfo);
3236         end_session = FALSE;
3237         bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
3238
3239 reswitch:
3240         switch (ahc->msg_type) {
3241         case MSG_TYPE_INITIATOR_MSGOUT:
3242         {
3243                 int lastbyte;
3244                 int phasemis;
3245                 int msgdone;
3246
3247                 if (ahc->msgout_len == 0)
3248                         panic("HOST_MSG_LOOP interrupt with no active message");
3249
3250 #ifdef AHC_DEBUG
3251                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3252                         ahc_print_devinfo(ahc, &devinfo);
3253                         printf("INITIATOR_MSG_OUT");
3254                 }
3255 #endif
3256                 phasemis = bus_phase != P_MESGOUT;
3257                 if (phasemis) {
3258 #ifdef AHC_DEBUG
3259                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3260                                 printf(" PHASEMIS %s\n",
3261                                        ahc_lookup_phase_entry(bus_phase)
3262                                                              ->phasemsg);
3263                         }
3264 #endif
3265                         if (bus_phase == P_MESGIN) {
3266                                 /*
3267                                  * Change gears and see if
3268                                  * this messages is of interest to
3269                                  * us or should be passed back to
3270                                  * the sequencer.
3271                                  */
3272                                 ahc_outb(ahc, CLRSINT1, CLRATNO);
3273                                 ahc->send_msg_perror = FALSE;
3274                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3275                                 ahc->msgin_index = 0;
3276                                 goto reswitch;
3277                         }
3278                         end_session = TRUE;
3279                         break;
3280                 }
3281
3282                 if (ahc->send_msg_perror) {
3283                         ahc_outb(ahc, CLRSINT1, CLRATNO);
3284                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3285 #ifdef AHC_DEBUG
3286                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3287                                 printf(" byte 0x%x\n", ahc->send_msg_perror);
3288 #endif
3289                         ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
3290                         break;
3291                 }
3292
3293                 msgdone = ahc->msgout_index == ahc->msgout_len;
3294                 if (msgdone) {
3295                         /*
3296                          * The target has requested a retry.
3297                          * Re-assert ATN, reset our message index to
3298                          * 0, and try again.
3299                          */
3300                         ahc->msgout_index = 0;
3301                         ahc_assert_atn(ahc);
3302                 }
3303
3304                 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
3305                 if (lastbyte) {
3306                         /* Last byte is signified by dropping ATN */
3307                         ahc_outb(ahc, CLRSINT1, CLRATNO);
3308                 }
3309
3310                 /*
3311                  * Clear our interrupt status and present
3312                  * the next byte on the bus.
3313                  */
3314                 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3315 #ifdef AHC_DEBUG
3316                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3317                         printf(" byte 0x%x\n",
3318                                ahc->msgout_buf[ahc->msgout_index]);
3319 #endif
3320                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3321                 break;
3322         }
3323         case MSG_TYPE_INITIATOR_MSGIN:
3324         {
3325                 int phasemis;
3326                 int message_done;
3327
3328 #ifdef AHC_DEBUG
3329                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3330                         ahc_print_devinfo(ahc, &devinfo);
3331                         printf("INITIATOR_MSG_IN");
3332                 }
3333 #endif
3334                 phasemis = bus_phase != P_MESGIN;
3335                 if (phasemis) {
3336 #ifdef AHC_DEBUG
3337                         if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3338                                 printf(" PHASEMIS %s\n",
3339                                        ahc_lookup_phase_entry(bus_phase)
3340                                                              ->phasemsg);
3341                         }
3342 #endif
3343                         ahc->msgin_index = 0;
3344                         if (bus_phase == P_MESGOUT
3345                          && (ahc->send_msg_perror == TRUE
3346                           || (ahc->msgout_len != 0
3347                            && ahc->msgout_index == 0))) {
3348                                 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3349                                 goto reswitch;
3350                         }
3351                         end_session = TRUE;
3352                         break;
3353                 }
3354
3355                 /* Pull the byte in without acking it */
3356                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
3357 #ifdef AHC_DEBUG
3358                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
3359                         printf(" byte 0x%x\n",
3360                                ahc->msgin_buf[ahc->msgin_index]);
3361 #endif
3362
3363                 message_done = ahc_parse_msg(ahc, &devinfo);
3364
3365                 if (message_done) {
3366                         /*
3367                          * Clear our incoming message buffer in case there
3368                          * is another message following this one.
3369                          */
3370                         ahc->msgin_index = 0;
3371
3372                         /*
3373                          * If this message illicited a response,
3374                          * assert ATN so the target takes us to the
3375                          * message out phase.
3376                          */
3377                         if (ahc->msgout_len != 0) {
3378 #ifdef AHC_DEBUG
3379                                 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
3380                                         ahc_print_devinfo(ahc, &devinfo);
3381                                         printf("Asserting ATN for response\n");
3382                                 }
3383 #endif
3384                                 ahc_assert_atn(ahc);
3385                         }
3386                 } else
3387                         ahc->msgin_index++;
3388
3389                 if (message_done == MSGLOOP_TERMINATED) {
3390                         end_session = TRUE;
3391                 } else {
3392                         /* Ack the byte */
3393                         ahc_outb(ahc, CLRSINT1, CLRREQINIT);
3394                         ahc_inb(ahc, SCSIDATL);
3395                 }
3396                 break;
3397         }
3398         case MSG_TYPE_TARGET_MSGIN:
3399         {
3400                 int msgdone;
3401                 int msgout_request;
3402
3403                 if (ahc->msgout_len == 0)
3404                         panic("Target MSGIN with no active message");
3405
3406                 /*
3407                  * If we interrupted a mesgout session, the initiator
3408                  * will not know this until our first REQ.  So, we
3409                  * only honor mesgout requests after we've sent our
3410                  * first byte.
3411                  */
3412                 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
3413                  && ahc->msgout_index > 0)
3414                         msgout_request = TRUE;
3415                 else
3416                         msgout_request = FALSE;
3417
3418                 if (msgout_request) {
3419
3420                         /*
3421                          * Change gears and see if
3422                          * this messages is of interest to
3423                          * us or should be passed back to
3424                          * the sequencer.
3425                          */
3426                         ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
3427                         ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
3428                         ahc->msgin_index = 0;
3429                         /* Dummy read to REQ for first byte */
3430                         ahc_inb(ahc, SCSIDATL);
3431                         ahc_outb(ahc, SXFRCTL0,
3432                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3433                         break;
3434                 }
3435
3436                 msgdone = ahc->msgout_index == ahc->msgout_len;
3437                 if (msgdone) {
3438                         ahc_outb(ahc, SXFRCTL0,
3439                                  ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3440                         end_session = TRUE;
3441                         break;
3442                 }
3443
3444                 /*
3445                  * Present the next byte on the bus.
3446                  */
3447                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3448                 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
3449                 break;
3450         }
3451         case MSG_TYPE_TARGET_MSGOUT:
3452         {
3453                 int lastbyte;
3454                 int msgdone;
3455
3456                 /*
3457                  * The initiator signals that this is
3458                  * the last byte by dropping ATN.
3459                  */
3460                 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
3461
3462                 /*
3463                  * Read the latched byte, but turn off SPIOEN first
3464                  * so that we don't inadvertently cause a REQ for the
3465                  * next byte.
3466                  */
3467                 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
3468                 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
3469                 msgdone = ahc_parse_msg(ahc, &devinfo);
3470                 if (msgdone == MSGLOOP_TERMINATED) {
3471                         /*
3472                          * The message is *really* done in that it caused
3473                          * us to go to bus free.  The sequencer has already
3474                          * been reset at this point, so pull the ejection
3475                          * handle.
3476                          */
3477                         return;
3478                 }
3479
3480                 ahc->msgin_index++;
3481
3482                 /*
3483                  * XXX Read spec about initiator dropping ATN too soon
3484                  *     and use msgdone to detect it.
3485                  */
3486                 if (msgdone == MSGLOOP_MSGCOMPLETE) {
3487                         ahc->msgin_index = 0;
3488
3489                         /*
3490                          * If this message illicited a response, transition
3491                          * to the Message in phase and send it.
3492                          */
3493                         if (ahc->msgout_len != 0) {
3494                                 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
3495                                 ahc_outb(ahc, SXFRCTL0,
3496                                          ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3497                                 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3498                                 ahc->msgin_index = 0;
3499                                 break;
3500                         }
3501                 }
3502
3503                 if (lastbyte)
3504                         end_session = TRUE;
3505                 else {
3506                         /* Ask for the next byte. */
3507                         ahc_outb(ahc, SXFRCTL0,
3508                                  ahc_inb(ahc, SXFRCTL0) | SPIOEN);
3509                 }
3510
3511                 break;
3512         }
3513         default:
3514                 panic("Unknown REQINIT message type");
3515         }
3516
3517         if (end_session) {
3518                 ahc_clear_msg_state(ahc);
3519                 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
3520         } else
3521                 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
3522 }
3523
3524 /*
3525  * See if we sent a particular extended message to the target.
3526  * If "full" is true, return true only if the target saw the full
3527  * message.  If "full" is false, return true if the target saw at
3528  * least the first byte of the message.
3529  */
3530 static int
3531 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
3532 {
3533         int found;
3534         u_int index;
3535
3536         found = FALSE;
3537         index = 0;
3538
3539         while (index < ahc->msgout_len) {
3540                 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
3541                         u_int end_index;
3542
3543                         end_index = index + 1 + ahc->msgout_buf[index + 1];
3544                         if (ahc->msgout_buf[index+2] == msgval
3545                          && type == AHCMSG_EXT) {
3546
3547                                 if (full) {
3548                                         if (ahc->msgout_index > end_index)
3549                                                 found = TRUE;
3550                                 } else if (ahc->msgout_index > index)
3551                                         found = TRUE;
3552                         }
3553                         index = end_index;
3554                 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
3555                         && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
3556
3557                         /* Skip tag type and tag id or residue param*/
3558                         index += 2;
3559                 } else {
3560                         /* Single byte message */
3561                         if (type == AHCMSG_1B
3562                          && ahc->msgout_buf[index] == msgval
3563                          && ahc->msgout_index > index)
3564                                 found = TRUE;
3565                         index++;
3566                 }
3567
3568                 if (found)
3569                         break;
3570         }
3571         return (found);
3572 }
3573
3574 /*
3575  * Wait for a complete incoming message, parse it, and respond accordingly.
3576  */
3577 static int
3578 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3579 {
3580         struct  ahc_initiator_tinfo *tinfo;
3581         struct  ahc_tmode_tstate *tstate;
3582         int     reject;
3583         int     done;
3584         int     response;
3585         u_int   targ_scsirate;
3586
3587         done = MSGLOOP_IN_PROG;
3588         response = FALSE;
3589         reject = FALSE;
3590         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3591                                     devinfo->target, &tstate);
3592         targ_scsirate = tinfo->scsirate;
3593
3594         /*
3595          * Parse as much of the message as is available,
3596          * rejecting it if we don't support it.  When
3597          * the entire message is available and has been
3598          * handled, return MSGLOOP_MSGCOMPLETE, indicating
3599          * that we have parsed an entire message.
3600          *
3601          * In the case of extended messages, we accept the length
3602          * byte outright and perform more checking once we know the
3603          * extended message type.
3604          */
3605         switch (ahc->msgin_buf[0]) {
3606         case MSG_DISCONNECT:
3607         case MSG_SAVEDATAPOINTER:
3608         case MSG_CMDCOMPLETE:
3609         case MSG_RESTOREPOINTERS:
3610         case MSG_IGN_WIDE_RESIDUE:
3611                 /*
3612                  * End our message loop as these are messages
3613                  * the sequencer handles on its own.
3614                  */
3615                 done = MSGLOOP_TERMINATED;
3616                 break;
3617         case MSG_MESSAGE_REJECT:
3618                 response = ahc_handle_msg_reject(ahc, devinfo);
3619                 /* FALLTHROUGH */
3620         case MSG_NOOP:
3621                 done = MSGLOOP_MSGCOMPLETE;
3622                 break;
3623         case MSG_EXTENDED:
3624         {
3625                 /* Wait for enough of the message to begin validation */
3626                 if (ahc->msgin_index < 2)
3627                         break;
3628                 switch (ahc->msgin_buf[2]) {
3629                 case MSG_EXT_SDTR:
3630                 {
3631                         const struct ahc_syncrate *syncrate;
3632                         u_int    period;
3633                         u_int    ppr_options;
3634                         u_int    offset;
3635                         u_int    saved_offset;
3636
3637                         if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3638                                 reject = TRUE;
3639                                 break;
3640                         }
3641
3642                         /*
3643                          * Wait until we have both args before validating
3644                          * and acting on this message.
3645                          *
3646                          * Add one to MSG_EXT_SDTR_LEN to account for
3647                          * the extended message preamble.
3648                          */
3649                         if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3650                                 break;
3651
3652                         period = ahc->msgin_buf[3];
3653                         ppr_options = 0;
3654                         saved_offset = offset = ahc->msgin_buf[4];
3655                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3656                                                            &ppr_options,
3657                                                            devinfo->role);
3658                         ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3659                                             targ_scsirate & WIDEXFER,
3660                                             devinfo->role);
3661                         if (bootverbose) {
3662                                 printf("(%s:%c:%d:%d): Received "
3663                                        "SDTR period %x, offset %x\n\t"
3664                                        "Filtered to period %x, offset %x\n",
3665                                        ahc_name(ahc), devinfo->channel,
3666                                        devinfo->target, devinfo->lun,
3667                                        ahc->msgin_buf[3], saved_offset,
3668                                        period, offset);
3669                         }
3670                         ahc_set_syncrate(ahc, devinfo,
3671                                          syncrate, period,
3672                                          offset, ppr_options,
3673                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3674                                          /*paused*/TRUE);
3675
3676                         /*
3677                          * See if we initiated Sync Negotiation
3678                          * and didn't have to fall down to async
3679                          * transfers.
3680                          */
3681                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3682                                 /* We started it */
3683                                 if (saved_offset != offset) {
3684                                         /* Went too low - force async */
3685                                         reject = TRUE;
3686                                 }
3687                         } else {
3688                                 /*
3689                                  * Send our own SDTR in reply
3690                                  */
3691                                 if (bootverbose
3692                                  && devinfo->role == ROLE_INITIATOR) {
3693                                         printf("(%s:%c:%d:%d): Target "
3694                                                "Initiated SDTR\n",
3695                                                ahc_name(ahc), devinfo->channel,
3696                                                devinfo->target, devinfo->lun);
3697                                 }
3698                                 ahc->msgout_index = 0;
3699                                 ahc->msgout_len = 0;
3700                                 ahc_construct_sdtr(ahc, devinfo,
3701                                                    period, offset);
3702                                 ahc->msgout_index = 0;
3703                                 response = TRUE;
3704                         }
3705                         done = MSGLOOP_MSGCOMPLETE;
3706                         break;
3707                 }
3708                 case MSG_EXT_WDTR:
3709                 {
3710                         u_int bus_width;
3711                         u_int saved_width;
3712                         u_int sending_reply;
3713
3714                         sending_reply = FALSE;
3715                         if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3716                                 reject = TRUE;
3717                                 break;
3718                         }
3719
3720                         /*
3721                          * Wait until we have our arg before validating
3722                          * and acting on this message.
3723                          *
3724                          * Add one to MSG_EXT_WDTR_LEN to account for
3725                          * the extended message preamble.
3726                          */
3727                         if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3728                                 break;
3729
3730                         bus_width = ahc->msgin_buf[3];
3731                         saved_width = bus_width;
3732                         ahc_validate_width(ahc, tinfo, &bus_width,
3733                                            devinfo->role);
3734                         if (bootverbose) {
3735                                 printf("(%s:%c:%d:%d): Received WDTR "
3736                                        "%x filtered to %x\n",
3737                                        ahc_name(ahc), devinfo->channel,
3738                                        devinfo->target, devinfo->lun,
3739                                        saved_width, bus_width);
3740                         }
3741
3742                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3743                                 /*
3744                                  * Don't send a WDTR back to the
3745                                  * target, since we asked first.
3746                                  * If the width went higher than our
3747                                  * request, reject it.
3748                                  */
3749                                 if (saved_width > bus_width) {
3750                                         reject = TRUE;
3751                                         printf("(%s:%c:%d:%d): requested %dBit "
3752                                                "transfers.  Rejecting...\n",
3753                                                ahc_name(ahc), devinfo->channel,
3754                                                devinfo->target, devinfo->lun,
3755                                                8 * (0x01 << bus_width));
3756                                         bus_width = 0;
3757                                 }
3758                         } else {
3759                                 /*
3760                                  * Send our own WDTR in reply
3761                                  */
3762                                 if (bootverbose
3763                                  && devinfo->role == ROLE_INITIATOR) {
3764                                         printf("(%s:%c:%d:%d): Target "
3765                                                "Initiated WDTR\n",
3766                                                ahc_name(ahc), devinfo->channel,
3767                                                devinfo->target, devinfo->lun);
3768                                 }
3769                                 ahc->msgout_index = 0;
3770                                 ahc->msgout_len = 0;
3771                                 ahc_construct_wdtr(ahc, devinfo, bus_width);
3772                                 ahc->msgout_index = 0;
3773                                 response = TRUE;
3774                                 sending_reply = TRUE;
3775                         }
3776                         /*
3777                          * After a wide message, we are async, but
3778                          * some devices don't seem to honor this portion
3779                          * of the spec.  Force a renegotiation of the
3780                          * sync component of our transfer agreement even
3781                          * if our goal is async.  By updating our width
3782                          * after forcing the negotiation, we avoid
3783                          * renegotiating for width.
3784                          */
3785                         ahc_update_neg_request(ahc, devinfo, tstate,
3786                                                tinfo, AHC_NEG_ALWAYS);
3787                         ahc_set_width(ahc, devinfo, bus_width,
3788                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3789                                       /*paused*/TRUE);
3790                         if (sending_reply == FALSE && reject == FALSE) {
3791
3792                                 /*
3793                                  * We will always have an SDTR to send.
3794                                  */
3795                                 ahc->msgout_index = 0;
3796                                 ahc->msgout_len = 0;
3797                                 ahc_build_transfer_msg(ahc, devinfo);
3798                                 ahc->msgout_index = 0;
3799                                 response = TRUE;
3800                         }
3801                         done = MSGLOOP_MSGCOMPLETE;
3802                         break;
3803                 }
3804                 case MSG_EXT_PPR:
3805                 {
3806                         const struct ahc_syncrate *syncrate;
3807                         u_int   period;
3808                         u_int   offset;
3809                         u_int   bus_width;
3810                         u_int   ppr_options;
3811                         u_int   saved_width;
3812                         u_int   saved_offset;
3813                         u_int   saved_ppr_options;
3814
3815                         if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3816                                 reject = TRUE;
3817                                 break;
3818                         }
3819
3820                         /*
3821                          * Wait until we have all args before validating
3822                          * and acting on this message.
3823                          *
3824                          * Add one to MSG_EXT_PPR_LEN to account for
3825                          * the extended message preamble.
3826                          */
3827                         if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3828                                 break;
3829
3830                         period = ahc->msgin_buf[3];
3831                         offset = ahc->msgin_buf[5];
3832                         bus_width = ahc->msgin_buf[6];
3833                         saved_width = bus_width;
3834                         ppr_options = ahc->msgin_buf[7];
3835                         /*
3836                          * According to the spec, a DT only
3837                          * period factor with no DT option
3838                          * set implies async.
3839                          */
3840                         if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3841                          && period == 9)
3842                                 offset = 0;
3843                         saved_ppr_options = ppr_options;
3844                         saved_offset = offset;
3845
3846                         /*
3847                          * Mask out any options we don't support
3848                          * on any controller.  Transfer options are
3849                          * only available if we are negotiating wide.
3850                          */
3851                         ppr_options &= MSG_EXT_PPR_DT_REQ;
3852                         if (bus_width == 0)
3853                                 ppr_options = 0;
3854
3855                         ahc_validate_width(ahc, tinfo, &bus_width,
3856                                            devinfo->role);
3857                         syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3858                                                            &ppr_options,
3859                                                            devinfo->role);
3860                         ahc_validate_offset(ahc, tinfo, syncrate,
3861                                             &offset, bus_width,
3862                                             devinfo->role);
3863
3864                         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3865                                 /*
3866                                  * If we are unable to do any of the
3867                                  * requested options (we went too low),
3868                                  * then we'll have to reject the message.
3869                                  */
3870                                 if (saved_width > bus_width
3871                                  || saved_offset != offset
3872                                  || saved_ppr_options != ppr_options) {
3873                                         reject = TRUE;
3874                                         period = 0;
3875                                         offset = 0;
3876                                         bus_width = 0;
3877                                         ppr_options = 0;
3878                                         syncrate = NULL;
3879                                 }
3880                         } else {
3881                                 if (devinfo->role != ROLE_TARGET)
3882                                         printf("(%s:%c:%d:%d): Target "
3883                                                "Initiated PPR\n",
3884                                                ahc_name(ahc), devinfo->channel,
3885                                                devinfo->target, devinfo->lun);
3886                                 else
3887                                         printf("(%s:%c:%d:%d): Initiator "
3888                                                "Initiated PPR\n",
3889                                                ahc_name(ahc), devinfo->channel,
3890                                                devinfo->target, devinfo->lun);
3891                                 ahc->msgout_index = 0;
3892                                 ahc->msgout_len = 0;
3893                                 ahc_construct_ppr(ahc, devinfo, period, offset,
3894                                                   bus_width, ppr_options);
3895                                 ahc->msgout_index = 0;
3896                                 response = TRUE;
3897                         }
3898                         if (bootverbose) {
3899                                 printf("(%s:%c:%d:%d): Received PPR width %x, "
3900                                        "period %x, offset %x,options %x\n"
3901                                        "\tFiltered to width %x, period %x, "
3902                                        "offset %x, options %x\n",
3903                                        ahc_name(ahc), devinfo->channel,
3904                                        devinfo->target, devinfo->lun,
3905                                        saved_width, ahc->msgin_buf[3],
3906                                        saved_offset, saved_ppr_options,
3907                                        bus_width, period, offset, ppr_options);
3908                         }
3909                         ahc_set_width(ahc, devinfo, bus_width,
3910                                       AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3911                                       /*paused*/TRUE);
3912                         ahc_set_syncrate(ahc, devinfo,
3913                                          syncrate, period,
3914                                          offset, ppr_options,
3915                                          AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3916                                          /*paused*/TRUE);
3917                         done = MSGLOOP_MSGCOMPLETE;
3918                         break;
3919                 }
3920                 default:
3921                         /* Unknown extended message.  Reject it. */
3922                         reject = TRUE;
3923                         break;
3924                 }
3925                 break;
3926         }
3927 #ifdef AHC_TARGET_MODE
3928         case MSG_BUS_DEV_RESET:
3929                 ahc_handle_devreset(ahc, devinfo,
3930                                     CAM_BDR_SENT,
3931                                     "Bus Device Reset Received",
3932                                     /*verbose_level*/0);
3933                 ahc_restart(ahc);
3934                 done = MSGLOOP_TERMINATED;
3935                 break;
3936         case MSG_ABORT_TAG:
3937         case MSG_ABORT:
3938         case MSG_CLEAR_QUEUE:
3939         {
3940                 int tag;
3941
3942                 /* Target mode messages */
3943                 if (devinfo->role != ROLE_TARGET) {
3944                         reject = TRUE;
3945                         break;
3946                 }
3947                 tag = SCB_LIST_NULL;
3948                 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3949                         tag = ahc_inb(ahc, INITIATOR_TAG);
3950                 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3951                                devinfo->lun, tag, ROLE_TARGET,
3952                                CAM_REQ_ABORTED);
3953
3954                 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3955                 if (tstate != NULL) {
3956                         struct ahc_tmode_lstate* lstate;
3957
3958                         lstate = tstate->enabled_luns[devinfo->lun];
3959                         if (lstate != NULL) {
3960                                 ahc_queue_lstate_event(ahc, lstate,
3961                                                        devinfo->our_scsiid,
3962                                                        ahc->msgin_buf[0],
3963                                                        /*arg*/tag);
3964                                 ahc_send_lstate_events(ahc, lstate);
3965                         }
3966                 }
3967                 ahc_restart(ahc);
3968                 done = MSGLOOP_TERMINATED;
3969                 break;
3970         }
3971 #endif
3972         case MSG_TERM_IO_PROC:
3973         default:
3974                 reject = TRUE;
3975                 break;
3976         }
3977
3978         if (reject) {
3979                 /*
3980                  * Setup to reject the message.
3981                  */
3982                 ahc->msgout_index = 0;
3983                 ahc->msgout_len = 1;
3984                 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3985                 done = MSGLOOP_MSGCOMPLETE;
3986                 response = TRUE;
3987         }
3988
3989         if (done != MSGLOOP_IN_PROG && !response)
3990                 /* Clear the outgoing message buffer */
3991                 ahc->msgout_len = 0;
3992
3993         return (done);
3994 }
3995
3996 /*
3997  * Process a message reject message.
3998  */
3999 static int
4000 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4001 {
4002         /*
4003          * What we care about here is if we had an
4004          * outstanding SDTR or WDTR message for this
4005          * target.  If we did, this is a signal that
4006          * the target is refusing negotiation.
4007          */
4008         struct scb *scb;
4009         struct ahc_initiator_tinfo *tinfo;
4010         struct ahc_tmode_tstate *tstate;
4011         u_int scb_index;
4012         u_int last_msg;
4013         int   response = 0;
4014
4015         scb_index = ahc_inb(ahc, SCB_TAG);
4016         scb = ahc_lookup_scb(ahc, scb_index);
4017         tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
4018                                     devinfo->our_scsiid,
4019                                     devinfo->target, &tstate);
4020         /* Might be necessary */
4021         last_msg = ahc_inb(ahc, LAST_MSG);
4022
4023         if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4024                 /*
4025                  * Target does not support the PPR message.
4026                  * Attempt to negotiate SPI-2 style.
4027                  */
4028                 if (bootverbose) {
4029                         printf("(%s:%c:%d:%d): PPR Rejected. "
4030                                "Trying WDTR/SDTR\n",
4031                                ahc_name(ahc), devinfo->channel,
4032                                devinfo->target, devinfo->lun);
4033                 }
4034                 tinfo->goal.ppr_options = 0;
4035                 tinfo->curr.transport_version = 2;
4036                 tinfo->goal.transport_version = 2;
4037                 ahc->msgout_index = 0;
4038                 ahc->msgout_len = 0;
4039                 ahc_build_transfer_msg(ahc, devinfo);
4040                 ahc->msgout_index = 0;
4041                 response = 1;
4042         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4043
4044                 /* note 8bit xfers */
4045                 printf("(%s:%c:%d:%d): refuses WIDE negotiation.  Using "
4046                        "8bit transfers\n", ahc_name(ahc),
4047                        devinfo->channel, devinfo->target, devinfo->lun);
4048                 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4049                               AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4050                               /*paused*/TRUE);
4051                 /*
4052                  * No need to clear the sync rate.  If the target
4053                  * did not accept the command, our syncrate is
4054                  * unaffected.  If the target started the negotiation,
4055                  * but rejected our response, we already cleared the
4056                  * sync rate before sending our WDTR.
4057                  */
4058                 if (tinfo->goal.offset != tinfo->curr.offset) {
4059
4060                         /* Start the sync negotiation */
4061                         ahc->msgout_index = 0;
4062                         ahc->msgout_len = 0;
4063                         ahc_build_transfer_msg(ahc, devinfo);
4064                         ahc->msgout_index = 0;
4065                         response = 1;
4066                 }
4067         } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4068                 /* note asynch xfers and clear flag */
4069                 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
4070                                  /*offset*/0, /*ppr_options*/0,
4071                                  AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
4072                                  /*paused*/TRUE);
4073                 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4074                        "Using asynchronous transfers\n",
4075                        ahc_name(ahc), devinfo->channel,
4076                        devinfo->target, devinfo->lun);
4077         } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4078                 int tag_type;
4079                 int mask;
4080
4081                 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4082
4083                 if (tag_type == MSG_SIMPLE_TASK) {
4084                         printf("(%s:%c:%d:%d): refuses tagged commands.  "
4085                                "Performing non-tagged I/O\n", ahc_name(ahc),
4086                                devinfo->channel, devinfo->target, devinfo->lun);
4087                         ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE);
4088                         mask = ~0x23;
4089                 } else {
4090                         printf("(%s:%c:%d:%d): refuses %s tagged commands.  "
4091                                "Performing simple queue tagged I/O only\n",
4092                                ahc_name(ahc), devinfo->channel, devinfo->target,
4093                                devinfo->lun, tag_type == MSG_ORDERED_TASK
4094                                ? "ordered" : "head of queue");
4095                         ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC);
4096                         mask = ~0x03;
4097                 }
4098
4099                 /*
4100                  * Resend the identify for this CCB as the target
4101                  * may believe that the selection is invalid otherwise.
4102                  */
4103                 ahc_outb(ahc, SCB_CONTROL,
4104                          ahc_inb(ahc, SCB_CONTROL) & mask);
4105                 scb->hscb->control &= mask;
4106                 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
4107                                         /*type*/MSG_SIMPLE_TASK);
4108                 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
4109                 ahc_assert_atn(ahc);
4110
4111                 /*
4112                  * This transaction is now at the head of
4113                  * the untagged queue for this target.
4114                  */
4115                 if ((ahc->flags & AHC_SCB_BTT) == 0) {
4116                         struct scb_tailq *untagged_q;
4117
4118                         untagged_q =
4119                             &(ahc->untagged_queues[devinfo->target_offset]);
4120                         TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
4121                         scb->flags |= SCB_UNTAGGEDQ;
4122                 }
4123                 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4124                              scb->hscb->tag);
4125
4126                 /*
4127                  * Requeue all tagged commands for this target
4128                  * currently in our posession so they can be
4129                  * converted to untagged commands.
4130                  */
4131                 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
4132                                    SCB_GET_CHANNEL(ahc, scb),
4133                                    SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4134                                    ROLE_INITIATOR, CAM_REQUEUE_REQ,
4135                                    SEARCH_COMPLETE);
4136         } else {
4137                 /*
4138                  * Otherwise, we ignore it.
4139                  */
4140                 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4141                        ahc_name(ahc), devinfo->channel, devinfo->target,
4142                        last_msg);
4143         }
4144         return (response);
4145 }
4146
4147 /*
4148  * Process an ingnore wide residue message.
4149  */
4150 static void
4151 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
4152 {
4153         u_int scb_index;
4154         struct scb *scb;
4155
4156         scb_index = ahc_inb(ahc, SCB_TAG);
4157         scb = ahc_lookup_scb(ahc, scb_index);
4158         /*
4159          * XXX Actually check data direction in the sequencer?
4160          * Perhaps add datadir to some spare bits in the hscb?
4161          */
4162         if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
4163          || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
4164                 /*
4165                  * Ignore the message if we haven't
4166                  * seen an appropriate data phase yet.
4167                  */
4168         } else {
4169                 /*
4170                  * If the residual occurred on the last
4171                  * transfer and the transfer request was
4172                  * expected to end on an odd count, do
4173                  * nothing.  Otherwise, subtract a byte
4174                  * and update the residual count accordingly.
4175                  */
4176                 uint32_t sgptr;
4177
4178                 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4179                 if ((sgptr & SG_LIST_NULL) != 0
4180                  && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
4181                         /*
4182                          * If the residual occurred on the last
4183                          * transfer and the transfer request was
4184                          * expected to end on an odd count, do
4185                          * nothing.
4186                          */
4187                 } else {
4188                         struct ahc_dma_seg *sg;
4189                         uint32_t data_cnt;
4190                         uint32_t data_addr;
4191                         uint32_t sglen;
4192
4193                         /* Pull in all of the sgptr */
4194                         sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
4195                         data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
4196
4197                         if ((sgptr & SG_LIST_NULL) != 0) {
4198                                 /*
4199                                  * The residual data count is not updated
4200                                  * for the command run to completion case.
4201                                  * Explicitly zero the count.
4202                                  */
4203                                 data_cnt &= ~AHC_SG_LEN_MASK;
4204                         }
4205
4206                         data_addr = ahc_inl(ahc, SHADDR);
4207
4208                         data_cnt += 1;
4209                         data_addr -= 1;
4210                         sgptr &= SG_PTR_MASK;
4211
4212                         sg = ahc_sg_bus_to_virt(scb, sgptr);
4213
4214                         /*
4215                          * The residual sg ptr points to the next S/G
4216                          * to load so we must go back one.
4217                          */
4218                         sg--;
4219                         sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
4220                         if (sg != scb->sg_list
4221                          && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
4222
4223                                 sg--;
4224                                 sglen = ahc_le32toh(sg->len);
4225                                 /*
4226                                  * Preserve High Address and SG_LIST bits
4227                                  * while setting the count to 1.
4228                                  */
4229                                 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
4230                                 data_addr = ahc_le32toh(sg->addr)
4231                                           + (sglen & AHC_SG_LEN_MASK) - 1;
4232
4233                                 /*
4234                                  * Increment sg so it points to the
4235                                  * "next" sg.
4236                                  */
4237                                 sg++;
4238                                 sgptr = ahc_sg_virt_to_bus(scb, sg);
4239                         }
4240                         ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
4241                         ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
4242                         /*
4243                          * Toggle the "oddness" of the transfer length
4244                          * to handle this mid-transfer ignore wide
4245                          * residue.  This ensures that the oddness is
4246                          * correct for subsequent data transfers.
4247                          */
4248                         ahc_outb(ahc, SCB_LUN,
4249                                  ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
4250                 }
4251         }
4252 }
4253
4254
4255 /*
4256  * Reinitialize the data pointers for the active transfer
4257  * based on its current residual.
4258  */
4259 static void
4260 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
4261 {
4262         struct   scb *scb;
4263         struct   ahc_dma_seg *sg;
4264         u_int    scb_index;
4265         uint32_t sgptr;
4266         uint32_t resid;
4267         uint32_t dataptr;
4268
4269         scb_index = ahc_inb(ahc, SCB_TAG);
4270         scb = ahc_lookup_scb(ahc, scb_index);
4271         sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
4272               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
4273               | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
4274               | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
4275
4276         sgptr &= SG_PTR_MASK;
4277         sg = ahc_sg_bus_to_virt(scb, sgptr);
4278
4279         /* The residual sg_ptr always points to the next sg */
4280         sg--;
4281
4282         resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
4283               | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
4284               | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
4285
4286         dataptr = ahc_le32toh(sg->addr)
4287                 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
4288                 - resid;
4289         if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
4290                 u_int dscommand1;
4291
4292                 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
4293                 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
4294                 ahc_outb(ahc, HADDR,
4295                          (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
4296                 ahc_outb(ahc, DSCOMMAND1, dscommand1);
4297         }
4298         ahc_outb(ahc, HADDR + 3, dataptr >> 24);
4299         ahc_outb(ahc, HADDR + 2, dataptr >> 16);
4300         ahc_outb(ahc, HADDR + 1, dataptr >> 8);
4301         ahc_outb(ahc, HADDR, dataptr);
4302         ahc_outb(ahc, HCNT + 2, resid >> 16);
4303         ahc_outb(ahc, HCNT + 1, resid >> 8);
4304         ahc_outb(ahc, HCNT, resid);
4305         if ((ahc->features & AHC_ULTRA2) == 0) {
4306                 ahc_outb(ahc, STCNT + 2, resid >> 16);
4307                 ahc_outb(ahc, STCNT + 1, resid >> 8);
4308                 ahc_outb(ahc, STCNT, resid);
4309         }
4310 }
4311
4312 /*
4313  * Handle the effects of issuing a bus device reset message.
4314  */
4315 static void
4316 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4317                     cam_status status, char *message, int verbose_level)
4318 {
4319 #ifdef AHC_TARGET_MODE
4320         struct ahc_tmode_tstate* tstate;
4321         u_int lun;
4322 #endif
4323         int found;
4324
4325         found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
4326                                CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
4327                                status);
4328
4329 #ifdef AHC_TARGET_MODE
4330         /*
4331          * Send an immediate notify ccb to all target mord peripheral
4332          * drivers affected by this action.
4333          */
4334         tstate = ahc->enabled_targets[devinfo->our_scsiid];
4335         if (tstate != NULL) {
4336                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
4337                         struct ahc_tmode_lstate* lstate;
4338
4339                         lstate = tstate->enabled_luns[lun];
4340                         if (lstate == NULL)
4341                                 continue;
4342
4343                         ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
4344                                                MSG_BUS_DEV_RESET, /*arg*/0);
4345                         ahc_send_lstate_events(ahc, lstate);
4346                 }
4347         }
4348 #endif
4349
4350         /*
4351          * Go back to async/narrow transfers and renegotiate.
4352          */
4353         ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4354                       AHC_TRANS_CUR, /*paused*/TRUE);
4355         ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
4356                          /*period*/0, /*offset*/0, /*ppr_options*/0,
4357                          AHC_TRANS_CUR, /*paused*/TRUE);
4358
4359         if (status != CAM_SEL_TIMEOUT)
4360                 ahc_send_async(ahc, devinfo->channel, devinfo->target,
4361                                CAM_LUN_WILDCARD, AC_SENT_BDR);
4362
4363         if (message != NULL
4364          && (verbose_level <= bootverbose))
4365                 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
4366                        message, devinfo->channel, devinfo->target, found);
4367 }
4368
4369 #ifdef AHC_TARGET_MODE
4370 static void
4371 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
4372                        struct scb *scb)
4373 {
4374
4375         /*
4376          * To facilitate adding multiple messages together,
4377          * each routine should increment the index and len
4378          * variables instead of setting them explicitly.
4379          */
4380         ahc->msgout_index = 0;
4381         ahc->msgout_len = 0;
4382
4383         if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
4384                 ahc_build_transfer_msg(ahc, devinfo);
4385         else
4386                 panic("ahc_intr: AWAITING target message with no message");
4387
4388         ahc->msgout_index = 0;
4389         ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
4390 }
4391 #endif
4392 /**************************** Initialization **********************************/
4393 /*
4394  * Allocate a controller structure for a new device
4395  * and perform initial initializion.
4396  */
4397 struct ahc_softc *
4398 ahc_alloc(void *platform_arg, char *name)
4399 {
4400         struct  ahc_softc *ahc;
4401         int     i;
4402
4403 #ifndef __FreeBSD__
4404         ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
4405         if (!ahc) {
4406                 printf("aic7xxx: cannot malloc softc!\n");
4407                 free(name, M_DEVBUF);
4408                 return NULL;
4409         }
4410 #else
4411         ahc = device_get_softc((device_t)platform_arg);
4412 #endif
4413         memset(ahc, 0, sizeof(*ahc));
4414         ahc->seep_config = malloc(sizeof(*ahc->seep_config),
4415                                   M_DEVBUF, M_NOWAIT);
4416         if (ahc->seep_config == NULL) {
4417 #ifndef __FreeBSD__
4418                 free(ahc, M_DEVBUF);
4419 #endif
4420                 free(name, M_DEVBUF);
4421                 return (NULL);
4422         }
4423         LIST_INIT(&ahc->pending_scbs);
4424         /* We don't know our unit number until the OSM sets it */
4425         ahc->name = name;
4426         ahc->unit = -1;
4427         ahc->description = NULL;
4428         ahc->channel = 'A';
4429         ahc->channel_b = 'B';
4430         ahc->chip = AHC_NONE;
4431         ahc->features = AHC_FENONE;
4432         ahc->bugs = AHC_BUGNONE;
4433         ahc->flags = AHC_FNONE;
4434         /*
4435          * Default to all error reporting enabled with the
4436          * sequencer operating at its fastest speed.
4437          * The bus attach code may modify this.
4438          */
4439         ahc->seqctl = FASTMODE;
4440
4441         for (i = 0; i < AHC_NUM_TARGETS; i++)
4442                 TAILQ_INIT(&ahc->untagged_queues[i]);
4443         if (ahc_platform_alloc(ahc, platform_arg) != 0) {
4444                 ahc_free(ahc);
4445                 ahc = NULL;
4446         }
4447         return (ahc);
4448 }
4449
4450 int
4451 ahc_softc_init(struct ahc_softc *ahc)
4452 {
4453
4454         /* The IRQMS bit is only valid on VL and EISA chips */
4455         if ((ahc->chip & AHC_PCI) == 0)
4456                 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
4457         else
4458                 ahc->unpause = 0;
4459         ahc->pause = ahc->unpause | PAUSE;
4460         /* XXX The shared scb data stuff should be deprecated */
4461         if (ahc->scb_data == NULL) {
4462                 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
4463                                        M_DEVBUF, M_NOWAIT);
4464                 if (ahc->scb_data == NULL)
4465                         return (ENOMEM);
4466                 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
4467         }
4468
4469         return (0);
4470 }
4471
4472 void
4473 ahc_set_unit(struct ahc_softc *ahc, int unit)
4474 {
4475         ahc->unit = unit;
4476 }
4477
4478 void
4479 ahc_set_name(struct ahc_softc *ahc, char *name)
4480 {
4481         if (ahc->name != NULL)
4482                 free(ahc->name, M_DEVBUF);
4483         ahc->name = name;
4484 }
4485
4486 void
4487 ahc_free(struct ahc_softc *ahc)
4488 {
4489         int i;
4490
4491         switch (ahc->init_level) {
4492         default:
4493         case 5:
4494                 ahc_shutdown(ahc);
4495                 /* FALLTHROUGH */
4496         case 4:
4497                 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
4498                                   ahc->shared_data_dmamap);
4499                 /* FALLTHROUGH */
4500         case 3:
4501                 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
4502                                 ahc->shared_data_dmamap);
4503                 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
4504                                    ahc->shared_data_dmamap);
4505                 /* FALLTHROUGH */
4506         case 2:
4507                 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
4508         case 1:
4509 #ifndef __linux__
4510                 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
4511 #endif
4512                 break;
4513         case 0:
4514                 break;
4515         }
4516
4517 #ifndef __linux__
4518         ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
4519 #endif
4520         ahc_platform_free(ahc);
4521         ahc_fini_scbdata(ahc);
4522         for (i = 0; i < AHC_NUM_TARGETS; i++) {
4523                 struct ahc_tmode_tstate *tstate;
4524
4525                 tstate = ahc->enabled_targets[i];
4526                 if (tstate != NULL) {
4527 #ifdef AHC_TARGET_MODE
4528                         int j;
4529
4530                         for (j = 0; j < AHC_NUM_LUNS; j++) {
4531                                 struct ahc_tmode_lstate *lstate;
4532
4533                                 lstate = tstate->enabled_luns[j];
4534                                 if (lstate != NULL) {
4535                                         xpt_free_path(lstate->path);
4536                                         free(lstate, M_DEVBUF);
4537                                 }
4538                         }
4539 #endif
4540                         free(tstate, M_DEVBUF);
4541                 }
4542         }
4543 #ifdef AHC_TARGET_MODE
4544         if (ahc->black_hole != NULL) {
4545                 xpt_free_path(ahc->black_hole->path);
4546                 free(ahc->black_hole, M_DEVBUF);
4547         }
4548 #endif
4549         if (ahc->name != NULL)
4550                 free(ahc->name, M_DEVBUF);
4551         if (ahc->seep_config != NULL)
4552                 free(ahc->seep_config, M_DEVBUF);
4553 #ifndef __FreeBSD__
4554         free(ahc, M_DEVBUF);
4555 #endif
4556         return;
4557 }
4558
4559 static void
4560 ahc_shutdown(void *arg)
4561 {
4562         struct  ahc_softc *ahc;
4563         int     i;
4564
4565         ahc = (struct ahc_softc *)arg;
4566
4567         /* This will reset most registers to 0, but not all */
4568         ahc_reset(ahc, /*reinit*/FALSE);
4569         ahc_outb(ahc, SCSISEQ, 0);
4570         ahc_outb(ahc, SXFRCTL0, 0);
4571         ahc_outb(ahc, DSPCISTATUS, 0);
4572
4573         for (i = TARG_SCSIRATE; i < SCSICONF; i++)
4574                 ahc_outb(ahc, i, 0);
4575 }
4576
4577 /*
4578  * Reset the controller and record some information about it
4579  * that is only available just after a reset.  If "reinit" is
4580  * non-zero, this reset occured after initial configuration
4581  * and the caller requests that the chip be fully reinitialized
4582  * to a runable state.  Chip interrupts are *not* enabled after
4583  * a reinitialization.  The caller must enable interrupts via
4584  * ahc_intr_enable().
4585  */
4586 int
4587 ahc_reset(struct ahc_softc *ahc, int reinit)
4588 {
4589         u_int   sblkctl;
4590         u_int   sxfrctl1_a, sxfrctl1_b;
4591         int     error;
4592         int     wait;
4593
4594         /*
4595          * Preserve the value of the SXFRCTL1 register for all channels.
4596          * It contains settings that affect termination and we don't want
4597          * to disturb the integrity of the bus.
4598          */
4599         ahc_pause(ahc);
4600         sxfrctl1_b = 0;
4601         if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4602                 u_int sblkctl;
4603
4604                 /*
4605                  * Save channel B's settings in case this chip
4606                  * is setup for TWIN channel operation.
4607                  */
4608                 sblkctl = ahc_inb(ahc, SBLKCTL);
4609                 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4610                 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4611                 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4612         }
4613         sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4614
4615         ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4616
4617         /*
4618          * Ensure that the reset has finished.  We delay 1000us
4619          * prior to reading the register to make sure the chip
4620          * has sufficiently completed its reset to handle register
4621          * accesses.
4622          */
4623         wait = 1000;
4624         do {
4625                 ahc_delay(1000);
4626         } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4627
4628         if (wait == 0) {
4629                 printf("%s: WARNING - Failed chip reset!  "
4630                        "Trying to initialize anyway.\n", ahc_name(ahc));
4631         }
4632         ahc_outb(ahc, HCNTRL, ahc->pause);
4633
4634         /* Determine channel configuration */
4635         sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4636         /* No Twin Channel PCI cards */
4637         if ((ahc->chip & AHC_PCI) != 0)
4638                 sblkctl &= ~SELBUSB;
4639         switch (sblkctl) {
4640         case 0:
4641                 /* Single Narrow Channel */
4642                 break;
4643         case 2:
4644                 /* Wide Channel */
4645                 ahc->features |= AHC_WIDE;
4646                 break;
4647         case 8:
4648                 /* Twin Channel */
4649                 ahc->features |= AHC_TWIN;
4650                 break;
4651         default:
4652                 printf(" Unsupported adapter type.  Ignoring\n");
4653                 return(-1);
4654         }
4655
4656         /*
4657          * Reload sxfrctl1.
4658          *
4659          * We must always initialize STPWEN to 1 before we
4660          * restore the saved values.  STPWEN is initialized
4661          * to a tri-state condition which can only be cleared
4662          * by turning it on.
4663          */
4664         if ((ahc->features & AHC_TWIN) != 0) {
4665                 u_int sblkctl;
4666
4667                 sblkctl = ahc_inb(ahc, SBLKCTL);
4668                 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4669                 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4670                 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4671         }
4672         ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4673
4674         error = 0;
4675         if (reinit != 0)
4676                 /*
4677                  * If a recovery action has forced a chip reset,
4678                  * re-initialize the chip to our liking.
4679                  */
4680                 error = ahc->bus_chip_init(ahc);
4681 #ifdef AHC_DUMP_SEQ
4682         else
4683                 ahc_dumpseq(ahc);
4684 #endif
4685
4686         return (error);
4687 }
4688
4689 /*
4690  * Determine the number of SCBs available on the controller
4691  */
4692 int
4693 ahc_probe_scbs(struct ahc_softc *ahc) {
4694         int i;
4695
4696         for (i = 0; i < AHC_SCB_MAX; i++) {
4697
4698                 ahc_outb(ahc, SCBPTR, i);
4699                 ahc_outb(ahc, SCB_BASE, i);
4700                 if (ahc_inb(ahc, SCB_BASE) != i)
4701                         break;
4702                 ahc_outb(ahc, SCBPTR, 0);
4703                 if (ahc_inb(ahc, SCB_BASE) != 0)
4704                         break;
4705         }
4706         return (i);
4707 }
4708
4709 static void
4710 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4711 {
4712         dma_addr_t *baddr;
4713
4714         baddr = (dma_addr_t *)arg;
4715         *baddr = segs->ds_addr;
4716 }
4717
4718 static void
4719 ahc_build_free_scb_list(struct ahc_softc *ahc)
4720 {
4721         int scbsize;
4722         int i;
4723
4724         scbsize = 32;
4725         if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4726                 scbsize = 64;
4727
4728         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4729                 int j;
4730
4731                 ahc_outb(ahc, SCBPTR, i);
4732
4733                 /*
4734                  * Touch all SCB bytes to avoid parity errors
4735                  * should one of our debugging routines read
4736                  * an otherwise uninitiatlized byte.
4737                  */
4738                 for (j = 0; j < scbsize; j++)
4739                         ahc_outb(ahc, SCB_BASE+j, 0xFF);
4740
4741                 /* Clear the control byte. */
4742                 ahc_outb(ahc, SCB_CONTROL, 0);
4743
4744                 /* Set the next pointer */
4745                 if ((ahc->flags & AHC_PAGESCBS) != 0)
4746                         ahc_outb(ahc, SCB_NEXT, i+1);
4747                 else
4748                         ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4749
4750                 /* Make the tag number, SCSIID, and lun invalid */
4751                 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4752                 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4753                 ahc_outb(ahc, SCB_LUN, 0xFF);
4754         }
4755
4756         if ((ahc->flags & AHC_PAGESCBS) != 0) {
4757                 /* SCB 0 heads the free list. */
4758                 ahc_outb(ahc, FREE_SCBH, 0);
4759         } else {
4760                 /* No free list. */
4761                 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4762         }
4763
4764         /* Make sure that the last SCB terminates the free list */
4765         ahc_outb(ahc, SCBPTR, i-1);
4766         ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4767 }
4768
4769 static int
4770 ahc_init_scbdata(struct ahc_softc *ahc)
4771 {
4772         struct scb_data *scb_data;
4773
4774         scb_data = ahc->scb_data;
4775         SLIST_INIT(&scb_data->free_scbs);
4776         SLIST_INIT(&scb_data->sg_maps);
4777
4778         /* Allocate SCB resources */
4779         scb_data->scbarray =
4780             (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4781                                  M_DEVBUF, M_NOWAIT);
4782         if (scb_data->scbarray == NULL)
4783                 return (ENOMEM);
4784         memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4785
4786         /* Determine the number of hardware SCBs and initialize them */
4787
4788         scb_data->maxhscbs = ahc_probe_scbs(ahc);
4789         if (ahc->scb_data->maxhscbs == 0) {
4790                 printf("%s: No SCB space found\n", ahc_name(ahc));
4791                 return (ENXIO);
4792         }
4793
4794         /*
4795          * Create our DMA tags.  These tags define the kinds of device
4796          * accessible memory allocations and memory mappings we will
4797          * need to perform during normal operation.
4798          *
4799          * Unless we need to further restrict the allocation, we rely
4800          * on the restrictions of the parent dmat, hence the common
4801          * use of MAXADDR and MAXSIZE.
4802          */
4803
4804         /* DMA tag for our hardware scb structures */
4805         if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4806                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4807                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4808                                /*highaddr*/BUS_SPACE_MAXADDR,
4809                                /*filter*/NULL, /*filterarg*/NULL,
4810                                AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4811                                /*nsegments*/1,
4812                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4813                                /*flags*/0, &scb_data->hscb_dmat) != 0) {
4814                 goto error_exit;
4815         }
4816
4817         scb_data->init_level++;
4818
4819         /* Allocation for our hscbs */
4820         if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4821                              (void **)&scb_data->hscbs,
4822                              BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4823                 goto error_exit;
4824         }
4825
4826         scb_data->init_level++;
4827
4828         /* And permanently map them */
4829         ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4830                         scb_data->hscbs,
4831                         AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4832                         ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4833
4834         scb_data->init_level++;
4835
4836         /* DMA tag for our sense buffers */
4837         if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4838                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4839                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4840                                /*highaddr*/BUS_SPACE_MAXADDR,
4841                                /*filter*/NULL, /*filterarg*/NULL,
4842                                AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4843                                /*nsegments*/1,
4844                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4845                                /*flags*/0, &scb_data->sense_dmat) != 0) {
4846                 goto error_exit;
4847         }
4848
4849         scb_data->init_level++;
4850
4851         /* Allocate them */
4852         if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4853                              (void **)&scb_data->sense,
4854                              BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4855                 goto error_exit;
4856         }
4857
4858         scb_data->init_level++;
4859
4860         /* And permanently map them */
4861         ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4862                         scb_data->sense,
4863                         AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4864                         ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4865
4866         scb_data->init_level++;
4867
4868         /* DMA tag for our S/G structures.  We allocate in page sized chunks */
4869         if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4870                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4871                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4872                                /*highaddr*/BUS_SPACE_MAXADDR,
4873                                /*filter*/NULL, /*filterarg*/NULL,
4874                                PAGE_SIZE, /*nsegments*/1,
4875                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4876                                /*flags*/0, &scb_data->sg_dmat) != 0) {
4877                 goto error_exit;
4878         }
4879
4880         scb_data->init_level++;
4881
4882         /* Perform initial CCB allocation */
4883         memset(scb_data->hscbs, 0,
4884                AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4885         ahc_alloc_scbs(ahc);
4886
4887         if (scb_data->numscbs == 0) {
4888                 printf("%s: ahc_init_scbdata - "
4889                        "Unable to allocate initial scbs\n",
4890                        ahc_name(ahc));
4891                 goto error_exit;
4892         }
4893
4894         /*
4895          * Reserve the next queued SCB.
4896          */
4897         ahc->next_queued_scb = ahc_get_scb(ahc);
4898
4899         /*
4900          * Note that we were successfull
4901          */
4902         return (0);
4903
4904 error_exit:
4905
4906         return (ENOMEM);
4907 }
4908
4909 static void
4910 ahc_fini_scbdata(struct ahc_softc *ahc)
4911 {
4912         struct scb_data *scb_data;
4913
4914         scb_data = ahc->scb_data;
4915         if (scb_data == NULL)
4916                 return;
4917
4918         switch (scb_data->init_level) {
4919         default:
4920         case 7:
4921         {
4922                 struct sg_map_node *sg_map;
4923
4924                 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4925                         SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4926                         ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4927                                           sg_map->sg_dmamap);
4928                         ahc_dmamem_free(ahc, scb_data->sg_dmat,
4929                                         sg_map->sg_vaddr,
4930                                         sg_map->sg_dmamap);
4931                         free(sg_map, M_DEVBUF);
4932                 }
4933                 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4934         }
4935         case 6:
4936                 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4937                                   scb_data->sense_dmamap);
4938         case 5:
4939                 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4940                                 scb_data->sense_dmamap);
4941                 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4942                                    scb_data->sense_dmamap);
4943         case 4:
4944                 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4945         case 3:
4946                 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4947                                   scb_data->hscb_dmamap);
4948         case 2:
4949                 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4950                                 scb_data->hscb_dmamap);
4951                 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4952                                    scb_data->hscb_dmamap);
4953         case 1:
4954                 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4955                 break;
4956         case 0:
4957                 break;
4958         }
4959         if (scb_data->scbarray != NULL)
4960                 free(scb_data->scbarray, M_DEVBUF);
4961 }
4962
4963 static void
4964 ahc_alloc_scbs(struct ahc_softc *ahc)
4965 {
4966         struct scb_data *scb_data;
4967         struct scb *next_scb;
4968         struct sg_map_node *sg_map;
4969         dma_addr_t physaddr;
4970         struct ahc_dma_seg *segs;
4971         int newcount;
4972         int i;
4973
4974         scb_data = ahc->scb_data;
4975         if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4976                 /* Can't allocate any more */
4977                 return;
4978
4979         next_scb = &scb_data->scbarray[scb_data->numscbs];
4980
4981         sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4982
4983         if (sg_map == NULL)
4984                 return;
4985
4986         /* Allocate S/G space for the next batch of SCBS */
4987         if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4988                              (void **)&sg_map->sg_vaddr,
4989                              BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4990                 free(sg_map, M_DEVBUF);
4991                 return;
4992         }
4993
4994         SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4995
4996         ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4997                         sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4998                         &sg_map->sg_physaddr, /*flags*/0);
4999
5000         segs = sg_map->sg_vaddr;
5001         physaddr = sg_map->sg_physaddr;
5002
5003         newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
5004         newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
5005         for (i = 0; i < newcount; i++) {
5006                 struct scb_platform_data *pdata;
5007 #ifndef __linux__
5008                 int error;
5009 #endif
5010                 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
5011                                                            M_DEVBUF, M_NOWAIT);
5012                 if (pdata == NULL)
5013                         break;
5014                 next_scb->platform_data = pdata;
5015                 next_scb->sg_map = sg_map;
5016                 next_scb->sg_list = segs;
5017                 /*
5018                  * The sequencer always starts with the second entry.
5019                  * The first entry is embedded in the scb.
5020                  */
5021                 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
5022                 next_scb->ahc_softc = ahc;
5023                 next_scb->flags = SCB_FREE;
5024 #ifndef __linux__
5025                 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
5026                                           &next_scb->dmamap);
5027                 if (error != 0)
5028                         break;
5029 #endif
5030                 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
5031                 next_scb->hscb->tag = ahc->scb_data->numscbs;
5032                 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
5033                                   next_scb, links.sle);
5034                 segs += AHC_NSEG;
5035                 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
5036                 next_scb++;
5037                 ahc->scb_data->numscbs++;
5038         }
5039 }
5040
5041 void
5042 ahc_controller_info(struct ahc_softc *ahc, char *buf)
5043 {
5044         int len;
5045
5046         len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
5047         buf += len;
5048         if ((ahc->features & AHC_TWIN) != 0)
5049                 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
5050                               "B SCSI Id=%d, primary %c, ",
5051                               ahc->our_id, ahc->our_id_b,
5052                               (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
5053         else {
5054                 const char *speed;
5055                 const char *type;
5056
5057                 speed = "";
5058                 if ((ahc->features & AHC_ULTRA) != 0) {
5059                         speed = "Ultra ";
5060                 } else if ((ahc->features & AHC_DT) != 0) {
5061                         speed = "Ultra160 ";
5062                 } else if ((ahc->features & AHC_ULTRA2) != 0) {
5063                         speed = "Ultra2 ";
5064                 }
5065                 if ((ahc->features & AHC_WIDE) != 0) {
5066                         type = "Wide";
5067                 } else {
5068                         type = "Single";
5069                 }
5070                 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
5071                               speed, type, ahc->channel, ahc->our_id);
5072         }
5073         buf += len;
5074
5075         if ((ahc->flags & AHC_PAGESCBS) != 0)
5076                 sprintf(buf, "%d/%d SCBs",
5077                         ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
5078         else
5079                 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
5080 }
5081
5082 int
5083 ahc_chip_init(struct ahc_softc *ahc)
5084 {
5085         int      term;
5086         int      error;
5087         u_int    i;
5088         u_int    scsi_conf;
5089         u_int    scsiseq_template;
5090         uint32_t physaddr;
5091
5092         ahc_outb(ahc, SEQ_FLAGS, 0);
5093         ahc_outb(ahc, SEQ_FLAGS2, 0);
5094
5095         /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
5096         if (ahc->features & AHC_TWIN) {
5097
5098                 /*
5099                  * Setup Channel B first.
5100                  */
5101                 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
5102                 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
5103                 ahc_outb(ahc, SCSIID, ahc->our_id_b);
5104                 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5105                 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5106                                         |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
5107                 if ((ahc->features & AHC_ULTRA2) != 0)
5108                         ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5109                 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5110                 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5111
5112                 /* Select Channel A */
5113                 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
5114         }
5115         term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
5116         if ((ahc->features & AHC_ULTRA2) != 0)
5117                 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
5118         else
5119                 ahc_outb(ahc, SCSIID, ahc->our_id);
5120         scsi_conf = ahc_inb(ahc, SCSICONF);
5121         ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
5122                                 |term|ahc->seltime
5123                                 |ENSTIMER|ACTNEGEN);
5124         if ((ahc->features & AHC_ULTRA2) != 0)
5125                 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
5126         ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
5127         ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
5128
5129         /* There are no untagged SCBs active yet. */
5130         for (i = 0; i < 16; i++) {
5131                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
5132                 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5133                         int lun;
5134
5135                         /*
5136                          * The SCB based BTT allows an entry per
5137                          * target and lun pair.
5138                          */
5139                         for (lun = 1; lun < AHC_NUM_LUNS; lun++)
5140                                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
5141                 }
5142         }
5143
5144         /* All of our queues are empty */
5145         for (i = 0; i < 256; i++)
5146                 ahc->qoutfifo[i] = SCB_LIST_NULL;
5147         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
5148
5149         for (i = 0; i < 256; i++)
5150                 ahc->qinfifo[i] = SCB_LIST_NULL;
5151
5152         if ((ahc->features & AHC_MULTI_TID) != 0) {
5153                 ahc_outb(ahc, TARGID, 0);
5154                 ahc_outb(ahc, TARGID + 1, 0);
5155         }
5156
5157         /*
5158          * Tell the sequencer where it can find our arrays in memory.
5159          */
5160         physaddr = ahc->scb_data->hscb_busaddr;
5161         ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
5162         ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
5163         ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
5164         ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
5165
5166         physaddr = ahc->shared_data_busaddr;
5167         ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
5168         ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
5169         ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
5170         ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
5171
5172         /*
5173          * Initialize the group code to command length table.
5174          * This overrides the values in TARG_SCSIRATE, so only
5175          * setup the table after we have processed that information.
5176          */
5177         ahc_outb(ahc, CMDSIZE_TABLE, 5);
5178         ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
5179         ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
5180         ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
5181         ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
5182         ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
5183         ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
5184         ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
5185
5186         if ((ahc->features & AHC_HS_MAILBOX) != 0)
5187                 ahc_outb(ahc, HS_MAILBOX, 0);
5188
5189         /* Tell the sequencer of our initial queue positions */
5190         if ((ahc->features & AHC_TARGETMODE) != 0) {
5191                 ahc->tqinfifonext = 1;
5192                 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
5193                 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
5194         }
5195         ahc->qinfifonext = 0;
5196         ahc->qoutfifonext = 0;
5197         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5198                 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
5199                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5200                 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
5201                 ahc_outb(ahc, SDSCB_QOFF, 0);
5202         } else {
5203                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5204                 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
5205                 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
5206         }
5207
5208         /* We don't have any waiting selections */
5209         ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
5210
5211         /* Our disconnection list is empty too */
5212         ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
5213
5214         /* Message out buffer starts empty */
5215         ahc_outb(ahc, MSG_OUT, MSG_NOOP);
5216
5217         /*
5218          * Setup the allowed SCSI Sequences based on operational mode.
5219          * If we are a target, we'll enalbe select in operations once
5220          * we've had a lun enabled.
5221          */
5222         scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
5223         if ((ahc->flags & AHC_INITIATORROLE) != 0)
5224                 scsiseq_template |= ENRSELI;
5225         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
5226
5227         /* Initialize our list of free SCBs. */
5228         ahc_build_free_scb_list(ahc);
5229
5230         /*
5231          * Tell the sequencer which SCB will be the next one it receives.
5232          */
5233         ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5234
5235         /*
5236          * Load the Sequencer program and Enable the adapter
5237          * in "fast" mode.
5238          */
5239         if (bootverbose)
5240                 printf("%s: Downloading Sequencer Program...",
5241                        ahc_name(ahc));
5242
5243         error = ahc_loadseq(ahc);
5244         if (error != 0)
5245                 return (error);
5246
5247         if ((ahc->features & AHC_ULTRA2) != 0) {
5248                 int wait;
5249
5250                 /*
5251                  * Wait for up to 500ms for our transceivers
5252                  * to settle.  If the adapter does not have
5253                  * a cable attached, the transceivers may
5254                  * never settle, so don't complain if we
5255                  * fail here.
5256                  */
5257                 for (wait = 5000;
5258                      (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
5259                      wait--)
5260                         ahc_delay(100);
5261         }
5262         ahc_restart(ahc);
5263         return (0);
5264 }
5265
5266 /*
5267  * Start the board, ready for normal operation
5268  */
5269 int
5270 ahc_init(struct ahc_softc *ahc)
5271 {
5272         int      max_targ;
5273         u_int    i;
5274         u_int    scsi_conf;
5275         u_int    ultraenb;
5276         u_int    discenable;
5277         u_int    tagenable;
5278         size_t   driver_data_size;
5279
5280 #ifdef AHC_DEBUG
5281         if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
5282                 ahc->flags |= AHC_SEQUENCER_DEBUG;
5283 #endif
5284
5285 #ifdef AHC_PRINT_SRAM
5286         printf("Scratch Ram:");
5287         for (i = 0x20; i < 0x5f; i++) {
5288                 if (((i % 8) == 0) && (i != 0)) {
5289                         printf ("\n              ");
5290                 }
5291                 printf (" 0x%x", ahc_inb(ahc, i));
5292         }
5293         if ((ahc->features & AHC_MORE_SRAM) != 0) {
5294                 for (i = 0x70; i < 0x7f; i++) {
5295                         if (((i % 8) == 0) && (i != 0)) {
5296                                 printf ("\n              ");
5297                         }
5298                         printf (" 0x%x", ahc_inb(ahc, i));
5299                 }
5300         }
5301         printf ("\n");
5302         /*
5303          * Reading uninitialized scratch ram may
5304          * generate parity errors.
5305          */
5306         ahc_outb(ahc, CLRINT, CLRPARERR);
5307         ahc_outb(ahc, CLRINT, CLRBRKADRINT);
5308 #endif
5309         max_targ = 15;
5310
5311         /*
5312          * Assume we have a board at this stage and it has been reset.
5313          */
5314         if ((ahc->flags & AHC_USEDEFAULTS) != 0)
5315                 ahc->our_id = ahc->our_id_b = 7;
5316
5317         /*
5318          * Default to allowing initiator operations.
5319          */
5320         ahc->flags |= AHC_INITIATORROLE;
5321
5322         /*
5323          * Only allow target mode features if this unit has them enabled.
5324          */
5325         if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
5326                 ahc->features &= ~AHC_TARGETMODE;
5327
5328 #ifndef __linux__
5329         /* DMA tag for mapping buffers into device visible space. */
5330         if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5331                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5332                                /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
5333                                         ? (dma_addr_t)0x7FFFFFFFFFULL
5334                                         : BUS_SPACE_MAXADDR_32BIT,
5335                                /*highaddr*/BUS_SPACE_MAXADDR,
5336                                /*filter*/NULL, /*filterarg*/NULL,
5337                                /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
5338                                /*nsegments*/AHC_NSEG,
5339                                /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
5340                                /*flags*/BUS_DMA_ALLOCNOW,
5341                                &ahc->buffer_dmat) != 0) {
5342                 return (ENOMEM);
5343         }
5344 #endif
5345
5346         ahc->init_level++;
5347
5348         /*
5349          * DMA tag for our command fifos and other data in system memory
5350          * the card's sequencer must be able to access.  For initiator
5351          * roles, we need to allocate space for the qinfifo and qoutfifo.
5352          * The qinfifo and qoutfifo are composed of 256 1 byte elements.
5353          * When providing for the target mode role, we must additionally
5354          * provide space for the incoming target command fifo and an extra
5355          * byte to deal with a dma bug in some chip versions.
5356          */
5357         driver_data_size = 2 * 256 * sizeof(uint8_t);
5358         if ((ahc->features & AHC_TARGETMODE) != 0)
5359                 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
5360                                  + /*DMA WideOdd Bug Buffer*/1;
5361         if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
5362                                /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5363                                /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5364                                /*highaddr*/BUS_SPACE_MAXADDR,
5365                                /*filter*/NULL, /*filterarg*/NULL,
5366                                driver_data_size,
5367                                /*nsegments*/1,
5368                                /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5369                                /*flags*/0, &ahc->shared_data_dmat) != 0) {
5370                 return (ENOMEM);
5371         }
5372
5373         ahc->init_level++;
5374
5375         /* Allocation of driver data */
5376         if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
5377                              (void **)&ahc->qoutfifo,
5378                              BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
5379                 return (ENOMEM);
5380         }
5381
5382         ahc->init_level++;
5383
5384         /* And permanently map it in */
5385         ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
5386                         ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
5387                         &ahc->shared_data_busaddr, /*flags*/0);
5388
5389         if ((ahc->features & AHC_TARGETMODE) != 0) {
5390                 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
5391                 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
5392                 ahc->dma_bug_buf = ahc->shared_data_busaddr
5393                                  + driver_data_size - 1;
5394                 /* All target command blocks start out invalid. */
5395                 for (i = 0; i < AHC_TMODE_CMDS; i++)
5396                         ahc->targetcmds[i].cmd_valid = 0;
5397                 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
5398                 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
5399         }
5400         ahc->qinfifo = &ahc->qoutfifo[256];
5401
5402         ahc->init_level++;
5403
5404         /* Allocate SCB data now that buffer_dmat is initialized */
5405         if (ahc->scb_data->maxhscbs == 0)
5406                 if (ahc_init_scbdata(ahc) != 0)
5407                         return (ENOMEM);
5408
5409         /*
5410          * Allocate a tstate to house information for our
5411          * initiator presence on the bus as well as the user
5412          * data for any target mode initiator.
5413          */
5414         if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
5415                 printf("%s: unable to allocate ahc_tmode_tstate.  "
5416                        "Failing attach\n", ahc_name(ahc));
5417                 return (ENOMEM);
5418         }
5419
5420         if ((ahc->features & AHC_TWIN) != 0) {
5421                 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
5422                         printf("%s: unable to allocate ahc_tmode_tstate.  "
5423                                "Failing attach\n", ahc_name(ahc));
5424                         return (ENOMEM);
5425                 }
5426         }
5427
5428         if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
5429                 ahc->flags |= AHC_PAGESCBS;
5430         } else {
5431                 ahc->flags &= ~AHC_PAGESCBS;
5432         }
5433
5434 #ifdef AHC_DEBUG
5435         if (ahc_debug & AHC_SHOW_MISC) {
5436                 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
5437                        "ahc_dma %u bytes\n",
5438                         ahc_name(ahc),
5439                         (u_int)sizeof(struct hardware_scb),
5440                         (u_int)sizeof(struct scb),
5441                         (u_int)sizeof(struct ahc_dma_seg));
5442         }
5443 #endif /* AHC_DEBUG */
5444
5445         /*
5446          * Look at the information that board initialization or
5447          * the board bios has left us.
5448          */
5449         if (ahc->features & AHC_TWIN) {
5450                 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
5451                 if ((scsi_conf & RESET_SCSI) != 0
5452                  && (ahc->flags & AHC_INITIATORROLE) != 0)
5453                         ahc->flags |= AHC_RESET_BUS_B;
5454         }
5455
5456         scsi_conf = ahc_inb(ahc, SCSICONF);
5457         if ((scsi_conf & RESET_SCSI) != 0
5458          && (ahc->flags & AHC_INITIATORROLE) != 0)
5459                 ahc->flags |= AHC_RESET_BUS_A;
5460
5461         ultraenb = 0;
5462         tagenable = ALL_TARGETS_MASK;
5463
5464         /* Grab the disconnection disable table and invert it for our needs */
5465         if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
5466                 printf("%s: Host Adapter Bios disabled.  Using default SCSI "
5467                         "device parameters\n", ahc_name(ahc));
5468                 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
5469                               AHC_TERM_ENB_A|AHC_TERM_ENB_B;
5470                 discenable = ALL_TARGETS_MASK;
5471                 if ((ahc->features & AHC_ULTRA) != 0)
5472                         ultraenb = ALL_TARGETS_MASK;
5473         } else {
5474                 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
5475                            | ahc_inb(ahc, DISC_DSB));
5476                 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
5477                         ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
5478                                       | ahc_inb(ahc, ULTRA_ENB);
5479         }
5480
5481         if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
5482                 max_targ = 7;
5483
5484         for (i = 0; i <= max_targ; i++) {
5485                 struct ahc_initiator_tinfo *tinfo;
5486                 struct ahc_tmode_tstate *tstate;
5487                 u_int our_id;
5488                 u_int target_id;
5489                 char channel;
5490
5491                 channel = 'A';
5492                 our_id = ahc->our_id;
5493                 target_id = i;
5494                 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
5495                         channel = 'B';
5496                         our_id = ahc->our_id_b;
5497                         target_id = i % 8;
5498                 }
5499                 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
5500                                             target_id, &tstate);
5501                 /* Default to async narrow across the board */
5502                 memset(tinfo, 0, sizeof(*tinfo));
5503                 if (ahc->flags & AHC_USEDEFAULTS) {
5504                         if ((ahc->features & AHC_WIDE) != 0)
5505                                 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5506
5507                         /*
5508                          * These will be truncated when we determine the
5509                          * connection type we have with the target.
5510                          */
5511                         tinfo->user.period = ahc_syncrates->period;
5512                         tinfo->user.offset = MAX_OFFSET;
5513                 } else {
5514                         u_int scsirate;
5515                         uint16_t mask;
5516
5517                         /* Take the settings leftover in scratch RAM. */
5518                         scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
5519                         mask = (0x01 << i);
5520                         if ((ahc->features & AHC_ULTRA2) != 0) {
5521                                 u_int offset;
5522                                 u_int maxsync;
5523
5524                                 if ((scsirate & SOFS) == 0x0F) {
5525                                         /*
5526                                          * Haven't negotiated yet,
5527                                          * so the format is different.
5528                                          */
5529                                         scsirate = (scsirate & SXFR) >> 4
5530                                                  | (ultraenb & mask)
5531                                                   ? 0x08 : 0x0
5532                                                  | (scsirate & WIDEXFER);
5533                                         offset = MAX_OFFSET_ULTRA2;
5534                                 } else
5535                                         offset = ahc_inb(ahc, TARG_OFFSET + i);
5536                                 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
5537                                         /* Set to the lowest sync rate, 5MHz */
5538                                         scsirate |= 0x1c;
5539                                 maxsync = AHC_SYNCRATE_ULTRA2;
5540                                 if ((ahc->features & AHC_DT) != 0)
5541                                         maxsync = AHC_SYNCRATE_DT;
5542                                 tinfo->user.period =
5543                                     ahc_find_period(ahc, scsirate, maxsync);
5544                                 if (offset == 0)
5545                                         tinfo->user.period = 0;
5546                                 else
5547                                         tinfo->user.offset = MAX_OFFSET;
5548                                 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
5549                                  && (ahc->features & AHC_DT) != 0)
5550                                         tinfo->user.ppr_options =
5551                                             MSG_EXT_PPR_DT_REQ;
5552                         } else if ((scsirate & SOFS) != 0) {
5553                                 if ((scsirate & SXFR) == 0x40
5554                                  && (ultraenb & mask) != 0) {
5555                                         /* Treat 10MHz as a non-ultra speed */
5556                                         scsirate &= ~SXFR;
5557                                         ultraenb &= ~mask;
5558                                 }
5559                                 tinfo->user.period =
5560                                     ahc_find_period(ahc, scsirate,
5561                                                     (ultraenb & mask)
5562                                                    ? AHC_SYNCRATE_ULTRA
5563                                                    : AHC_SYNCRATE_FAST);
5564                                 if (tinfo->user.period != 0)
5565                                         tinfo->user.offset = MAX_OFFSET;
5566                         }
5567                         if (tinfo->user.period == 0)
5568                                 tinfo->user.offset = 0;
5569                         if ((scsirate & WIDEXFER) != 0
5570                          && (ahc->features & AHC_WIDE) != 0)
5571                                 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
5572                         tinfo->user.protocol_version = 4;
5573                         if ((ahc->features & AHC_DT) != 0)
5574                                 tinfo->user.transport_version = 3;
5575                         else
5576                                 tinfo->user.transport_version = 2;
5577                         tinfo->goal.protocol_version = 2;
5578                         tinfo->goal.transport_version = 2;
5579                         tinfo->curr.protocol_version = 2;
5580                         tinfo->curr.transport_version = 2;
5581                 }
5582                 tstate->ultraenb = 0;
5583         }
5584         ahc->user_discenable = discenable;
5585         ahc->user_tagenable = tagenable;
5586
5587         return (ahc->bus_chip_init(ahc));
5588 }
5589
5590 void
5591 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5592 {
5593         u_int hcntrl;
5594
5595         hcntrl = ahc_inb(ahc, HCNTRL);
5596         hcntrl &= ~INTEN;
5597         ahc->pause &= ~INTEN;
5598         ahc->unpause &= ~INTEN;
5599         if (enable) {
5600                 hcntrl |= INTEN;
5601                 ahc->pause |= INTEN;
5602                 ahc->unpause |= INTEN;
5603         }
5604         ahc_outb(ahc, HCNTRL, hcntrl);
5605 }
5606
5607 /*
5608  * Ensure that the card is paused in a location
5609  * outside of all critical sections and that all
5610  * pending work is completed prior to returning.
5611  * This routine should only be called from outside
5612  * an interrupt context.
5613  */
5614 void
5615 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5616 {
5617         int intstat;
5618         int maxloops;
5619         int paused;
5620
5621         maxloops = 1000;
5622         ahc->flags |= AHC_ALL_INTERRUPTS;
5623         paused = FALSE;
5624         do {
5625                 if (paused) {
5626                         ahc_unpause(ahc);
5627                         /*
5628                          * Give the sequencer some time to service
5629                          * any active selections.
5630                          */
5631                         ahc_delay(500);
5632                 }
5633                 ahc_intr(ahc);
5634                 ahc_pause(ahc);
5635                 paused = TRUE;
5636                 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5637                 intstat = ahc_inb(ahc, INTSTAT);
5638                 if ((intstat & INT_PEND) == 0) {
5639                         ahc_clear_critical_section(ahc);
5640                         intstat = ahc_inb(ahc, INTSTAT);
5641                 }
5642         } while (--maxloops
5643               && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5644               && ((intstat & INT_PEND) != 0
5645                || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5646         if (maxloops == 0) {
5647                 printf("Infinite interrupt loop, INTSTAT = %x",
5648                        ahc_inb(ahc, INTSTAT));
5649         }
5650         ahc_platform_flushwork(ahc);
5651         ahc->flags &= ~AHC_ALL_INTERRUPTS;
5652 }
5653
5654 #ifdef CONFIG_PM
5655 int
5656 ahc_suspend(struct ahc_softc *ahc)
5657 {
5658
5659         ahc_pause_and_flushwork(ahc);
5660
5661         if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5662                 ahc_unpause(ahc);
5663                 return (EBUSY);
5664         }
5665
5666 #ifdef AHC_TARGET_MODE
5667         /*
5668          * XXX What about ATIOs that have not yet been serviced?
5669          * Perhaps we should just refuse to be suspended if we
5670          * are acting in a target role.
5671          */
5672         if (ahc->pending_device != NULL) {
5673                 ahc_unpause(ahc);
5674                 return (EBUSY);
5675         }
5676 #endif
5677         ahc_shutdown(ahc);
5678         return (0);
5679 }
5680
5681 int
5682 ahc_resume(struct ahc_softc *ahc)
5683 {
5684
5685         ahc_reset(ahc, /*reinit*/TRUE);
5686         ahc_intr_enable(ahc, TRUE);
5687         ahc_restart(ahc);
5688         return (0);
5689 }
5690 #endif
5691 /************************** Busy Target Table *********************************/
5692 /*
5693  * Return the untagged transaction id for a given target/channel lun.
5694  * Optionally, clear the entry.
5695  */
5696 static u_int
5697 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5698 {
5699         u_int scbid;
5700         u_int target_offset;
5701
5702         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5703                 u_int saved_scbptr;
5704
5705                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5706                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5707                 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5708                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5709         } else {
5710                 target_offset = TCL_TARGET_OFFSET(tcl);
5711                 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5712         }
5713
5714         return (scbid);
5715 }
5716
5717 static void
5718 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5719 {
5720         u_int target_offset;
5721
5722         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5723                 u_int saved_scbptr;
5724
5725                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5726                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5727                 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5728                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5729         } else {
5730                 target_offset = TCL_TARGET_OFFSET(tcl);
5731                 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5732         }
5733 }
5734
5735 static void
5736 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5737 {
5738         u_int target_offset;
5739
5740         if ((ahc->flags & AHC_SCB_BTT) != 0) {
5741                 u_int saved_scbptr;
5742
5743                 saved_scbptr = ahc_inb(ahc, SCBPTR);
5744                 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5745                 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5746                 ahc_outb(ahc, SCBPTR, saved_scbptr);
5747         } else {
5748                 target_offset = TCL_TARGET_OFFSET(tcl);
5749                 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5750         }
5751 }
5752
5753 /************************** SCB and SCB queue management **********************/
5754 int
5755 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5756               char channel, int lun, u_int tag, role_t role)
5757 {
5758         int targ = SCB_GET_TARGET(ahc, scb);
5759         char chan = SCB_GET_CHANNEL(ahc, scb);
5760         int slun = SCB_GET_LUN(scb);
5761         int match;
5762
5763         match = ((chan == channel) || (channel == ALL_CHANNELS));
5764         if (match != 0)
5765                 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5766         if (match != 0)
5767                 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5768         if (match != 0) {
5769 #ifdef AHC_TARGET_MODE
5770                 int group;
5771
5772                 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5773                 if (role == ROLE_INITIATOR) {
5774                         match = (group != XPT_FC_GROUP_TMODE)
5775                               && ((tag == scb->hscb->tag)
5776                                || (tag == SCB_LIST_NULL));
5777                 } else if (role == ROLE_TARGET) {
5778                         match = (group == XPT_FC_GROUP_TMODE)
5779                               && ((tag == scb->io_ctx->csio.tag_id)
5780                                || (tag == SCB_LIST_NULL));
5781                 }
5782 #else /* !AHC_TARGET_MODE */
5783                 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5784 #endif /* AHC_TARGET_MODE */
5785         }
5786
5787         return match;
5788 }
5789
5790 static void
5791 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5792 {
5793         int     target;
5794         char    channel;
5795         int     lun;
5796
5797         target = SCB_GET_TARGET(ahc, scb);
5798         lun = SCB_GET_LUN(scb);
5799         channel = SCB_GET_CHANNEL(ahc, scb);
5800
5801         ahc_search_qinfifo(ahc, target, channel, lun,
5802                            /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5803                            CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5804
5805         ahc_platform_freeze_devq(ahc, scb);
5806 }
5807
5808 void
5809 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5810 {
5811         struct scb *prev_scb;
5812
5813         prev_scb = NULL;
5814         if (ahc_qinfifo_count(ahc) != 0) {
5815                 u_int prev_tag;
5816                 uint8_t prev_pos;
5817
5818                 prev_pos = ahc->qinfifonext - 1;
5819                 prev_tag = ahc->qinfifo[prev_pos];
5820                 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5821         }
5822         ahc_qinfifo_requeue(ahc, prev_scb, scb);
5823         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5824                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5825         } else {
5826                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5827         }
5828 }
5829
5830 static void
5831 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5832                     struct scb *scb)
5833 {
5834         if (prev_scb == NULL) {
5835                 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5836         } else {
5837                 prev_scb->hscb->next = scb->hscb->tag;
5838                 ahc_sync_scb(ahc, prev_scb,
5839                              BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5840         }
5841         ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5842         scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5843         ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5844 }
5845
5846 static int
5847 ahc_qinfifo_count(struct ahc_softc *ahc)
5848 {
5849         uint8_t qinpos;
5850         uint8_t diff;
5851
5852         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5853                 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5854                 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5855         } else
5856                 qinpos = ahc_inb(ahc, QINPOS);
5857         diff = ahc->qinfifonext - qinpos;
5858         return (diff);
5859 }
5860
5861 int
5862 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5863                    int lun, u_int tag, role_t role, uint32_t status,
5864                    ahc_search_action action)
5865 {
5866         struct  scb *scb;
5867         struct  scb *prev_scb;
5868         uint8_t qinstart;
5869         uint8_t qinpos;
5870         uint8_t qintail;
5871         uint8_t next;
5872         uint8_t prev;
5873         uint8_t curscbptr;
5874         int     found;
5875         int     have_qregs;
5876
5877         qintail = ahc->qinfifonext;
5878         have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5879         if (have_qregs) {
5880                 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5881                 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5882         } else
5883                 qinstart = ahc_inb(ahc, QINPOS);
5884         qinpos = qinstart;
5885         found = 0;
5886         prev_scb = NULL;
5887
5888         if (action == SEARCH_COMPLETE) {
5889                 /*
5890                  * Don't attempt to run any queued untagged transactions
5891                  * until we are done with the abort process.
5892                  */
5893                 ahc_freeze_untagged_queues(ahc);
5894         }
5895
5896         /*
5897          * Start with an empty queue.  Entries that are not chosen
5898          * for removal will be re-added to the queue as we go.
5899          */
5900         ahc->qinfifonext = qinpos;
5901         ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5902
5903         while (qinpos != qintail) {
5904                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5905                 if (scb == NULL) {
5906                         printf("qinpos = %d, SCB index = %d\n",
5907                                 qinpos, ahc->qinfifo[qinpos]);
5908                         panic("Loop 1\n");
5909                 }
5910
5911                 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5912                         /*
5913                          * We found an scb that needs to be acted on.
5914                          */
5915                         found++;
5916                         switch (action) {
5917                         case SEARCH_COMPLETE:
5918                         {
5919                                 cam_status ostat;
5920                                 cam_status cstat;
5921
5922                                 ostat = ahc_get_transaction_status(scb);
5923                                 if (ostat == CAM_REQ_INPROG)
5924                                         ahc_set_transaction_status(scb, status);
5925                                 cstat = ahc_get_transaction_status(scb);
5926                                 if (cstat != CAM_REQ_CMP)
5927                                         ahc_freeze_scb(scb);
5928                                 if ((scb->flags & SCB_ACTIVE) == 0)
5929                                         printf("Inactive SCB in qinfifo\n");
5930                                 ahc_done(ahc, scb);
5931
5932                                 /* FALLTHROUGH */
5933                         }
5934                         case SEARCH_REMOVE:
5935                                 break;
5936                         case SEARCH_COUNT:
5937                                 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5938                                 prev_scb = scb;
5939                                 break;
5940                         }
5941                 } else {
5942                         ahc_qinfifo_requeue(ahc, prev_scb, scb);
5943                         prev_scb = scb;
5944                 }
5945                 qinpos++;
5946         }
5947
5948         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5949                 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5950         } else {
5951                 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5952         }
5953
5954         if (action != SEARCH_COUNT
5955          && (found != 0)
5956          && (qinstart != ahc->qinfifonext)) {
5957                 /*
5958                  * The sequencer may be in the process of dmaing
5959                  * down the SCB at the beginning of the queue.
5960                  * This could be problematic if either the first,
5961                  * or the second SCB is removed from the queue
5962                  * (the first SCB includes a pointer to the "next"
5963                  * SCB to dma). If we have removed any entries, swap
5964                  * the first element in the queue with the next HSCB
5965                  * so the sequencer will notice that NEXT_QUEUED_SCB
5966                  * has changed during its dma attempt and will retry
5967                  * the DMA.
5968                  */
5969                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5970
5971                 if (scb == NULL) {
5972                         printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5973                                 found, qinstart, ahc->qinfifonext);
5974                         panic("First/Second Qinfifo fixup\n");
5975                 }
5976                 /*
5977                  * ahc_swap_with_next_hscb forces our next pointer to
5978                  * point to the reserved SCB for future commands.  Save
5979                  * and restore our original next pointer to maintain
5980                  * queue integrity.
5981                  */
5982                 next = scb->hscb->next;
5983                 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5984                 ahc_swap_with_next_hscb(ahc, scb);
5985                 scb->hscb->next = next;
5986                 ahc->qinfifo[qinstart] = scb->hscb->tag;
5987
5988                 /* Tell the card about the new head of the qinfifo. */
5989                 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5990
5991                 /* Fixup the tail "next" pointer. */
5992                 qintail = ahc->qinfifonext - 1;
5993                 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5994                 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5995         }
5996
5997         /*
5998          * Search waiting for selection list.
5999          */
6000         curscbptr = ahc_inb(ahc, SCBPTR);
6001         next = ahc_inb(ahc, WAITING_SCBH);  /* Start at head of list. */
6002         prev = SCB_LIST_NULL;
6003
6004         while (next != SCB_LIST_NULL) {
6005                 uint8_t scb_index;
6006
6007                 ahc_outb(ahc, SCBPTR, next);
6008                 scb_index = ahc_inb(ahc, SCB_TAG);
6009                 if (scb_index >= ahc->scb_data->numscbs) {
6010                         printf("Waiting List inconsistency. "
6011                                "SCB index == %d, yet numscbs == %d.",
6012                                scb_index, ahc->scb_data->numscbs);
6013                         ahc_dump_card_state(ahc);
6014                         panic("for safety");
6015                 }
6016                 scb = ahc_lookup_scb(ahc, scb_index);
6017                 if (scb == NULL) {
6018                         printf("scb_index = %d, next = %d\n",
6019                                 scb_index, next);
6020                         panic("Waiting List traversal\n");
6021                 }
6022                 if (ahc_match_scb(ahc, scb, target, channel,
6023                                   lun, SCB_LIST_NULL, role)) {
6024                         /*
6025                          * We found an scb that needs to be acted on.
6026                          */
6027                         found++;
6028                         switch (action) {
6029                         case SEARCH_COMPLETE:
6030                         {
6031                                 cam_status ostat;
6032                                 cam_status cstat;
6033
6034                                 ostat = ahc_get_transaction_status(scb);
6035                                 if (ostat == CAM_REQ_INPROG)
6036                                         ahc_set_transaction_status(scb,
6037                                                                    status);
6038                                 cstat = ahc_get_transaction_status(scb);
6039                                 if (cstat != CAM_REQ_CMP)
6040                                         ahc_freeze_scb(scb);
6041                                 if ((scb->flags & SCB_ACTIVE) == 0)
6042                                         printf("Inactive SCB in Waiting List\n");
6043                                 ahc_done(ahc, scb);
6044                                 /* FALLTHROUGH */
6045                         }
6046                         case SEARCH_REMOVE:
6047                                 next = ahc_rem_wscb(ahc, next, prev);
6048                                 break;
6049                         case SEARCH_COUNT:
6050                                 prev = next;
6051                                 next = ahc_inb(ahc, SCB_NEXT);
6052                                 break;
6053                         }
6054                 } else {
6055
6056                         prev = next;
6057                         next = ahc_inb(ahc, SCB_NEXT);
6058                 }
6059         }
6060         ahc_outb(ahc, SCBPTR, curscbptr);
6061
6062         found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
6063                                             channel, lun, status, action);
6064
6065         if (action == SEARCH_COMPLETE)
6066                 ahc_release_untagged_queues(ahc);
6067         return (found);
6068 }
6069
6070 int
6071 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
6072                            int target, char channel, int lun, uint32_t status,
6073                            ahc_search_action action)
6074 {
6075         struct  scb *scb;
6076         int     maxtarget;
6077         int     found;
6078         int     i;
6079
6080         if (action == SEARCH_COMPLETE) {
6081                 /*
6082                  * Don't attempt to run any queued untagged transactions
6083                  * until we are done with the abort process.
6084                  */
6085                 ahc_freeze_untagged_queues(ahc);
6086         }
6087
6088         found = 0;
6089         i = 0;
6090         if ((ahc->flags & AHC_SCB_BTT) == 0) {
6091
6092                 maxtarget = 16;
6093                 if (target != CAM_TARGET_WILDCARD) {
6094
6095                         i = target;
6096                         if (channel == 'B')
6097                                 i += 8;
6098                         maxtarget = i + 1;
6099                 }
6100         } else {
6101                 maxtarget = 0;
6102         }
6103
6104         for (; i < maxtarget; i++) {
6105                 struct scb_tailq *untagged_q;
6106                 struct scb *next_scb;
6107
6108                 untagged_q = &(ahc->untagged_queues[i]);
6109                 next_scb = TAILQ_FIRST(untagged_q);
6110                 while (next_scb != NULL) {
6111
6112                         scb = next_scb;
6113                         next_scb = TAILQ_NEXT(scb, links.tqe);
6114
6115                         /*
6116                          * The head of the list may be the currently
6117                          * active untagged command for a device.
6118                          * We're only searching for commands that
6119                          * have not been started.  A transaction
6120                          * marked active but still in the qinfifo
6121                          * is removed by the qinfifo scanning code
6122                          * above.
6123                          */
6124                         if ((scb->flags & SCB_ACTIVE) != 0)
6125                                 continue;
6126
6127                         if (ahc_match_scb(ahc, scb, target, channel, lun,
6128                                           SCB_LIST_NULL, ROLE_INITIATOR) == 0
6129                          || (ctx != NULL && ctx != scb->io_ctx))
6130                                 continue;
6131
6132                         /*
6133                          * We found an scb that needs to be acted on.
6134                          */
6135                         found++;
6136                         switch (action) {
6137                         case SEARCH_COMPLETE:
6138                         {
6139                                 cam_status ostat;
6140                                 cam_status cstat;
6141
6142                                 ostat = ahc_get_transaction_status(scb);
6143                                 if (ostat == CAM_REQ_INPROG)
6144                                         ahc_set_transaction_status(scb, status);
6145                                 cstat = ahc_get_transaction_status(scb);
6146                                 if (cstat != CAM_REQ_CMP)
6147                                         ahc_freeze_scb(scb);
6148                                 if ((scb->flags & SCB_ACTIVE) == 0)
6149                                         printf("Inactive SCB in untaggedQ\n");
6150                                 ahc_done(ahc, scb);
6151                                 break;
6152                         }
6153                         case SEARCH_REMOVE:
6154                                 scb->flags &= ~SCB_UNTAGGEDQ;
6155                                 TAILQ_REMOVE(untagged_q, scb, links.tqe);
6156                                 break;
6157                         case SEARCH_COUNT:
6158                                 break;
6159                         }
6160                 }
6161         }
6162
6163         if (action == SEARCH_COMPLETE)
6164                 ahc_release_untagged_queues(ahc);
6165         return (found);
6166 }
6167
6168 int
6169 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
6170                      int lun, u_int tag, int stop_on_first, int remove,
6171                      int save_state)
6172 {
6173         struct  scb *scbp;
6174         u_int   next;
6175         u_int   prev;
6176         u_int   count;
6177         u_int   active_scb;
6178
6179         count = 0;
6180         next = ahc_inb(ahc, DISCONNECTED_SCBH);
6181         prev = SCB_LIST_NULL;
6182
6183         if (save_state) {
6184                 /* restore this when we're done */
6185                 active_scb = ahc_inb(ahc, SCBPTR);
6186         } else
6187                 /* Silence compiler */
6188                 active_scb = SCB_LIST_NULL;
6189
6190         while (next != SCB_LIST_NULL) {
6191                 u_int scb_index;
6192
6193                 ahc_outb(ahc, SCBPTR, next);
6194                 scb_index = ahc_inb(ahc, SCB_TAG);
6195                 if (scb_index >= ahc->scb_data->numscbs) {
6196                         printf("Disconnected List inconsistency. "
6197                                "SCB index == %d, yet numscbs == %d.",
6198                                scb_index, ahc->scb_data->numscbs);
6199                         ahc_dump_card_state(ahc);
6200                         panic("for safety");
6201                 }
6202
6203                 if (next == prev) {
6204                         panic("Disconnected List Loop. "
6205                               "cur SCBPTR == %x, prev SCBPTR == %x.",
6206                               next, prev);
6207                 }
6208                 scbp = ahc_lookup_scb(ahc, scb_index);
6209                 if (ahc_match_scb(ahc, scbp, target, channel, lun,
6210                                   tag, ROLE_INITIATOR)) {
6211                         count++;
6212                         if (remove) {
6213                                 next =
6214                                     ahc_rem_scb_from_disc_list(ahc, prev, next);
6215                         } else {
6216                                 prev = next;
6217                                 next = ahc_inb(ahc, SCB_NEXT);
6218                         }
6219                         if (stop_on_first)
6220                                 break;
6221                 } else {
6222                         prev = next;
6223                         next = ahc_inb(ahc, SCB_NEXT);
6224                 }
6225         }
6226         if (save_state)
6227                 ahc_outb(ahc, SCBPTR, active_scb);
6228         return (count);
6229 }
6230
6231 /*
6232  * Remove an SCB from the on chip list of disconnected transactions.
6233  * This is empty/unused if we are not performing SCB paging.
6234  */
6235 static u_int
6236 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
6237 {
6238         u_int next;
6239
6240         ahc_outb(ahc, SCBPTR, scbptr);
6241         next = ahc_inb(ahc, SCB_NEXT);
6242
6243         ahc_outb(ahc, SCB_CONTROL, 0);
6244
6245         ahc_add_curscb_to_free_list(ahc);
6246
6247         if (prev != SCB_LIST_NULL) {
6248                 ahc_outb(ahc, SCBPTR, prev);
6249                 ahc_outb(ahc, SCB_NEXT, next);
6250         } else
6251                 ahc_outb(ahc, DISCONNECTED_SCBH, next);
6252
6253         return (next);
6254 }
6255
6256 /*
6257  * Add the SCB as selected by SCBPTR onto the on chip list of
6258  * free hardware SCBs.  This list is empty/unused if we are not
6259  * performing SCB paging.
6260  */
6261 static void
6262 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
6263 {
6264         /*
6265          * Invalidate the tag so that our abort
6266          * routines don't think it's active.
6267          */
6268         ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
6269
6270         if ((ahc->flags & AHC_PAGESCBS) != 0) {
6271                 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
6272                 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
6273         }
6274 }
6275
6276 /*
6277  * Manipulate the waiting for selection list and return the
6278  * scb that follows the one that we remove.
6279  */
6280 static u_int
6281 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
6282 {
6283         u_int curscb, next;
6284
6285         /*
6286          * Select the SCB we want to abort and
6287          * pull the next pointer out of it.
6288          */
6289         curscb = ahc_inb(ahc, SCBPTR);
6290         ahc_outb(ahc, SCBPTR, scbpos);
6291         next = ahc_inb(ahc, SCB_NEXT);
6292
6293         /* Clear the necessary fields */
6294         ahc_outb(ahc, SCB_CONTROL, 0);
6295
6296         ahc_add_curscb_to_free_list(ahc);
6297
6298         /* update the waiting list */
6299         if (prev == SCB_LIST_NULL) {
6300                 /* First in the list */
6301                 ahc_outb(ahc, WAITING_SCBH, next);
6302
6303                 /*
6304                  * Ensure we aren't attempting to perform
6305                  * selection for this entry.
6306                  */
6307                 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
6308         } else {
6309                 /*
6310                  * Select the scb that pointed to us
6311                  * and update its next pointer.
6312                  */
6313                 ahc_outb(ahc, SCBPTR, prev);
6314                 ahc_outb(ahc, SCB_NEXT, next);
6315         }
6316
6317         /*
6318          * Point us back at the original scb position.
6319          */
6320         ahc_outb(ahc, SCBPTR, curscb);
6321         return next;
6322 }
6323
6324 /******************************** Error Handling ******************************/
6325 /*
6326  * Abort all SCBs that match the given description (target/channel/lun/tag),
6327  * setting their status to the passed in status if the status has not already
6328  * been modified from CAM_REQ_INPROG.  This routine assumes that the sequencer
6329  * is paused before it is called.
6330  */
6331 static int
6332 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
6333                int lun, u_int tag, role_t role, uint32_t status)
6334 {
6335         struct  scb *scbp;
6336         struct  scb *scbp_next;
6337         u_int   active_scb;
6338         int     i, j;
6339         int     maxtarget;
6340         int     minlun;
6341         int     maxlun;
6342
6343         int     found;
6344
6345         /*
6346          * Don't attempt to run any queued untagged transactions
6347          * until we are done with the abort process.
6348          */
6349         ahc_freeze_untagged_queues(ahc);
6350
6351         /* restore this when we're done */
6352         active_scb = ahc_inb(ahc, SCBPTR);
6353
6354         found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
6355                                    role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
6356
6357         /*
6358          * Clean out the busy target table for any untagged commands.
6359          */
6360         i = 0;
6361         maxtarget = 16;
6362         if (target != CAM_TARGET_WILDCARD) {
6363                 i = target;
6364                 if (channel == 'B')
6365                         i += 8;
6366                 maxtarget = i + 1;
6367         }
6368
6369         if (lun == CAM_LUN_WILDCARD) {
6370
6371                 /*
6372                  * Unless we are using an SCB based
6373                  * busy targets table, there is only
6374                  * one table entry for all luns of
6375                  * a target.
6376                  */
6377                 minlun = 0;
6378                 maxlun = 1;
6379                 if ((ahc->flags & AHC_SCB_BTT) != 0)
6380                         maxlun = AHC_NUM_LUNS;
6381         } else {
6382                 minlun = lun;
6383                 maxlun = lun + 1;
6384         }
6385
6386         if (role != ROLE_TARGET) {
6387                 for (;i < maxtarget; i++) {
6388                         for (j = minlun;j < maxlun; j++) {
6389                                 u_int scbid;
6390                                 u_int tcl;
6391
6392                                 tcl = BUILD_TCL(i << 4, j);
6393                                 scbid = ahc_index_busy_tcl(ahc, tcl);
6394                                 scbp = ahc_lookup_scb(ahc, scbid);
6395                                 if (scbp == NULL
6396                                  || ahc_match_scb(ahc, scbp, target, channel,
6397                                                   lun, tag, role) == 0)
6398                                         continue;
6399                                 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
6400                         }
6401                 }
6402
6403                 /*
6404                  * Go through the disconnected list and remove any entries we
6405                  * have queued for completion, 0'ing their control byte too.
6406                  * We save the active SCB and restore it ourselves, so there
6407                  * is no reason for this search to restore it too.
6408                  */
6409                 ahc_search_disc_list(ahc, target, channel, lun, tag,
6410                                      /*stop_on_first*/FALSE, /*remove*/TRUE,
6411                                      /*save_state*/FALSE);
6412         }
6413
6414         /*
6415          * Go through the hardware SCB array looking for commands that
6416          * were active but not on any list.  In some cases, these remnants
6417          * might not still have mappings in the scbindex array (e.g. unexpected
6418          * bus free with the same scb queued for an abort).  Don't hold this
6419          * against them.
6420          */
6421         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6422                 u_int scbid;
6423
6424                 ahc_outb(ahc, SCBPTR, i);
6425                 scbid = ahc_inb(ahc, SCB_TAG);
6426                 scbp = ahc_lookup_scb(ahc, scbid);
6427                 if ((scbp == NULL && scbid != SCB_LIST_NULL)
6428                  || (scbp != NULL
6429                   && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
6430                         ahc_add_curscb_to_free_list(ahc);
6431         }
6432
6433         /*
6434          * Go through the pending CCB list and look for
6435          * commands for this target that are still active.
6436          * These are other tagged commands that were
6437          * disconnected when the reset occurred.
6438          */
6439         scbp_next = LIST_FIRST(&ahc->pending_scbs);
6440         while (scbp_next != NULL) {
6441                 scbp = scbp_next;
6442                 scbp_next = LIST_NEXT(scbp, pending_links);
6443                 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
6444                         cam_status ostat;
6445
6446                         ostat = ahc_get_transaction_status(scbp);
6447                         if (ostat == CAM_REQ_INPROG)
6448                                 ahc_set_transaction_status(scbp, status);
6449                         if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
6450                                 ahc_freeze_scb(scbp);
6451                         if ((scbp->flags & SCB_ACTIVE) == 0)
6452                                 printf("Inactive SCB on pending list\n");
6453                         ahc_done(ahc, scbp);
6454                         found++;
6455                 }
6456         }
6457         ahc_outb(ahc, SCBPTR, active_scb);
6458         ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
6459         ahc_release_untagged_queues(ahc);
6460         return found;
6461 }
6462
6463 static void
6464 ahc_reset_current_bus(struct ahc_softc *ahc)
6465 {
6466         uint8_t scsiseq;
6467
6468         ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
6469         scsiseq = ahc_inb(ahc, SCSISEQ);
6470         ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
6471         ahc_flush_device_writes(ahc);
6472         ahc_delay(AHC_BUSRESET_DELAY);
6473         /* Turn off the bus reset */
6474         ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
6475
6476         ahc_clear_intstat(ahc);
6477
6478         /* Re-enable reset interrupts */
6479         ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
6480 }
6481
6482 int
6483 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
6484 {
6485         struct  ahc_devinfo devinfo;
6486         u_int   initiator, target, max_scsiid;
6487         u_int   sblkctl;
6488         u_int   scsiseq;
6489         u_int   simode1;
6490         int     found;
6491         int     restart_needed;
6492         char    cur_channel;
6493
6494         ahc->pending_device = NULL;
6495
6496         ahc_compile_devinfo(&devinfo,
6497                             CAM_TARGET_WILDCARD,
6498                             CAM_TARGET_WILDCARD,
6499                             CAM_LUN_WILDCARD,
6500                             channel, ROLE_UNKNOWN);
6501         ahc_pause(ahc);
6502
6503         /* Make sure the sequencer is in a safe location. */
6504         ahc_clear_critical_section(ahc);
6505
6506         /*
6507          * Run our command complete fifos to ensure that we perform
6508          * completion processing on any commands that 'completed'
6509          * before the reset occurred.
6510          */
6511         ahc_run_qoutfifo(ahc);
6512 #ifdef AHC_TARGET_MODE
6513         /*
6514          * XXX - In Twin mode, the tqinfifo may have commands
6515          *       for an unaffected channel in it.  However, if
6516          *       we have run out of ATIO resources to drain that
6517          *       queue, we may not get them all out here.  Further,
6518          *       the blocked transactions for the reset channel
6519          *       should just be killed off, irrespecitve of whether
6520          *       we are blocked on ATIO resources.  Write a routine
6521          *       to compact the tqinfifo appropriately.
6522          */
6523         if ((ahc->flags & AHC_TARGETROLE) != 0) {
6524                 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
6525         }
6526 #endif
6527
6528         /*
6529          * Reset the bus if we are initiating this reset
6530          */
6531         sblkctl = ahc_inb(ahc, SBLKCTL);
6532         cur_channel = 'A';
6533         if ((ahc->features & AHC_TWIN) != 0
6534          && ((sblkctl & SELBUSB) != 0))
6535             cur_channel = 'B';
6536         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
6537         if (cur_channel != channel) {
6538                 /* Case 1: Command for another bus is active
6539                  * Stealthily reset the other bus without
6540                  * upsetting the current bus.
6541                  */
6542                 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
6543                 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6544 #ifdef AHC_TARGET_MODE
6545                 /*
6546                  * Bus resets clear ENSELI, so we cannot
6547                  * defer re-enabling bus reset interrupts
6548                  * if we are in target mode.
6549                  */
6550                 if ((ahc->flags & AHC_TARGETROLE) != 0)
6551                         simode1 |= ENSCSIRST;
6552 #endif
6553                 ahc_outb(ahc, SIMODE1, simode1);
6554                 if (initiate_reset)
6555                         ahc_reset_current_bus(ahc);
6556                 ahc_clear_intstat(ahc);
6557                 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6558                 ahc_outb(ahc, SBLKCTL, sblkctl);
6559                 restart_needed = FALSE;
6560         } else {
6561                 /* Case 2: A command from this bus is active or we're idle */
6562                 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
6563 #ifdef AHC_TARGET_MODE
6564                 /*
6565                  * Bus resets clear ENSELI, so we cannot
6566                  * defer re-enabling bus reset interrupts
6567                  * if we are in target mode.
6568                  */
6569                 if ((ahc->flags & AHC_TARGETROLE) != 0)
6570                         simode1 |= ENSCSIRST;
6571 #endif
6572                 ahc_outb(ahc, SIMODE1, simode1);
6573                 if (initiate_reset)
6574                         ahc_reset_current_bus(ahc);
6575                 ahc_clear_intstat(ahc);
6576                 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
6577                 restart_needed = TRUE;
6578         }
6579
6580         /*
6581          * Clean up all the state information for the
6582          * pending transactions on this bus.
6583          */
6584         found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
6585                                CAM_LUN_WILDCARD, SCB_LIST_NULL,
6586                                ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6587
6588         max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6589
6590 #ifdef AHC_TARGET_MODE
6591         /*
6592          * Send an immediate notify ccb to all target more peripheral
6593          * drivers affected by this action.
6594          */
6595         for (target = 0; target <= max_scsiid; target++) {
6596                 struct ahc_tmode_tstate* tstate;
6597                 u_int lun;
6598
6599                 tstate = ahc->enabled_targets[target];
6600                 if (tstate == NULL)
6601                         continue;
6602                 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6603                         struct ahc_tmode_lstate* lstate;
6604
6605                         lstate = tstate->enabled_luns[lun];
6606                         if (lstate == NULL)
6607                                 continue;
6608
6609                         ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6610                                                EVENT_TYPE_BUS_RESET, /*arg*/0);
6611                         ahc_send_lstate_events(ahc, lstate);
6612                 }
6613         }
6614 #endif
6615         /* Notify the XPT that a bus reset occurred */
6616         ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6617                        CAM_LUN_WILDCARD, AC_BUS_RESET);
6618
6619         /*
6620          * Revert to async/narrow transfers until we renegotiate.
6621          */
6622         for (target = 0; target <= max_scsiid; target++) {
6623
6624                 if (ahc->enabled_targets[target] == NULL)
6625                         continue;
6626                 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6627                         struct ahc_devinfo devinfo;
6628
6629                         ahc_compile_devinfo(&devinfo, target, initiator,
6630                                             CAM_LUN_WILDCARD,
6631                                             channel, ROLE_UNKNOWN);
6632                         ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6633                                       AHC_TRANS_CUR, /*paused*/TRUE);
6634                         ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6635                                          /*period*/0, /*offset*/0,
6636                                          /*ppr_options*/0, AHC_TRANS_CUR,
6637                                          /*paused*/TRUE);
6638                 }
6639         }
6640
6641         if (restart_needed)
6642                 ahc_restart(ahc);
6643         else
6644                 ahc_unpause(ahc);
6645         return found;
6646 }
6647
6648
6649 /***************************** Residual Processing ****************************/
6650 /*
6651  * Calculate the residual for a just completed SCB.
6652  */
6653 static void
6654 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6655 {
6656         struct hardware_scb *hscb;
6657         struct status_pkt *spkt;
6658         uint32_t sgptr;
6659         uint32_t resid_sgptr;
6660         uint32_t resid;
6661
6662         /*
6663          * 5 cases.
6664          * 1) No residual.
6665          *    SG_RESID_VALID clear in sgptr.
6666          * 2) Transferless command
6667          * 3) Never performed any transfers.
6668          *    sgptr has SG_FULL_RESID set.
6669          * 4) No residual but target did not
6670          *    save data pointers after the
6671          *    last transfer, so sgptr was
6672          *    never updated.
6673          * 5) We have a partial residual.
6674          *    Use residual_sgptr to determine
6675          *    where we are.
6676          */
6677
6678         hscb = scb->hscb;
6679         sgptr = ahc_le32toh(hscb->sgptr);
6680         if ((sgptr & SG_RESID_VALID) == 0)
6681                 /* Case 1 */
6682                 return;
6683         sgptr &= ~SG_RESID_VALID;
6684
6685         if ((sgptr & SG_LIST_NULL) != 0)
6686                 /* Case 2 */
6687                 return;
6688
6689         spkt = &hscb->shared_data.status;
6690         resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6691         if ((sgptr & SG_FULL_RESID) != 0) {
6692                 /* Case 3 */
6693                 resid = ahc_get_transfer_length(scb);
6694         } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6695                 /* Case 4 */
6696                 return;
6697         } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6698                 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6699         } else {
6700                 struct ahc_dma_seg *sg;
6701
6702                 /*
6703                  * Remainder of the SG where the transfer
6704                  * stopped.
6705                  */
6706                 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6707                 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6708
6709                 /* The residual sg_ptr always points to the next sg */
6710                 sg--;
6711
6712                 /*
6713                  * Add up the contents of all residual
6714                  * SG segments that are after the SG where
6715                  * the transfer stopped.
6716                  */
6717                 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6718                         sg++;
6719                         resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6720                 }
6721         }
6722         if ((scb->flags & SCB_SENSE) == 0)
6723                 ahc_set_residual(scb, resid);
6724         else
6725                 ahc_set_sense_residual(scb, resid);
6726
6727 #ifdef AHC_DEBUG
6728         if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6729                 ahc_print_path(ahc, scb);
6730                 printf("Handled %sResidual of %d bytes\n",
6731                        (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6732         }
6733 #endif
6734 }
6735
6736 /******************************* Target Mode **********************************/
6737 #ifdef AHC_TARGET_MODE
6738 /*
6739  * Add a target mode event to this lun's queue
6740  */
6741 static void
6742 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6743                        u_int initiator_id, u_int event_type, u_int event_arg)
6744 {
6745         struct ahc_tmode_event *event;
6746         int pending;
6747
6748         xpt_freeze_devq(lstate->path, /*count*/1);
6749         if (lstate->event_w_idx >= lstate->event_r_idx)
6750                 pending = lstate->event_w_idx - lstate->event_r_idx;
6751         else
6752                 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6753                         - (lstate->event_r_idx - lstate->event_w_idx);
6754
6755         if (event_type == EVENT_TYPE_BUS_RESET
6756          || event_type == MSG_BUS_DEV_RESET) {
6757                 /*
6758                  * Any earlier events are irrelevant, so reset our buffer.
6759                  * This has the effect of allowing us to deal with reset
6760                  * floods (an external device holding down the reset line)
6761                  * without losing the event that is really interesting.
6762                  */
6763                 lstate->event_r_idx = 0;
6764                 lstate->event_w_idx = 0;
6765                 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6766         }
6767
6768         if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6769                 xpt_print_path(lstate->path);
6770                 printf("immediate event %x:%x lost\n",
6771                        lstate->event_buffer[lstate->event_r_idx].event_type,
6772                        lstate->event_buffer[lstate->event_r_idx].event_arg);
6773                 lstate->event_r_idx++;
6774                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6775                         lstate->event_r_idx = 0;
6776                 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6777         }
6778
6779         event = &lstate->event_buffer[lstate->event_w_idx];
6780         event->initiator_id = initiator_id;
6781         event->event_type = event_type;
6782         event->event_arg = event_arg;
6783         lstate->event_w_idx++;
6784         if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6785                 lstate->event_w_idx = 0;
6786 }
6787
6788 /*
6789  * Send any target mode events queued up waiting
6790  * for immediate notify resources.
6791  */
6792 void
6793 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6794 {
6795         struct ccb_hdr *ccbh;
6796         struct ccb_immed_notify *inot;
6797
6798         while (lstate->event_r_idx != lstate->event_w_idx
6799             && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6800                 struct ahc_tmode_event *event;
6801
6802                 event = &lstate->event_buffer[lstate->event_r_idx];
6803                 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6804                 inot = (struct ccb_immed_notify *)ccbh;
6805                 switch (event->event_type) {
6806                 case EVENT_TYPE_BUS_RESET:
6807                         ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6808                         break;
6809                 default:
6810                         ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6811                         inot->message_args[0] = event->event_type;
6812                         inot->message_args[1] = event->event_arg;
6813                         break;
6814                 }
6815                 inot->initiator_id = event->initiator_id;
6816                 inot->sense_len = 0;
6817                 xpt_done((union ccb *)inot);
6818                 lstate->event_r_idx++;
6819                 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6820                         lstate->event_r_idx = 0;
6821         }
6822 }
6823 #endif
6824
6825 /******************** Sequencer Program Patching/Download *********************/
6826
6827 #ifdef AHC_DUMP_SEQ
6828 void
6829 ahc_dumpseq(struct ahc_softc* ahc)
6830 {
6831         int i;
6832
6833         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6834         ahc_outb(ahc, SEQADDR0, 0);
6835         ahc_outb(ahc, SEQADDR1, 0);
6836         for (i = 0; i < ahc->instruction_ram_size; i++) {
6837                 uint8_t ins_bytes[4];
6838
6839                 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6840                 printf("0x%08x\n", ins_bytes[0] << 24
6841                                  | ins_bytes[1] << 16
6842                                  | ins_bytes[2] << 8
6843                                  | ins_bytes[3]);
6844         }
6845 }
6846 #endif
6847
6848 static int
6849 ahc_loadseq(struct ahc_softc *ahc)
6850 {
6851         struct  cs cs_table[num_critical_sections];
6852         u_int   begin_set[num_critical_sections];
6853         u_int   end_set[num_critical_sections];
6854         struct  patch *cur_patch;
6855         u_int   cs_count;
6856         u_int   cur_cs;
6857         u_int   i;
6858         u_int   skip_addr;
6859         u_int   sg_prefetch_cnt;
6860         int     downloaded;
6861         uint8_t download_consts[7];
6862
6863         /*
6864          * Start out with 0 critical sections
6865          * that apply to this firmware load.
6866          */
6867         cs_count = 0;
6868         cur_cs = 0;
6869         memset(begin_set, 0, sizeof(begin_set));
6870         memset(end_set, 0, sizeof(end_set));
6871
6872         /* Setup downloadable constant table */
6873         download_consts[QOUTFIFO_OFFSET] = 0;
6874         if (ahc->targetcmds != NULL)
6875                 download_consts[QOUTFIFO_OFFSET] += 32;
6876         download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6877         download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6878         download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6879         sg_prefetch_cnt = ahc->pci_cachesize;
6880         if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6881                 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6882         download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6883         download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6884         download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6885
6886         cur_patch = patches;
6887         downloaded = 0;
6888         skip_addr = 0;
6889         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6890         ahc_outb(ahc, SEQADDR0, 0);
6891         ahc_outb(ahc, SEQADDR1, 0);
6892
6893         for (i = 0; i < sizeof(seqprog)/4; i++) {
6894                 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6895                         /*
6896                          * Don't download this instruction as it
6897                          * is in a patch that was removed.
6898                          */
6899                         continue;
6900                 }
6901
6902                 if (downloaded == ahc->instruction_ram_size) {
6903                         /*
6904                          * We're about to exceed the instruction
6905                          * storage capacity for this chip.  Fail
6906                          * the load.
6907                          */
6908                         printf("\n%s: Program too large for instruction memory "
6909                                "size of %d!\n", ahc_name(ahc),
6910                                ahc->instruction_ram_size);
6911                         return (ENOMEM);
6912                 }
6913
6914                 /*
6915                  * Move through the CS table until we find a CS
6916                  * that might apply to this instruction.
6917                  */
6918                 for (; cur_cs < num_critical_sections; cur_cs++) {
6919                         if (critical_sections[cur_cs].end <= i) {
6920                                 if (begin_set[cs_count] == TRUE
6921                                  && end_set[cs_count] == FALSE) {
6922                                         cs_table[cs_count].end = downloaded;
6923                                         end_set[cs_count] = TRUE;
6924                                         cs_count++;
6925                                 }
6926                                 continue;
6927                         }
6928                         if (critical_sections[cur_cs].begin <= i
6929                          && begin_set[cs_count] == FALSE) {
6930                                 cs_table[cs_count].begin = downloaded;
6931                                 begin_set[cs_count] = TRUE;
6932                         }
6933                         break;
6934                 }
6935                 ahc_download_instr(ahc, i, download_consts);
6936                 downloaded++;
6937         }
6938
6939         ahc->num_critical_sections = cs_count;
6940         if (cs_count != 0) {
6941
6942                 cs_count *= sizeof(struct cs);
6943                 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6944                 if (ahc->critical_sections == NULL)
6945                         panic("ahc_loadseq: Could not malloc");
6946                 memcpy(ahc->critical_sections, cs_table, cs_count);
6947         }
6948         ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6949
6950         if (bootverbose) {
6951                 printf(" %d instructions downloaded\n", downloaded);
6952                 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6953                        ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6954         }
6955         return (0);
6956 }
6957
6958 static int
6959 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6960                 u_int start_instr, u_int *skip_addr)
6961 {
6962         struct  patch *cur_patch;
6963         struct  patch *last_patch;
6964         u_int   num_patches;
6965
6966         num_patches = ARRAY_SIZE(patches);
6967         last_patch = &patches[num_patches];
6968         cur_patch = *start_patch;
6969
6970         while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6971
6972                 if (cur_patch->patch_func(ahc) == 0) {
6973
6974                         /* Start rejecting code */
6975                         *skip_addr = start_instr + cur_patch->skip_instr;
6976                         cur_patch += cur_patch->skip_patch;
6977                 } else {
6978                         /* Accepted this patch.  Advance to the next
6979                          * one and wait for our intruction pointer to
6980                          * hit this point.
6981                          */
6982                         cur_patch++;
6983                 }
6984         }
6985
6986         *start_patch = cur_patch;
6987         if (start_instr < *skip_addr)
6988                 /* Still skipping */
6989                 return (0);
6990
6991         return (1);
6992 }
6993
6994 static void
6995 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6996 {
6997         union   ins_formats instr;
6998         struct  ins_format1 *fmt1_ins;
6999         struct  ins_format3 *fmt3_ins;
7000         u_int   opcode;
7001
7002         /*
7003          * The firmware is always compiled into a little endian format.
7004          */
7005         instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
7006
7007         fmt1_ins = &instr.format1;
7008         fmt3_ins = NULL;
7009
7010         /* Pull the opcode */
7011         opcode = instr.format1.opcode;
7012         switch (opcode) {
7013         case AIC_OP_JMP:
7014         case AIC_OP_JC:
7015         case AIC_OP_JNC:
7016         case AIC_OP_CALL:
7017         case AIC_OP_JNE:
7018         case AIC_OP_JNZ:
7019         case AIC_OP_JE:
7020         case AIC_OP_JZ:
7021         {
7022                 struct patch *cur_patch;
7023                 int address_offset;
7024                 u_int address;
7025                 u_int skip_addr;
7026                 u_int i;
7027
7028                 fmt3_ins = &instr.format3;
7029                 address_offset = 0;
7030                 address = fmt3_ins->address;
7031                 cur_patch = patches;
7032                 skip_addr = 0;
7033
7034                 for (i = 0; i < address;) {
7035
7036                         ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
7037
7038                         if (skip_addr > i) {
7039                                 int end_addr;
7040
7041                                 end_addr = min(address, skip_addr);
7042                                 address_offset += end_addr - i;
7043                                 i = skip_addr;
7044                         } else {
7045                                 i++;
7046                         }
7047                 }
7048                 address -= address_offset;
7049                 fmt3_ins->address = address;
7050                 /* FALLTHROUGH */
7051         }
7052         case AIC_OP_OR:
7053         case AIC_OP_AND:
7054         case AIC_OP_XOR:
7055         case AIC_OP_ADD:
7056         case AIC_OP_ADC:
7057         case AIC_OP_BMOV:
7058                 if (fmt1_ins->parity != 0) {
7059                         fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
7060                 }
7061                 fmt1_ins->parity = 0;
7062                 if ((ahc->features & AHC_CMD_CHAN) == 0
7063                  && opcode == AIC_OP_BMOV) {
7064                         /*
7065                          * Block move was added at the same time
7066                          * as the command channel.  Verify that
7067                          * this is only a move of a single element
7068                          * and convert the BMOV to a MOV
7069                          * (AND with an immediate of FF).
7070                          */
7071                         if (fmt1_ins->immediate != 1)
7072                                 panic("%s: BMOV not supported\n",
7073                                       ahc_name(ahc));
7074                         fmt1_ins->opcode = AIC_OP_AND;
7075                         fmt1_ins->immediate = 0xff;
7076                 }
7077                 /* FALLTHROUGH */
7078         case AIC_OP_ROL:
7079                 if ((ahc->features & AHC_ULTRA2) != 0) {
7080                         int i, count;
7081
7082                         /* Calculate odd parity for the instruction */
7083                         for (i = 0, count = 0; i < 31; i++) {
7084                                 uint32_t mask;
7085
7086                                 mask = 0x01 << i;
7087                                 if ((instr.integer & mask) != 0)
7088                                         count++;
7089                         }
7090                         if ((count & 0x01) == 0)
7091                                 instr.format1.parity = 1;
7092                 } else {
7093                         /* Compress the instruction for older sequencers */
7094                         if (fmt3_ins != NULL) {
7095                                 instr.integer =
7096                                         fmt3_ins->immediate
7097                                       | (fmt3_ins->source << 8)
7098                                       | (fmt3_ins->address << 16)
7099                                       | (fmt3_ins->opcode << 25);
7100                         } else {
7101                                 instr.integer =
7102                                         fmt1_ins->immediate
7103                                       | (fmt1_ins->source << 8)
7104                                       | (fmt1_ins->destination << 16)
7105                                       | (fmt1_ins->ret << 24)
7106                                       | (fmt1_ins->opcode << 25);
7107                         }
7108                 }
7109                 /* The sequencer is a little endian cpu */
7110                 instr.integer = ahc_htole32(instr.integer);
7111                 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
7112                 break;
7113         default:
7114                 panic("Unknown opcode encountered in seq program");
7115                 break;
7116         }
7117 }
7118
7119 int
7120 ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries,
7121                    const char *name, u_int address, u_int value,
7122                    u_int *cur_column, u_int wrap_point)
7123 {
7124         int     printed;
7125         u_int   printed_mask;
7126
7127         if (cur_column != NULL && *cur_column >= wrap_point) {
7128                 printf("\n");
7129                 *cur_column = 0;
7130         }
7131         printed = printf("%s[0x%x]", name, value);
7132         if (table == NULL) {
7133                 printed += printf(" ");
7134                 *cur_column += printed;
7135                 return (printed);
7136         }
7137         printed_mask = 0;
7138         while (printed_mask != 0xFF) {
7139                 int entry;
7140
7141                 for (entry = 0; entry < num_entries; entry++) {
7142                         if (((value & table[entry].mask)
7143                           != table[entry].value)
7144                          || ((printed_mask & table[entry].mask)
7145                           == table[entry].mask))
7146                                 continue;
7147
7148                         printed += printf("%s%s",
7149                                           printed_mask == 0 ? ":(" : "|",
7150                                           table[entry].name);
7151                         printed_mask |= table[entry].mask;
7152
7153                         break;
7154                 }
7155                 if (entry >= num_entries)
7156                         break;
7157         }
7158         if (printed_mask != 0)
7159                 printed += printf(") ");
7160         else
7161                 printed += printf(" ");
7162         if (cur_column != NULL)
7163                 *cur_column += printed;
7164         return (printed);
7165 }
7166
7167 void
7168 ahc_dump_card_state(struct ahc_softc *ahc)
7169 {
7170         struct  scb *scb;
7171         struct  scb_tailq *untagged_q;
7172         u_int   cur_col;
7173         int     paused;
7174         int     target;
7175         int     maxtarget;
7176         int     i;
7177         uint8_t last_phase;
7178         uint8_t qinpos;
7179         uint8_t qintail;
7180         uint8_t qoutpos;
7181         uint8_t scb_index;
7182         uint8_t saved_scbptr;
7183
7184         if (ahc_is_paused(ahc)) {
7185                 paused = 1;
7186         } else {
7187                 paused = 0;
7188                 ahc_pause(ahc);
7189         }
7190
7191         saved_scbptr = ahc_inb(ahc, SCBPTR);
7192         last_phase = ahc_inb(ahc, LASTPHASE);
7193         printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
7194                "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
7195                ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
7196                ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
7197         if (paused)
7198                 printf("Card was paused\n");
7199         printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
7200                ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
7201                ahc_inb(ahc, ARG_2));
7202         printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
7203                ahc_inb(ahc, SCBPTR));
7204         cur_col = 0;
7205         if ((ahc->features & AHC_DT) != 0)
7206                 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
7207         ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
7208         ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
7209         ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
7210         ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
7211         ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
7212         ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
7213         ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
7214         ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
7215         ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
7216         ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
7217         ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
7218         ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
7219         ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
7220         ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
7221         ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
7222         ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
7223         ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
7224         ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
7225         if (cur_col != 0)
7226                 printf("\n");
7227         printf("STACK:");
7228         for (i = 0; i < STACK_SIZE; i++)
7229                printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
7230         printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
7231         printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
7232         printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
7233         /* QINFIFO */
7234         printf("QINFIFO entries: ");
7235         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
7236                 qinpos = ahc_inb(ahc, SNSCB_QOFF);
7237                 ahc_outb(ahc, SNSCB_QOFF, qinpos);
7238         } else
7239                 qinpos = ahc_inb(ahc, QINPOS);
7240         qintail = ahc->qinfifonext;
7241         while (qinpos != qintail) {
7242                 printf("%d ", ahc->qinfifo[qinpos]);
7243                 qinpos++;
7244         }
7245         printf("\n");
7246
7247         printf("Waiting Queue entries: ");
7248         scb_index = ahc_inb(ahc, WAITING_SCBH);
7249         i = 0;
7250         while (scb_index != SCB_LIST_NULL && i++ < 256) {
7251                 ahc_outb(ahc, SCBPTR, scb_index);
7252                 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7253                 scb_index = ahc_inb(ahc, SCB_NEXT);
7254         }
7255         printf("\n");
7256
7257         printf("Disconnected Queue entries: ");
7258         scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
7259         i = 0;
7260         while (scb_index != SCB_LIST_NULL && i++ < 256) {
7261                 ahc_outb(ahc, SCBPTR, scb_index);
7262                 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
7263                 scb_index = ahc_inb(ahc, SCB_NEXT);
7264         }
7265         printf("\n");
7266
7267         ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
7268         printf("QOUTFIFO entries: ");
7269         qoutpos = ahc->qoutfifonext;
7270         i = 0;
7271         while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
7272                 printf("%d ", ahc->qoutfifo[qoutpos]);
7273                 qoutpos++;
7274         }
7275         printf("\n");
7276
7277         printf("Sequencer Free SCB List: ");
7278         scb_index = ahc_inb(ahc, FREE_SCBH);
7279         i = 0;
7280         while (scb_index != SCB_LIST_NULL && i++ < 256) {
7281                 ahc_outb(ahc, SCBPTR, scb_index);
7282                 printf("%d ", scb_index);
7283                 scb_index = ahc_inb(ahc, SCB_NEXT);
7284         }
7285         printf("\n");
7286
7287         printf("Sequencer SCB Info: ");
7288         for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
7289                 ahc_outb(ahc, SCBPTR, i);
7290                 cur_col = printf("\n%3d ", i);
7291
7292                 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
7293                 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
7294                 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
7295                 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7296         }
7297         printf("\n");
7298
7299         printf("Pending list: ");
7300         i = 0;
7301         LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7302                 if (i++ > 256)
7303                         break;
7304                 cur_col = printf("\n%3d ", scb->hscb->tag);
7305                 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
7306                 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
7307                 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
7308                 if ((ahc->flags & AHC_PAGESCBS) == 0) {
7309                         ahc_outb(ahc, SCBPTR, scb->hscb->tag);
7310                         printf("(");
7311                         ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
7312                                               &cur_col, 60);
7313                         ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
7314                         printf(")");
7315                 }
7316         }
7317         printf("\n");
7318
7319         printf("Kernel Free SCB list: ");
7320         i = 0;
7321         SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
7322                 if (i++ > 256)
7323                         break;
7324                 printf("%d ", scb->hscb->tag);
7325         }
7326         printf("\n");
7327
7328         maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
7329         for (target = 0; target <= maxtarget; target++) {
7330                 untagged_q = &ahc->untagged_queues[target];
7331                 if (TAILQ_FIRST(untagged_q) == NULL)
7332                         continue;
7333                 printf("Untagged Q(%d): ", target);
7334                 i = 0;
7335                 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
7336                         if (i++ > 256)
7337                                 break;
7338                         printf("%d ", scb->hscb->tag);
7339                 }
7340                 printf("\n");
7341         }
7342
7343         ahc_platform_dump_card_state(ahc);
7344         printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
7345         ahc_outb(ahc, SCBPTR, saved_scbptr);
7346         if (paused == 0)
7347                 ahc_unpause(ahc);
7348 }
7349
7350 /************************* Target Mode ****************************************/
7351 #ifdef AHC_TARGET_MODE
7352 cam_status
7353 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
7354                     struct ahc_tmode_tstate **tstate,
7355                     struct ahc_tmode_lstate **lstate,
7356                     int notfound_failure)
7357 {
7358
7359         if ((ahc->features & AHC_TARGETMODE) == 0)
7360                 return (CAM_REQ_INVALID);
7361
7362         /*
7363          * Handle the 'black hole' device that sucks up
7364          * requests to unattached luns on enabled targets.
7365          */
7366         if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
7367          && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
7368                 *tstate = NULL;
7369                 *lstate = ahc->black_hole;
7370         } else {
7371                 u_int max_id;
7372
7373                 max_id = (ahc->features & AHC_WIDE) ? 16 : 8;
7374                 if (ccb->ccb_h.target_id >= max_id)
7375                         return (CAM_TID_INVALID);
7376
7377                 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
7378                         return (CAM_LUN_INVALID);
7379
7380                 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
7381                 *lstate = NULL;
7382                 if (*tstate != NULL)
7383                         *lstate =
7384                             (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
7385         }
7386
7387         if (notfound_failure != 0 && *lstate == NULL)
7388                 return (CAM_PATH_INVALID);
7389
7390         return (CAM_REQ_CMP);
7391 }
7392
7393 void
7394 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
7395 {
7396         struct     ahc_tmode_tstate *tstate;
7397         struct     ahc_tmode_lstate *lstate;
7398         struct     ccb_en_lun *cel;
7399         cam_status status;
7400         u_long     s;
7401         u_int      target;
7402         u_int      lun;
7403         u_int      target_mask;
7404         u_int      our_id;
7405         int        error;
7406         char       channel;
7407
7408         status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
7409                                      /*notfound_failure*/FALSE);
7410
7411         if (status != CAM_REQ_CMP) {
7412                 ccb->ccb_h.status = status;
7413                 return;
7414         }
7415
7416         if (cam_sim_bus(sim) == 0)
7417                 our_id = ahc->our_id;
7418         else
7419                 our_id = ahc->our_id_b;
7420
7421         if (ccb->ccb_h.target_id != our_id) {
7422                 /*
7423                  * our_id represents our initiator ID, or
7424                  * the ID of the first target to have an
7425                  * enabled lun in target mode.  There are
7426                  * two cases that may preclude enabling a
7427                  * target id other than our_id.
7428                  *
7429                  *   o our_id is for an active initiator role.
7430                  *     Since the hardware does not support
7431                  *     reselections to the initiator role at
7432                  *     anything other than our_id, and our_id
7433                  *     is used by the hardware to indicate the
7434                  *     ID to use for both select-out and
7435                  *     reselect-out operations, the only target
7436                  *     ID we can support in this mode is our_id.
7437                  *
7438                  *   o The MULTARGID feature is not available and
7439                  *     a previous target mode ID has been enabled.
7440                  */
7441                 if ((ahc->features & AHC_MULTIROLE) != 0) {
7442
7443                         if ((ahc->features & AHC_MULTI_TID) != 0
7444                          && (ahc->flags & AHC_INITIATORROLE) != 0) {
7445                                 /*
7446                                  * Only allow additional targets if
7447                                  * the initiator role is disabled.
7448                                  * The hardware cannot handle a re-select-in
7449                                  * on the initiator id during a re-select-out
7450                                  * on a different target id.
7451                                  */
7452                                 status = CAM_TID_INVALID;
7453                         } else if ((ahc->flags & AHC_INITIATORROLE) != 0
7454                                 || ahc->enabled_luns > 0) {
7455                                 /*
7456                                  * Only allow our target id to change
7457                                  * if the initiator role is not configured
7458                                  * and there are no enabled luns which
7459                                  * are attached to the currently registered
7460                                  * scsi id.
7461                                  */
7462                                 status = CAM_TID_INVALID;
7463                         }
7464                 } else if ((ahc->features & AHC_MULTI_TID) == 0
7465                         && ahc->enabled_luns > 0) {
7466
7467                         status = CAM_TID_INVALID;
7468                 }
7469         }
7470
7471         if (status != CAM_REQ_CMP) {
7472                 ccb->ccb_h.status = status;
7473                 return;
7474         }
7475
7476         /*
7477          * We now have an id that is valid.
7478          * If we aren't in target mode, switch modes.
7479          */
7480         if ((ahc->flags & AHC_TARGETROLE) == 0
7481          && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
7482                 u_long   s;
7483                 ahc_flag saved_flags;
7484
7485                 printf("Configuring Target Mode\n");
7486                 ahc_lock(ahc, &s);
7487                 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
7488                         ccb->ccb_h.status = CAM_BUSY;
7489                         ahc_unlock(ahc, &s);
7490                         return;
7491                 }
7492                 saved_flags = ahc->flags;
7493                 ahc->flags |= AHC_TARGETROLE;
7494                 if ((ahc->features & AHC_MULTIROLE) == 0)
7495                         ahc->flags &= ~AHC_INITIATORROLE;
7496                 ahc_pause(ahc);
7497                 error = ahc_loadseq(ahc);
7498                 if (error != 0) {
7499                         /*
7500                          * Restore original configuration and notify
7501                          * the caller that we cannot support target mode.
7502                          * Since the adapter started out in this
7503                          * configuration, the firmware load will succeed,
7504                          * so there is no point in checking ahc_loadseq's
7505                          * return value.
7506                          */
7507                         ahc->flags = saved_flags;
7508                         (void)ahc_loadseq(ahc);
7509                         ahc_restart(ahc);
7510                         ahc_unlock(ahc, &s);
7511                         ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
7512                         return;
7513                 }
7514                 ahc_restart(ahc);
7515                 ahc_unlock(ahc, &s);
7516         }
7517         cel = &ccb->cel;
7518         target = ccb->ccb_h.target_id;
7519         lun = ccb->ccb_h.target_lun;
7520         channel = SIM_CHANNEL(ahc, sim);
7521         target_mask = 0x01 << target;
7522         if (channel == 'B')
7523                 target_mask <<= 8;
7524
7525         if (cel->enable != 0) {
7526                 u_int scsiseq;
7527
7528                 /* Are we already enabled?? */
7529                 if (lstate != NULL) {
7530                         xpt_print_path(ccb->ccb_h.path);
7531                         printf("Lun already enabled\n");
7532                         ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
7533                         return;
7534                 }
7535
7536                 if (cel->grp6_len != 0
7537                  || cel->grp7_len != 0) {
7538                         /*
7539                          * Don't (yet?) support vendor
7540                          * specific commands.
7541                          */
7542                         ccb->ccb_h.status = CAM_REQ_INVALID;
7543                         printf("Non-zero Group Codes\n");
7544                         return;
7545                 }
7546
7547                 /*
7548                  * Seems to be okay.
7549                  * Setup our data structures.
7550                  */
7551                 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
7552                         tstate = ahc_alloc_tstate(ahc, target, channel);
7553                         if (tstate == NULL) {
7554                                 xpt_print_path(ccb->ccb_h.path);
7555                                 printf("Couldn't allocate tstate\n");
7556                                 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7557                                 return;
7558                         }
7559                 }
7560                 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
7561                 if (lstate == NULL) {
7562                         xpt_print_path(ccb->ccb_h.path);
7563                         printf("Couldn't allocate lstate\n");
7564                         ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7565                         return;
7566                 }
7567                 memset(lstate, 0, sizeof(*lstate));
7568                 status = xpt_create_path(&lstate->path, /*periph*/NULL,
7569                                          xpt_path_path_id(ccb->ccb_h.path),
7570                                          xpt_path_target_id(ccb->ccb_h.path),
7571                                          xpt_path_lun_id(ccb->ccb_h.path));
7572                 if (status != CAM_REQ_CMP) {
7573                         free(lstate, M_DEVBUF);
7574                         xpt_print_path(ccb->ccb_h.path);
7575                         printf("Couldn't allocate path\n");
7576                         ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
7577                         return;
7578                 }
7579                 SLIST_INIT(&lstate->accept_tios);
7580                 SLIST_INIT(&lstate->immed_notifies);
7581                 ahc_lock(ahc, &s);
7582                 ahc_pause(ahc);
7583                 if (target != CAM_TARGET_WILDCARD) {
7584                         tstate->enabled_luns[lun] = lstate;
7585                         ahc->enabled_luns++;
7586
7587                         if ((ahc->features & AHC_MULTI_TID) != 0) {
7588                                 u_int targid_mask;
7589
7590                                 targid_mask = ahc_inb(ahc, TARGID)
7591                                             | (ahc_inb(ahc, TARGID + 1) << 8);
7592
7593                                 targid_mask |= target_mask;
7594                                 ahc_outb(ahc, TARGID, targid_mask);
7595                                 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7596
7597                                 ahc_update_scsiid(ahc, targid_mask);
7598                         } else {
7599                                 u_int our_id;
7600                                 char  channel;
7601
7602                                 channel = SIM_CHANNEL(ahc, sim);
7603                                 our_id = SIM_SCSI_ID(ahc, sim);
7604
7605                                 /*
7606                                  * This can only happen if selections
7607                                  * are not enabled
7608                                  */
7609                                 if (target != our_id) {
7610                                         u_int sblkctl;
7611                                         char  cur_channel;
7612                                         int   swap;
7613
7614                                         sblkctl = ahc_inb(ahc, SBLKCTL);
7615                                         cur_channel = (sblkctl & SELBUSB)
7616                                                     ? 'B' : 'A';
7617                                         if ((ahc->features & AHC_TWIN) == 0)
7618                                                 cur_channel = 'A';
7619                                         swap = cur_channel != channel;
7620                                         if (channel == 'A')
7621                                                 ahc->our_id = target;
7622                                         else
7623                                                 ahc->our_id_b = target;
7624
7625                                         if (swap)
7626                                                 ahc_outb(ahc, SBLKCTL,
7627                                                          sblkctl ^ SELBUSB);
7628
7629                                         ahc_outb(ahc, SCSIID, target);
7630
7631                                         if (swap)
7632                                                 ahc_outb(ahc, SBLKCTL, sblkctl);
7633                                 }
7634                         }
7635                 } else
7636                         ahc->black_hole = lstate;
7637                 /* Allow select-in operations */
7638                 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7639                         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7640                         scsiseq |= ENSELI;
7641                         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7642                         scsiseq = ahc_inb(ahc, SCSISEQ);
7643                         scsiseq |= ENSELI;
7644                         ahc_outb(ahc, SCSISEQ, scsiseq);
7645                 }
7646                 ahc_unpause(ahc);
7647                 ahc_unlock(ahc, &s);
7648                 ccb->ccb_h.status = CAM_REQ_CMP;
7649                 xpt_print_path(ccb->ccb_h.path);
7650                 printf("Lun now enabled for target mode\n");
7651         } else {
7652                 struct scb *scb;
7653                 int i, empty;
7654
7655                 if (lstate == NULL) {
7656                         ccb->ccb_h.status = CAM_LUN_INVALID;
7657                         return;
7658                 }
7659
7660                 ahc_lock(ahc, &s);
7661
7662                 ccb->ccb_h.status = CAM_REQ_CMP;
7663                 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7664                         struct ccb_hdr *ccbh;
7665
7666                         ccbh = &scb->io_ctx->ccb_h;
7667                         if (ccbh->func_code == XPT_CONT_TARGET_IO
7668                          && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7669                                 printf("CTIO pending\n");
7670                                 ccb->ccb_h.status = CAM_REQ_INVALID;
7671                                 ahc_unlock(ahc, &s);
7672                                 return;
7673                         }
7674                 }
7675
7676                 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7677                         printf("ATIOs pending\n");
7678                         ccb->ccb_h.status = CAM_REQ_INVALID;
7679                 }
7680
7681                 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7682                         printf("INOTs pending\n");
7683                         ccb->ccb_h.status = CAM_REQ_INVALID;
7684                 }
7685
7686                 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7687                         ahc_unlock(ahc, &s);
7688                         return;
7689                 }
7690
7691                 xpt_print_path(ccb->ccb_h.path);
7692                 printf("Target mode disabled\n");
7693                 xpt_free_path(lstate->path);
7694                 free(lstate, M_DEVBUF);
7695
7696                 ahc_pause(ahc);
7697                 /* Can we clean up the target too? */
7698                 if (target != CAM_TARGET_WILDCARD) {
7699                         tstate->enabled_luns[lun] = NULL;
7700                         ahc->enabled_luns--;
7701                         for (empty = 1, i = 0; i < 8; i++)
7702                                 if (tstate->enabled_luns[i] != NULL) {
7703                                         empty = 0;
7704                                         break;
7705                                 }
7706
7707                         if (empty) {
7708                                 ahc_free_tstate(ahc, target, channel,
7709                                                 /*force*/FALSE);
7710                                 if (ahc->features & AHC_MULTI_TID) {
7711                                         u_int targid_mask;
7712
7713                                         targid_mask = ahc_inb(ahc, TARGID)
7714                                                     | (ahc_inb(ahc, TARGID + 1)
7715                                                        << 8);
7716
7717                                         targid_mask &= ~target_mask;
7718                                         ahc_outb(ahc, TARGID, targid_mask);
7719                                         ahc_outb(ahc, TARGID+1,
7720                                                  (targid_mask >> 8));
7721                                         ahc_update_scsiid(ahc, targid_mask);
7722                                 }
7723                         }
7724                 } else {
7725
7726                         ahc->black_hole = NULL;
7727
7728                         /*
7729                          * We can't allow selections without
7730                          * our black hole device.
7731                          */
7732                         empty = TRUE;
7733                 }
7734                 if (ahc->enabled_luns == 0) {
7735                         /* Disallow select-in */
7736                         u_int scsiseq;
7737
7738                         scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7739                         scsiseq &= ~ENSELI;
7740                         ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7741                         scsiseq = ahc_inb(ahc, SCSISEQ);
7742                         scsiseq &= ~ENSELI;
7743                         ahc_outb(ahc, SCSISEQ, scsiseq);
7744
7745                         if ((ahc->features & AHC_MULTIROLE) == 0) {
7746                                 printf("Configuring Initiator Mode\n");
7747                                 ahc->flags &= ~AHC_TARGETROLE;
7748                                 ahc->flags |= AHC_INITIATORROLE;
7749                                 /*
7750                                  * Returning to a configuration that
7751                                  * fit previously will always succeed.
7752                                  */
7753                                 (void)ahc_loadseq(ahc);
7754                                 ahc_restart(ahc);
7755                                 /*
7756                                  * Unpaused.  The extra unpause
7757                                  * that follows is harmless.
7758                                  */
7759                         }
7760                 }
7761                 ahc_unpause(ahc);
7762                 ahc_unlock(ahc, &s);
7763         }
7764 }
7765
7766 static void
7767 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7768 {
7769         u_int scsiid_mask;
7770         u_int scsiid;
7771
7772         if ((ahc->features & AHC_MULTI_TID) == 0)
7773                 panic("ahc_update_scsiid called on non-multitid unit\n");
7774
7775         /*
7776          * Since we will rely on the TARGID mask
7777          * for selection enables, ensure that OID
7778          * in SCSIID is not set to some other ID
7779          * that we don't want to allow selections on.
7780          */
7781         if ((ahc->features & AHC_ULTRA2) != 0)
7782                 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7783         else
7784                 scsiid = ahc_inb(ahc, SCSIID);
7785         scsiid_mask = 0x1 << (scsiid & OID);
7786         if ((targid_mask & scsiid_mask) == 0) {
7787                 u_int our_id;
7788
7789                 /* ffs counts from 1 */
7790                 our_id = ffs(targid_mask);
7791                 if (our_id == 0)
7792                         our_id = ahc->our_id;
7793                 else
7794                         our_id--;
7795                 scsiid &= TID;
7796                 scsiid |= our_id;
7797         }
7798         if ((ahc->features & AHC_ULTRA2) != 0)
7799                 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7800         else
7801                 ahc_outb(ahc, SCSIID, scsiid);
7802 }
7803
7804 static void
7805 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7806 {
7807         struct target_cmd *cmd;
7808
7809         /*
7810          * If the card supports auto-access pause,
7811          * we can access the card directly regardless
7812          * of whether it is paused or not.
7813          */
7814         if ((ahc->features & AHC_AUTOPAUSE) != 0)
7815                 paused = TRUE;
7816
7817         ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7818         while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7819
7820                 /*
7821                  * Only advance through the queue if we
7822                  * have the resources to process the command.
7823                  */
7824                 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7825                         break;
7826
7827                 cmd->cmd_valid = 0;
7828                 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7829                                 ahc->shared_data_dmamap,
7830                                 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7831                                 sizeof(struct target_cmd),
7832                                 BUS_DMASYNC_PREREAD);
7833                 ahc->tqinfifonext++;
7834
7835                 /*
7836                  * Lazily update our position in the target mode incoming
7837                  * command queue as seen by the sequencer.
7838                  */
7839                 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7840                         if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7841                                 u_int hs_mailbox;
7842
7843                                 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7844                                 hs_mailbox &= ~HOST_TQINPOS;
7845                                 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7846                                 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7847                         } else {
7848                                 if (!paused)
7849                                         ahc_pause(ahc);
7850                                 ahc_outb(ahc, KERNEL_TQINPOS,
7851                                          ahc->tqinfifonext & HOST_TQINPOS);
7852                                 if (!paused)
7853                                         ahc_unpause(ahc);
7854                         }
7855                 }
7856         }
7857 }
7858
7859 static int
7860 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7861 {
7862         struct    ahc_tmode_tstate *tstate;
7863         struct    ahc_tmode_lstate *lstate;
7864         struct    ccb_accept_tio *atio;
7865         uint8_t *byte;
7866         int       initiator;
7867         int       target;
7868         int       lun;
7869
7870         initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7871         target = SCSIID_OUR_ID(cmd->scsiid);
7872         lun    = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7873
7874         byte = cmd->bytes;
7875         tstate = ahc->enabled_targets[target];
7876         lstate = NULL;
7877         if (tstate != NULL)
7878                 lstate = tstate->enabled_luns[lun];
7879
7880         /*
7881          * Commands for disabled luns go to the black hole driver.
7882          */
7883         if (lstate == NULL)
7884                 lstate = ahc->black_hole;
7885
7886         atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7887         if (atio == NULL) {
7888                 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7889                 /*
7890                  * Wait for more ATIOs from the peripheral driver for this lun.
7891                  */
7892                 if (bootverbose)
7893                         printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7894                 return (1);
7895         } else
7896                 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7897 #if 0
7898         printf("Incoming command from %d for %d:%d%s\n",
7899                initiator, target, lun,
7900                lstate == ahc->black_hole ? "(Black Holed)" : "");
7901 #endif
7902         SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7903
7904         if (lstate == ahc->black_hole) {
7905                 /* Fill in the wildcards */
7906                 atio->ccb_h.target_id = target;
7907                 atio->ccb_h.target_lun = lun;
7908         }
7909
7910         /*
7911          * Package it up and send it off to
7912          * whomever has this lun enabled.
7913          */
7914         atio->sense_len = 0;
7915         atio->init_id = initiator;
7916         if (byte[0] != 0xFF) {
7917                 /* Tag was included */
7918                 atio->tag_action = *byte++;
7919                 atio->tag_id = *byte++;
7920                 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7921         } else {
7922                 atio->ccb_h.flags = 0;
7923         }
7924         byte++;
7925
7926         /* Okay.  Now determine the cdb size based on the command code */
7927         switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7928         case 0:
7929                 atio->cdb_len = 6;
7930                 break;
7931         case 1:
7932         case 2:
7933                 atio->cdb_len = 10;
7934                 break;
7935         case 4:
7936                 atio->cdb_len = 16;
7937                 break;
7938         case 5:
7939                 atio->cdb_len = 12;
7940                 break;
7941         case 3:
7942         default:
7943                 /* Only copy the opcode. */
7944                 atio->cdb_len = 1;
7945                 printf("Reserved or VU command code type encountered\n");
7946                 break;
7947         }
7948
7949         memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7950
7951         atio->ccb_h.status |= CAM_CDB_RECVD;
7952
7953         if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7954                 /*
7955                  * We weren't allowed to disconnect.
7956                  * We're hanging on the bus until a
7957                  * continue target I/O comes in response
7958                  * to this accept tio.
7959                  */
7960 #if 0
7961                 printf("Received Immediate Command %d:%d:%d - %p\n",
7962                        initiator, target, lun, ahc->pending_device);
7963 #endif
7964                 ahc->pending_device = lstate;
7965                 ahc_freeze_ccb((union ccb *)atio);
7966                 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7967         }
7968         xpt_done((union ccb*)atio);
7969         return (0);
7970 }
7971
7972 #endif