2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <dev/aic7xxx/aic7xxx_osm.h>
49 #include <dev/aic7xxx/aic7xxx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
71 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
74 * Hardware error codes.
76 struct ahc_hard_error_entry {
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referrenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" },
85 { SQPARERR, "Sequencer Parity Error" },
86 { DPARERR, "Data-path Parity Error" },
87 { MPARERR, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT, "PCI Error detected" },
89 { CIOPARERR, "CIOBUS Parity Error" },
91 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
93 static struct ahc_phase_table_entry ahc_phase_table[] =
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
99 { P_COMMAND, MSG_NOOP, "in Command phase" },
100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
103 { P_BUSFREE, MSG_NOOP, "while idle" },
104 { 0, MSG_NOOP, "in unknown phase" }
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
111 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
118 static struct ahc_syncrate ahc_syncrates[] =
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL }
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc *ahc,
143 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145 ahc_alloc_tstate(struct ahc_softc *ahc,
146 u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force);
151 static struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *,
157 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
159 struct ahc_devinfo *devinfo);
160 static void ahc_scb_devinfo(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
163 static void ahc_assert_atn(struct ahc_softc *ahc);
164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
167 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo);
169 static void ahc_construct_sdtr(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 u_int period, u_int offset);
172 static void ahc_construct_wdtr(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo,
175 static void ahc_construct_ppr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset,
178 u_int bus_width, u_int ppr_options);
179 static void ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void ahc_handle_message_phase(struct ahc_softc *ahc);
187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188 u_int msgval, int full);
189 static int ahc_parse_msg(struct ahc_softc *ahc,
190 struct ahc_devinfo *devinfo);
191 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
192 struct ahc_devinfo *devinfo);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void ahc_handle_devreset(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo,
198 cam_status status, char *message,
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
206 static bus_dmamap_callback_t ahc_dmamap_cb;
207 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int ahc_init_scbdata(struct ahc_softc *ahc);
209 static void ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb,
213 static int ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215 u_int prev, u_int scbptr);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
218 u_int scbpos, u_int prev);
219 static void ahc_reset_current_bus(struct ahc_softc *ahc);
221 static void ahc_dumpseq(struct ahc_softc *ahc);
223 static int ahc_loadseq(struct ahc_softc *ahc);
224 static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr);
227 static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts);
229 #ifdef AHC_TARGET_MODE
230 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
231 struct ahc_tmode_lstate *lstate,
235 static void ahc_update_scsiid(struct ahc_softc *ahc,
237 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
238 struct target_cmd *cmd);
240 /************************* Sequencer Execution Control ************************/
242 * Restart the sequencer program from address zero
245 ahc_restart(struct ahc_softc *ahc)
250 /* No more pending messages. */
251 ahc_clear_msg_state(ahc);
253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
256 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
257 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
258 ahc_outb(ahc, SAVED_LUN, 0xFF);
261 * Ensure that the sequencer's idea of TQINPOS
262 * matches our own. The sequencer increments TQINPOS
263 * only after it sees a DMA complete and a reset could
264 * occur before the increment leaving the kernel to believe
265 * the command arrived but the sequencer to not.
267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
269 /* Always allow reselection */
270 ahc_outb(ahc, SCSISEQ,
271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
272 if ((ahc->features & AHC_CMD_CHAN) != 0) {
273 /* Ensure that no DMA operations are in progress */
274 ahc_outb(ahc, CCSCBCNT, 0);
275 ahc_outb(ahc, CCSGCTL, 0);
276 ahc_outb(ahc, CCSCBCTL, 0);
279 * If we were in the process of DMA'ing SCB data into
280 * an SCB, replace that SCB on the free list. This prevents
283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
284 ahc_add_curscb_to_free_list(ahc);
285 ahc_outb(ahc, SEQ_FLAGS2,
286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
290 * Clear any pending sequencer interrupt. It is no
291 * longer relevant since we're resetting the Program
294 ahc_outb(ahc, CLRINT, CLRSEQINT);
296 ahc_outb(ahc, MWI_RESIDUAL, 0);
297 ahc_outb(ahc, SEQCTL, ahc->seqctl);
298 ahc_outb(ahc, SEQADDR0, 0);
299 ahc_outb(ahc, SEQADDR1, 0);
304 /************************* Input/Output Queues ********************************/
306 ahc_run_qoutfifo(struct ahc_softc *ahc)
311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
314 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
315 if ((ahc->qoutfifonext & 0x03) == 0x03) {
319 * Clear 32bits of QOUTFIFO at a time
320 * so that we don't clobber an incoming
321 * byte DMA to the array on architectures
322 * that only support 32bit load and store
325 modnext = ahc->qoutfifonext & ~0x3;
326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
328 ahc->shared_data_dmamap,
329 /*offset*/modnext, /*len*/4,
330 BUS_DMASYNC_PREREAD);
334 scb = ahc_lookup_scb(ahc, scb_index);
336 printf("%s: WARNING no command for scb %d "
337 "(cmdcmplt)\nQOUTPOS = %d\n",
338 ahc_name(ahc), scb_index,
339 (ahc->qoutfifonext - 1) & 0xFF);
344 * Save off the residual
347 ahc_update_residual(ahc, scb);
353 ahc_run_untagged_queues(struct ahc_softc *ahc)
357 for (i = 0; i < 16; i++)
358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
366 if (ahc->untagged_queue_lock != 0)
369 if ((scb = TAILQ_FIRST(queue)) != NULL
370 && (scb->flags & SCB_ACTIVE) == 0) {
371 scb->flags |= SCB_ACTIVE;
372 ahc_queue_scb(ahc, scb);
376 /************************* Interrupt Handling *********************************/
378 ahc_handle_brkadrint(struct ahc_softc *ahc)
381 * We upset the sequencer :-(
382 * Lookup the error message
387 error = ahc_inb(ahc, ERROR);
388 for (i = 0; error != 1 && i < num_errors; i++)
390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
391 ahc_name(ahc), ahc_hard_errors[i].errmesg,
392 ahc_inb(ahc, SEQADDR0) |
393 (ahc_inb(ahc, SEQADDR1) << 8));
395 ahc_dump_card_state(ahc);
397 /* Tell everyone that this HBA is no longer available */
398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
402 /* Disable all interrupt sources by resetting the controller */
407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
410 struct ahc_devinfo devinfo;
412 ahc_fetch_devinfo(ahc, &devinfo);
415 * Clear the upper byte that holds SEQINT status
416 * codes and clear the SEQINT bit. We will unpause
417 * the sequencer, if appropriate, after servicing
420 ahc_outb(ahc, CLRINT, CLRSEQINT);
421 switch (intstat & SEQINT_MASK) {
425 struct hardware_scb *hscb;
428 * Set the default return value to 0 (don't
429 * send sense). The sense code will change
432 ahc_outb(ahc, RETURN_1, 0);
435 * The sequencer will notify us when a command
436 * has an error that would be of interest to
437 * the kernel. This allows us to leave the sequencer
438 * running in the common case of command completes
439 * without error. The sequencer will already have
440 * dma'd the SCB back up to us, so we can reference
441 * the in kernel copy directly.
443 scb_index = ahc_inb(ahc, SCB_TAG);
444 scb = ahc_lookup_scb(ahc, scb_index);
446 ahc_print_devinfo(ahc, &devinfo);
447 printf("ahc_intr - referenced scb "
448 "not valid during seqint 0x%x scb(%d)\n",
450 ahc_dump_card_state(ahc);
457 /* Don't want to clobber the original sense code */
458 if ((scb->flags & SCB_SENSE) != 0) {
460 * Clear the SCB_SENSE Flag and have
461 * the sequencer do a normal command
464 scb->flags &= ~SCB_SENSE;
465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
469 /* Freeze the queue until the client sees the error. */
470 ahc_freeze_devq(ahc, scb);
472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
473 switch (hscb->shared_data.status.scsi_status) {
475 printf("%s: Interrupted for staus of 0???\n",
478 case SCSI_STATUS_CMD_TERMINATED:
479 case SCSI_STATUS_CHECK_COND:
481 struct ahc_dma_seg *sg;
482 struct scsi_sense *sc;
483 struct ahc_initiator_tinfo *targ_info;
484 struct ahc_tmode_tstate *tstate;
485 struct ahc_transinfo *tinfo;
487 if (ahc_debug & AHC_SHOW_SENSE) {
488 ahc_print_path(ahc, scb);
489 printf("SCB %d: requests Check Status\n",
494 if (ahc_perform_autosense(scb) == 0)
497 targ_info = ahc_fetch_transinfo(ahc,
502 tinfo = &targ_info->curr;
504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
506 * Save off the residual if there is one.
508 ahc_update_residual(ahc, scb);
510 if (ahc_debug & AHC_SHOW_SENSE) {
511 ahc_print_path(ahc, scb);
512 printf("Sending Sense\n");
515 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
516 sg->len = ahc_get_sense_bufsize(ahc, scb);
517 sg->len |= AHC_DMA_LAST_SEG;
519 /* Fixup byte order */
520 sg->addr = ahc_htole32(sg->addr);
521 sg->len = ahc_htole32(sg->len);
523 sc->opcode = REQUEST_SENSE;
525 if (tinfo->protocol_version <= SCSI_REV_2
526 && SCB_GET_LUN(scb) < 8)
527 sc->byte2 = SCB_GET_LUN(scb) << 5;
530 sc->length = sg->len;
534 * We can't allow the target to disconnect.
535 * This will be an untagged transaction and
536 * having the target disconnect will make this
537 * transaction indestinguishable from outstanding
538 * tagged transactions.
543 * This request sense could be because the
544 * the device lost power or in some other
545 * way has lost our transfer negotiations.
546 * Renegotiate if appropriate. Unit attention
547 * errors will be reported before any data
550 if (ahc_get_residual(scb)
551 == ahc_get_transfer_length(scb)) {
552 ahc_update_neg_request(ahc, &devinfo,
554 AHC_NEG_IF_NON_ASYNC);
556 if (tstate->auto_negotiate & devinfo.target_mask) {
557 hscb->control |= MK_MESSAGE;
558 scb->flags &= ~SCB_NEGOTIATE;
559 scb->flags |= SCB_AUTO_NEGOTIATE;
561 hscb->cdb_len = sizeof(*sc);
562 hscb->dataptr = sg->addr;
563 hscb->datacnt = sg->len;
564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
565 hscb->sgptr = ahc_htole32(hscb->sgptr);
567 scb->flags |= SCB_SENSE;
568 ahc_qinfifo_requeue_tail(ahc, scb);
569 ahc_outb(ahc, RETURN_1, SEND_SENSE);
571 * Ensure we have enough time to actually
572 * retrieve the sense.
574 ahc_scb_timer_reset(scb, 5 * 1000000);
584 /* Ensure we don't leave the selection hardware on */
585 ahc_outb(ahc, SCSISEQ,
586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
588 printf("%s:%c:%d: no active SCB for reconnecting "
589 "target - issuing BUS DEVICE RESET\n",
590 ahc_name(ahc), devinfo.channel, devinfo.target);
591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
592 "ARG_1 == 0x%x ACCUM = 0x%x\n",
593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
598 ahc_index_busy_tcl(ahc,
599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
600 ahc_inb(ahc, SAVED_LUN))),
601 ahc_inb(ahc, SINDEX));
602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
606 ahc_inb(ahc, SCB_CONTROL));
607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
611 ahc_dump_card_state(ahc);
612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
614 ahc->msgout_index = 0;
615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
616 ahc_outb(ahc, MSG_OUT, HOST_MSG);
622 u_int rejbyte = ahc_inb(ahc, ACCUM);
623 printf("%s:%c:%d: Warning - unknown message received from "
624 "target (0x%x). Rejecting\n",
625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
628 case PROTO_VIOLATION:
630 ahc_handle_proto_violation(ahc);
634 ahc_handle_ign_wide_residue(ahc, &devinfo);
637 ahc_reinitialize_dataptrs(ahc);
643 lastphase = ahc_inb(ahc, LASTPHASE);
644 printf("%s:%c:%d: unknown scsi bus phase %x, "
645 "lastphase = 0x%x. Attempting to continue\n",
646 ahc_name(ahc), devinfo.channel, devinfo.target,
647 lastphase, ahc_inb(ahc, SCSISIGI));
654 lastphase = ahc_inb(ahc, LASTPHASE);
655 printf("%s:%c:%d: Missed busfree. "
656 "Lastphase = 0x%x, Curphase = 0x%x\n",
657 ahc_name(ahc), devinfo.channel, devinfo.target,
658 lastphase, ahc_inb(ahc, SCSISIGI));
665 * The sequencer has encountered a message phase
666 * that requires host assistance for completion.
667 * While handling the message phase(s), we will be
668 * notified by the sequencer after each byte is
669 * transfered so we can track bus phase changes.
671 * If this is the first time we've seen a HOST_MSG_LOOP
672 * interrupt, initialize the state of the host message
675 if (ahc->msg_type == MSG_TYPE_NONE) {
680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
681 if (bus_phase != P_MESGIN
682 && bus_phase != P_MESGOUT) {
683 printf("ahc_intr: HOST_MSG_LOOP bad "
687 * Probably transitioned to bus free before
688 * we got here. Just punt the message.
690 ahc_clear_intstat(ahc);
695 scb_index = ahc_inb(ahc, SCB_TAG);
696 scb = ahc_lookup_scb(ahc, scb_index);
697 if (devinfo.role == ROLE_INITIATOR) {
699 panic("HOST_MSG_LOOP with "
700 "invalid SCB %x\n", scb_index);
702 if (bus_phase == P_MESGOUT)
703 ahc_setup_initiator_msgout(ahc,
708 MSG_TYPE_INITIATOR_MSGIN;
709 ahc->msgin_index = 0;
712 #ifdef AHC_TARGET_MODE
714 if (bus_phase == P_MESGOUT) {
716 MSG_TYPE_TARGET_MSGOUT;
717 ahc->msgin_index = 0;
720 ahc_setup_target_msgin(ahc,
727 ahc_handle_message_phase(ahc);
733 * If we've cleared the parity error interrupt
734 * but the sequencer still believes that SCSIPERR
735 * is true, it must be that the parity error is
736 * for the currently presented byte on the bus,
737 * and we are not in a phase (data-in) where we will
738 * eventually ack this byte. Ack the byte and
739 * throw it away in the hope that the target will
740 * take us to message out to deliver the appropriate
743 if ((intstat & SCSIINT) == 0
744 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
746 if ((ahc->features & AHC_DT) == 0) {
750 * The hardware will only let you ack bytes
751 * if the expected phase in SCSISIGO matches
752 * the current phase. Make sure this is
753 * currently the case.
755 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
756 ahc_outb(ahc, LASTPHASE, curphase);
757 ahc_outb(ahc, SCSISIGO, curphase);
759 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
763 * In a data phase. Faster to bitbucket
764 * the data than to individually ack each
765 * byte. This is also the only strategy
766 * that will work with AUTOACK enabled.
768 ahc_outb(ahc, SXFRCTL1,
769 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
771 while (--wait != 0) {
772 if ((ahc_inb(ahc, SCSISIGI)
777 ahc_outb(ahc, SXFRCTL1,
778 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
783 ahc_print_devinfo(ahc, &devinfo);
784 printf("Unable to clear parity error. "
786 scb_index = ahc_inb(ahc, SCB_TAG);
787 scb = ahc_lookup_scb(ahc, scb_index);
789 ahc_set_transaction_status(scb,
791 ahc_reset_channel(ahc, devinfo.channel,
795 ahc_inb(ahc, SCSIDATL);
803 * When the sequencer detects an overrun, it
804 * places the controller in "BITBUCKET" mode
805 * and allows the target to complete its transfer.
806 * Unfortunately, none of the counters get updated
807 * when the controller is in this mode, so we have
808 * no way of knowing how large the overrun was.
810 u_int scbindex = ahc_inb(ahc, SCB_TAG);
811 u_int lastphase = ahc_inb(ahc, LASTPHASE);
814 scb = ahc_lookup_scb(ahc, scbindex);
815 for (i = 0; i < num_phases; i++) {
816 if (lastphase == ahc_phase_table[i].phase)
819 ahc_print_path(ahc, scb);
820 printf("data overrun detected %s."
822 ahc_phase_table[i].phasemsg,
824 ahc_print_path(ahc, scb);
825 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
826 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
827 ahc_get_transfer_length(scb), scb->sg_count);
828 if (scb->sg_count > 0) {
829 for (i = 0; i < scb->sg_count; i++) {
831 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
833 (ahc_le32toh(scb->sg_list[i].len) >> 24
834 & SG_HIGH_ADDR_BITS),
835 ahc_le32toh(scb->sg_list[i].addr),
836 ahc_le32toh(scb->sg_list[i].len)
841 * Set this and it will take effect when the
842 * target does a command complete.
844 ahc_freeze_devq(ahc, scb);
845 if ((scb->flags & SCB_SENSE) == 0) {
846 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
848 scb->flags &= ~SCB_SENSE;
849 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
853 if ((ahc->features & AHC_ULTRA2) != 0) {
855 * Clear the channel in case we return
856 * to data phase later.
858 ahc_outb(ahc, SXFRCTL0,
859 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
860 ahc_outb(ahc, SXFRCTL0,
861 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
863 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
866 /* Ensure HHADDR is 0 for future DMA operations. */
867 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
868 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
869 ahc_outb(ahc, HADDR, 0);
870 ahc_outb(ahc, DSCOMMAND1, dscommand1);
878 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
879 ahc_name(ahc), devinfo.channel, devinfo.target,
881 scbindex = ahc_inb(ahc, SCB_TAG);
882 scb = ahc_lookup_scb(ahc, scbindex);
884 && (scb->flags & SCB_RECOVERY_SCB) != 0)
886 * Ensure that we didn't put a second instance of this
887 * SCB into the QINFIFO.
889 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
890 SCB_GET_CHANNEL(ahc, scb),
891 SCB_GET_LUN(scb), scb->hscb->tag,
892 ROLE_INITIATOR, /*status*/0,
898 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
899 ahc_dump_card_state(ahc);
907 scbptr = ahc_inb(ahc, SCBPTR);
908 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
909 scbptr, ahc_inb(ahc, ARG_1),
910 ahc->scb_data->hscbs[scbptr].tag);
911 ahc_dump_card_state(ahc);
917 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
918 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
919 "ARG_1 == 0x%x ACCUM = 0x%x\n",
920 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
921 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
922 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
923 "SINDEX == 0x%x\n, A == 0x%x\n",
924 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
925 ahc_index_busy_tcl(ahc,
926 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
927 ahc_inb(ahc, SAVED_LUN))),
928 ahc_inb(ahc, SINDEX),
929 ahc_inb(ahc, ACCUM));
930 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
931 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
932 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
933 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
934 ahc_inb(ahc, SCB_CONTROL));
935 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
936 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
937 ahc_dump_card_state(ahc);
942 printf("ahc_intr: seqint, "
943 "intstat == 0x%x, scsisigi = 0x%x\n",
944 intstat, ahc_inb(ahc, SCSISIGI));
949 * The sequencer is paused immediately on
950 * a SEQINT, so we should restart it when
957 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
966 if ((ahc->features & AHC_TWIN) != 0
967 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
971 intr_channel = cur_channel;
973 if ((ahc->features & AHC_ULTRA2) != 0)
974 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
977 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
978 if (status == 0 && status0 == 0) {
979 if ((ahc->features & AHC_TWIN) != 0) {
980 /* Try the other channel */
981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982 status = ahc_inb(ahc, SSTAT1)
983 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
984 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
987 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
988 ahc_outb(ahc, CLRINT, CLRSCSIINT);
994 /* Make sure the sequencer is in a safe location. */
995 ahc_clear_critical_section(ahc);
997 scb_index = ahc_inb(ahc, SCB_TAG);
998 scb = ahc_lookup_scb(ahc, scb_index);
1000 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1003 if ((ahc->features & AHC_ULTRA2) != 0
1004 && (status0 & IOERR) != 0) {
1007 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1008 printf("%s: Transceiver State Has Changed to %s mode\n",
1009 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1010 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1012 * When transitioning to SE mode, the reset line
1013 * glitches, triggering an arbitration bug in some
1014 * Ultra2 controllers. This bug is cleared when we
1015 * assert the reset line. Since a reset glitch has
1016 * already occurred with this transition and a
1017 * transceiver state change is handled just like
1018 * a bus reset anyway, asserting the reset line
1019 * ourselves is safe.
1021 ahc_reset_channel(ahc, intr_channel,
1022 /*Initiate Reset*/now_lvd == 0);
1023 } else if ((status & SCSIRSTI) != 0) {
1024 printf("%s: Someone reset channel %c\n",
1025 ahc_name(ahc), intr_channel);
1026 if (intr_channel != cur_channel)
1027 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1028 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1029 } else if ((status & SCSIPERR) != 0) {
1031 * Determine the bus phase and queue an appropriate message.
1032 * SCSIPERR is latched true as soon as a parity error
1033 * occurs. If the sequencer acked the transfer that
1034 * caused the parity error and the currently presented
1035 * transfer on the bus has correct parity, SCSIPERR will
1036 * be cleared by CLRSCSIPERR. Use this to determine if
1037 * we should look at the last phase the sequencer recorded,
1038 * or the current phase presented on the bus.
1040 struct ahc_devinfo devinfo;
1050 lastphase = ahc_inb(ahc, LASTPHASE);
1051 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1052 sstat2 = ahc_inb(ahc, SSTAT2);
1053 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1055 * For all phases save DATA, the sequencer won't
1056 * automatically ack a byte that has a parity error
1057 * in it. So the only way that the current phase
1058 * could be 'data-in' is if the parity error is for
1059 * an already acked byte in the data phase. During
1060 * synchronous data-in transfers, we may actually
1061 * ack bytes before latching the current phase in
1062 * LASTPHASE, leading to the discrepancy between
1063 * curphase and lastphase.
1065 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1066 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1067 errorphase = curphase;
1069 errorphase = lastphase;
1071 for (i = 0; i < num_phases; i++) {
1072 if (errorphase == ahc_phase_table[i].phase)
1075 mesg_out = ahc_phase_table[i].mesg_out;
1078 if (SCB_IS_SILENT(scb))
1081 ahc_print_path(ahc, scb);
1082 scb->flags |= SCB_TRANSMISSION_ERROR;
1084 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1085 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1086 scsirate = ahc_inb(ahc, SCSIRATE);
1087 if (silent == FALSE) {
1088 printf("parity error detected %s. "
1089 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1090 ahc_phase_table[i].phasemsg,
1091 ahc_inw(ahc, SEQADDR0),
1093 if ((ahc->features & AHC_DT) != 0) {
1094 if ((sstat2 & CRCVALERR) != 0)
1095 printf("\tCRC Value Mismatch\n");
1096 if ((sstat2 & CRCENDERR) != 0)
1097 printf("\tNo terminal CRC packet "
1099 if ((sstat2 & CRCREQERR) != 0)
1100 printf("\tIllegal CRC packet "
1102 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1103 printf("\tUnexpected %sDT Data Phase\n",
1104 (scsirate & SINGLE_EDGE)
1109 if ((ahc->features & AHC_DT) != 0
1110 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1112 * This error applies regardless of
1113 * data direction, so ignore the value
1114 * in the phase table.
1116 mesg_out = MSG_INITIATOR_DET_ERR;
1120 * We've set the hardware to assert ATN if we
1121 * get a parity error on "in" phases, so all we
1122 * need to do is stuff the message buffer with
1123 * the appropriate message. "In" phases have set
1124 * mesg_out to something other than MSG_NOP.
1126 if (mesg_out != MSG_NOOP) {
1127 if (ahc->msg_type != MSG_TYPE_NONE)
1128 ahc->send_msg_perror = TRUE;
1130 ahc_outb(ahc, MSG_OUT, mesg_out);
1133 * Force a renegotiation with this target just in
1134 * case we are out of sync for some external reason
1135 * unknown (or unreported) by the target.
1137 ahc_fetch_devinfo(ahc, &devinfo);
1138 ahc_force_renegotiation(ahc, &devinfo);
1140 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1142 } else if ((status & SELTO) != 0) {
1145 /* Stop the selection */
1146 ahc_outb(ahc, SCSISEQ, 0);
1148 /* No more pending messages */
1149 ahc_clear_msg_state(ahc);
1151 /* Clear interrupt state */
1152 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1153 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1156 * Although the driver does not care about the
1157 * 'Selection in Progress' status bit, the busy
1158 * LED does. SELINGO is only cleared by a sucessfull
1159 * selection, so we must manually clear it to insure
1160 * the LED turns off just incase no future successful
1161 * selections occur (e.g. no devices on the bus).
1163 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1165 scbptr = ahc_inb(ahc, WAITING_SCBH);
1166 ahc_outb(ahc, SCBPTR, scbptr);
1167 scb_index = ahc_inb(ahc, SCB_TAG);
1169 scb = ahc_lookup_scb(ahc, scb_index);
1171 printf("%s: ahc_intr - referenced scb not "
1172 "valid during SELTO scb(%d, %d)\n",
1173 ahc_name(ahc), scbptr, scb_index);
1174 ahc_dump_card_state(ahc);
1176 struct ahc_devinfo devinfo;
1178 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1179 ahc_print_path(ahc, scb);
1180 printf("Saw Selection Timeout for SCB 0x%x\n",
1184 ahc_scb_devinfo(ahc, &devinfo, scb);
1185 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1186 ahc_freeze_devq(ahc, scb);
1189 * Cancel any pending transactions on the device
1190 * now that it seems to be missing. This will
1191 * also revert us to async/narrow transfers until
1192 * we can renegotiate with the device.
1194 ahc_handle_devreset(ahc, &devinfo,
1196 "Selection Timeout",
1197 /*verbose_level*/1);
1199 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1201 } else if ((status & BUSFREE) != 0
1202 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1203 struct ahc_devinfo devinfo;
1208 u_int initiator_role_id;
1213 * Clear our selection hardware as soon as possible.
1214 * We may have an entry in the waiting Q for this target,
1215 * that is affected by this busfree and we don't want to
1216 * go about selecting the target while we handle the event.
1218 ahc_outb(ahc, SCSISEQ,
1219 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1222 * Disable busfree interrupts and clear the busfree
1223 * interrupt status. We do this here so that several
1224 * bus transactions occur prior to clearing the SCSIINT
1225 * latch. It can take a bit for the clearing to take effect.
1227 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1228 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1231 * Look at what phase we were last in.
1232 * If its message out, chances are pretty good
1233 * that the busfree was in response to one of
1234 * our abort requests.
1236 lastphase = ahc_inb(ahc, LASTPHASE);
1237 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1238 saved_lun = ahc_inb(ahc, SAVED_LUN);
1239 target = SCSIID_TARGET(ahc, saved_scsiid);
1240 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1241 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1242 ahc_compile_devinfo(&devinfo, initiator_role_id,
1243 target, saved_lun, channel, ROLE_INITIATOR);
1246 if (lastphase == P_MESGOUT) {
1249 tag = SCB_LIST_NULL;
1250 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1251 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1252 if (ahc->msgout_buf[ahc->msgout_index - 1]
1254 tag = scb->hscb->tag;
1255 ahc_print_path(ahc, scb);
1256 printf("SCB %d - Abort%s Completed.\n",
1257 scb->hscb->tag, tag == SCB_LIST_NULL ?
1259 ahc_abort_scbs(ahc, target, channel,
1264 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1265 MSG_BUS_DEV_RESET, TRUE)) {
1268 * Don't mark the user's request for this BDR
1269 * as completing with CAM_BDR_SENT. CAM3
1270 * specifies CAM_REQ_CMP.
1273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1274 && ahc_match_scb(ahc, scb, target, channel,
1278 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1281 ahc_compile_devinfo(&devinfo,
1287 ahc_handle_devreset(ahc, &devinfo,
1290 /*verbose_level*/0);
1292 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1293 MSG_EXT_PPR, FALSE)) {
1294 struct ahc_initiator_tinfo *tinfo;
1295 struct ahc_tmode_tstate *tstate;
1298 * PPR Rejected. Try non-ppr negotiation
1299 * and retry command.
1301 tinfo = ahc_fetch_transinfo(ahc,
1306 tinfo->curr.transport_version = 2;
1307 tinfo->goal.transport_version = 2;
1308 tinfo->goal.ppr_options = 0;
1309 ahc_qinfifo_requeue_tail(ahc, scb);
1311 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1312 MSG_EXT_WDTR, FALSE)) {
1314 * Negotiation Rejected. Go-narrow and
1317 ahc_set_width(ahc, &devinfo,
1318 MSG_EXT_WDTR_BUS_8_BIT,
1319 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1321 ahc_qinfifo_requeue_tail(ahc, scb);
1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324 MSG_EXT_SDTR, FALSE)) {
1326 * Negotiation Rejected. Go-async and
1329 ahc_set_syncrate(ahc, &devinfo,
1331 /*period*/0, /*offset*/0,
1333 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1335 ahc_qinfifo_requeue_tail(ahc, scb);
1339 if (printerror != 0) {
1345 if ((scb->hscb->control & TAG_ENB) != 0)
1346 tag = scb->hscb->tag;
1348 tag = SCB_LIST_NULL;
1349 ahc_print_path(ahc, scb);
1350 ahc_abort_scbs(ahc, target, channel,
1351 SCB_GET_LUN(scb), tag,
1356 * We had not fully identified this connection,
1357 * so we cannot abort anything.
1359 printf("%s: ", ahc_name(ahc));
1361 for (i = 0; i < num_phases; i++) {
1362 if (lastphase == ahc_phase_table[i].phase)
1365 if (lastphase != P_BUSFREE) {
1367 * Renegotiate with this device at the
1368 * next oportunity just in case this busfree
1369 * is due to a negotiation mismatch with the
1372 ahc_force_renegotiation(ahc, &devinfo);
1374 printf("Unexpected busfree %s\n"
1375 "SEQADDR == 0x%x\n",
1376 ahc_phase_table[i].phasemsg,
1377 ahc_inb(ahc, SEQADDR0)
1378 | (ahc_inb(ahc, SEQADDR1) << 8));
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1383 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1384 ahc_name(ahc), status);
1385 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1390 * Force renegotiation to occur the next time we initiate
1391 * a command to the current device.
1394 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1396 struct ahc_initiator_tinfo *targ_info;
1397 struct ahc_tmode_tstate *tstate;
1399 targ_info = ahc_fetch_transinfo(ahc,
1401 devinfo->our_scsiid,
1404 ahc_update_neg_request(ahc, devinfo, tstate,
1405 targ_info, AHC_NEG_IF_NON_ASYNC);
1408 #define AHC_MAX_STEPS 2000
1410 ahc_clear_critical_section(struct ahc_softc *ahc)
1417 if (ahc->num_critical_sections == 0)
1429 seqaddr = ahc_inb(ahc, SEQADDR0)
1430 | (ahc_inb(ahc, SEQADDR1) << 8);
1433 * Seqaddr represents the next instruction to execute,
1434 * so we are really executing the instruction just
1439 cs = ahc->critical_sections;
1440 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1442 if (cs->begin < seqaddr && cs->end >= seqaddr)
1446 if (i == ahc->num_critical_sections)
1449 if (steps > AHC_MAX_STEPS) {
1450 printf("%s: Infinite loop in critical section\n",
1452 ahc_dump_card_state(ahc);
1453 panic("critical section loop");
1457 if (stepping == FALSE) {
1460 * Disable all interrupt sources so that the
1461 * sequencer will not be stuck by a pausing
1462 * interrupt condition while we attempt to
1463 * leave a critical section.
1465 simode0 = ahc_inb(ahc, SIMODE0);
1466 ahc_outb(ahc, SIMODE0, 0);
1467 simode1 = ahc_inb(ahc, SIMODE1);
1468 if ((ahc->features & AHC_DT) != 0)
1470 * On DT class controllers, we
1471 * use the enhanced busfree logic.
1472 * Unfortunately we cannot re-enable
1473 * busfree detection within the
1474 * current connection, so we must
1475 * leave it on while single stepping.
1477 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1479 ahc_outb(ahc, SIMODE1, 0);
1480 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1481 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1484 if ((ahc->features & AHC_DT) != 0) {
1485 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1486 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1488 ahc_outb(ahc, HCNTRL, ahc->unpause);
1489 while (!ahc_is_paused(ahc))
1493 ahc_outb(ahc, SIMODE0, simode0);
1494 ahc_outb(ahc, SIMODE1, simode1);
1495 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1500 * Clear any pending interrupt status.
1503 ahc_clear_intstat(struct ahc_softc *ahc)
1505 /* Clear any interrupt conditions this may have caused */
1506 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1507 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1509 ahc_flush_device_writes(ahc);
1510 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1511 ahc_flush_device_writes(ahc);
1512 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1513 ahc_flush_device_writes(ahc);
1516 /**************************** Debugging Routines ******************************/
1518 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1522 ahc_print_scb(struct scb *scb)
1526 struct hardware_scb *hscb = scb->hscb;
1528 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1534 printf("Shared Data: ");
1535 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1536 printf("%#02x", hscb->shared_data.cdb[i]);
1537 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1538 ahc_le32toh(hscb->dataptr),
1539 ahc_le32toh(hscb->datacnt),
1540 ahc_le32toh(hscb->sgptr),
1542 if (scb->sg_count > 0) {
1543 for (i = 0; i < scb->sg_count; i++) {
1544 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1546 (ahc_le32toh(scb->sg_list[i].len) >> 24
1547 & SG_HIGH_ADDR_BITS),
1548 ahc_le32toh(scb->sg_list[i].addr),
1549 ahc_le32toh(scb->sg_list[i].len));
1554 /************************* Transfer Negotiation *******************************/
1556 * Allocate per target mode instance (ID we respond to as a target)
1557 * transfer negotiation data structures.
1559 static struct ahc_tmode_tstate *
1560 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1562 struct ahc_tmode_tstate *master_tstate;
1563 struct ahc_tmode_tstate *tstate;
1566 master_tstate = ahc->enabled_targets[ahc->our_id];
1567 if (channel == 'B') {
1569 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1571 if (ahc->enabled_targets[scsi_id] != NULL
1572 && ahc->enabled_targets[scsi_id] != master_tstate)
1573 panic("%s: ahc_alloc_tstate - Target already allocated",
1575 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1576 M_DEVBUF, M_NOWAIT);
1581 * If we have allocated a master tstate, copy user settings from
1582 * the master tstate (taken from SRAM or the EEPROM) for this
1583 * channel, but reset our current and goal settings to async/narrow
1584 * until an initiator talks to us.
1586 if (master_tstate != NULL) {
1587 memcpy(tstate, master_tstate, sizeof(*tstate));
1588 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1589 tstate->ultraenb = 0;
1590 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1591 memset(&tstate->transinfo[i].curr, 0,
1592 sizeof(tstate->transinfo[i].curr));
1593 memset(&tstate->transinfo[i].goal, 0,
1594 sizeof(tstate->transinfo[i].goal));
1597 memset(tstate, 0, sizeof(*tstate));
1598 ahc->enabled_targets[scsi_id] = tstate;
1602 #ifdef AHC_TARGET_MODE
1604 * Free per target mode instance (ID we respond to as a target)
1605 * transfer negotiation data structures.
1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1610 struct ahc_tmode_tstate *tstate;
1613 * Don't clean up our "master" tstate.
1614 * It has our default user settings.
1616 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1617 || (channel == 'A' && scsi_id == ahc->our_id))
1623 tstate = ahc->enabled_targets[scsi_id];
1625 free(tstate, M_DEVBUF);
1626 ahc->enabled_targets[scsi_id] = NULL;
1631 * Called when we have an active connection to a target on the bus,
1632 * this function finds the nearest syncrate to the input period limited
1633 * by the capabilities of the bus connectivity of and sync settings for
1636 struct ahc_syncrate *
1637 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1638 struct ahc_initiator_tinfo *tinfo,
1639 u_int *period, u_int *ppr_options, role_t role)
1641 struct ahc_transinfo *transinfo;
1644 if ((ahc->features & AHC_ULTRA2) != 0) {
1645 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1646 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1647 maxsync = AHC_SYNCRATE_DT;
1649 maxsync = AHC_SYNCRATE_ULTRA;
1650 /* Can't do DT on an SE bus */
1651 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1653 } else if ((ahc->features & AHC_ULTRA) != 0) {
1654 maxsync = AHC_SYNCRATE_ULTRA;
1656 maxsync = AHC_SYNCRATE_FAST;
1659 * Never allow a value higher than our current goal
1660 * period otherwise we may allow a target initiated
1661 * negotiation to go above the limit as set by the
1662 * user. In the case of an initiator initiated
1663 * sync negotiation, we limit based on the user
1664 * setting. This allows the system to still accept
1665 * incoming negotiations even if target initiated
1666 * negotiation is not performed.
1668 if (role == ROLE_TARGET)
1669 transinfo = &tinfo->user;
1671 transinfo = &tinfo->goal;
1672 *ppr_options &= transinfo->ppr_options;
1673 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1674 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1675 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1677 if (transinfo->period == 0) {
1682 *period = MAX(*period, transinfo->period);
1683 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1687 * Look up the valid period to SCSIRATE conversion in our table.
1688 * Return the period and offset that should be sent to the target
1689 * if this was the beginning of an SDTR.
1691 struct ahc_syncrate *
1692 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1693 u_int *ppr_options, u_int maxsync)
1695 struct ahc_syncrate *syncrate;
1697 if ((ahc->features & AHC_DT) == 0)
1698 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1700 /* Skip all DT only entries if DT is not available */
1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1702 && maxsync < AHC_SYNCRATE_ULTRA2)
1703 maxsync = AHC_SYNCRATE_ULTRA2;
1705 for (syncrate = &ahc_syncrates[maxsync];
1706 syncrate->rate != NULL;
1710 * The Ultra2 table doesn't go as low
1711 * as for the Fast/Ultra cards.
1713 if ((ahc->features & AHC_ULTRA2) != 0
1714 && (syncrate->sxfr_u2 == 0))
1717 if (*period <= syncrate->period) {
1719 * When responding to a target that requests
1720 * sync, the requested rate may fall between
1721 * two rates that we can output, but still be
1722 * a rate that we can receive. Because of this,
1723 * we want to respond to the target with
1724 * the same rate that it sent to us even
1725 * if the period we use to send data to it
1726 * is lower. Only lower the response period
1729 if (syncrate == &ahc_syncrates[maxsync])
1730 *period = syncrate->period;
1733 * At some speeds, we only support
1736 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1737 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1743 || (syncrate->rate == NULL)
1744 || ((ahc->features & AHC_ULTRA2) != 0
1745 && (syncrate->sxfr_u2 == 0))) {
1746 /* Use asynchronous transfers. */
1749 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1755 * Convert from an entry in our syncrate table to the SCSI equivalent
1756 * sync "period" factor.
1759 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1761 struct ahc_syncrate *syncrate;
1763 if ((ahc->features & AHC_ULTRA2) != 0)
1764 scsirate &= SXFR_ULTRA2;
1768 syncrate = &ahc_syncrates[maxsync];
1769 while (syncrate->rate != NULL) {
1771 if ((ahc->features & AHC_ULTRA2) != 0) {
1772 if (syncrate->sxfr_u2 == 0)
1774 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1775 return (syncrate->period);
1776 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1777 return (syncrate->period);
1781 return (0); /* async */
1785 * Truncate the given synchronous offset to a value the
1786 * current adapter type and syncrate are capable of.
1789 ahc_validate_offset(struct ahc_softc *ahc,
1790 struct ahc_initiator_tinfo *tinfo,
1791 struct ahc_syncrate *syncrate,
1792 u_int *offset, int wide, role_t role)
1796 /* Limit offset to what we can do */
1797 if (syncrate == NULL) {
1799 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1800 maxoffset = MAX_OFFSET_ULTRA2;
1803 maxoffset = MAX_OFFSET_16BIT;
1805 maxoffset = MAX_OFFSET_8BIT;
1807 *offset = MIN(*offset, maxoffset);
1808 if (tinfo != NULL) {
1809 if (role == ROLE_TARGET)
1810 *offset = MIN(*offset, tinfo->user.offset);
1812 *offset = MIN(*offset, tinfo->goal.offset);
1817 * Truncate the given transfer width parameter to a value the
1818 * current adapter type is capable of.
1821 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1822 u_int *bus_width, role_t role)
1824 switch (*bus_width) {
1826 if (ahc->features & AHC_WIDE) {
1828 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1832 case MSG_EXT_WDTR_BUS_8_BIT:
1833 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1836 if (tinfo != NULL) {
1837 if (role == ROLE_TARGET)
1838 *bus_width = MIN(tinfo->user.width, *bus_width);
1840 *bus_width = MIN(tinfo->goal.width, *bus_width);
1845 * Update the bitmask of targets for which the controller should
1846 * negotiate with at the next convenient oportunity. This currently
1847 * means the next time we send the initial identify messages for
1848 * a new transaction.
1851 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1852 struct ahc_tmode_tstate *tstate,
1853 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1855 u_int auto_negotiate_orig;
1857 auto_negotiate_orig = tstate->auto_negotiate;
1858 if (neg_type == AHC_NEG_ALWAYS) {
1860 * Force our "current" settings to be
1861 * unknown so that unless a bus reset
1862 * occurs the need to renegotiate is
1863 * recorded persistently.
1865 if ((ahc->features & AHC_WIDE) != 0)
1866 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1867 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1868 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1870 if (tinfo->curr.period != tinfo->goal.period
1871 || tinfo->curr.width != tinfo->goal.width
1872 || tinfo->curr.offset != tinfo->goal.offset
1873 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1874 || (neg_type == AHC_NEG_IF_NON_ASYNC
1875 && (tinfo->goal.offset != 0
1876 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1877 || tinfo->goal.ppr_options != 0)))
1878 tstate->auto_negotiate |= devinfo->target_mask;
1880 tstate->auto_negotiate &= ~devinfo->target_mask;
1882 return (auto_negotiate_orig != tstate->auto_negotiate);
1886 * Update the user/goal/curr tables of synchronous negotiation
1887 * parameters as well as, in the case of a current or active update,
1888 * any data structures on the host controller. In the case of an
1889 * active update, the specified target is currently talking to us on
1890 * the bus, so the transfer parameter update must take effect
1894 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1895 struct ahc_syncrate *syncrate, u_int period,
1896 u_int offset, u_int ppr_options, u_int type, int paused)
1898 struct ahc_initiator_tinfo *tinfo;
1899 struct ahc_tmode_tstate *tstate;
1906 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1909 if (syncrate == NULL) {
1914 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1915 devinfo->target, &tstate);
1917 if ((type & AHC_TRANS_USER) != 0) {
1918 tinfo->user.period = period;
1919 tinfo->user.offset = offset;
1920 tinfo->user.ppr_options = ppr_options;
1923 if ((type & AHC_TRANS_GOAL) != 0) {
1924 tinfo->goal.period = period;
1925 tinfo->goal.offset = offset;
1926 tinfo->goal.ppr_options = ppr_options;
1929 old_period = tinfo->curr.period;
1930 old_offset = tinfo->curr.offset;
1931 old_ppr = tinfo->curr.ppr_options;
1933 if ((type & AHC_TRANS_CUR) != 0
1934 && (old_period != period
1935 || old_offset != offset
1936 || old_ppr != ppr_options)) {
1940 scsirate = tinfo->scsirate;
1941 if ((ahc->features & AHC_ULTRA2) != 0) {
1943 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1944 if (syncrate != NULL) {
1945 scsirate |= syncrate->sxfr_u2;
1946 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1947 scsirate |= ENABLE_CRC;
1949 scsirate |= SINGLE_EDGE;
1953 scsirate &= ~(SXFR|SOFS);
1955 * Ensure Ultra mode is set properly for
1958 tstate->ultraenb &= ~devinfo->target_mask;
1959 if (syncrate != NULL) {
1960 if (syncrate->sxfr & ULTRA_SXFR) {
1962 devinfo->target_mask;
1964 scsirate |= syncrate->sxfr & SXFR;
1965 scsirate |= offset & SOFS;
1970 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1971 sxfrctl0 &= ~FAST20;
1972 if (tstate->ultraenb & devinfo->target_mask)
1974 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1978 ahc_outb(ahc, SCSIRATE, scsirate);
1979 if ((ahc->features & AHC_ULTRA2) != 0)
1980 ahc_outb(ahc, SCSIOFFSET, offset);
1983 tinfo->scsirate = scsirate;
1984 tinfo->curr.period = period;
1985 tinfo->curr.offset = offset;
1986 tinfo->curr.ppr_options = ppr_options;
1988 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1989 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1992 printf("%s: target %d synchronous at %sMHz%s, "
1993 "offset = 0x%x\n", ahc_name(ahc),
1994 devinfo->target, syncrate->rate,
1995 (ppr_options & MSG_EXT_PPR_DT_REQ)
1996 ? " DT" : "", offset);
1998 printf("%s: target %d using "
1999 "asynchronous transfers\n",
2000 ahc_name(ahc), devinfo->target);
2005 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2006 tinfo, AHC_NEG_TO_GOAL);
2009 ahc_update_pending_scbs(ahc);
2013 * Update the user/goal/curr tables of wide negotiation
2014 * parameters as well as, in the case of a current or active update,
2015 * any data structures on the host controller. In the case of an
2016 * active update, the specified target is currently talking to us on
2017 * the bus, so the transfer parameter update must take effect
2021 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2022 u_int width, u_int type, int paused)
2024 struct ahc_initiator_tinfo *tinfo;
2025 struct ahc_tmode_tstate *tstate;
2030 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2032 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2033 devinfo->target, &tstate);
2035 if ((type & AHC_TRANS_USER) != 0)
2036 tinfo->user.width = width;
2038 if ((type & AHC_TRANS_GOAL) != 0)
2039 tinfo->goal.width = width;
2041 oldwidth = tinfo->curr.width;
2042 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2046 scsirate = tinfo->scsirate;
2047 scsirate &= ~WIDEXFER;
2048 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2049 scsirate |= WIDEXFER;
2051 tinfo->scsirate = scsirate;
2054 ahc_outb(ahc, SCSIRATE, scsirate);
2056 tinfo->curr.width = width;
2058 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2059 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2061 printf("%s: target %d using %dbit transfers\n",
2062 ahc_name(ahc), devinfo->target,
2063 8 * (0x01 << width));
2067 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2068 tinfo, AHC_NEG_TO_GOAL);
2070 ahc_update_pending_scbs(ahc);
2074 * Update the current state of tagged queuing for a given target.
2077 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2080 ahc_platform_set_tags(ahc, devinfo, alg);
2081 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2082 devinfo->lun, AC_TRANSFER_NEG, &alg);
2086 * When the transfer settings for a connection change, update any
2087 * in-transit SCBs to contain the new data so the hardware will
2088 * be set correctly during future (re)selections.
2091 ahc_update_pending_scbs(struct ahc_softc *ahc)
2093 struct scb *pending_scb;
2094 int pending_scb_count;
2100 * Traverse the pending SCB list and ensure that all of the
2101 * SCBs there have the proper settings.
2103 pending_scb_count = 0;
2104 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2105 struct ahc_devinfo devinfo;
2106 struct hardware_scb *pending_hscb;
2107 struct ahc_initiator_tinfo *tinfo;
2108 struct ahc_tmode_tstate *tstate;
2110 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2111 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2113 devinfo.target, &tstate);
2114 pending_hscb = pending_scb->hscb;
2115 pending_hscb->control &= ~ULTRAENB;
2116 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2117 pending_hscb->control |= ULTRAENB;
2118 pending_hscb->scsirate = tinfo->scsirate;
2119 pending_hscb->scsioffset = tinfo->curr.offset;
2120 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2121 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2122 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2123 pending_hscb->control &= ~MK_MESSAGE;
2125 ahc_sync_scb(ahc, pending_scb,
2126 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2127 pending_scb_count++;
2130 if (pending_scb_count == 0)
2133 if (ahc_is_paused(ahc)) {
2140 saved_scbptr = ahc_inb(ahc, SCBPTR);
2141 /* Ensure that the hscbs down on the card match the new information */
2142 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2143 struct hardware_scb *pending_hscb;
2147 ahc_outb(ahc, SCBPTR, i);
2148 scb_tag = ahc_inb(ahc, SCB_TAG);
2149 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2150 if (pending_scb == NULL)
2153 pending_hscb = pending_scb->hscb;
2154 control = ahc_inb(ahc, SCB_CONTROL);
2155 control &= ~(ULTRAENB|MK_MESSAGE);
2156 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2157 ahc_outb(ahc, SCB_CONTROL, control);
2158 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2159 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2161 ahc_outb(ahc, SCBPTR, saved_scbptr);
2167 /**************************** Pathing Information *****************************/
2169 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2175 if (ahc_inb(ahc, SSTAT0) & TARGET)
2178 role = ROLE_INITIATOR;
2180 if (role == ROLE_TARGET
2181 && (ahc->features & AHC_MULTI_TID) != 0
2182 && (ahc_inb(ahc, SEQ_FLAGS)
2183 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2184 /* We were selected, so pull our id from TARGIDIN */
2185 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2186 } else if ((ahc->features & AHC_ULTRA2) != 0)
2187 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2189 our_id = ahc_inb(ahc, SCSIID) & OID;
2191 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2192 ahc_compile_devinfo(devinfo,
2194 SCSIID_TARGET(ahc, saved_scsiid),
2195 ahc_inb(ahc, SAVED_LUN),
2196 SCSIID_CHANNEL(ahc, saved_scsiid),
2200 struct ahc_phase_table_entry*
2201 ahc_lookup_phase_entry(int phase)
2203 struct ahc_phase_table_entry *entry;
2204 struct ahc_phase_table_entry *last_entry;
2207 * num_phases doesn't include the default entry which
2208 * will be returned if the phase doesn't match.
2210 last_entry = &ahc_phase_table[num_phases];
2211 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2212 if (phase == entry->phase)
2219 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2220 u_int lun, char channel, role_t role)
2222 devinfo->our_scsiid = our_id;
2223 devinfo->target = target;
2225 devinfo->target_offset = target;
2226 devinfo->channel = channel;
2227 devinfo->role = role;
2229 devinfo->target_offset += 8;
2230 devinfo->target_mask = (0x01 << devinfo->target_offset);
2234 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2236 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2237 devinfo->target, devinfo->lun);
2241 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2247 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2248 role = ROLE_INITIATOR;
2249 if ((scb->flags & SCB_TARGET_SCB) != 0)
2251 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2252 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2256 /************************ Message Phase Processing ****************************/
2258 ahc_assert_atn(struct ahc_softc *ahc)
2263 if ((ahc->features & AHC_DT) == 0)
2264 scsisigo |= ahc_inb(ahc, SCSISIGI);
2265 ahc_outb(ahc, SCSISIGO, scsisigo);
2269 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2270 * or enters the initial message out phase, we are interrupted. Fill our
2271 * outgoing message buffer with the appropriate message and beging handing
2272 * the message phase(s) manually.
2275 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2279 * To facilitate adding multiple messages together,
2280 * each routine should increment the index and len
2281 * variables instead of setting them explicitly.
2283 ahc->msgout_index = 0;
2284 ahc->msgout_len = 0;
2286 if ((scb->flags & SCB_DEVICE_RESET) == 0
2287 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2290 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2291 if ((scb->hscb->control & DISCENB) != 0)
2292 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2293 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2296 if ((scb->hscb->control & TAG_ENB) != 0) {
2297 ahc->msgout_buf[ahc->msgout_index++] =
2298 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2299 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2300 ahc->msgout_len += 2;
2304 if (scb->flags & SCB_DEVICE_RESET) {
2305 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2307 ahc_print_path(ahc, scb);
2308 printf("Bus Device Reset Message Sent\n");
2310 * Clear our selection hardware in advance of
2311 * the busfree. We may have an entry in the waiting
2312 * Q for this target, and we don't want to go about
2313 * selecting while we handle the busfree and blow it
2316 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2317 } else if ((scb->flags & SCB_ABORT) != 0) {
2318 if ((scb->hscb->control & TAG_ENB) != 0)
2319 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2321 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2323 ahc_print_path(ahc, scb);
2324 printf("Abort%s Message Sent\n",
2325 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2327 * Clear our selection hardware in advance of
2328 * the busfree. We may have an entry in the waiting
2329 * Q for this target, and we don't want to go about
2330 * selecting while we handle the busfree and blow it
2333 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2334 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2335 ahc_build_transfer_msg(ahc, devinfo);
2337 printf("ahc_intr: AWAITING_MSG for an SCB that "
2338 "does not have a waiting message\n");
2339 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2340 devinfo->target_mask);
2341 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2342 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2343 ahc_inb(ahc, MSG_OUT), scb->flags);
2347 * Clear the MK_MESSAGE flag from the SCB so we aren't
2348 * asked to send this message again.
2350 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2351 scb->hscb->control &= ~MK_MESSAGE;
2352 ahc->msgout_index = 0;
2353 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2357 * Build an appropriate transfer negotiation message for the
2358 * currently active target.
2361 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2364 * We need to initiate transfer negotiations.
2365 * If our current and goal settings are identical,
2366 * we want to renegotiate due to a check condition.
2368 struct ahc_initiator_tinfo *tinfo;
2369 struct ahc_tmode_tstate *tstate;
2370 struct ahc_syncrate *rate;
2378 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2379 devinfo->target, &tstate);
2381 * Filter our period based on the current connection.
2382 * If we can't perform DT transfers on this segment (not in LVD
2383 * mode for instance), then our decision to issue a PPR message
2386 period = tinfo->goal.period;
2387 offset = tinfo->goal.offset;
2388 ppr_options = tinfo->goal.ppr_options;
2389 /* Target initiated PPR is not allowed in the SCSI spec */
2390 if (devinfo->role == ROLE_TARGET)
2392 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2393 &ppr_options, devinfo->role);
2394 dowide = tinfo->curr.width != tinfo->goal.width;
2395 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2397 * Only use PPR if we have options that need it, even if the device
2398 * claims to support it. There might be an expander in the way
2401 doppr = ppr_options != 0;
2403 if (!dowide && !dosync && !doppr) {
2404 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2405 dosync = tinfo->goal.offset != 0;
2408 if (!dowide && !dosync && !doppr) {
2410 * Force async with a WDTR message if we have a wide bus,
2411 * or just issue an SDTR with a 0 offset.
2413 if ((ahc->features & AHC_WIDE) != 0)
2419 ahc_print_devinfo(ahc, devinfo);
2420 printf("Ensuring async\n");
2424 /* Target initiated PPR is not allowed in the SCSI spec */
2425 if (devinfo->role == ROLE_TARGET)
2429 * Both the PPR message and SDTR message require the
2430 * goal syncrate to be limited to what the target device
2431 * is capable of handling (based on whether an LVD->SE
2432 * expander is on the bus), so combine these two cases.
2433 * Regardless, guarantee that if we are using WDTR and SDTR
2434 * messages that WDTR comes first.
2436 if (doppr || (dosync && !dowide)) {
2438 offset = tinfo->goal.offset;
2439 ahc_validate_offset(ahc, tinfo, rate, &offset,
2440 doppr ? tinfo->goal.width
2441 : tinfo->curr.width,
2444 ahc_construct_ppr(ahc, devinfo, period, offset,
2445 tinfo->goal.width, ppr_options);
2447 ahc_construct_sdtr(ahc, devinfo, period, offset);
2450 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2455 * Build a synchronous negotiation message in our message
2456 * buffer based on the input parameters.
2459 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2460 u_int period, u_int offset)
2463 period = AHC_ASYNC_XFER_PERIOD;
2464 ahc->msgout_index += spi_populate_sync_msg(
2465 ahc->msgout_buf + ahc->msgout_index, period, offset);
2466 ahc->msgout_len += 5;
2468 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2469 ahc_name(ahc), devinfo->channel, devinfo->target,
2470 devinfo->lun, period, offset);
2475 * Build a wide negotiation message in our message
2476 * buffer based on the input parameters.
2479 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2482 ahc->msgout_index += spi_populate_width_msg(
2483 ahc->msgout_buf + ahc->msgout_index, bus_width);
2484 ahc->msgout_len += 4;
2486 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2487 ahc_name(ahc), devinfo->channel, devinfo->target,
2488 devinfo->lun, bus_width);
2493 * Build a parallel protocol request message in our message
2494 * buffer based on the input parameters.
2497 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2498 u_int period, u_int offset, u_int bus_width,
2502 period = AHC_ASYNC_XFER_PERIOD;
2503 ahc->msgout_index += spi_populate_ppr_msg(
2504 ahc->msgout_buf + ahc->msgout_index, period, offset,
2505 bus_width, ppr_options);
2506 ahc->msgout_len += 8;
2508 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2509 "offset %x, ppr_options %x\n", ahc_name(ahc),
2510 devinfo->channel, devinfo->target, devinfo->lun,
2511 bus_width, period, offset, ppr_options);
2516 * Clear any active message state.
2519 ahc_clear_msg_state(struct ahc_softc *ahc)
2521 ahc->msgout_len = 0;
2522 ahc->msgin_index = 0;
2523 ahc->msg_type = MSG_TYPE_NONE;
2524 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2526 * The target didn't care to respond to our
2527 * message request, so clear ATN.
2529 ahc_outb(ahc, CLRSINT1, CLRATNO);
2531 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2532 ahc_outb(ahc, SEQ_FLAGS2,
2533 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2537 ahc_handle_proto_violation(struct ahc_softc *ahc)
2539 struct ahc_devinfo devinfo;
2547 ahc_fetch_devinfo(ahc, &devinfo);
2548 scbid = ahc_inb(ahc, SCB_TAG);
2549 scb = ahc_lookup_scb(ahc, scbid);
2550 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2551 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2552 lastphase = ahc_inb(ahc, LASTPHASE);
2553 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2556 * The reconnecting target either did not send an
2557 * identify message, or did, but we didn't find an SCB
2560 ahc_print_devinfo(ahc, &devinfo);
2561 printf("Target did not send an IDENTIFY message. "
2562 "LASTPHASE = 0x%x.\n", lastphase);
2564 } else if (scb == NULL) {
2566 * We don't seem to have an SCB active for this
2567 * transaction. Print an error and reset the bus.
2569 ahc_print_devinfo(ahc, &devinfo);
2570 printf("No SCB found during protocol violation\n");
2571 goto proto_violation_reset;
2573 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2574 if ((seq_flags & NO_CDB_SENT) != 0) {
2575 ahc_print_path(ahc, scb);
2576 printf("No or incomplete CDB sent to device.\n");
2577 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2579 * The target never bothered to provide status to
2580 * us prior to completing the command. Since we don't
2581 * know the disposition of this command, we must attempt
2582 * to abort it. Assert ATN and prepare to send an abort
2585 ahc_print_path(ahc, scb);
2586 printf("Completed command without status.\n");
2588 ahc_print_path(ahc, scb);
2589 printf("Unknown protocol violation.\n");
2590 ahc_dump_card_state(ahc);
2593 if ((lastphase & ~P_DATAIN_DT) == 0
2594 || lastphase == P_COMMAND) {
2595 proto_violation_reset:
2597 * Target either went directly to data/command
2598 * phase or didn't respond to our ATN.
2599 * The only safe thing to do is to blow
2600 * it away with a bus reset.
2602 found = ahc_reset_channel(ahc, 'A', TRUE);
2603 printf("%s: Issued Channel %c Bus Reset. "
2604 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2607 * Leave the selection hardware off in case
2608 * this abort attempt will affect yet to
2611 ahc_outb(ahc, SCSISEQ,
2612 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2613 ahc_assert_atn(ahc);
2614 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2616 ahc_print_devinfo(ahc, &devinfo);
2617 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2618 ahc->msgout_len = 1;
2619 ahc->msgout_index = 0;
2620 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2622 ahc_print_path(ahc, scb);
2623 scb->flags |= SCB_ABORT;
2625 printf("Protocol violation %s. Attempting to abort.\n",
2626 ahc_lookup_phase_entry(curphase)->phasemsg);
2631 * Manual message loop handler.
2634 ahc_handle_message_phase(struct ahc_softc *ahc)
2636 struct ahc_devinfo devinfo;
2640 ahc_fetch_devinfo(ahc, &devinfo);
2641 end_session = FALSE;
2642 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2645 switch (ahc->msg_type) {
2646 case MSG_TYPE_INITIATOR_MSGOUT:
2652 if (ahc->msgout_len == 0)
2653 panic("HOST_MSG_LOOP interrupt with no active message");
2656 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2657 ahc_print_devinfo(ahc, &devinfo);
2658 printf("INITIATOR_MSG_OUT");
2661 phasemis = bus_phase != P_MESGOUT;
2664 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2665 printf(" PHASEMIS %s\n",
2666 ahc_lookup_phase_entry(bus_phase)
2670 if (bus_phase == P_MESGIN) {
2672 * Change gears and see if
2673 * this messages is of interest to
2674 * us or should be passed back to
2677 ahc_outb(ahc, CLRSINT1, CLRATNO);
2678 ahc->send_msg_perror = FALSE;
2679 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2680 ahc->msgin_index = 0;
2687 if (ahc->send_msg_perror) {
2688 ahc_outb(ahc, CLRSINT1, CLRATNO);
2689 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2691 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2692 printf(" byte 0x%x\n", ahc->send_msg_perror);
2694 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2698 msgdone = ahc->msgout_index == ahc->msgout_len;
2701 * The target has requested a retry.
2702 * Re-assert ATN, reset our message index to
2705 ahc->msgout_index = 0;
2706 ahc_assert_atn(ahc);
2709 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2711 /* Last byte is signified by dropping ATN */
2712 ahc_outb(ahc, CLRSINT1, CLRATNO);
2716 * Clear our interrupt status and present
2717 * the next byte on the bus.
2719 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2721 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2722 printf(" byte 0x%x\n",
2723 ahc->msgout_buf[ahc->msgout_index]);
2725 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2728 case MSG_TYPE_INITIATOR_MSGIN:
2734 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2735 ahc_print_devinfo(ahc, &devinfo);
2736 printf("INITIATOR_MSG_IN");
2739 phasemis = bus_phase != P_MESGIN;
2742 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2743 printf(" PHASEMIS %s\n",
2744 ahc_lookup_phase_entry(bus_phase)
2748 ahc->msgin_index = 0;
2749 if (bus_phase == P_MESGOUT
2750 && (ahc->send_msg_perror == TRUE
2751 || (ahc->msgout_len != 0
2752 && ahc->msgout_index == 0))) {
2753 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2760 /* Pull the byte in without acking it */
2761 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2763 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2764 printf(" byte 0x%x\n",
2765 ahc->msgin_buf[ahc->msgin_index]);
2768 message_done = ahc_parse_msg(ahc, &devinfo);
2772 * Clear our incoming message buffer in case there
2773 * is another message following this one.
2775 ahc->msgin_index = 0;
2778 * If this message illicited a response,
2779 * assert ATN so the target takes us to the
2780 * message out phase.
2782 if (ahc->msgout_len != 0) {
2784 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2785 ahc_print_devinfo(ahc, &devinfo);
2786 printf("Asserting ATN for response\n");
2789 ahc_assert_atn(ahc);
2794 if (message_done == MSGLOOP_TERMINATED) {
2798 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2799 ahc_inb(ahc, SCSIDATL);
2803 case MSG_TYPE_TARGET_MSGIN:
2808 if (ahc->msgout_len == 0)
2809 panic("Target MSGIN with no active message");
2812 * If we interrupted a mesgout session, the initiator
2813 * will not know this until our first REQ. So, we
2814 * only honor mesgout requests after we've sent our
2817 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2818 && ahc->msgout_index > 0)
2819 msgout_request = TRUE;
2821 msgout_request = FALSE;
2823 if (msgout_request) {
2826 * Change gears and see if
2827 * this messages is of interest to
2828 * us or should be passed back to
2831 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2832 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2833 ahc->msgin_index = 0;
2834 /* Dummy read to REQ for first byte */
2835 ahc_inb(ahc, SCSIDATL);
2836 ahc_outb(ahc, SXFRCTL0,
2837 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2841 msgdone = ahc->msgout_index == ahc->msgout_len;
2843 ahc_outb(ahc, SXFRCTL0,
2844 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2850 * Present the next byte on the bus.
2852 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2853 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2856 case MSG_TYPE_TARGET_MSGOUT:
2862 * The initiator signals that this is
2863 * the last byte by dropping ATN.
2865 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2868 * Read the latched byte, but turn off SPIOEN first
2869 * so that we don't inadvertently cause a REQ for the
2872 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2873 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2874 msgdone = ahc_parse_msg(ahc, &devinfo);
2875 if (msgdone == MSGLOOP_TERMINATED) {
2877 * The message is *really* done in that it caused
2878 * us to go to bus free. The sequencer has already
2879 * been reset at this point, so pull the ejection
2888 * XXX Read spec about initiator dropping ATN too soon
2889 * and use msgdone to detect it.
2891 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2892 ahc->msgin_index = 0;
2895 * If this message illicited a response, transition
2896 * to the Message in phase and send it.
2898 if (ahc->msgout_len != 0) {
2899 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2900 ahc_outb(ahc, SXFRCTL0,
2901 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2902 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2903 ahc->msgin_index = 0;
2911 /* Ask for the next byte. */
2912 ahc_outb(ahc, SXFRCTL0,
2913 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2919 panic("Unknown REQINIT message type");
2923 ahc_clear_msg_state(ahc);
2924 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2926 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2930 * See if we sent a particular extended message to the target.
2931 * If "full" is true, return true only if the target saw the full
2932 * message. If "full" is false, return true if the target saw at
2933 * least the first byte of the message.
2936 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2944 while (index < ahc->msgout_len) {
2945 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2948 end_index = index + 1 + ahc->msgout_buf[index + 1];
2949 if (ahc->msgout_buf[index+2] == msgval
2950 && type == AHCMSG_EXT) {
2953 if (ahc->msgout_index > end_index)
2955 } else if (ahc->msgout_index > index)
2959 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2960 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2962 /* Skip tag type and tag id or residue param*/
2965 /* Single byte message */
2966 if (type == AHCMSG_1B
2967 && ahc->msgout_buf[index] == msgval
2968 && ahc->msgout_index > index)
2980 * Wait for a complete incoming message, parse it, and respond accordingly.
2983 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2985 struct ahc_initiator_tinfo *tinfo;
2986 struct ahc_tmode_tstate *tstate;
2990 u_int targ_scsirate;
2992 done = MSGLOOP_IN_PROG;
2995 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2996 devinfo->target, &tstate);
2997 targ_scsirate = tinfo->scsirate;
3000 * Parse as much of the message as is available,
3001 * rejecting it if we don't support it. When
3002 * the entire message is available and has been
3003 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3004 * that we have parsed an entire message.
3006 * In the case of extended messages, we accept the length
3007 * byte outright and perform more checking once we know the
3008 * extended message type.
3010 switch (ahc->msgin_buf[0]) {
3011 case MSG_DISCONNECT:
3012 case MSG_SAVEDATAPOINTER:
3013 case MSG_CMDCOMPLETE:
3014 case MSG_RESTOREPOINTERS:
3015 case MSG_IGN_WIDE_RESIDUE:
3017 * End our message loop as these are messages
3018 * the sequencer handles on its own.
3020 done = MSGLOOP_TERMINATED;
3022 case MSG_MESSAGE_REJECT:
3023 response = ahc_handle_msg_reject(ahc, devinfo);
3026 done = MSGLOOP_MSGCOMPLETE;
3030 /* Wait for enough of the message to begin validation */
3031 if (ahc->msgin_index < 2)
3033 switch (ahc->msgin_buf[2]) {
3036 struct ahc_syncrate *syncrate;
3042 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3048 * Wait until we have both args before validating
3049 * and acting on this message.
3051 * Add one to MSG_EXT_SDTR_LEN to account for
3052 * the extended message preamble.
3054 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3057 period = ahc->msgin_buf[3];
3059 saved_offset = offset = ahc->msgin_buf[4];
3060 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3063 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3064 targ_scsirate & WIDEXFER,
3067 printf("(%s:%c:%d:%d): Received "
3068 "SDTR period %x, offset %x\n\t"
3069 "Filtered to period %x, offset %x\n",
3070 ahc_name(ahc), devinfo->channel,
3071 devinfo->target, devinfo->lun,
3072 ahc->msgin_buf[3], saved_offset,
3075 ahc_set_syncrate(ahc, devinfo,
3077 offset, ppr_options,
3078 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3082 * See if we initiated Sync Negotiation
3083 * and didn't have to fall down to async
3086 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3088 if (saved_offset != offset) {
3089 /* Went too low - force async */
3094 * Send our own SDTR in reply
3097 && devinfo->role == ROLE_INITIATOR) {
3098 printf("(%s:%c:%d:%d): Target "
3100 ahc_name(ahc), devinfo->channel,
3101 devinfo->target, devinfo->lun);
3103 ahc->msgout_index = 0;
3104 ahc->msgout_len = 0;
3105 ahc_construct_sdtr(ahc, devinfo,
3107 ahc->msgout_index = 0;
3110 done = MSGLOOP_MSGCOMPLETE;
3117 u_int sending_reply;
3119 sending_reply = FALSE;
3120 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3126 * Wait until we have our arg before validating
3127 * and acting on this message.
3129 * Add one to MSG_EXT_WDTR_LEN to account for
3130 * the extended message preamble.
3132 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3135 bus_width = ahc->msgin_buf[3];
3136 saved_width = bus_width;
3137 ahc_validate_width(ahc, tinfo, &bus_width,
3140 printf("(%s:%c:%d:%d): Received WDTR "
3141 "%x filtered to %x\n",
3142 ahc_name(ahc), devinfo->channel,
3143 devinfo->target, devinfo->lun,
3144 saved_width, bus_width);
3147 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3149 * Don't send a WDTR back to the
3150 * target, since we asked first.
3151 * If the width went higher than our
3152 * request, reject it.
3154 if (saved_width > bus_width) {
3156 printf("(%s:%c:%d:%d): requested %dBit "
3157 "transfers. Rejecting...\n",
3158 ahc_name(ahc), devinfo->channel,
3159 devinfo->target, devinfo->lun,
3160 8 * (0x01 << bus_width));
3165 * Send our own WDTR in reply
3168 && devinfo->role == ROLE_INITIATOR) {
3169 printf("(%s:%c:%d:%d): Target "
3171 ahc_name(ahc), devinfo->channel,
3172 devinfo->target, devinfo->lun);
3174 ahc->msgout_index = 0;
3175 ahc->msgout_len = 0;
3176 ahc_construct_wdtr(ahc, devinfo, bus_width);
3177 ahc->msgout_index = 0;
3179 sending_reply = TRUE;
3182 * After a wide message, we are async, but
3183 * some devices don't seem to honor this portion
3184 * of the spec. Force a renegotiation of the
3185 * sync component of our transfer agreement even
3186 * if our goal is async. By updating our width
3187 * after forcing the negotiation, we avoid
3188 * renegotiating for width.
3190 ahc_update_neg_request(ahc, devinfo, tstate,
3191 tinfo, AHC_NEG_ALWAYS);
3192 ahc_set_width(ahc, devinfo, bus_width,
3193 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3195 if (sending_reply == FALSE && reject == FALSE) {
3198 * We will always have an SDTR to send.
3200 ahc->msgout_index = 0;
3201 ahc->msgout_len = 0;
3202 ahc_build_transfer_msg(ahc, devinfo);
3203 ahc->msgout_index = 0;
3206 done = MSGLOOP_MSGCOMPLETE;
3211 struct ahc_syncrate *syncrate;
3218 u_int saved_ppr_options;
3220 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3226 * Wait until we have all args before validating
3227 * and acting on this message.
3229 * Add one to MSG_EXT_PPR_LEN to account for
3230 * the extended message preamble.
3232 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3235 period = ahc->msgin_buf[3];
3236 offset = ahc->msgin_buf[5];
3237 bus_width = ahc->msgin_buf[6];
3238 saved_width = bus_width;
3239 ppr_options = ahc->msgin_buf[7];
3241 * According to the spec, a DT only
3242 * period factor with no DT option
3243 * set implies async.
3245 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3248 saved_ppr_options = ppr_options;
3249 saved_offset = offset;
3252 * Mask out any options we don't support
3253 * on any controller. Transfer options are
3254 * only available if we are negotiating wide.
3256 ppr_options &= MSG_EXT_PPR_DT_REQ;
3260 ahc_validate_width(ahc, tinfo, &bus_width,
3262 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3265 ahc_validate_offset(ahc, tinfo, syncrate,
3269 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3271 * If we are unable to do any of the
3272 * requested options (we went too low),
3273 * then we'll have to reject the message.
3275 if (saved_width > bus_width
3276 || saved_offset != offset
3277 || saved_ppr_options != ppr_options) {
3286 if (devinfo->role != ROLE_TARGET)
3287 printf("(%s:%c:%d:%d): Target "
3289 ahc_name(ahc), devinfo->channel,
3290 devinfo->target, devinfo->lun);
3292 printf("(%s:%c:%d:%d): Initiator "
3294 ahc_name(ahc), devinfo->channel,
3295 devinfo->target, devinfo->lun);
3296 ahc->msgout_index = 0;
3297 ahc->msgout_len = 0;
3298 ahc_construct_ppr(ahc, devinfo, period, offset,
3299 bus_width, ppr_options);
3300 ahc->msgout_index = 0;
3304 printf("(%s:%c:%d:%d): Received PPR width %x, "
3305 "period %x, offset %x,options %x\n"
3306 "\tFiltered to width %x, period %x, "
3307 "offset %x, options %x\n",
3308 ahc_name(ahc), devinfo->channel,
3309 devinfo->target, devinfo->lun,
3310 saved_width, ahc->msgin_buf[3],
3311 saved_offset, saved_ppr_options,
3312 bus_width, period, offset, ppr_options);
3314 ahc_set_width(ahc, devinfo, bus_width,
3315 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3317 ahc_set_syncrate(ahc, devinfo,
3319 offset, ppr_options,
3320 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3322 done = MSGLOOP_MSGCOMPLETE;
3326 /* Unknown extended message. Reject it. */
3332 #ifdef AHC_TARGET_MODE
3333 case MSG_BUS_DEV_RESET:
3334 ahc_handle_devreset(ahc, devinfo,
3336 "Bus Device Reset Received",
3337 /*verbose_level*/0);
3339 done = MSGLOOP_TERMINATED;
3343 case MSG_CLEAR_QUEUE:
3347 /* Target mode messages */
3348 if (devinfo->role != ROLE_TARGET) {
3352 tag = SCB_LIST_NULL;
3353 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3354 tag = ahc_inb(ahc, INITIATOR_TAG);
3355 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3356 devinfo->lun, tag, ROLE_TARGET,
3359 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3360 if (tstate != NULL) {
3361 struct ahc_tmode_lstate* lstate;
3363 lstate = tstate->enabled_luns[devinfo->lun];
3364 if (lstate != NULL) {
3365 ahc_queue_lstate_event(ahc, lstate,
3366 devinfo->our_scsiid,
3369 ahc_send_lstate_events(ahc, lstate);
3373 done = MSGLOOP_TERMINATED;
3377 case MSG_TERM_IO_PROC:
3385 * Setup to reject the message.
3387 ahc->msgout_index = 0;
3388 ahc->msgout_len = 1;
3389 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3390 done = MSGLOOP_MSGCOMPLETE;
3394 if (done != MSGLOOP_IN_PROG && !response)
3395 /* Clear the outgoing message buffer */
3396 ahc->msgout_len = 0;
3402 * Process a message reject message.
3405 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3408 * What we care about here is if we had an
3409 * outstanding SDTR or WDTR message for this
3410 * target. If we did, this is a signal that
3411 * the target is refusing negotiation.
3414 struct ahc_initiator_tinfo *tinfo;
3415 struct ahc_tmode_tstate *tstate;
3420 scb_index = ahc_inb(ahc, SCB_TAG);
3421 scb = ahc_lookup_scb(ahc, scb_index);
3422 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3423 devinfo->our_scsiid,
3424 devinfo->target, &tstate);
3425 /* Might be necessary */
3426 last_msg = ahc_inb(ahc, LAST_MSG);
3428 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3430 * Target does not support the PPR message.
3431 * Attempt to negotiate SPI-2 style.
3434 printf("(%s:%c:%d:%d): PPR Rejected. "
3435 "Trying WDTR/SDTR\n",
3436 ahc_name(ahc), devinfo->channel,
3437 devinfo->target, devinfo->lun);
3439 tinfo->goal.ppr_options = 0;
3440 tinfo->curr.transport_version = 2;
3441 tinfo->goal.transport_version = 2;
3442 ahc->msgout_index = 0;
3443 ahc->msgout_len = 0;
3444 ahc_build_transfer_msg(ahc, devinfo);
3445 ahc->msgout_index = 0;
3447 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3449 /* note 8bit xfers */
3450 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3451 "8bit transfers\n", ahc_name(ahc),
3452 devinfo->channel, devinfo->target, devinfo->lun);
3453 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3454 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3457 * No need to clear the sync rate. If the target
3458 * did not accept the command, our syncrate is
3459 * unaffected. If the target started the negotiation,
3460 * but rejected our response, we already cleared the
3461 * sync rate before sending our WDTR.
3463 if (tinfo->goal.offset != tinfo->curr.offset) {
3465 /* Start the sync negotiation */
3466 ahc->msgout_index = 0;
3467 ahc->msgout_len = 0;
3468 ahc_build_transfer_msg(ahc, devinfo);
3469 ahc->msgout_index = 0;
3472 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3473 /* note asynch xfers and clear flag */
3474 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3475 /*offset*/0, /*ppr_options*/0,
3476 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3478 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3479 "Using asynchronous transfers\n",
3480 ahc_name(ahc), devinfo->channel,
3481 devinfo->target, devinfo->lun);
3482 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3486 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3488 if (tag_type == MSG_SIMPLE_TASK) {
3489 printf("(%s:%c:%d:%d): refuses tagged commands. "
3490 "Performing non-tagged I/O\n", ahc_name(ahc),
3491 devinfo->channel, devinfo->target, devinfo->lun);
3492 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3495 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3496 "Performing simple queue tagged I/O only\n",
3497 ahc_name(ahc), devinfo->channel, devinfo->target,
3498 devinfo->lun, tag_type == MSG_ORDERED_TASK
3499 ? "ordered" : "head of queue");
3500 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3505 * Resend the identify for this CCB as the target
3506 * may believe that the selection is invalid otherwise.
3508 ahc_outb(ahc, SCB_CONTROL,
3509 ahc_inb(ahc, SCB_CONTROL) & mask);
3510 scb->hscb->control &= mask;
3511 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3512 /*type*/MSG_SIMPLE_TASK);
3513 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3514 ahc_assert_atn(ahc);
3517 * This transaction is now at the head of
3518 * the untagged queue for this target.
3520 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3521 struct scb_tailq *untagged_q;
3524 &(ahc->untagged_queues[devinfo->target_offset]);
3525 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3526 scb->flags |= SCB_UNTAGGEDQ;
3528 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3532 * Requeue all tagged commands for this target
3533 * currently in our posession so they can be
3534 * converted to untagged commands.
3536 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3537 SCB_GET_CHANNEL(ahc, scb),
3538 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3539 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3543 * Otherwise, we ignore it.
3545 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3546 ahc_name(ahc), devinfo->channel, devinfo->target,
3553 * Process an ingnore wide residue message.
3556 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3561 scb_index = ahc_inb(ahc, SCB_TAG);
3562 scb = ahc_lookup_scb(ahc, scb_index);
3564 * XXX Actually check data direction in the sequencer?
3565 * Perhaps add datadir to some spare bits in the hscb?
3567 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3568 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3570 * Ignore the message if we haven't
3571 * seen an appropriate data phase yet.
3575 * If the residual occurred on the last
3576 * transfer and the transfer request was
3577 * expected to end on an odd count, do
3578 * nothing. Otherwise, subtract a byte
3579 * and update the residual count accordingly.
3583 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3584 if ((sgptr & SG_LIST_NULL) != 0
3585 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3587 * If the residual occurred on the last
3588 * transfer and the transfer request was
3589 * expected to end on an odd count, do
3593 struct ahc_dma_seg *sg;
3598 /* Pull in all of the sgptr */
3599 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3600 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3602 if ((sgptr & SG_LIST_NULL) != 0) {
3604 * The residual data count is not updated
3605 * for the command run to completion case.
3606 * Explicitly zero the count.
3608 data_cnt &= ~AHC_SG_LEN_MASK;
3611 data_addr = ahc_inl(ahc, SHADDR);
3615 sgptr &= SG_PTR_MASK;
3617 sg = ahc_sg_bus_to_virt(scb, sgptr);
3620 * The residual sg ptr points to the next S/G
3621 * to load so we must go back one.
3624 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3625 if (sg != scb->sg_list
3626 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3629 sglen = ahc_le32toh(sg->len);
3631 * Preserve High Address and SG_LIST bits
3632 * while setting the count to 1.
3634 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3635 data_addr = ahc_le32toh(sg->addr)
3636 + (sglen & AHC_SG_LEN_MASK) - 1;
3639 * Increment sg so it points to the
3643 sgptr = ahc_sg_virt_to_bus(scb, sg);
3645 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3646 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3648 * Toggle the "oddness" of the transfer length
3649 * to handle this mid-transfer ignore wide
3650 * residue. This ensures that the oddness is
3651 * correct for subsequent data transfers.
3653 ahc_outb(ahc, SCB_LUN,
3654 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3661 * Reinitialize the data pointers for the active transfer
3662 * based on its current residual.
3665 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3668 struct ahc_dma_seg *sg;
3674 scb_index = ahc_inb(ahc, SCB_TAG);
3675 scb = ahc_lookup_scb(ahc, scb_index);
3676 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3677 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3678 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3679 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3681 sgptr &= SG_PTR_MASK;
3682 sg = ahc_sg_bus_to_virt(scb, sgptr);
3684 /* The residual sg_ptr always points to the next sg */
3687 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3688 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3689 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3691 dataptr = ahc_le32toh(sg->addr)
3692 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3694 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3697 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3698 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3699 ahc_outb(ahc, HADDR,
3700 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3701 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3703 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3704 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3705 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3706 ahc_outb(ahc, HADDR, dataptr);
3707 ahc_outb(ahc, HCNT + 2, resid >> 16);
3708 ahc_outb(ahc, HCNT + 1, resid >> 8);
3709 ahc_outb(ahc, HCNT, resid);
3710 if ((ahc->features & AHC_ULTRA2) == 0) {
3711 ahc_outb(ahc, STCNT + 2, resid >> 16);
3712 ahc_outb(ahc, STCNT + 1, resid >> 8);
3713 ahc_outb(ahc, STCNT, resid);
3718 * Handle the effects of issuing a bus device reset message.
3721 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3722 cam_status status, char *message, int verbose_level)
3724 #ifdef AHC_TARGET_MODE
3725 struct ahc_tmode_tstate* tstate;
3730 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3731 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3734 #ifdef AHC_TARGET_MODE
3736 * Send an immediate notify ccb to all target mord peripheral
3737 * drivers affected by this action.
3739 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3740 if (tstate != NULL) {
3741 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3742 struct ahc_tmode_lstate* lstate;
3744 lstate = tstate->enabled_luns[lun];
3748 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3749 MSG_BUS_DEV_RESET, /*arg*/0);
3750 ahc_send_lstate_events(ahc, lstate);
3756 * Go back to async/narrow transfers and renegotiate.
3758 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3759 AHC_TRANS_CUR, /*paused*/TRUE);
3760 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3761 /*period*/0, /*offset*/0, /*ppr_options*/0,
3762 AHC_TRANS_CUR, /*paused*/TRUE);
3764 if (status != CAM_SEL_TIMEOUT)
3765 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3766 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3769 && (verbose_level <= bootverbose))
3770 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3771 message, devinfo->channel, devinfo->target, found);
3774 #ifdef AHC_TARGET_MODE
3776 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3781 * To facilitate adding multiple messages together,
3782 * each routine should increment the index and len
3783 * variables instead of setting them explicitly.
3785 ahc->msgout_index = 0;
3786 ahc->msgout_len = 0;
3788 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3789 ahc_build_transfer_msg(ahc, devinfo);
3791 panic("ahc_intr: AWAITING target message with no message");
3793 ahc->msgout_index = 0;
3794 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3797 /**************************** Initialization **********************************/
3799 * Allocate a controller structure for a new device
3800 * and perform initial initializion.
3803 ahc_alloc(void *platform_arg, char *name)
3805 struct ahc_softc *ahc;
3809 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3811 printf("aic7xxx: cannot malloc softc!\n");
3812 free(name, M_DEVBUF);
3816 ahc = device_get_softc((device_t)platform_arg);
3818 memset(ahc, 0, sizeof(*ahc));
3819 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3820 M_DEVBUF, M_NOWAIT);
3821 if (ahc->seep_config == NULL) {
3823 free(ahc, M_DEVBUF);
3825 free(name, M_DEVBUF);
3828 LIST_INIT(&ahc->pending_scbs);
3829 /* We don't know our unit number until the OSM sets it */
3832 ahc->description = NULL;
3834 ahc->channel_b = 'B';
3835 ahc->chip = AHC_NONE;
3836 ahc->features = AHC_FENONE;
3837 ahc->bugs = AHC_BUGNONE;
3838 ahc->flags = AHC_FNONE;
3840 * Default to all error reporting enabled with the
3841 * sequencer operating at its fastest speed.
3842 * The bus attach code may modify this.
3844 ahc->seqctl = FASTMODE;
3846 for (i = 0; i < AHC_NUM_TARGETS; i++)
3847 TAILQ_INIT(&ahc->untagged_queues[i]);
3848 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3856 ahc_softc_init(struct ahc_softc *ahc)
3859 /* The IRQMS bit is only valid on VL and EISA chips */
3860 if ((ahc->chip & AHC_PCI) == 0)
3861 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3864 ahc->pause = ahc->unpause | PAUSE;
3865 /* XXX The shared scb data stuff should be deprecated */
3866 if (ahc->scb_data == NULL) {
3867 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3868 M_DEVBUF, M_NOWAIT);
3869 if (ahc->scb_data == NULL)
3871 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3878 ahc_set_unit(struct ahc_softc *ahc, int unit)
3884 ahc_set_name(struct ahc_softc *ahc, char *name)
3886 if (ahc->name != NULL)
3887 free(ahc->name, M_DEVBUF);
3892 ahc_free(struct ahc_softc *ahc)
3896 switch (ahc->init_level) {
3902 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3903 ahc->shared_data_dmamap);
3906 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3907 ahc->shared_data_dmamap);
3908 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3909 ahc->shared_data_dmamap);
3912 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3915 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3923 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
3925 ahc_platform_free(ahc);
3926 ahc_fini_scbdata(ahc);
3927 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3928 struct ahc_tmode_tstate *tstate;
3930 tstate = ahc->enabled_targets[i];
3931 if (tstate != NULL) {
3932 #ifdef AHC_TARGET_MODE
3935 for (j = 0; j < AHC_NUM_LUNS; j++) {
3936 struct ahc_tmode_lstate *lstate;
3938 lstate = tstate->enabled_luns[j];
3939 if (lstate != NULL) {
3940 xpt_free_path(lstate->path);
3941 free(lstate, M_DEVBUF);
3945 free(tstate, M_DEVBUF);
3948 #ifdef AHC_TARGET_MODE
3949 if (ahc->black_hole != NULL) {
3950 xpt_free_path(ahc->black_hole->path);
3951 free(ahc->black_hole, M_DEVBUF);
3954 if (ahc->name != NULL)
3955 free(ahc->name, M_DEVBUF);
3956 if (ahc->seep_config != NULL)
3957 free(ahc->seep_config, M_DEVBUF);
3959 free(ahc, M_DEVBUF);
3965 ahc_shutdown(void *arg)
3967 struct ahc_softc *ahc;
3970 ahc = (struct ahc_softc *)arg;
3972 /* This will reset most registers to 0, but not all */
3973 ahc_reset(ahc, /*reinit*/FALSE);
3974 ahc_outb(ahc, SCSISEQ, 0);
3975 ahc_outb(ahc, SXFRCTL0, 0);
3976 ahc_outb(ahc, DSPCISTATUS, 0);
3978 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
3979 ahc_outb(ahc, i, 0);
3983 * Reset the controller and record some information about it
3984 * that is only available just after a reset. If "reinit" is
3985 * non-zero, this reset occured after initial configuration
3986 * and the caller requests that the chip be fully reinitialized
3987 * to a runable state. Chip interrupts are *not* enabled after
3988 * a reinitialization. The caller must enable interrupts via
3989 * ahc_intr_enable().
3992 ahc_reset(struct ahc_softc *ahc, int reinit)
3995 u_int sxfrctl1_a, sxfrctl1_b;
4000 * Preserve the value of the SXFRCTL1 register for all channels.
4001 * It contains settings that affect termination and we don't want
4002 * to disturb the integrity of the bus.
4006 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4010 * Save channel B's settings in case this chip
4011 * is setup for TWIN channel operation.
4013 sblkctl = ahc_inb(ahc, SBLKCTL);
4014 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4015 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4016 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4018 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4020 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4023 * Ensure that the reset has finished. We delay 1000us
4024 * prior to reading the register to make sure the chip
4025 * has sufficiently completed its reset to handle register
4031 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4034 printf("%s: WARNING - Failed chip reset! "
4035 "Trying to initialize anyway.\n", ahc_name(ahc));
4037 ahc_outb(ahc, HCNTRL, ahc->pause);
4039 /* Determine channel configuration */
4040 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4041 /* No Twin Channel PCI cards */
4042 if ((ahc->chip & AHC_PCI) != 0)
4043 sblkctl &= ~SELBUSB;
4046 /* Single Narrow Channel */
4050 ahc->features |= AHC_WIDE;
4054 ahc->features |= AHC_TWIN;
4057 printf(" Unsupported adapter type. Ignoring\n");
4064 * We must always initialize STPWEN to 1 before we
4065 * restore the saved values. STPWEN is initialized
4066 * to a tri-state condition which can only be cleared
4069 if ((ahc->features & AHC_TWIN) != 0) {
4072 sblkctl = ahc_inb(ahc, SBLKCTL);
4073 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4074 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4075 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4077 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4082 * If a recovery action has forced a chip reset,
4083 * re-initialize the chip to our liking.
4085 error = ahc->bus_chip_init(ahc);
4095 * Determine the number of SCBs available on the controller
4098 ahc_probe_scbs(struct ahc_softc *ahc) {
4101 for (i = 0; i < AHC_SCB_MAX; i++) {
4103 ahc_outb(ahc, SCBPTR, i);
4104 ahc_outb(ahc, SCB_BASE, i);
4105 if (ahc_inb(ahc, SCB_BASE) != i)
4107 ahc_outb(ahc, SCBPTR, 0);
4108 if (ahc_inb(ahc, SCB_BASE) != 0)
4115 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4119 baddr = (dma_addr_t *)arg;
4120 *baddr = segs->ds_addr;
4124 ahc_build_free_scb_list(struct ahc_softc *ahc)
4130 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4133 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4136 ahc_outb(ahc, SCBPTR, i);
4139 * Touch all SCB bytes to avoid parity errors
4140 * should one of our debugging routines read
4141 * an otherwise uninitiatlized byte.
4143 for (j = 0; j < scbsize; j++)
4144 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4146 /* Clear the control byte. */
4147 ahc_outb(ahc, SCB_CONTROL, 0);
4149 /* Set the next pointer */
4150 if ((ahc->flags & AHC_PAGESCBS) != 0)
4151 ahc_outb(ahc, SCB_NEXT, i+1);
4153 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4155 /* Make the tag number, SCSIID, and lun invalid */
4156 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4157 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4158 ahc_outb(ahc, SCB_LUN, 0xFF);
4161 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4162 /* SCB 0 heads the free list. */
4163 ahc_outb(ahc, FREE_SCBH, 0);
4166 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4169 /* Make sure that the last SCB terminates the free list */
4170 ahc_outb(ahc, SCBPTR, i-1);
4171 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4175 ahc_init_scbdata(struct ahc_softc *ahc)
4177 struct scb_data *scb_data;
4179 scb_data = ahc->scb_data;
4180 SLIST_INIT(&scb_data->free_scbs);
4181 SLIST_INIT(&scb_data->sg_maps);
4183 /* Allocate SCB resources */
4184 scb_data->scbarray =
4185 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4186 M_DEVBUF, M_NOWAIT);
4187 if (scb_data->scbarray == NULL)
4189 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4191 /* Determine the number of hardware SCBs and initialize them */
4193 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4194 if (ahc->scb_data->maxhscbs == 0) {
4195 printf("%s: No SCB space found\n", ahc_name(ahc));
4200 * Create our DMA tags. These tags define the kinds of device
4201 * accessible memory allocations and memory mappings we will
4202 * need to perform during normal operation.
4204 * Unless we need to further restrict the allocation, we rely
4205 * on the restrictions of the parent dmat, hence the common
4206 * use of MAXADDR and MAXSIZE.
4209 /* DMA tag for our hardware scb structures */
4210 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4211 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4212 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4213 /*highaddr*/BUS_SPACE_MAXADDR,
4214 /*filter*/NULL, /*filterarg*/NULL,
4215 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4217 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4218 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4222 scb_data->init_level++;
4224 /* Allocation for our hscbs */
4225 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4226 (void **)&scb_data->hscbs,
4227 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4231 scb_data->init_level++;
4233 /* And permanently map them */
4234 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4236 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4237 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4239 scb_data->init_level++;
4241 /* DMA tag for our sense buffers */
4242 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4243 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4244 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4245 /*highaddr*/BUS_SPACE_MAXADDR,
4246 /*filter*/NULL, /*filterarg*/NULL,
4247 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4249 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4250 /*flags*/0, &scb_data->sense_dmat) != 0) {
4254 scb_data->init_level++;
4257 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4258 (void **)&scb_data->sense,
4259 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4263 scb_data->init_level++;
4265 /* And permanently map them */
4266 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4268 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4269 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4271 scb_data->init_level++;
4273 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4274 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4275 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4276 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4277 /*highaddr*/BUS_SPACE_MAXADDR,
4278 /*filter*/NULL, /*filterarg*/NULL,
4279 PAGE_SIZE, /*nsegments*/1,
4280 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4281 /*flags*/0, &scb_data->sg_dmat) != 0) {
4285 scb_data->init_level++;
4287 /* Perform initial CCB allocation */
4288 memset(scb_data->hscbs, 0,
4289 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4290 ahc_alloc_scbs(ahc);
4292 if (scb_data->numscbs == 0) {
4293 printf("%s: ahc_init_scbdata - "
4294 "Unable to allocate initial scbs\n",
4300 * Reserve the next queued SCB.
4302 ahc->next_queued_scb = ahc_get_scb(ahc);
4305 * Note that we were successfull
4315 ahc_fini_scbdata(struct ahc_softc *ahc)
4317 struct scb_data *scb_data;
4319 scb_data = ahc->scb_data;
4320 if (scb_data == NULL)
4323 switch (scb_data->init_level) {
4327 struct sg_map_node *sg_map;
4329 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4330 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4331 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4333 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4336 free(sg_map, M_DEVBUF);
4338 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4341 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4342 scb_data->sense_dmamap);
4344 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4345 scb_data->sense_dmamap);
4346 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4347 scb_data->sense_dmamap);
4349 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4351 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4352 scb_data->hscb_dmamap);
4354 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4355 scb_data->hscb_dmamap);
4356 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4357 scb_data->hscb_dmamap);
4359 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4364 if (scb_data->scbarray != NULL)
4365 free(scb_data->scbarray, M_DEVBUF);
4369 ahc_alloc_scbs(struct ahc_softc *ahc)
4371 struct scb_data *scb_data;
4372 struct scb *next_scb;
4373 struct sg_map_node *sg_map;
4374 dma_addr_t physaddr;
4375 struct ahc_dma_seg *segs;
4379 scb_data = ahc->scb_data;
4380 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4381 /* Can't allocate any more */
4384 next_scb = &scb_data->scbarray[scb_data->numscbs];
4386 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4391 /* Allocate S/G space for the next batch of SCBS */
4392 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4393 (void **)&sg_map->sg_vaddr,
4394 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4395 free(sg_map, M_DEVBUF);
4399 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4401 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4402 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4403 &sg_map->sg_physaddr, /*flags*/0);
4405 segs = sg_map->sg_vaddr;
4406 physaddr = sg_map->sg_physaddr;
4408 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4409 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4410 for (i = 0; i < newcount; i++) {
4411 struct scb_platform_data *pdata;
4415 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4416 M_DEVBUF, M_NOWAIT);
4419 next_scb->platform_data = pdata;
4420 next_scb->sg_map = sg_map;
4421 next_scb->sg_list = segs;
4423 * The sequencer always starts with the second entry.
4424 * The first entry is embedded in the scb.
4426 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4427 next_scb->ahc_softc = ahc;
4428 next_scb->flags = SCB_FREE;
4430 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4435 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4436 next_scb->hscb->tag = ahc->scb_data->numscbs;
4437 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4438 next_scb, links.sle);
4440 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4442 ahc->scb_data->numscbs++;
4447 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4451 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4453 if ((ahc->features & AHC_TWIN) != 0)
4454 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4455 "B SCSI Id=%d, primary %c, ",
4456 ahc->our_id, ahc->our_id_b,
4457 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4463 if ((ahc->features & AHC_ULTRA) != 0) {
4465 } else if ((ahc->features & AHC_DT) != 0) {
4466 speed = "Ultra160 ";
4467 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4470 if ((ahc->features & AHC_WIDE) != 0) {
4475 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4476 speed, type, ahc->channel, ahc->our_id);
4480 if ((ahc->flags & AHC_PAGESCBS) != 0)
4481 sprintf(buf, "%d/%d SCBs",
4482 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4484 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4488 ahc_chip_init(struct ahc_softc *ahc)
4494 u_int scsiseq_template;
4497 ahc_outb(ahc, SEQ_FLAGS, 0);
4498 ahc_outb(ahc, SEQ_FLAGS2, 0);
4500 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4501 if (ahc->features & AHC_TWIN) {
4504 * Setup Channel B first.
4506 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4507 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4508 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4509 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4510 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4511 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4512 if ((ahc->features & AHC_ULTRA2) != 0)
4513 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4514 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4515 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4517 /* Select Channel A */
4518 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4520 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4521 if ((ahc->features & AHC_ULTRA2) != 0)
4522 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4524 ahc_outb(ahc, SCSIID, ahc->our_id);
4525 scsi_conf = ahc_inb(ahc, SCSICONF);
4526 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4528 |ENSTIMER|ACTNEGEN);
4529 if ((ahc->features & AHC_ULTRA2) != 0)
4530 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4531 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4532 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4534 /* There are no untagged SCBs active yet. */
4535 for (i = 0; i < 16; i++) {
4536 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4537 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4541 * The SCB based BTT allows an entry per
4542 * target and lun pair.
4544 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4545 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4549 /* All of our queues are empty */
4550 for (i = 0; i < 256; i++)
4551 ahc->qoutfifo[i] = SCB_LIST_NULL;
4552 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4554 for (i = 0; i < 256; i++)
4555 ahc->qinfifo[i] = SCB_LIST_NULL;
4557 if ((ahc->features & AHC_MULTI_TID) != 0) {
4558 ahc_outb(ahc, TARGID, 0);
4559 ahc_outb(ahc, TARGID + 1, 0);
4563 * Tell the sequencer where it can find our arrays in memory.
4565 physaddr = ahc->scb_data->hscb_busaddr;
4566 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4567 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4568 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4569 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4571 physaddr = ahc->shared_data_busaddr;
4572 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4573 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4574 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4575 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4578 * Initialize the group code to command length table.
4579 * This overrides the values in TARG_SCSIRATE, so only
4580 * setup the table after we have processed that information.
4582 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4583 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4584 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4585 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4586 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4587 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4588 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4589 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4591 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4592 ahc_outb(ahc, HS_MAILBOX, 0);
4594 /* Tell the sequencer of our initial queue positions */
4595 if ((ahc->features & AHC_TARGETMODE) != 0) {
4596 ahc->tqinfifonext = 1;
4597 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4598 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4600 ahc->qinfifonext = 0;
4601 ahc->qoutfifonext = 0;
4602 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4603 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4604 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4605 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4606 ahc_outb(ahc, SDSCB_QOFF, 0);
4608 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4609 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4610 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4613 /* We don't have any waiting selections */
4614 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4616 /* Our disconnection list is empty too */
4617 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4619 /* Message out buffer starts empty */
4620 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4623 * Setup the allowed SCSI Sequences based on operational mode.
4624 * If we are a target, we'll enalbe select in operations once
4625 * we've had a lun enabled.
4627 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4628 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4629 scsiseq_template |= ENRSELI;
4630 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4632 /* Initialize our list of free SCBs. */
4633 ahc_build_free_scb_list(ahc);
4636 * Tell the sequencer which SCB will be the next one it receives.
4638 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4641 * Load the Sequencer program and Enable the adapter
4645 printf("%s: Downloading Sequencer Program...",
4648 error = ahc_loadseq(ahc);
4652 if ((ahc->features & AHC_ULTRA2) != 0) {
4656 * Wait for up to 500ms for our transceivers
4657 * to settle. If the adapter does not have
4658 * a cable attached, the transceivers may
4659 * never settle, so don't complain if we
4663 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4672 * Start the board, ready for normal operation
4675 ahc_init(struct ahc_softc *ahc)
4683 size_t driver_data_size;
4686 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4687 ahc->flags |= AHC_SEQUENCER_DEBUG;
4690 #ifdef AHC_PRINT_SRAM
4691 printf("Scratch Ram:");
4692 for (i = 0x20; i < 0x5f; i++) {
4693 if (((i % 8) == 0) && (i != 0)) {
4696 printf (" 0x%x", ahc_inb(ahc, i));
4698 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4699 for (i = 0x70; i < 0x7f; i++) {
4700 if (((i % 8) == 0) && (i != 0)) {
4703 printf (" 0x%x", ahc_inb(ahc, i));
4708 * Reading uninitialized scratch ram may
4709 * generate parity errors.
4711 ahc_outb(ahc, CLRINT, CLRPARERR);
4712 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4717 * Assume we have a board at this stage and it has been reset.
4719 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4720 ahc->our_id = ahc->our_id_b = 7;
4723 * Default to allowing initiator operations.
4725 ahc->flags |= AHC_INITIATORROLE;
4728 * Only allow target mode features if this unit has them enabled.
4730 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4731 ahc->features &= ~AHC_TARGETMODE;
4734 /* DMA tag for mapping buffers into device visible space. */
4735 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4736 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4737 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4738 ? (dma_addr_t)0x7FFFFFFFFFULL
4739 : BUS_SPACE_MAXADDR_32BIT,
4740 /*highaddr*/BUS_SPACE_MAXADDR,
4741 /*filter*/NULL, /*filterarg*/NULL,
4742 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4743 /*nsegments*/AHC_NSEG,
4744 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4745 /*flags*/BUS_DMA_ALLOCNOW,
4746 &ahc->buffer_dmat) != 0) {
4754 * DMA tag for our command fifos and other data in system memory
4755 * the card's sequencer must be able to access. For initiator
4756 * roles, we need to allocate space for the qinfifo and qoutfifo.
4757 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4758 * When providing for the target mode role, we must additionally
4759 * provide space for the incoming target command fifo and an extra
4760 * byte to deal with a dma bug in some chip versions.
4762 driver_data_size = 2 * 256 * sizeof(uint8_t);
4763 if ((ahc->features & AHC_TARGETMODE) != 0)
4764 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4765 + /*DMA WideOdd Bug Buffer*/1;
4766 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4767 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4768 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4769 /*highaddr*/BUS_SPACE_MAXADDR,
4770 /*filter*/NULL, /*filterarg*/NULL,
4773 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4774 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4780 /* Allocation of driver data */
4781 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4782 (void **)&ahc->qoutfifo,
4783 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4789 /* And permanently map it in */
4790 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4791 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4792 &ahc->shared_data_busaddr, /*flags*/0);
4794 if ((ahc->features & AHC_TARGETMODE) != 0) {
4795 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4796 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4797 ahc->dma_bug_buf = ahc->shared_data_busaddr
4798 + driver_data_size - 1;
4799 /* All target command blocks start out invalid. */
4800 for (i = 0; i < AHC_TMODE_CMDS; i++)
4801 ahc->targetcmds[i].cmd_valid = 0;
4802 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4803 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4805 ahc->qinfifo = &ahc->qoutfifo[256];
4809 /* Allocate SCB data now that buffer_dmat is initialized */
4810 if (ahc->scb_data->maxhscbs == 0)
4811 if (ahc_init_scbdata(ahc) != 0)
4815 * Allocate a tstate to house information for our
4816 * initiator presence on the bus as well as the user
4817 * data for any target mode initiator.
4819 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4820 printf("%s: unable to allocate ahc_tmode_tstate. "
4821 "Failing attach\n", ahc_name(ahc));
4825 if ((ahc->features & AHC_TWIN) != 0) {
4826 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4827 printf("%s: unable to allocate ahc_tmode_tstate. "
4828 "Failing attach\n", ahc_name(ahc));
4833 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4834 ahc->flags |= AHC_PAGESCBS;
4836 ahc->flags &= ~AHC_PAGESCBS;
4840 if (ahc_debug & AHC_SHOW_MISC) {
4841 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4842 "ahc_dma %u bytes\n",
4844 (u_int)sizeof(struct hardware_scb),
4845 (u_int)sizeof(struct scb),
4846 (u_int)sizeof(struct ahc_dma_seg));
4848 #endif /* AHC_DEBUG */
4851 * Look at the information that board initialization or
4852 * the board bios has left us.
4854 if (ahc->features & AHC_TWIN) {
4855 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4856 if ((scsi_conf & RESET_SCSI) != 0
4857 && (ahc->flags & AHC_INITIATORROLE) != 0)
4858 ahc->flags |= AHC_RESET_BUS_B;
4861 scsi_conf = ahc_inb(ahc, SCSICONF);
4862 if ((scsi_conf & RESET_SCSI) != 0
4863 && (ahc->flags & AHC_INITIATORROLE) != 0)
4864 ahc->flags |= AHC_RESET_BUS_A;
4867 tagenable = ALL_TARGETS_MASK;
4869 /* Grab the disconnection disable table and invert it for our needs */
4870 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4871 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4872 "device parameters\n", ahc_name(ahc));
4873 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4874 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4875 discenable = ALL_TARGETS_MASK;
4876 if ((ahc->features & AHC_ULTRA) != 0)
4877 ultraenb = ALL_TARGETS_MASK;
4879 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4880 | ahc_inb(ahc, DISC_DSB));
4881 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4882 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4883 | ahc_inb(ahc, ULTRA_ENB);
4886 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4889 for (i = 0; i <= max_targ; i++) {
4890 struct ahc_initiator_tinfo *tinfo;
4891 struct ahc_tmode_tstate *tstate;
4897 our_id = ahc->our_id;
4899 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4901 our_id = ahc->our_id_b;
4904 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4905 target_id, &tstate);
4906 /* Default to async narrow across the board */
4907 memset(tinfo, 0, sizeof(*tinfo));
4908 if (ahc->flags & AHC_USEDEFAULTS) {
4909 if ((ahc->features & AHC_WIDE) != 0)
4910 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4913 * These will be truncated when we determine the
4914 * connection type we have with the target.
4916 tinfo->user.period = ahc_syncrates->period;
4917 tinfo->user.offset = MAX_OFFSET;
4922 /* Take the settings leftover in scratch RAM. */
4923 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4925 if ((ahc->features & AHC_ULTRA2) != 0) {
4929 if ((scsirate & SOFS) == 0x0F) {
4931 * Haven't negotiated yet,
4932 * so the format is different.
4934 scsirate = (scsirate & SXFR) >> 4
4937 | (scsirate & WIDEXFER);
4938 offset = MAX_OFFSET_ULTRA2;
4940 offset = ahc_inb(ahc, TARG_OFFSET + i);
4941 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4942 /* Set to the lowest sync rate, 5MHz */
4944 maxsync = AHC_SYNCRATE_ULTRA2;
4945 if ((ahc->features & AHC_DT) != 0)
4946 maxsync = AHC_SYNCRATE_DT;
4947 tinfo->user.period =
4948 ahc_find_period(ahc, scsirate, maxsync);
4950 tinfo->user.period = 0;
4952 tinfo->user.offset = MAX_OFFSET;
4953 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4954 && (ahc->features & AHC_DT) != 0)
4955 tinfo->user.ppr_options =
4957 } else if ((scsirate & SOFS) != 0) {
4958 if ((scsirate & SXFR) == 0x40
4959 && (ultraenb & mask) != 0) {
4960 /* Treat 10MHz as a non-ultra speed */
4964 tinfo->user.period =
4965 ahc_find_period(ahc, scsirate,
4967 ? AHC_SYNCRATE_ULTRA
4968 : AHC_SYNCRATE_FAST);
4969 if (tinfo->user.period != 0)
4970 tinfo->user.offset = MAX_OFFSET;
4972 if (tinfo->user.period == 0)
4973 tinfo->user.offset = 0;
4974 if ((scsirate & WIDEXFER) != 0
4975 && (ahc->features & AHC_WIDE) != 0)
4976 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4977 tinfo->user.protocol_version = 4;
4978 if ((ahc->features & AHC_DT) != 0)
4979 tinfo->user.transport_version = 3;
4981 tinfo->user.transport_version = 2;
4982 tinfo->goal.protocol_version = 2;
4983 tinfo->goal.transport_version = 2;
4984 tinfo->curr.protocol_version = 2;
4985 tinfo->curr.transport_version = 2;
4987 tstate->ultraenb = 0;
4989 ahc->user_discenable = discenable;
4990 ahc->user_tagenable = tagenable;
4992 return (ahc->bus_chip_init(ahc));
4996 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5000 hcntrl = ahc_inb(ahc, HCNTRL);
5002 ahc->pause &= ~INTEN;
5003 ahc->unpause &= ~INTEN;
5006 ahc->pause |= INTEN;
5007 ahc->unpause |= INTEN;
5009 ahc_outb(ahc, HCNTRL, hcntrl);
5013 * Ensure that the card is paused in a location
5014 * outside of all critical sections and that all
5015 * pending work is completed prior to returning.
5016 * This routine should only be called from outside
5017 * an interrupt context.
5020 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5027 ahc->flags |= AHC_ALL_INTERRUPTS;
5033 * Give the sequencer some time to service
5034 * any active selections.
5041 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5042 intstat = ahc_inb(ahc, INTSTAT);
5043 if ((intstat & INT_PEND) == 0) {
5044 ahc_clear_critical_section(ahc);
5045 intstat = ahc_inb(ahc, INTSTAT);
5048 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5049 && ((intstat & INT_PEND) != 0
5050 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5051 if (maxloops == 0) {
5052 printf("Infinite interrupt loop, INTSTAT = %x",
5053 ahc_inb(ahc, INTSTAT));
5055 ahc_platform_flushwork(ahc);
5056 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5060 ahc_suspend(struct ahc_softc *ahc)
5063 ahc_pause_and_flushwork(ahc);
5065 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5070 #ifdef AHC_TARGET_MODE
5072 * XXX What about ATIOs that have not yet been serviced?
5073 * Perhaps we should just refuse to be suspended if we
5074 * are acting in a target role.
5076 if (ahc->pending_device != NULL) {
5086 ahc_resume(struct ahc_softc *ahc)
5089 ahc_reset(ahc, /*reinit*/TRUE);
5090 ahc_intr_enable(ahc, TRUE);
5095 /************************** Busy Target Table *********************************/
5097 * Return the untagged transaction id for a given target/channel lun.
5098 * Optionally, clear the entry.
5101 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5104 u_int target_offset;
5106 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5109 saved_scbptr = ahc_inb(ahc, SCBPTR);
5110 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5111 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5112 ahc_outb(ahc, SCBPTR, saved_scbptr);
5114 target_offset = TCL_TARGET_OFFSET(tcl);
5115 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5122 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5124 u_int target_offset;
5126 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5129 saved_scbptr = ahc_inb(ahc, SCBPTR);
5130 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5131 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5132 ahc_outb(ahc, SCBPTR, saved_scbptr);
5134 target_offset = TCL_TARGET_OFFSET(tcl);
5135 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5140 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5142 u_int target_offset;
5144 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5147 saved_scbptr = ahc_inb(ahc, SCBPTR);
5148 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5149 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5150 ahc_outb(ahc, SCBPTR, saved_scbptr);
5152 target_offset = TCL_TARGET_OFFSET(tcl);
5153 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5157 /************************** SCB and SCB queue management **********************/
5159 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5160 char channel, int lun, u_int tag, role_t role)
5162 int targ = SCB_GET_TARGET(ahc, scb);
5163 char chan = SCB_GET_CHANNEL(ahc, scb);
5164 int slun = SCB_GET_LUN(scb);
5167 match = ((chan == channel) || (channel == ALL_CHANNELS));
5169 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5171 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5173 #ifdef AHC_TARGET_MODE
5176 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5177 if (role == ROLE_INITIATOR) {
5178 match = (group != XPT_FC_GROUP_TMODE)
5179 && ((tag == scb->hscb->tag)
5180 || (tag == SCB_LIST_NULL));
5181 } else if (role == ROLE_TARGET) {
5182 match = (group == XPT_FC_GROUP_TMODE)
5183 && ((tag == scb->io_ctx->csio.tag_id)
5184 || (tag == SCB_LIST_NULL));
5186 #else /* !AHC_TARGET_MODE */
5187 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5188 #endif /* AHC_TARGET_MODE */
5195 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5201 target = SCB_GET_TARGET(ahc, scb);
5202 lun = SCB_GET_LUN(scb);
5203 channel = SCB_GET_CHANNEL(ahc, scb);
5205 ahc_search_qinfifo(ahc, target, channel, lun,
5206 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5207 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5209 ahc_platform_freeze_devq(ahc, scb);
5213 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5215 struct scb *prev_scb;
5218 if (ahc_qinfifo_count(ahc) != 0) {
5222 prev_pos = ahc->qinfifonext - 1;
5223 prev_tag = ahc->qinfifo[prev_pos];
5224 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5226 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5227 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5228 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5230 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5235 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5238 if (prev_scb == NULL) {
5239 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5241 prev_scb->hscb->next = scb->hscb->tag;
5242 ahc_sync_scb(ahc, prev_scb,
5243 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5245 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5246 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5247 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5251 ahc_qinfifo_count(struct ahc_softc *ahc)
5256 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5257 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5258 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5260 qinpos = ahc_inb(ahc, QINPOS);
5261 diff = ahc->qinfifonext - qinpos;
5266 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5267 int lun, u_int tag, role_t role, uint32_t status,
5268 ahc_search_action action)
5271 struct scb *prev_scb;
5281 qintail = ahc->qinfifonext;
5282 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5284 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5285 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5287 qinstart = ahc_inb(ahc, QINPOS);
5292 if (action == SEARCH_COMPLETE) {
5294 * Don't attempt to run any queued untagged transactions
5295 * until we are done with the abort process.
5297 ahc_freeze_untagged_queues(ahc);
5301 * Start with an empty queue. Entries that are not chosen
5302 * for removal will be re-added to the queue as we go.
5304 ahc->qinfifonext = qinpos;
5305 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5307 while (qinpos != qintail) {
5308 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5310 printf("qinpos = %d, SCB index = %d\n",
5311 qinpos, ahc->qinfifo[qinpos]);
5315 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5317 * We found an scb that needs to be acted on.
5321 case SEARCH_COMPLETE:
5326 ostat = ahc_get_transaction_status(scb);
5327 if (ostat == CAM_REQ_INPROG)
5328 ahc_set_transaction_status(scb, status);
5329 cstat = ahc_get_transaction_status(scb);
5330 if (cstat != CAM_REQ_CMP)
5331 ahc_freeze_scb(scb);
5332 if ((scb->flags & SCB_ACTIVE) == 0)
5333 printf("Inactive SCB in qinfifo\n");
5341 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5346 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5352 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5353 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5355 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5358 if (action != SEARCH_COUNT
5360 && (qinstart != ahc->qinfifonext)) {
5362 * The sequencer may be in the process of dmaing
5363 * down the SCB at the beginning of the queue.
5364 * This could be problematic if either the first,
5365 * or the second SCB is removed from the queue
5366 * (the first SCB includes a pointer to the "next"
5367 * SCB to dma). If we have removed any entries, swap
5368 * the first element in the queue with the next HSCB
5369 * so the sequencer will notice that NEXT_QUEUED_SCB
5370 * has changed during its dma attempt and will retry
5373 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5376 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5377 found, qinstart, ahc->qinfifonext);
5378 panic("First/Second Qinfifo fixup\n");
5381 * ahc_swap_with_next_hscb forces our next pointer to
5382 * point to the reserved SCB for future commands. Save
5383 * and restore our original next pointer to maintain
5386 next = scb->hscb->next;
5387 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5388 ahc_swap_with_next_hscb(ahc, scb);
5389 scb->hscb->next = next;
5390 ahc->qinfifo[qinstart] = scb->hscb->tag;
5392 /* Tell the card about the new head of the qinfifo. */
5393 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5395 /* Fixup the tail "next" pointer. */
5396 qintail = ahc->qinfifonext - 1;
5397 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5398 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5402 * Search waiting for selection list.
5404 curscbptr = ahc_inb(ahc, SCBPTR);
5405 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5406 prev = SCB_LIST_NULL;
5408 while (next != SCB_LIST_NULL) {
5411 ahc_outb(ahc, SCBPTR, next);
5412 scb_index = ahc_inb(ahc, SCB_TAG);
5413 if (scb_index >= ahc->scb_data->numscbs) {
5414 printf("Waiting List inconsistency. "
5415 "SCB index == %d, yet numscbs == %d.",
5416 scb_index, ahc->scb_data->numscbs);
5417 ahc_dump_card_state(ahc);
5418 panic("for safety");
5420 scb = ahc_lookup_scb(ahc, scb_index);
5422 printf("scb_index = %d, next = %d\n",
5424 panic("Waiting List traversal\n");
5426 if (ahc_match_scb(ahc, scb, target, channel,
5427 lun, SCB_LIST_NULL, role)) {
5429 * We found an scb that needs to be acted on.
5433 case SEARCH_COMPLETE:
5438 ostat = ahc_get_transaction_status(scb);
5439 if (ostat == CAM_REQ_INPROG)
5440 ahc_set_transaction_status(scb,
5442 cstat = ahc_get_transaction_status(scb);
5443 if (cstat != CAM_REQ_CMP)
5444 ahc_freeze_scb(scb);
5445 if ((scb->flags & SCB_ACTIVE) == 0)
5446 printf("Inactive SCB in Waiting List\n");
5451 next = ahc_rem_wscb(ahc, next, prev);
5455 next = ahc_inb(ahc, SCB_NEXT);
5461 next = ahc_inb(ahc, SCB_NEXT);
5464 ahc_outb(ahc, SCBPTR, curscbptr);
5466 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5467 channel, lun, status, action);
5469 if (action == SEARCH_COMPLETE)
5470 ahc_release_untagged_queues(ahc);
5475 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5476 int target, char channel, int lun, uint32_t status,
5477 ahc_search_action action)
5484 if (action == SEARCH_COMPLETE) {
5486 * Don't attempt to run any queued untagged transactions
5487 * until we are done with the abort process.
5489 ahc_freeze_untagged_queues(ahc);
5494 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5497 if (target != CAM_TARGET_WILDCARD) {
5508 for (; i < maxtarget; i++) {
5509 struct scb_tailq *untagged_q;
5510 struct scb *next_scb;
5512 untagged_q = &(ahc->untagged_queues[i]);
5513 next_scb = TAILQ_FIRST(untagged_q);
5514 while (next_scb != NULL) {
5517 next_scb = TAILQ_NEXT(scb, links.tqe);
5520 * The head of the list may be the currently
5521 * active untagged command for a device.
5522 * We're only searching for commands that
5523 * have not been started. A transaction
5524 * marked active but still in the qinfifo
5525 * is removed by the qinfifo scanning code
5528 if ((scb->flags & SCB_ACTIVE) != 0)
5531 if (ahc_match_scb(ahc, scb, target, channel, lun,
5532 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5533 || (ctx != NULL && ctx != scb->io_ctx))
5537 * We found an scb that needs to be acted on.
5541 case SEARCH_COMPLETE:
5546 ostat = ahc_get_transaction_status(scb);
5547 if (ostat == CAM_REQ_INPROG)
5548 ahc_set_transaction_status(scb, status);
5549 cstat = ahc_get_transaction_status(scb);
5550 if (cstat != CAM_REQ_CMP)
5551 ahc_freeze_scb(scb);
5552 if ((scb->flags & SCB_ACTIVE) == 0)
5553 printf("Inactive SCB in untaggedQ\n");
5558 scb->flags &= ~SCB_UNTAGGEDQ;
5559 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5567 if (action == SEARCH_COMPLETE)
5568 ahc_release_untagged_queues(ahc);
5573 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5574 int lun, u_int tag, int stop_on_first, int remove,
5584 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5585 prev = SCB_LIST_NULL;
5588 /* restore this when we're done */
5589 active_scb = ahc_inb(ahc, SCBPTR);
5591 /* Silence compiler */
5592 active_scb = SCB_LIST_NULL;
5594 while (next != SCB_LIST_NULL) {
5597 ahc_outb(ahc, SCBPTR, next);
5598 scb_index = ahc_inb(ahc, SCB_TAG);
5599 if (scb_index >= ahc->scb_data->numscbs) {
5600 printf("Disconnected List inconsistency. "
5601 "SCB index == %d, yet numscbs == %d.",
5602 scb_index, ahc->scb_data->numscbs);
5603 ahc_dump_card_state(ahc);
5604 panic("for safety");
5608 panic("Disconnected List Loop. "
5609 "cur SCBPTR == %x, prev SCBPTR == %x.",
5612 scbp = ahc_lookup_scb(ahc, scb_index);
5613 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5614 tag, ROLE_INITIATOR)) {
5618 ahc_rem_scb_from_disc_list(ahc, prev, next);
5621 next = ahc_inb(ahc, SCB_NEXT);
5627 next = ahc_inb(ahc, SCB_NEXT);
5631 ahc_outb(ahc, SCBPTR, active_scb);
5636 * Remove an SCB from the on chip list of disconnected transactions.
5637 * This is empty/unused if we are not performing SCB paging.
5640 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5644 ahc_outb(ahc, SCBPTR, scbptr);
5645 next = ahc_inb(ahc, SCB_NEXT);
5647 ahc_outb(ahc, SCB_CONTROL, 0);
5649 ahc_add_curscb_to_free_list(ahc);
5651 if (prev != SCB_LIST_NULL) {
5652 ahc_outb(ahc, SCBPTR, prev);
5653 ahc_outb(ahc, SCB_NEXT, next);
5655 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5661 * Add the SCB as selected by SCBPTR onto the on chip list of
5662 * free hardware SCBs. This list is empty/unused if we are not
5663 * performing SCB paging.
5666 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5669 * Invalidate the tag so that our abort
5670 * routines don't think it's active.
5672 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5674 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5675 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5676 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5681 * Manipulate the waiting for selection list and return the
5682 * scb that follows the one that we remove.
5685 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5690 * Select the SCB we want to abort and
5691 * pull the next pointer out of it.
5693 curscb = ahc_inb(ahc, SCBPTR);
5694 ahc_outb(ahc, SCBPTR, scbpos);
5695 next = ahc_inb(ahc, SCB_NEXT);
5697 /* Clear the necessary fields */
5698 ahc_outb(ahc, SCB_CONTROL, 0);
5700 ahc_add_curscb_to_free_list(ahc);
5702 /* update the waiting list */
5703 if (prev == SCB_LIST_NULL) {
5704 /* First in the list */
5705 ahc_outb(ahc, WAITING_SCBH, next);
5708 * Ensure we aren't attempting to perform
5709 * selection for this entry.
5711 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5714 * Select the scb that pointed to us
5715 * and update its next pointer.
5717 ahc_outb(ahc, SCBPTR, prev);
5718 ahc_outb(ahc, SCB_NEXT, next);
5722 * Point us back at the original scb position.
5724 ahc_outb(ahc, SCBPTR, curscb);
5728 /******************************** Error Handling ******************************/
5730 * Abort all SCBs that match the given description (target/channel/lun/tag),
5731 * setting their status to the passed in status if the status has not already
5732 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5733 * is paused before it is called.
5736 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5737 int lun, u_int tag, role_t role, uint32_t status)
5740 struct scb *scbp_next;
5750 * Don't attempt to run any queued untagged transactions
5751 * until we are done with the abort process.
5753 ahc_freeze_untagged_queues(ahc);
5755 /* restore this when we're done */
5756 active_scb = ahc_inb(ahc, SCBPTR);
5758 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5759 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5762 * Clean out the busy target table for any untagged commands.
5766 if (target != CAM_TARGET_WILDCARD) {
5773 if (lun == CAM_LUN_WILDCARD) {
5776 * Unless we are using an SCB based
5777 * busy targets table, there is only
5778 * one table entry for all luns of
5783 if ((ahc->flags & AHC_SCB_BTT) != 0)
5784 maxlun = AHC_NUM_LUNS;
5790 if (role != ROLE_TARGET) {
5791 for (;i < maxtarget; i++) {
5792 for (j = minlun;j < maxlun; j++) {
5796 tcl = BUILD_TCL(i << 4, j);
5797 scbid = ahc_index_busy_tcl(ahc, tcl);
5798 scbp = ahc_lookup_scb(ahc, scbid);
5800 || ahc_match_scb(ahc, scbp, target, channel,
5801 lun, tag, role) == 0)
5803 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5808 * Go through the disconnected list and remove any entries we
5809 * have queued for completion, 0'ing their control byte too.
5810 * We save the active SCB and restore it ourselves, so there
5811 * is no reason for this search to restore it too.
5813 ahc_search_disc_list(ahc, target, channel, lun, tag,
5814 /*stop_on_first*/FALSE, /*remove*/TRUE,
5815 /*save_state*/FALSE);
5819 * Go through the hardware SCB array looking for commands that
5820 * were active but not on any list. In some cases, these remnants
5821 * might not still have mappings in the scbindex array (e.g. unexpected
5822 * bus free with the same scb queued for an abort). Don't hold this
5825 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5828 ahc_outb(ahc, SCBPTR, i);
5829 scbid = ahc_inb(ahc, SCB_TAG);
5830 scbp = ahc_lookup_scb(ahc, scbid);
5831 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5833 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5834 ahc_add_curscb_to_free_list(ahc);
5838 * Go through the pending CCB list and look for
5839 * commands for this target that are still active.
5840 * These are other tagged commands that were
5841 * disconnected when the reset occurred.
5843 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5844 while (scbp_next != NULL) {
5846 scbp_next = LIST_NEXT(scbp, pending_links);
5847 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5850 ostat = ahc_get_transaction_status(scbp);
5851 if (ostat == CAM_REQ_INPROG)
5852 ahc_set_transaction_status(scbp, status);
5853 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5854 ahc_freeze_scb(scbp);
5855 if ((scbp->flags & SCB_ACTIVE) == 0)
5856 printf("Inactive SCB on pending list\n");
5857 ahc_done(ahc, scbp);
5861 ahc_outb(ahc, SCBPTR, active_scb);
5862 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5863 ahc_release_untagged_queues(ahc);
5868 ahc_reset_current_bus(struct ahc_softc *ahc)
5872 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5873 scsiseq = ahc_inb(ahc, SCSISEQ);
5874 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5875 ahc_flush_device_writes(ahc);
5876 ahc_delay(AHC_BUSRESET_DELAY);
5877 /* Turn off the bus reset */
5878 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5880 ahc_clear_intstat(ahc);
5882 /* Re-enable reset interrupts */
5883 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5887 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5889 struct ahc_devinfo devinfo;
5890 u_int initiator, target, max_scsiid;
5898 ahc->pending_device = NULL;
5900 ahc_compile_devinfo(&devinfo,
5901 CAM_TARGET_WILDCARD,
5902 CAM_TARGET_WILDCARD,
5904 channel, ROLE_UNKNOWN);
5907 /* Make sure the sequencer is in a safe location. */
5908 ahc_clear_critical_section(ahc);
5911 * Run our command complete fifos to ensure that we perform
5912 * completion processing on any commands that 'completed'
5913 * before the reset occurred.
5915 ahc_run_qoutfifo(ahc);
5916 #ifdef AHC_TARGET_MODE
5918 * XXX - In Twin mode, the tqinfifo may have commands
5919 * for an unaffected channel in it. However, if
5920 * we have run out of ATIO resources to drain that
5921 * queue, we may not get them all out here. Further,
5922 * the blocked transactions for the reset channel
5923 * should just be killed off, irrespecitve of whether
5924 * we are blocked on ATIO resources. Write a routine
5925 * to compact the tqinfifo appropriately.
5927 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5928 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5933 * Reset the bus if we are initiating this reset
5935 sblkctl = ahc_inb(ahc, SBLKCTL);
5937 if ((ahc->features & AHC_TWIN) != 0
5938 && ((sblkctl & SELBUSB) != 0))
5940 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5941 if (cur_channel != channel) {
5942 /* Case 1: Command for another bus is active
5943 * Stealthily reset the other bus without
5944 * upsetting the current bus.
5946 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5947 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5948 #ifdef AHC_TARGET_MODE
5950 * Bus resets clear ENSELI, so we cannot
5951 * defer re-enabling bus reset interrupts
5952 * if we are in target mode.
5954 if ((ahc->flags & AHC_TARGETROLE) != 0)
5955 simode1 |= ENSCSIRST;
5957 ahc_outb(ahc, SIMODE1, simode1);
5959 ahc_reset_current_bus(ahc);
5960 ahc_clear_intstat(ahc);
5961 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5962 ahc_outb(ahc, SBLKCTL, sblkctl);
5963 restart_needed = FALSE;
5965 /* Case 2: A command from this bus is active or we're idle */
5966 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5967 #ifdef AHC_TARGET_MODE
5969 * Bus resets clear ENSELI, so we cannot
5970 * defer re-enabling bus reset interrupts
5971 * if we are in target mode.
5973 if ((ahc->flags & AHC_TARGETROLE) != 0)
5974 simode1 |= ENSCSIRST;
5976 ahc_outb(ahc, SIMODE1, simode1);
5978 ahc_reset_current_bus(ahc);
5979 ahc_clear_intstat(ahc);
5980 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5981 restart_needed = TRUE;
5985 * Clean up all the state information for the
5986 * pending transactions on this bus.
5988 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
5989 CAM_LUN_WILDCARD, SCB_LIST_NULL,
5990 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
5992 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
5994 #ifdef AHC_TARGET_MODE
5996 * Send an immediate notify ccb to all target more peripheral
5997 * drivers affected by this action.
5999 for (target = 0; target <= max_scsiid; target++) {
6000 struct ahc_tmode_tstate* tstate;
6003 tstate = ahc->enabled_targets[target];
6006 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6007 struct ahc_tmode_lstate* lstate;
6009 lstate = tstate->enabled_luns[lun];
6013 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6014 EVENT_TYPE_BUS_RESET, /*arg*/0);
6015 ahc_send_lstate_events(ahc, lstate);
6019 /* Notify the XPT that a bus reset occurred */
6020 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6021 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6024 * Revert to async/narrow transfers until we renegotiate.
6026 for (target = 0; target <= max_scsiid; target++) {
6028 if (ahc->enabled_targets[target] == NULL)
6030 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6031 struct ahc_devinfo devinfo;
6033 ahc_compile_devinfo(&devinfo, target, initiator,
6035 channel, ROLE_UNKNOWN);
6036 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6037 AHC_TRANS_CUR, /*paused*/TRUE);
6038 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6039 /*period*/0, /*offset*/0,
6040 /*ppr_options*/0, AHC_TRANS_CUR,
6053 /***************************** Residual Processing ****************************/
6055 * Calculate the residual for a just completed SCB.
6058 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6060 struct hardware_scb *hscb;
6061 struct status_pkt *spkt;
6063 uint32_t resid_sgptr;
6069 * SG_RESID_VALID clear in sgptr.
6070 * 2) Transferless command
6071 * 3) Never performed any transfers.
6072 * sgptr has SG_FULL_RESID set.
6073 * 4) No residual but target did not
6074 * save data pointers after the
6075 * last transfer, so sgptr was
6077 * 5) We have a partial residual.
6078 * Use residual_sgptr to determine
6083 sgptr = ahc_le32toh(hscb->sgptr);
6084 if ((sgptr & SG_RESID_VALID) == 0)
6087 sgptr &= ~SG_RESID_VALID;
6089 if ((sgptr & SG_LIST_NULL) != 0)
6093 spkt = &hscb->shared_data.status;
6094 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6095 if ((sgptr & SG_FULL_RESID) != 0) {
6097 resid = ahc_get_transfer_length(scb);
6098 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6101 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6102 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6104 struct ahc_dma_seg *sg;
6107 * Remainder of the SG where the transfer
6110 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6111 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6113 /* The residual sg_ptr always points to the next sg */
6117 * Add up the contents of all residual
6118 * SG segments that are after the SG where
6119 * the transfer stopped.
6121 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6123 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6126 if ((scb->flags & SCB_SENSE) == 0)
6127 ahc_set_residual(scb, resid);
6129 ahc_set_sense_residual(scb, resid);
6132 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6133 ahc_print_path(ahc, scb);
6134 printf("Handled %sResidual of %d bytes\n",
6135 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6140 /******************************* Target Mode **********************************/
6141 #ifdef AHC_TARGET_MODE
6143 * Add a target mode event to this lun's queue
6146 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6147 u_int initiator_id, u_int event_type, u_int event_arg)
6149 struct ahc_tmode_event *event;
6152 xpt_freeze_devq(lstate->path, /*count*/1);
6153 if (lstate->event_w_idx >= lstate->event_r_idx)
6154 pending = lstate->event_w_idx - lstate->event_r_idx;
6156 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6157 - (lstate->event_r_idx - lstate->event_w_idx);
6159 if (event_type == EVENT_TYPE_BUS_RESET
6160 || event_type == MSG_BUS_DEV_RESET) {
6162 * Any earlier events are irrelevant, so reset our buffer.
6163 * This has the effect of allowing us to deal with reset
6164 * floods (an external device holding down the reset line)
6165 * without losing the event that is really interesting.
6167 lstate->event_r_idx = 0;
6168 lstate->event_w_idx = 0;
6169 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6172 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6173 xpt_print_path(lstate->path);
6174 printf("immediate event %x:%x lost\n",
6175 lstate->event_buffer[lstate->event_r_idx].event_type,
6176 lstate->event_buffer[lstate->event_r_idx].event_arg);
6177 lstate->event_r_idx++;
6178 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6179 lstate->event_r_idx = 0;
6180 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6183 event = &lstate->event_buffer[lstate->event_w_idx];
6184 event->initiator_id = initiator_id;
6185 event->event_type = event_type;
6186 event->event_arg = event_arg;
6187 lstate->event_w_idx++;
6188 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6189 lstate->event_w_idx = 0;
6193 * Send any target mode events queued up waiting
6194 * for immediate notify resources.
6197 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6199 struct ccb_hdr *ccbh;
6200 struct ccb_immed_notify *inot;
6202 while (lstate->event_r_idx != lstate->event_w_idx
6203 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6204 struct ahc_tmode_event *event;
6206 event = &lstate->event_buffer[lstate->event_r_idx];
6207 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6208 inot = (struct ccb_immed_notify *)ccbh;
6209 switch (event->event_type) {
6210 case EVENT_TYPE_BUS_RESET:
6211 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6214 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6215 inot->message_args[0] = event->event_type;
6216 inot->message_args[1] = event->event_arg;
6219 inot->initiator_id = event->initiator_id;
6220 inot->sense_len = 0;
6221 xpt_done((union ccb *)inot);
6222 lstate->event_r_idx++;
6223 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6224 lstate->event_r_idx = 0;
6229 /******************** Sequencer Program Patching/Download *********************/
6233 ahc_dumpseq(struct ahc_softc* ahc)
6237 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6238 ahc_outb(ahc, SEQADDR0, 0);
6239 ahc_outb(ahc, SEQADDR1, 0);
6240 for (i = 0; i < ahc->instruction_ram_size; i++) {
6241 uint8_t ins_bytes[4];
6243 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6244 printf("0x%08x\n", ins_bytes[0] << 24
6245 | ins_bytes[1] << 16
6253 ahc_loadseq(struct ahc_softc *ahc)
6255 struct cs cs_table[num_critical_sections];
6256 u_int begin_set[num_critical_sections];
6257 u_int end_set[num_critical_sections];
6258 struct patch *cur_patch;
6263 u_int sg_prefetch_cnt;
6265 uint8_t download_consts[7];
6268 * Start out with 0 critical sections
6269 * that apply to this firmware load.
6273 memset(begin_set, 0, sizeof(begin_set));
6274 memset(end_set, 0, sizeof(end_set));
6276 /* Setup downloadable constant table */
6277 download_consts[QOUTFIFO_OFFSET] = 0;
6278 if (ahc->targetcmds != NULL)
6279 download_consts[QOUTFIFO_OFFSET] += 32;
6280 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6281 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6282 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6283 sg_prefetch_cnt = ahc->pci_cachesize;
6284 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6285 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6286 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6287 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6288 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6290 cur_patch = patches;
6293 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6294 ahc_outb(ahc, SEQADDR0, 0);
6295 ahc_outb(ahc, SEQADDR1, 0);
6297 for (i = 0; i < sizeof(seqprog)/4; i++) {
6298 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6300 * Don't download this instruction as it
6301 * is in a patch that was removed.
6306 if (downloaded == ahc->instruction_ram_size) {
6308 * We're about to exceed the instruction
6309 * storage capacity for this chip. Fail
6312 printf("\n%s: Program too large for instruction memory "
6313 "size of %d!\n", ahc_name(ahc),
6314 ahc->instruction_ram_size);
6319 * Move through the CS table until we find a CS
6320 * that might apply to this instruction.
6322 for (; cur_cs < num_critical_sections; cur_cs++) {
6323 if (critical_sections[cur_cs].end <= i) {
6324 if (begin_set[cs_count] == TRUE
6325 && end_set[cs_count] == FALSE) {
6326 cs_table[cs_count].end = downloaded;
6327 end_set[cs_count] = TRUE;
6332 if (critical_sections[cur_cs].begin <= i
6333 && begin_set[cs_count] == FALSE) {
6334 cs_table[cs_count].begin = downloaded;
6335 begin_set[cs_count] = TRUE;
6339 ahc_download_instr(ahc, i, download_consts);
6343 ahc->num_critical_sections = cs_count;
6344 if (cs_count != 0) {
6346 cs_count *= sizeof(struct cs);
6347 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6348 if (ahc->critical_sections == NULL)
6349 panic("ahc_loadseq: Could not malloc");
6350 memcpy(ahc->critical_sections, cs_table, cs_count);
6352 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6355 printf(" %d instructions downloaded\n", downloaded);
6356 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6357 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6363 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6364 u_int start_instr, u_int *skip_addr)
6366 struct patch *cur_patch;
6367 struct patch *last_patch;
6370 num_patches = sizeof(patches)/sizeof(struct patch);
6371 last_patch = &patches[num_patches];
6372 cur_patch = *start_patch;
6374 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6376 if (cur_patch->patch_func(ahc) == 0) {
6378 /* Start rejecting code */
6379 *skip_addr = start_instr + cur_patch->skip_instr;
6380 cur_patch += cur_patch->skip_patch;
6382 /* Accepted this patch. Advance to the next
6383 * one and wait for our intruction pointer to
6390 *start_patch = cur_patch;
6391 if (start_instr < *skip_addr)
6392 /* Still skipping */
6399 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6401 union ins_formats instr;
6402 struct ins_format1 *fmt1_ins;
6403 struct ins_format3 *fmt3_ins;
6407 * The firmware is always compiled into a little endian format.
6409 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6411 fmt1_ins = &instr.format1;
6414 /* Pull the opcode */
6415 opcode = instr.format1.opcode;
6426 struct patch *cur_patch;
6432 fmt3_ins = &instr.format3;
6434 address = fmt3_ins->address;
6435 cur_patch = patches;
6438 for (i = 0; i < address;) {
6440 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6442 if (skip_addr > i) {
6445 end_addr = MIN(address, skip_addr);
6446 address_offset += end_addr - i;
6452 address -= address_offset;
6453 fmt3_ins->address = address;
6462 if (fmt1_ins->parity != 0) {
6463 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6465 fmt1_ins->parity = 0;
6466 if ((ahc->features & AHC_CMD_CHAN) == 0
6467 && opcode == AIC_OP_BMOV) {
6469 * Block move was added at the same time
6470 * as the command channel. Verify that
6471 * this is only a move of a single element
6472 * and convert the BMOV to a MOV
6473 * (AND with an immediate of FF).
6475 if (fmt1_ins->immediate != 1)
6476 panic("%s: BMOV not supported\n",
6478 fmt1_ins->opcode = AIC_OP_AND;
6479 fmt1_ins->immediate = 0xff;
6483 if ((ahc->features & AHC_ULTRA2) != 0) {
6486 /* Calculate odd parity for the instruction */
6487 for (i = 0, count = 0; i < 31; i++) {
6491 if ((instr.integer & mask) != 0)
6494 if ((count & 0x01) == 0)
6495 instr.format1.parity = 1;
6497 /* Compress the instruction for older sequencers */
6498 if (fmt3_ins != NULL) {
6501 | (fmt3_ins->source << 8)
6502 | (fmt3_ins->address << 16)
6503 | (fmt3_ins->opcode << 25);
6507 | (fmt1_ins->source << 8)
6508 | (fmt1_ins->destination << 16)
6509 | (fmt1_ins->ret << 24)
6510 | (fmt1_ins->opcode << 25);
6513 /* The sequencer is a little endian cpu */
6514 instr.integer = ahc_htole32(instr.integer);
6515 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6518 panic("Unknown opcode encountered in seq program");
6524 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6525 const char *name, u_int address, u_int value,
6526 u_int *cur_column, u_int wrap_point)
6531 if (cur_column != NULL && *cur_column >= wrap_point) {
6535 printed = printf("%s[0x%x]", name, value);
6536 if (table == NULL) {
6537 printed += printf(" ");
6538 *cur_column += printed;
6542 while (printed_mask != 0xFF) {
6545 for (entry = 0; entry < num_entries; entry++) {
6546 if (((value & table[entry].mask)
6547 != table[entry].value)
6548 || ((printed_mask & table[entry].mask)
6549 == table[entry].mask))
6552 printed += printf("%s%s",
6553 printed_mask == 0 ? ":(" : "|",
6555 printed_mask |= table[entry].mask;
6559 if (entry >= num_entries)
6562 if (printed_mask != 0)
6563 printed += printf(") ");
6565 printed += printf(" ");
6566 if (cur_column != NULL)
6567 *cur_column += printed;
6572 ahc_dump_card_state(struct ahc_softc *ahc)
6575 struct scb_tailq *untagged_q;
6586 uint8_t saved_scbptr;
6588 if (ahc_is_paused(ahc)) {
6595 saved_scbptr = ahc_inb(ahc, SCBPTR);
6596 last_phase = ahc_inb(ahc, LASTPHASE);
6597 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6598 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6599 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6600 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6602 printf("Card was paused\n");
6603 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6604 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6605 ahc_inb(ahc, ARG_2));
6606 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6607 ahc_inb(ahc, SCBPTR));
6609 if ((ahc->features & AHC_DT) != 0)
6610 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6611 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6612 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6613 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6614 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6615 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6616 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6617 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6618 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6619 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6620 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6621 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6622 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6623 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6624 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6625 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6626 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6627 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6628 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6632 for (i = 0; i < STACK_SIZE; i++)
6633 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6634 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6635 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6636 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6638 printf("QINFIFO entries: ");
6639 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6640 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6641 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6643 qinpos = ahc_inb(ahc, QINPOS);
6644 qintail = ahc->qinfifonext;
6645 while (qinpos != qintail) {
6646 printf("%d ", ahc->qinfifo[qinpos]);
6651 printf("Waiting Queue entries: ");
6652 scb_index = ahc_inb(ahc, WAITING_SCBH);
6654 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6655 ahc_outb(ahc, SCBPTR, scb_index);
6656 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6657 scb_index = ahc_inb(ahc, SCB_NEXT);
6661 printf("Disconnected Queue entries: ");
6662 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6664 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6665 ahc_outb(ahc, SCBPTR, scb_index);
6666 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6667 scb_index = ahc_inb(ahc, SCB_NEXT);
6671 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6672 printf("QOUTFIFO entries: ");
6673 qoutpos = ahc->qoutfifonext;
6675 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6676 printf("%d ", ahc->qoutfifo[qoutpos]);
6681 printf("Sequencer Free SCB List: ");
6682 scb_index = ahc_inb(ahc, FREE_SCBH);
6684 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6685 ahc_outb(ahc, SCBPTR, scb_index);
6686 printf("%d ", scb_index);
6687 scb_index = ahc_inb(ahc, SCB_NEXT);
6691 printf("Sequencer SCB Info: ");
6692 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6693 ahc_outb(ahc, SCBPTR, i);
6694 cur_col = printf("\n%3d ", i);
6696 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6697 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6698 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6699 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6703 printf("Pending list: ");
6705 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6708 cur_col = printf("\n%3d ", scb->hscb->tag);
6709 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6710 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6711 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6712 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6713 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6715 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6717 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6723 printf("Kernel Free SCB list: ");
6725 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6728 printf("%d ", scb->hscb->tag);
6732 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6733 for (target = 0; target <= maxtarget; target++) {
6734 untagged_q = &ahc->untagged_queues[target];
6735 if (TAILQ_FIRST(untagged_q) == NULL)
6737 printf("Untagged Q(%d): ", target);
6739 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6742 printf("%d ", scb->hscb->tag);
6747 ahc_platform_dump_card_state(ahc);
6748 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6749 ahc_outb(ahc, SCBPTR, saved_scbptr);
6754 /************************* Target Mode ****************************************/
6755 #ifdef AHC_TARGET_MODE
6757 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6758 struct ahc_tmode_tstate **tstate,
6759 struct ahc_tmode_lstate **lstate,
6760 int notfound_failure)
6763 if ((ahc->features & AHC_TARGETMODE) == 0)
6764 return (CAM_REQ_INVALID);
6767 * Handle the 'black hole' device that sucks up
6768 * requests to unattached luns on enabled targets.
6770 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6771 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6773 *lstate = ahc->black_hole;
6777 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6778 if (ccb->ccb_h.target_id > max_id)
6779 return (CAM_TID_INVALID);
6781 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6782 return (CAM_LUN_INVALID);
6784 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6786 if (*tstate != NULL)
6788 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6791 if (notfound_failure != 0 && *lstate == NULL)
6792 return (CAM_PATH_INVALID);
6794 return (CAM_REQ_CMP);
6798 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6800 struct ahc_tmode_tstate *tstate;
6801 struct ahc_tmode_lstate *lstate;
6802 struct ccb_en_lun *cel;
6812 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6813 /*notfound_failure*/FALSE);
6815 if (status != CAM_REQ_CMP) {
6816 ccb->ccb_h.status = status;
6820 if (cam_sim_bus(sim) == 0)
6821 our_id = ahc->our_id;
6823 our_id = ahc->our_id_b;
6825 if (ccb->ccb_h.target_id != our_id) {
6827 * our_id represents our initiator ID, or
6828 * the ID of the first target to have an
6829 * enabled lun in target mode. There are
6830 * two cases that may preclude enabling a
6831 * target id other than our_id.
6833 * o our_id is for an active initiator role.
6834 * Since the hardware does not support
6835 * reselections to the initiator role at
6836 * anything other than our_id, and our_id
6837 * is used by the hardware to indicate the
6838 * ID to use for both select-out and
6839 * reselect-out operations, the only target
6840 * ID we can support in this mode is our_id.
6842 * o The MULTARGID feature is not available and
6843 * a previous target mode ID has been enabled.
6845 if ((ahc->features & AHC_MULTIROLE) != 0) {
6847 if ((ahc->features & AHC_MULTI_TID) != 0
6848 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6850 * Only allow additional targets if
6851 * the initiator role is disabled.
6852 * The hardware cannot handle a re-select-in
6853 * on the initiator id during a re-select-out
6854 * on a different target id.
6856 status = CAM_TID_INVALID;
6857 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6858 || ahc->enabled_luns > 0) {
6860 * Only allow our target id to change
6861 * if the initiator role is not configured
6862 * and there are no enabled luns which
6863 * are attached to the currently registered
6866 status = CAM_TID_INVALID;
6868 } else if ((ahc->features & AHC_MULTI_TID) == 0
6869 && ahc->enabled_luns > 0) {
6871 status = CAM_TID_INVALID;
6875 if (status != CAM_REQ_CMP) {
6876 ccb->ccb_h.status = status;
6881 * We now have an id that is valid.
6882 * If we aren't in target mode, switch modes.
6884 if ((ahc->flags & AHC_TARGETROLE) == 0
6885 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6887 ahc_flag saved_flags;
6889 printf("Configuring Target Mode\n");
6891 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6892 ccb->ccb_h.status = CAM_BUSY;
6893 ahc_unlock(ahc, &s);
6896 saved_flags = ahc->flags;
6897 ahc->flags |= AHC_TARGETROLE;
6898 if ((ahc->features & AHC_MULTIROLE) == 0)
6899 ahc->flags &= ~AHC_INITIATORROLE;
6901 error = ahc_loadseq(ahc);
6904 * Restore original configuration and notify
6905 * the caller that we cannot support target mode.
6906 * Since the adapter started out in this
6907 * configuration, the firmware load will succeed,
6908 * so there is no point in checking ahc_loadseq's
6911 ahc->flags = saved_flags;
6912 (void)ahc_loadseq(ahc);
6914 ahc_unlock(ahc, &s);
6915 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6919 ahc_unlock(ahc, &s);
6922 target = ccb->ccb_h.target_id;
6923 lun = ccb->ccb_h.target_lun;
6924 channel = SIM_CHANNEL(ahc, sim);
6925 target_mask = 0x01 << target;
6929 if (cel->enable != 0) {
6932 /* Are we already enabled?? */
6933 if (lstate != NULL) {
6934 xpt_print_path(ccb->ccb_h.path);
6935 printf("Lun already enabled\n");
6936 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6940 if (cel->grp6_len != 0
6941 || cel->grp7_len != 0) {
6943 * Don't (yet?) support vendor
6944 * specific commands.
6946 ccb->ccb_h.status = CAM_REQ_INVALID;
6947 printf("Non-zero Group Codes\n");
6953 * Setup our data structures.
6955 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6956 tstate = ahc_alloc_tstate(ahc, target, channel);
6957 if (tstate == NULL) {
6958 xpt_print_path(ccb->ccb_h.path);
6959 printf("Couldn't allocate tstate\n");
6960 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6964 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6965 if (lstate == NULL) {
6966 xpt_print_path(ccb->ccb_h.path);
6967 printf("Couldn't allocate lstate\n");
6968 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6971 memset(lstate, 0, sizeof(*lstate));
6972 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6973 xpt_path_path_id(ccb->ccb_h.path),
6974 xpt_path_target_id(ccb->ccb_h.path),
6975 xpt_path_lun_id(ccb->ccb_h.path));
6976 if (status != CAM_REQ_CMP) {
6977 free(lstate, M_DEVBUF);
6978 xpt_print_path(ccb->ccb_h.path);
6979 printf("Couldn't allocate path\n");
6980 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6983 SLIST_INIT(&lstate->accept_tios);
6984 SLIST_INIT(&lstate->immed_notifies);
6987 if (target != CAM_TARGET_WILDCARD) {
6988 tstate->enabled_luns[lun] = lstate;
6989 ahc->enabled_luns++;
6991 if ((ahc->features & AHC_MULTI_TID) != 0) {
6994 targid_mask = ahc_inb(ahc, TARGID)
6995 | (ahc_inb(ahc, TARGID + 1) << 8);
6997 targid_mask |= target_mask;
6998 ahc_outb(ahc, TARGID, targid_mask);
6999 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7001 ahc_update_scsiid(ahc, targid_mask);
7006 channel = SIM_CHANNEL(ahc, sim);
7007 our_id = SIM_SCSI_ID(ahc, sim);
7010 * This can only happen if selections
7013 if (target != our_id) {
7018 sblkctl = ahc_inb(ahc, SBLKCTL);
7019 cur_channel = (sblkctl & SELBUSB)
7021 if ((ahc->features & AHC_TWIN) == 0)
7023 swap = cur_channel != channel;
7025 ahc->our_id = target;
7027 ahc->our_id_b = target;
7030 ahc_outb(ahc, SBLKCTL,
7033 ahc_outb(ahc, SCSIID, target);
7036 ahc_outb(ahc, SBLKCTL, sblkctl);
7040 ahc->black_hole = lstate;
7041 /* Allow select-in operations */
7042 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7043 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7045 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7046 scsiseq = ahc_inb(ahc, SCSISEQ);
7048 ahc_outb(ahc, SCSISEQ, scsiseq);
7051 ahc_unlock(ahc, &s);
7052 ccb->ccb_h.status = CAM_REQ_CMP;
7053 xpt_print_path(ccb->ccb_h.path);
7054 printf("Lun now enabled for target mode\n");
7059 if (lstate == NULL) {
7060 ccb->ccb_h.status = CAM_LUN_INVALID;
7066 ccb->ccb_h.status = CAM_REQ_CMP;
7067 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7068 struct ccb_hdr *ccbh;
7070 ccbh = &scb->io_ctx->ccb_h;
7071 if (ccbh->func_code == XPT_CONT_TARGET_IO
7072 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7073 printf("CTIO pending\n");
7074 ccb->ccb_h.status = CAM_REQ_INVALID;
7075 ahc_unlock(ahc, &s);
7080 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7081 printf("ATIOs pending\n");
7082 ccb->ccb_h.status = CAM_REQ_INVALID;
7085 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7086 printf("INOTs pending\n");
7087 ccb->ccb_h.status = CAM_REQ_INVALID;
7090 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7091 ahc_unlock(ahc, &s);
7095 xpt_print_path(ccb->ccb_h.path);
7096 printf("Target mode disabled\n");
7097 xpt_free_path(lstate->path);
7098 free(lstate, M_DEVBUF);
7101 /* Can we clean up the target too? */
7102 if (target != CAM_TARGET_WILDCARD) {
7103 tstate->enabled_luns[lun] = NULL;
7104 ahc->enabled_luns--;
7105 for (empty = 1, i = 0; i < 8; i++)
7106 if (tstate->enabled_luns[i] != NULL) {
7112 ahc_free_tstate(ahc, target, channel,
7114 if (ahc->features & AHC_MULTI_TID) {
7117 targid_mask = ahc_inb(ahc, TARGID)
7118 | (ahc_inb(ahc, TARGID + 1)
7121 targid_mask &= ~target_mask;
7122 ahc_outb(ahc, TARGID, targid_mask);
7123 ahc_outb(ahc, TARGID+1,
7124 (targid_mask >> 8));
7125 ahc_update_scsiid(ahc, targid_mask);
7130 ahc->black_hole = NULL;
7133 * We can't allow selections without
7134 * our black hole device.
7138 if (ahc->enabled_luns == 0) {
7139 /* Disallow select-in */
7142 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7144 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7145 scsiseq = ahc_inb(ahc, SCSISEQ);
7147 ahc_outb(ahc, SCSISEQ, scsiseq);
7149 if ((ahc->features & AHC_MULTIROLE) == 0) {
7150 printf("Configuring Initiator Mode\n");
7151 ahc->flags &= ~AHC_TARGETROLE;
7152 ahc->flags |= AHC_INITIATORROLE;
7154 * Returning to a configuration that
7155 * fit previously will always succeed.
7157 (void)ahc_loadseq(ahc);
7160 * Unpaused. The extra unpause
7161 * that follows is harmless.
7166 ahc_unlock(ahc, &s);
7171 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7176 if ((ahc->features & AHC_MULTI_TID) == 0)
7177 panic("ahc_update_scsiid called on non-multitid unit\n");
7180 * Since we will rely on the TARGID mask
7181 * for selection enables, ensure that OID
7182 * in SCSIID is not set to some other ID
7183 * that we don't want to allow selections on.
7185 if ((ahc->features & AHC_ULTRA2) != 0)
7186 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7188 scsiid = ahc_inb(ahc, SCSIID);
7189 scsiid_mask = 0x1 << (scsiid & OID);
7190 if ((targid_mask & scsiid_mask) == 0) {
7193 /* ffs counts from 1 */
7194 our_id = ffs(targid_mask);
7196 our_id = ahc->our_id;
7202 if ((ahc->features & AHC_ULTRA2) != 0)
7203 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7205 ahc_outb(ahc, SCSIID, scsiid);
7209 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7211 struct target_cmd *cmd;
7214 * If the card supports auto-access pause,
7215 * we can access the card directly regardless
7216 * of whether it is paused or not.
7218 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7221 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7222 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7225 * Only advance through the queue if we
7226 * have the resources to process the command.
7228 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7232 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7233 ahc->shared_data_dmamap,
7234 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7235 sizeof(struct target_cmd),
7236 BUS_DMASYNC_PREREAD);
7237 ahc->tqinfifonext++;
7240 * Lazily update our position in the target mode incoming
7241 * command queue as seen by the sequencer.
7243 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7244 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7247 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7248 hs_mailbox &= ~HOST_TQINPOS;
7249 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7250 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7254 ahc_outb(ahc, KERNEL_TQINPOS,
7255 ahc->tqinfifonext & HOST_TQINPOS);
7264 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7266 struct ahc_tmode_tstate *tstate;
7267 struct ahc_tmode_lstate *lstate;
7268 struct ccb_accept_tio *atio;
7274 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7275 target = SCSIID_OUR_ID(cmd->scsiid);
7276 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7279 tstate = ahc->enabled_targets[target];
7282 lstate = tstate->enabled_luns[lun];
7285 * Commands for disabled luns go to the black hole driver.
7288 lstate = ahc->black_hole;
7290 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7292 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7294 * Wait for more ATIOs from the peripheral driver for this lun.
7297 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7300 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7302 printf("Incoming command from %d for %d:%d%s\n",
7303 initiator, target, lun,
7304 lstate == ahc->black_hole ? "(Black Holed)" : "");
7306 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7308 if (lstate == ahc->black_hole) {
7309 /* Fill in the wildcards */
7310 atio->ccb_h.target_id = target;
7311 atio->ccb_h.target_lun = lun;
7315 * Package it up and send it off to
7316 * whomever has this lun enabled.
7318 atio->sense_len = 0;
7319 atio->init_id = initiator;
7320 if (byte[0] != 0xFF) {
7321 /* Tag was included */
7322 atio->tag_action = *byte++;
7323 atio->tag_id = *byte++;
7324 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7326 atio->ccb_h.flags = 0;
7330 /* Okay. Now determine the cdb size based on the command code */
7331 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7347 /* Only copy the opcode. */
7349 printf("Reserved or VU command code type encountered\n");
7353 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7355 atio->ccb_h.status |= CAM_CDB_RECVD;
7357 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7359 * We weren't allowed to disconnect.
7360 * We're hanging on the bus until a
7361 * continue target I/O comes in response
7362 * to this accept tio.
7365 printf("Received Immediate Command %d:%d:%d - %p\n",
7366 initiator, target, lun, ahc->pending_device);
7368 ahc->pending_device = lstate;
7369 ahc_freeze_ccb((union ccb *)atio);
7370 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7372 xpt_done((union ccb*)atio);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob