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   1 /*
   2  *      drivers/pci/setup-res.c
   3  *
   4  * Extruded from code written by
   5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
   6  *      David Mosberger (davidm@cs.arizona.edu)
   7  *      David Miller (davem@redhat.com)
   8  *
   9  * Support routines for initializing a PCI subsystem.
  10  */
  11
  12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
  13
  14 /*
  15  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  16  *           Resource sorting
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/cache.h>
  25 #include <linux/slab.h>
  26 #include "pci.h"
  27
  28
  29 void pci_update_resource(struct pci_dev *dev, int resno)
  30 {
  31         struct pci_bus_region region;
  32         u32 new, check, mask;
  33         int reg;
  34         enum pci_bar_type type;
  35         struct resource *res = dev->resource + resno;
  36
  37         /*
  38          * Ignore resources for unimplemented BARs and unused resource slots
  39          * for 64 bit BARs.
  40          */
  41         if (!res->flags)
  42                 return;
  43
  44         /*
  45          * Ignore non-moveable resources.  This might be legacy resources for
  46          * which no functional BAR register exists or another important
  47          * system resource we shouldn't move around.
  48          */
  49         if (res->flags & IORESOURCE_PCI_FIXED)
  50                 return;
  51
  52         pcibios_resource_to_bus(dev, &region, res);
  53
  54         new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
  55         if (res->flags & IORESOURCE_IO)
  56                 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
  57         else
  58                 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
  59
  60         reg = pci_resource_bar(dev, resno, &type);
  61         if (!reg)
  62                 return;
  63         if (type != pci_bar_unknown) {
  64                 if (!(res->flags & IORESOURCE_ROM_ENABLE))
  65                         return;
  66                 new |= PCI_ROM_ADDRESS_ENABLE;
  67         }
  68
  69         pci_write_config_dword(dev, reg, new);
  70         pci_read_config_dword(dev, reg, &check);
  71
  72         if ((new ^ check) & mask) {
  73                 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
  74                         resno, new, check);
  75         }
  76
  77         if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
  78             (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
  79                 new = region.start >> 16 >> 16;
  80                 pci_write_config_dword(dev, reg + 4, new);
  81                 pci_read_config_dword(dev, reg + 4, &check);
  82                 if (check != new) {
  83                         dev_err(&dev->dev, "BAR %d: error updating "
  84                                "(high %#08x != %#08x)\n", resno, new, check);
  85                 }
  86         }
  87         res->flags &= ~IORESOURCE_UNSET;
  88         dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx]\n",
  89                  resno, res, (unsigned long long)region.start,
  90                  (unsigned long long)region.end);
  91 }
  92
  93 int pci_claim_resource(struct pci_dev *dev, int resource)
  94 {
  95         struct resource *res = &dev->resource[resource];
  96         struct resource *root;
  97         int err;
  98
  99         root = pci_find_parent_resource(dev, res);
 100         if (!root) {
 101                 dev_err(&dev->dev, "no compatible bridge window for %pR\n",
 102                         res);
 103                 return -EINVAL;
 104         }
 105
 106         err = request_resource(root, res);
 107         if (err)
 108                 dev_err(&dev->dev,
 109                         "address space collision: %pR already in use\n", res);
 110
 111         return err;
 112 }
 113 EXPORT_SYMBOL(pci_claim_resource);
 114
 115 #ifdef CONFIG_PCI_QUIRKS
 116 void pci_disable_bridge_window(struct pci_dev *dev)
 117 {
 118         dev_info(&dev->dev, "disabling bridge mem windows\n");
 119
 120         /* MMIO Base/Limit */
 121         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
 122
 123         /* Prefetchable MMIO Base/Limit */
 124         pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
 125         pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
 126         pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
 127 }
 128 #endif  /* CONFIG_PCI_QUIRKS */
 129
 130 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
 131                                  int resno)
 132 {
 133         struct resource *res = dev->resource + resno;
 134         resource_size_t size, min, align;
 135         int ret;
 136
 137         size = resource_size(res);
 138         min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 139         align = pci_resource_alignment(dev, res);
 140
 141         /* First, try exact prefetching match.. */
 142         ret = pci_bus_alloc_resource(bus, res, size, align, min,
 143                                      IORESOURCE_PREFETCH,
 144                                      pcibios_align_resource, dev);
 145
 146         if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
 147                 /*
 148                  * That failed.
 149                  *
 150                  * But a prefetching area can handle a non-prefetching
 151                  * window (it will just not perform as well).
 152                  */
 153                 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
 154                                              pcibios_align_resource, dev);
 155         }
 156
 157         if (!ret) {
 158                 res->flags &= ~IORESOURCE_STARTALIGN;
 159                 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
 160                 if (resno < PCI_BRIDGE_RESOURCES)
 161                         pci_update_resource(dev, resno);
 162         }
 163
 164         return ret;
 165 }
 166
 167 int pci_assign_resource(struct pci_dev *dev, int resno)
 168 {
 169         struct resource *res = dev->resource + resno;
 170         resource_size_t align;
 171         struct pci_bus *bus;
 172         int ret;
 173         char *type;
 174
 175         align = pci_resource_alignment(dev, res);
 176         if (!align) {
 177                 dev_info(&dev->dev, "BAR %d: can't assign %pR "
 178                          "(bogus alignment)\n", resno, res);
 179                 return -EINVAL;
 180         }
 181
 182         bus = dev->bus;
 183         while ((ret = __pci_assign_resource(bus, dev, resno))) {
 184                 if (bus->parent && bus->self->transparent)
 185                         bus = bus->parent;
 186                 else
 187                         bus = NULL;
 188                 if (bus)
 189                         continue;
 190                 break;
 191         }
 192
 193         if (ret) {
 194                 if (res->flags & IORESOURCE_MEM)
 195                         if (res->flags & IORESOURCE_PREFETCH)
 196                                 type = "mem pref";
 197                         else
 198                                 type = "mem";
 199                 else if (res->flags & IORESOURCE_IO)
 200                         type = "io";
 201                 else
 202                         type = "unknown";
 203                 dev_info(&dev->dev,
 204                          "BAR %d: can't assign %s (size %#llx)\n",
 205                          resno, type, (unsigned long long) resource_size(res));
 206         }
 207
 208         return ret;
 209 }
 210
 211 /* Sort resources by alignment */
 212 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
 213 {
 214         int i;
 215
 216         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 217                 struct resource *r;
 218                 struct resource_list *list, *tmp;
 219                 resource_size_t r_align;
 220
 221                 r = &dev->resource[i];
 222
 223                 if (r->flags & IORESOURCE_PCI_FIXED)
 224                         continue;
 225
 226                 if (!(r->flags) || r->parent)
 227                         continue;
 228
 229                 r_align = pci_resource_alignment(dev, r);
 230                 if (!r_align) {
 231                         dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
 232                                  i, r);
 233                         continue;
 234                 }
 235                 for (list = head; ; list = list->next) {
 236                         resource_size_t align = 0;
 237                         struct resource_list *ln = list->next;
 238
 239                         if (ln)
 240                                 align = pci_resource_alignment(ln->dev, ln->res);
 241
 242                         if (r_align > align) {
 243                                 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
 244                                 if (!tmp)
 245                                         panic("pdev_sort_resources(): "
 246                                               "kmalloc() failed!\n");
 247                                 tmp->next = ln;
 248                                 tmp->res = r;
 249                                 tmp->dev = dev;
 250                                 list->next = tmp;
 251                                 break;
 252                         }
 253                 }
 254         }
 255 }
 256
 257 int pci_enable_resources(struct pci_dev *dev, int mask)
 258 {
 259         u16 cmd, old_cmd;
 260         int i;
 261         struct resource *r;
 262
 263         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 264         old_cmd = cmd;
 265
 266         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 267                 if (!(mask & (1 << i)))
 268                         continue;
 269
 270                 r = &dev->resource[i];
 271
 272                 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
 273                         continue;
 274                 if ((i == PCI_ROM_RESOURCE) &&
 275                                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
 276                         continue;
 277
 278                 if (!r->parent) {
 279                         dev_err(&dev->dev, "device not available "
 280                                 "(can't reserve %pR)\n", r);
 281                         return -EINVAL;
 282                 }
 283
 284                 if (r->flags & IORESOURCE_IO)
 285                         cmd |= PCI_COMMAND_IO;
 286                 if (r->flags & IORESOURCE_MEM)
 287                         cmd |= PCI_COMMAND_MEMORY;
 288         }
 289
 290         if (cmd != old_cmd) {
 291                 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
 292                          old_cmd, cmd);
 293                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 294         }
 295         return 0;
 296 }