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   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317
 318 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 319                              unsigned long *delay_on,
 320                              unsigned long *delay_off)
 321 {
 322         struct rt2x00_led *led =
 323             container_of(led_cdev, struct rt2x00_led, led_dev);
 324         u32 reg;
 325
 326         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 327         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 328         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 329         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 330
 331         return 0;
 332 }
 333
 334 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 335                              struct rt2x00_led *led,
 336                              enum led_type type)
 337 {
 338         led->rt2x00dev = rt2x00dev;
 339         led->type = type;
 340         led->led_dev.brightness_set = rt61pci_brightness_set;
 341         led->led_dev.blink_set = rt61pci_blink_set;
 342         led->flags = LED_INITIALIZED;
 343 }
 344 #endif /* CONFIG_RT61PCI_LEDS */
 345
 346 /*
 347  * Configuration handlers.
 348  */
 349 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 350                                      struct rt2x00lib_crypto *crypto,
 351                                      struct ieee80211_key_conf *key)
 352 {
 353         struct hw_key_entry key_entry;
 354         struct rt2x00_field32 field;
 355         u32 mask;
 356         u32 reg;
 357
 358         if (crypto->cmd == SET_KEY) {
 359                 /*
 360                  * rt2x00lib can't determine the correct free
 361                  * key_idx for shared keys. We have 1 register
 362                  * with key valid bits. The goal is simple, read
 363                  * the register, if that is full we have no slots
 364                  * left.
 365                  * Note that each BSS is allowed to have up to 4
 366                  * shared keys, so put a mask over the allowed
 367                  * entries.
 368                  */
 369                 mask = (0xf << crypto->bssidx);
 370
 371                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 372                 reg &= mask;
 373
 374                 if (reg && reg == mask)
 375                         return -ENOSPC;
 376
 377                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 378
 379                 /*
 380                  * Upload key to hardware
 381                  */
 382                 memcpy(key_entry.key, crypto->key,
 383                        sizeof(key_entry.key));
 384                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 385                        sizeof(key_entry.tx_mic));
 386                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 387                        sizeof(key_entry.rx_mic));
 388
 389                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 390                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 391                                               &key_entry, sizeof(key_entry));
 392
 393                 /*
 394                  * The cipher types are stored over 2 registers.
 395                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 396                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 397                  * Using the correct defines correctly will cause overhead,
 398                  * so just calculate the correct offset.
 399                  */
 400                 if (key->hw_key_idx < 8) {
 401                         field.bit_offset = (3 * key->hw_key_idx);
 402                         field.bit_mask = 0x7 << field.bit_offset;
 403
 404                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 405                         rt2x00_set_field32(&reg, field, crypto->cipher);
 406                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 407                 } else {
 408                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 409                         field.bit_mask = 0x7 << field.bit_offset;
 410
 411                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 412                         rt2x00_set_field32(&reg, field, crypto->cipher);
 413                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 414                 }
 415
 416                 /*
 417                  * The driver does not support the IV/EIV generation
 418                  * in hardware. However it doesn't support the IV/EIV
 419                  * inside the ieee80211 frame either, but requires it
 420                  * to be provided seperately for the descriptor.
 421                  * rt2x00lib will cut the IV/EIV data out of all frames
 422                  * given to us by mac80211, but we must tell mac80211
 423                  * to generate the IV/EIV data.
 424                  */
 425                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 426         }
 427
 428         /*
 429          * SEC_CSR0 contains only single-bit fields to indicate
 430          * a particular key is valid. Because using the FIELD32()
 431          * defines directly will cause a lot of overhead we use
 432          * a calculation to determine the correct bit directly.
 433          */
 434         mask = 1 << key->hw_key_idx;
 435
 436         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 437         if (crypto->cmd == SET_KEY)
 438                 reg |= mask;
 439         else if (crypto->cmd == DISABLE_KEY)
 440                 reg &= ~mask;
 441         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 442
 443         return 0;
 444 }
 445
 446 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 447                                        struct rt2x00lib_crypto *crypto,
 448                                        struct ieee80211_key_conf *key)
 449 {
 450         struct hw_pairwise_ta_entry addr_entry;
 451         struct hw_key_entry key_entry;
 452         u32 mask;
 453         u32 reg;
 454
 455         if (crypto->cmd == SET_KEY) {
 456                 /*
 457                  * rt2x00lib can't determine the correct free
 458                  * key_idx for pairwise keys. We have 2 registers
 459                  * with key valid bits. The goal is simple, read
 460                  * the first register, if that is full move to
 461                  * the next register.
 462                  * When both registers are full, we drop the key,
 463                  * otherwise we use the first invalid entry.
 464                  */
 465                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 466                 if (reg && reg == ~0) {
 467                         key->hw_key_idx = 32;
 468                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 469                         if (reg && reg == ~0)
 470                                 return -ENOSPC;
 471                 }
 472
 473                 key->hw_key_idx += reg ? (ffz(reg) - 1) : 0;
 474
 475                 /*
 476                  * Upload key to hardware
 477                  */
 478                 memcpy(key_entry.key, crypto->key,
 479                        sizeof(key_entry.key));
 480                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 481                        sizeof(key_entry.tx_mic));
 482                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 483                        sizeof(key_entry.rx_mic));
 484
 485                 memset(&addr_entry, 0, sizeof(addr_entry));
 486                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 487                 addr_entry.cipher = crypto->cipher;
 488
 489                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 490                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 491                                               &key_entry, sizeof(key_entry));
 492
 493                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 494                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 495                                               &addr_entry, sizeof(addr_entry));
 496
 497                 /*
 498                  * Enable pairwise lookup table for given BSS idx,
 499                  * without this received frames will not be decrypted
 500                  * by the hardware.
 501                  */
 502                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 503                 reg |= (1 << crypto->bssidx);
 504                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 505
 506                 /*
 507                  * The driver does not support the IV/EIV generation
 508                  * in hardware. However it doesn't support the IV/EIV
 509                  * inside the ieee80211 frame either, but requires it
 510                  * to be provided seperately for the descriptor.
 511                  * rt2x00lib will cut the IV/EIV data out of all frames
 512                  * given to us by mac80211, but we must tell mac80211
 513                  * to generate the IV/EIV data.
 514                  */
 515                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 516         }
 517
 518         /*
 519          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 520          * a particular key is valid. Because using the FIELD32()
 521          * defines directly will cause a lot of overhead we use
 522          * a calculation to determine the correct bit directly.
 523          */
 524         if (key->hw_key_idx < 32) {
 525                 mask = 1 << key->hw_key_idx;
 526
 527                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 528                 if (crypto->cmd == SET_KEY)
 529                         reg |= mask;
 530                 else if (crypto->cmd == DISABLE_KEY)
 531                         reg &= ~mask;
 532                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 533         } else {
 534                 mask = 1 << (key->hw_key_idx - 32);
 535
 536                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 537                 if (crypto->cmd == SET_KEY)
 538                         reg |= mask;
 539                 else if (crypto->cmd == DISABLE_KEY)
 540                         reg &= ~mask;
 541                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 542         }
 543
 544         return 0;
 545 }
 546
 547 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 548                                   const unsigned int filter_flags)
 549 {
 550         u32 reg;
 551
 552         /*
 553          * Start configuration steps.
 554          * Note that the version error will always be dropped
 555          * and broadcast frames will always be accepted since
 556          * there is no filter for it at this time.
 557          */
 558         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 559         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 560                            !(filter_flags & FIF_FCSFAIL));
 561         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 562                            !(filter_flags & FIF_PLCPFAIL));
 563         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 564                            !(filter_flags & FIF_CONTROL));
 565         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 566                            !(filter_flags & FIF_PROMISC_IN_BSS));
 567         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 568                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 569                            !rt2x00dev->intf_ap_count);
 570         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 571         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 572                            !(filter_flags & FIF_ALLMULTI));
 573         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 574         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 575                            !(filter_flags & FIF_CONTROL));
 576         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 577 }
 578
 579 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 580                                 struct rt2x00_intf *intf,
 581                                 struct rt2x00intf_conf *conf,
 582                                 const unsigned int flags)
 583 {
 584         unsigned int beacon_base;
 585         u32 reg;
 586
 587         if (flags & CONFIG_UPDATE_TYPE) {
 588                 /*
 589                  * Clear current synchronisation setup.
 590                  * For the Beacon base registers we only need to clear
 591                  * the first byte since that byte contains the VALID and OWNER
 592                  * bits which (when set to 0) will invalidate the entire beacon.
 593                  */
 594                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 595                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 596
 597                 /*
 598                  * Enable synchronisation.
 599                  */
 600                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 601                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 602                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 603                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 604                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 605         }
 606
 607         if (flags & CONFIG_UPDATE_MAC) {
 608                 reg = le32_to_cpu(conf->mac[1]);
 609                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 610                 conf->mac[1] = cpu_to_le32(reg);
 611
 612                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 613                                               conf->mac, sizeof(conf->mac));
 614         }
 615
 616         if (flags & CONFIG_UPDATE_BSSID) {
 617                 reg = le32_to_cpu(conf->bssid[1]);
 618                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 619                 conf->bssid[1] = cpu_to_le32(reg);
 620
 621                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 622                                               conf->bssid, sizeof(conf->bssid));
 623         }
 624 }
 625
 626 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 627                                struct rt2x00lib_erp *erp)
 628 {
 629         u32 reg;
 630
 631         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 632         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 633         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 634
 635         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 636         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 637                            !!erp->short_preamble);
 638         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 639 }
 640
 641
 642 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 643                                     struct rt2x00lib_conf *libconf)
 644 {
 645         u16 eeprom;
 646         short lna_gain = 0;
 647
 648         if (libconf->band == IEEE80211_BAND_2GHZ) {
 649                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 650                         lna_gain += 14;
 651
 652                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 653                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 654         } else {
 655                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 656                         lna_gain += 14;
 657
 658                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 659                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 660         }
 661
 662         rt2x00dev->lna_gain = lna_gain;
 663 }
 664
 665 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 666                                    const int basic_rate_mask)
 667 {
 668         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 669 }
 670
 671 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 672                                    struct rf_channel *rf, const int txpower)
 673 {
 674         u8 r3;
 675         u8 r94;
 676         u8 smart;
 677
 678         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 679         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 680
 681         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 682                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 683
 684         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 685         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 686         rt61pci_bbp_write(rt2x00dev, 3, r3);
 687
 688         r94 = 6;
 689         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 690                 r94 += txpower - MAX_TXPOWER;
 691         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 692                 r94 += txpower;
 693         rt61pci_bbp_write(rt2x00dev, 94, r94);
 694
 695         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 696         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 697         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 698         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 699
 700         udelay(200);
 701
 702         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 703         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 704         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 705         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 706
 707         udelay(200);
 708
 709         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 710         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 711         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 712         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 713
 714         msleep(1);
 715 }
 716
 717 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 718                                    const int txpower)
 719 {
 720         struct rf_channel rf;
 721
 722         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 723         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 724         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 725         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 726
 727         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 728 }
 729
 730 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 731                                       struct antenna_setup *ant)
 732 {
 733         u8 r3;
 734         u8 r4;
 735         u8 r77;
 736
 737         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 738         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 739         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 740
 741         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 742                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 743
 744         /*
 745          * Configure the RX antenna.
 746          */
 747         switch (ant->rx) {
 748         case ANTENNA_HW_DIVERSITY:
 749                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 750                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 751                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 752                 break;
 753         case ANTENNA_A:
 754                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 755                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 756                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 757                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 758                 else
 759                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 760                 break;
 761         case ANTENNA_B:
 762         default:
 763                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 764                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 765                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 766                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 767                 else
 768                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 769                 break;
 770         }
 771
 772         rt61pci_bbp_write(rt2x00dev, 77, r77);
 773         rt61pci_bbp_write(rt2x00dev, 3, r3);
 774         rt61pci_bbp_write(rt2x00dev, 4, r4);
 775 }
 776
 777 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 778                                       struct antenna_setup *ant)
 779 {
 780         u8 r3;
 781         u8 r4;
 782         u8 r77;
 783
 784         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 785         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 786         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 787
 788         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 789                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 790         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 791                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 792
 793         /*
 794          * Configure the RX antenna.
 795          */
 796         switch (ant->rx) {
 797         case ANTENNA_HW_DIVERSITY:
 798                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 799                 break;
 800         case ANTENNA_A:
 801                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 802                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 803                 break;
 804         case ANTENNA_B:
 805         default:
 806                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 807                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 808                 break;
 809         }
 810
 811         rt61pci_bbp_write(rt2x00dev, 77, r77);
 812         rt61pci_bbp_write(rt2x00dev, 3, r3);
 813         rt61pci_bbp_write(rt2x00dev, 4, r4);
 814 }
 815
 816 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 817                                            const int p1, const int p2)
 818 {
 819         u32 reg;
 820
 821         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 822
 823         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 824         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 825
 826         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 827         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 828
 829         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 830 }
 831
 832 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 833                                         struct antenna_setup *ant)
 834 {
 835         u8 r3;
 836         u8 r4;
 837         u8 r77;
 838
 839         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 840         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 841         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 842
 843         /*
 844          * Configure the RX antenna.
 845          */
 846         switch (ant->rx) {
 847         case ANTENNA_A:
 848                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 849                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 850                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 851                 break;
 852         case ANTENNA_HW_DIVERSITY:
 853                 /*
 854                  * FIXME: Antenna selection for the rf 2529 is very confusing
 855                  * in the legacy driver. Just default to antenna B until the
 856                  * legacy code can be properly translated into rt2x00 code.
 857                  */
 858         case ANTENNA_B:
 859         default:
 860                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 861                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 862                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 863                 break;
 864         }
 865
 866         rt61pci_bbp_write(rt2x00dev, 77, r77);
 867         rt61pci_bbp_write(rt2x00dev, 3, r3);
 868         rt61pci_bbp_write(rt2x00dev, 4, r4);
 869 }
 870
 871 struct antenna_sel {
 872         u8 word;
 873         /*
 874          * value[0] -> non-LNA
 875          * value[1] -> LNA
 876          */
 877         u8 value[2];
 878 };
 879
 880 static const struct antenna_sel antenna_sel_a[] = {
 881         { 96,  { 0x58, 0x78 } },
 882         { 104, { 0x38, 0x48 } },
 883         { 75,  { 0xfe, 0x80 } },
 884         { 86,  { 0xfe, 0x80 } },
 885         { 88,  { 0xfe, 0x80 } },
 886         { 35,  { 0x60, 0x60 } },
 887         { 97,  { 0x58, 0x58 } },
 888         { 98,  { 0x58, 0x58 } },
 889 };
 890
 891 static const struct antenna_sel antenna_sel_bg[] = {
 892         { 96,  { 0x48, 0x68 } },
 893         { 104, { 0x2c, 0x3c } },
 894         { 75,  { 0xfe, 0x80 } },
 895         { 86,  { 0xfe, 0x80 } },
 896         { 88,  { 0xfe, 0x80 } },
 897         { 35,  { 0x50, 0x50 } },
 898         { 97,  { 0x48, 0x48 } },
 899         { 98,  { 0x48, 0x48 } },
 900 };
 901
 902 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 903                                    struct antenna_setup *ant)
 904 {
 905         const struct antenna_sel *sel;
 906         unsigned int lna;
 907         unsigned int i;
 908         u32 reg;
 909
 910         /*
 911          * We should never come here because rt2x00lib is supposed
 912          * to catch this and send us the correct antenna explicitely.
 913          */
 914         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 915                ant->tx == ANTENNA_SW_DIVERSITY);
 916
 917         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 918                 sel = antenna_sel_a;
 919                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 920         } else {
 921                 sel = antenna_sel_bg;
 922                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 923         }
 924
 925         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 926                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 927
 928         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 929
 930         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 931                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 932         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 933                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 934
 935         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 936
 937         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 938             rt2x00_rf(&rt2x00dev->chip, RF5325))
 939                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 940         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 941                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 942         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 943                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 944                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 945                 else
 946                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 947         }
 948 }
 949
 950 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 951                                     struct rt2x00lib_conf *libconf)
 952 {
 953         u32 reg;
 954
 955         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 956         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 957         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 958
 959         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 960         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 961         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 962         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 963         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 964
 965         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 966         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 967         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 968
 969         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 970         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 971         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 972
 973         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 974         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 975                            libconf->conf->beacon_int * 16);
 976         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 977 }
 978
 979 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 980                            struct rt2x00lib_conf *libconf,
 981                            const unsigned int flags)
 982 {
 983         /* Always recalculate LNA gain before changing configuration */
 984         rt61pci_config_lna_gain(rt2x00dev, libconf);
 985
 986         if (flags & CONFIG_UPDATE_PHYMODE)
 987                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 988         if (flags & CONFIG_UPDATE_CHANNEL)
 989                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 990                                        libconf->conf->power_level);
 991         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 992                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 993         if (flags & CONFIG_UPDATE_ANTENNA)
 994                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 995         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 996                 rt61pci_config_duration(rt2x00dev, libconf);
 997 }
 998
 999 /*
1000  * Link tuning
1001  */
1002 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1003                                struct link_qual *qual)
1004 {
1005         u32 reg;
1006
1007         /*
1008          * Update FCS error count from register.
1009          */
1010         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1011         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1012
1013         /*
1014          * Update False CCA count from register.
1015          */
1016         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1017         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1018 }
1019
1020 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1021 {
1022         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
1023         rt2x00dev->link.vgc_level = 0x20;
1024 }
1025
1026 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1027 {
1028         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
1029         u8 r17;
1030         u8 up_bound;
1031         u8 low_bound;
1032
1033         rt61pci_bbp_read(rt2x00dev, 17, &r17);
1034
1035         /*
1036          * Determine r17 bounds.
1037          */
1038         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1039                 low_bound = 0x28;
1040                 up_bound = 0x48;
1041                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1042                         low_bound += 0x10;
1043                         up_bound += 0x10;
1044                 }
1045         } else {
1046                 low_bound = 0x20;
1047                 up_bound = 0x40;
1048                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1049                         low_bound += 0x10;
1050                         up_bound += 0x10;
1051                 }
1052         }
1053
1054         /*
1055          * If we are not associated, we should go straight to the
1056          * dynamic CCA tuning.
1057          */
1058         if (!rt2x00dev->intf_associated)
1059                 goto dynamic_cca_tune;
1060
1061         /*
1062          * Special big-R17 for very short distance
1063          */
1064         if (rssi >= -35) {
1065                 if (r17 != 0x60)
1066                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
1067                 return;
1068         }
1069
1070         /*
1071          * Special big-R17 for short distance
1072          */
1073         if (rssi >= -58) {
1074                 if (r17 != up_bound)
1075                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1076                 return;
1077         }
1078
1079         /*
1080          * Special big-R17 for middle-short distance
1081          */
1082         if (rssi >= -66) {
1083                 low_bound += 0x10;
1084                 if (r17 != low_bound)
1085                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1086                 return;
1087         }
1088
1089         /*
1090          * Special mid-R17 for middle distance
1091          */
1092         if (rssi >= -74) {
1093                 low_bound += 0x08;
1094                 if (r17 != low_bound)
1095                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
1096                 return;
1097         }
1098
1099         /*
1100          * Special case: Change up_bound based on the rssi.
1101          * Lower up_bound when rssi is weaker then -74 dBm.
1102          */
1103         up_bound -= 2 * (-74 - rssi);
1104         if (low_bound > up_bound)
1105                 up_bound = low_bound;
1106
1107         if (r17 > up_bound) {
1108                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
1109                 return;
1110         }
1111
1112 dynamic_cca_tune:
1113
1114         /*
1115          * r17 does not yet exceed upper limit, continue and base
1116          * the r17 tuning on the false CCA count.
1117          */
1118         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
1119                 if (++r17 > up_bound)
1120                         r17 = up_bound;
1121                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1122         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
1123                 if (--r17 < low_bound)
1124                         r17 = low_bound;
1125                 rt61pci_bbp_write(rt2x00dev, 17, r17);
1126         }
1127 }
1128
1129 /*
1130  * Firmware functions
1131  */
1132 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1133 {
1134         char *fw_name;
1135
1136         switch (rt2x00dev->chip.rt) {
1137         case RT2561:
1138                 fw_name = FIRMWARE_RT2561;
1139                 break;
1140         case RT2561s:
1141                 fw_name = FIRMWARE_RT2561s;
1142                 break;
1143         case RT2661:
1144                 fw_name = FIRMWARE_RT2661;
1145                 break;
1146         default:
1147                 fw_name = NULL;
1148                 break;
1149         }
1150
1151         return fw_name;
1152 }
1153
1154 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1155 {
1156         u16 crc;
1157
1158         /*
1159          * Use the crc itu-t algorithm.
1160          * The last 2 bytes in the firmware array are the crc checksum itself,
1161          * this means that we should never pass those 2 bytes to the crc
1162          * algorithm.
1163          */
1164         crc = crc_itu_t(0, data, len - 2);
1165         crc = crc_itu_t_byte(crc, 0);
1166         crc = crc_itu_t_byte(crc, 0);
1167
1168         return crc;
1169 }
1170
1171 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1172                                  const size_t len)
1173 {
1174         int i;
1175         u32 reg;
1176
1177         /*
1178          * Wait for stable hardware.
1179          */
1180         for (i = 0; i < 100; i++) {
1181                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1182                 if (reg)
1183                         break;
1184                 msleep(1);
1185         }
1186
1187         if (!reg) {
1188                 ERROR(rt2x00dev, "Unstable hardware.\n");
1189                 return -EBUSY;
1190         }
1191
1192         /*
1193          * Prepare MCU and mailbox for firmware loading.
1194          */
1195         reg = 0;
1196         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1197         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1198         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1199         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1200         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1201
1202         /*
1203          * Write firmware to device.
1204          */
1205         reg = 0;
1206         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1207         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1208         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1209
1210         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1211                                       data, len);
1212
1213         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1214         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1215
1216         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1217         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1218
1219         for (i = 0; i < 100; i++) {
1220                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1221                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1222                         break;
1223                 msleep(1);
1224         }
1225
1226         if (i == 100) {
1227                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1228                 return -EBUSY;
1229         }
1230
1231         /*
1232          * Hardware needs another millisecond before it is ready.
1233          */
1234         msleep(1);
1235
1236         /*
1237          * Reset MAC and BBP registers.
1238          */
1239         reg = 0;
1240         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1241         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1242         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1243
1244         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1245         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1246         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1247         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1248
1249         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1250         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1251         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1252
1253         return 0;
1254 }
1255
1256 /*
1257  * Initialization functions.
1258  */
1259 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1260                                  struct queue_entry *entry)
1261 {
1262         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1263         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1264         u32 word;
1265
1266         rt2x00_desc_read(entry_priv->desc, 5, &word);
1267         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1268                            skbdesc->skb_dma);
1269         rt2x00_desc_write(entry_priv->desc, 5, word);
1270
1271         rt2x00_desc_read(entry_priv->desc, 0, &word);
1272         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1273         rt2x00_desc_write(entry_priv->desc, 0, word);
1274 }
1275
1276 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1277                                  struct queue_entry *entry)
1278 {
1279         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1280         u32 word;
1281
1282         rt2x00_desc_read(entry_priv->desc, 0, &word);
1283         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1284         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1285         rt2x00_desc_write(entry_priv->desc, 0, word);
1286 }
1287
1288 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1289 {
1290         struct queue_entry_priv_pci *entry_priv;
1291         u32 reg;
1292
1293         /*
1294          * Initialize registers.
1295          */
1296         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1297         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1298                            rt2x00dev->tx[0].limit);
1299         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1300                            rt2x00dev->tx[1].limit);
1301         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1302                            rt2x00dev->tx[2].limit);
1303         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1304                            rt2x00dev->tx[3].limit);
1305         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1306
1307         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1308         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1309                            rt2x00dev->tx[0].desc_size / 4);
1310         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1311
1312         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1313         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1314         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1315                            entry_priv->desc_dma);
1316         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1317
1318         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1319         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1320         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1321                            entry_priv->desc_dma);
1322         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1323
1324         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1325         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1326         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1327                            entry_priv->desc_dma);
1328         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1329
1330         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1331         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1332         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1333                            entry_priv->desc_dma);
1334         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1335
1336         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1337         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1338         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1339                            rt2x00dev->rx->desc_size / 4);
1340         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1341         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1342
1343         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1344         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1345         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1346                            entry_priv->desc_dma);
1347         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1348
1349         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1350         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1351         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1352         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1353         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1354         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1355
1356         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1357         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1358         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1359         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1360         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1361         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1362
1363         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1364         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1365         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1366
1367         return 0;
1368 }
1369
1370 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1371 {
1372         u32 reg;
1373
1374         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1375         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1376         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1377         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1378         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1379
1380         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1381         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1382         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1383         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1384         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1385         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1386         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1387         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1388         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1389         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1390
1391         /*
1392          * CCK TXD BBP registers
1393          */
1394         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1395         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1396         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1397         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1398         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1399         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1400         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1401         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1402         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1403         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1404
1405         /*
1406          * OFDM TXD BBP registers
1407          */
1408         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1409         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1410         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1411         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1412         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1413         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1414         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1415         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1416
1417         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1418         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1419         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1420         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1421         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1422         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1423
1424         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1425         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1426         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1427         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1428         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1430
1431         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1432         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1433         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1434         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1435         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1436         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1437         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1438         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1439
1440         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1441
1442         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1443
1444         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1445         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1446         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1447
1448         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1449
1450         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1451                 return -EBUSY;
1452
1453         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1454
1455         /*
1456          * Invalidate all Shared Keys (SEC_CSR0),
1457          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1458          */
1459         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1460         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1461         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1462
1463         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1464         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1465         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1466         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1467
1468         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1469
1470         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1471
1472         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1473
1474         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1475         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1476         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1477         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1478
1479         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1480         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1481         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1482         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1483
1484         /*
1485          * Clear all beacons
1486          * For the Beacon base registers we only need to clear
1487          * the first byte since that byte contains the VALID and OWNER
1488          * bits which (when set to 0) will invalidate the entire beacon.
1489          */
1490         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1491         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1492         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1493         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1494
1495         /*
1496          * We must clear the error counters.
1497          * These registers are cleared on read,
1498          * so we may pass a useless variable to store the value.
1499          */
1500         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1501         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1502         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1503
1504         /*
1505          * Reset MAC and BBP registers.
1506          */
1507         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1508         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1509         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1510         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1511
1512         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1513         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1514         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1515         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1516
1517         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1518         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1519         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1520
1521         return 0;
1522 }
1523
1524 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1525 {
1526         unsigned int i;
1527         u8 value;
1528
1529         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1530                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1531                 if ((value != 0xff) && (value != 0x00))
1532                         return 0;
1533                 udelay(REGISTER_BUSY_DELAY);
1534         }
1535
1536         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1537         return -EACCES;
1538 }
1539
1540 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1541 {
1542         unsigned int i;
1543         u16 eeprom;
1544         u8 reg_id;
1545         u8 value;
1546
1547         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1548                 return -EACCES;
1549
1550         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1551         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1552         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1553         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1554         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1555         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1556         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1557         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1558         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1559         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1560         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1561         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1562         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1563         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1564         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1565         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1566         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1567         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1568         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1569         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1570         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1571         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1572         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1573         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1574
1575         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1576                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1577
1578                 if (eeprom != 0xffff && eeprom != 0x0000) {
1579                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1580                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1581                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1582                 }
1583         }
1584
1585         return 0;
1586 }
1587
1588 /*
1589  * Device state switch handlers.
1590  */
1591 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1592                               enum dev_state state)
1593 {
1594         u32 reg;
1595
1596         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1597         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1598                            (state == STATE_RADIO_RX_OFF) ||
1599                            (state == STATE_RADIO_RX_OFF_LINK));
1600         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1601 }
1602
1603 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1604                                enum dev_state state)
1605 {
1606         int mask = (state == STATE_RADIO_IRQ_OFF);
1607         u32 reg;
1608
1609         /*
1610          * When interrupts are being enabled, the interrupt registers
1611          * should clear the register to assure a clean state.
1612          */
1613         if (state == STATE_RADIO_IRQ_ON) {
1614                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1615                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1616
1617                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1618                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1619         }
1620
1621         /*
1622          * Only toggle the interrupts bits we are going to use.
1623          * Non-checked interrupt bits are disabled by default.
1624          */
1625         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1626         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1627         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1628         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1629         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1630         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1631
1632         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1633         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1634         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1635         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1636         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1637         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1638         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1639         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1640         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1641         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1642 }
1643
1644 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1645 {
1646         u32 reg;
1647
1648         /*
1649          * Initialize all registers.
1650          */
1651         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1652                      rt61pci_init_registers(rt2x00dev) ||
1653                      rt61pci_init_bbp(rt2x00dev)))
1654                 return -EIO;
1655
1656         /*
1657          * Enable RX.
1658          */
1659         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1660         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1661         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1662
1663         return 0;
1664 }
1665
1666 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1667 {
1668         u32 reg;
1669
1670         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1671
1672         /*
1673          * Disable synchronisation.
1674          */
1675         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1676
1677         /*
1678          * Cancel RX and TX.
1679          */
1680         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1681         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1682         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1683         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1684         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1685         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1686 }
1687
1688 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1689 {
1690         u32 reg;
1691         unsigned int i;
1692         char put_to_sleep;
1693
1694         put_to_sleep = (state != STATE_AWAKE);
1695
1696         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1697         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1698         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1699         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1700
1701         /*
1702          * Device is not guaranteed to be in the requested state yet.
1703          * We must wait until the register indicates that the
1704          * device has entered the correct state.
1705          */
1706         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1707                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1708                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1709                 if (state == !put_to_sleep)
1710                         return 0;
1711                 msleep(10);
1712         }
1713
1714         return -EBUSY;
1715 }
1716
1717 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1718                                     enum dev_state state)
1719 {
1720         int retval = 0;
1721
1722         switch (state) {
1723         case STATE_RADIO_ON:
1724                 retval = rt61pci_enable_radio(rt2x00dev);
1725                 break;
1726         case STATE_RADIO_OFF:
1727                 rt61pci_disable_radio(rt2x00dev);
1728                 break;
1729         case STATE_RADIO_RX_ON:
1730         case STATE_RADIO_RX_ON_LINK:
1731         case STATE_RADIO_RX_OFF:
1732         case STATE_RADIO_RX_OFF_LINK:
1733                 rt61pci_toggle_rx(rt2x00dev, state);
1734                 break;
1735         case STATE_RADIO_IRQ_ON:
1736         case STATE_RADIO_IRQ_OFF:
1737                 rt61pci_toggle_irq(rt2x00dev, state);
1738                 break;
1739         case STATE_DEEP_SLEEP:
1740         case STATE_SLEEP:
1741         case STATE_STANDBY:
1742         case STATE_AWAKE:
1743                 retval = rt61pci_set_state(rt2x00dev, state);
1744                 break;
1745         default:
1746                 retval = -ENOTSUPP;
1747                 break;
1748         }
1749
1750         if (unlikely(retval))
1751                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1752                       state, retval);
1753
1754         return retval;
1755 }
1756
1757 /*
1758  * TX descriptor initialization
1759  */
1760 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1761                                   struct sk_buff *skb,
1762                                   struct txentry_desc *txdesc)
1763 {
1764         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1765         __le32 *txd = skbdesc->desc;
1766         u32 word;
1767
1768         /*
1769          * Start writing the descriptor words.
1770          */
1771         rt2x00_desc_read(txd, 1, &word);
1772         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1773         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1774         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1775         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1776         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1777         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1778                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1779         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1780         rt2x00_desc_write(txd, 1, word);
1781
1782         rt2x00_desc_read(txd, 2, &word);
1783         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1784         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1785         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1786         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1787         rt2x00_desc_write(txd, 2, word);
1788
1789         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1790                 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1791                 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1792         }
1793
1794         rt2x00_desc_read(txd, 5, &word);
1795         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1796         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1797                            skbdesc->entry->entry_idx);
1798         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1799                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1800         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1801         rt2x00_desc_write(txd, 5, word);
1802
1803         rt2x00_desc_read(txd, 6, &word);
1804         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1805                            skbdesc->skb_dma);
1806         rt2x00_desc_write(txd, 6, word);
1807
1808         if (skbdesc->desc_len > TXINFO_SIZE) {
1809                 rt2x00_desc_read(txd, 11, &word);
1810                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1811                 rt2x00_desc_write(txd, 11, word);
1812         }
1813
1814         rt2x00_desc_read(txd, 0, &word);
1815         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1816         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1817         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1818                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1819         rt2x00_set_field32(&word, TXD_W0_ACK,
1820                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1821         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1822                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1823         rt2x00_set_field32(&word, TXD_W0_OFDM,
1824                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1825         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1826         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1827                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1828         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1829                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1830         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1831                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1832         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1833         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1834         rt2x00_set_field32(&word, TXD_W0_BURST,
1835                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1836         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1837         rt2x00_desc_write(txd, 0, word);
1838 }
1839
1840 /*
1841  * TX data initialization
1842  */
1843 static void rt61pci_write_beacon(struct queue_entry *entry)
1844 {
1845         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1846         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1847         unsigned int beacon_base;
1848         u32 reg;
1849
1850         /*
1851          * Disable beaconing while we are reloading the beacon data,
1852          * otherwise we might be sending out invalid data.
1853          */
1854         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1855         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1856         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1857         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1858         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1859
1860         /*
1861          * Write entire beacon with descriptor to register.
1862          */
1863         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1864         rt2x00pci_register_multiwrite(rt2x00dev,
1865                                       beacon_base,
1866                                       skbdesc->desc, skbdesc->desc_len);
1867         rt2x00pci_register_multiwrite(rt2x00dev,
1868                                       beacon_base + skbdesc->desc_len,
1869                                       entry->skb->data, entry->skb->len);
1870
1871         /*
1872          * Clean up beacon skb.
1873          */
1874         dev_kfree_skb_any(entry->skb);
1875         entry->skb = NULL;
1876 }
1877
1878 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1879                                   const enum data_queue_qid queue)
1880 {
1881         u32 reg;
1882
1883         if (queue == QID_BEACON) {
1884                 /*
1885                  * For Wi-Fi faily generated beacons between participating
1886                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1887                  */
1888                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1889
1890                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1891                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1892                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1893                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1894                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1895                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1896                 }
1897                 return;
1898         }
1899
1900         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1901         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1902         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1903         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1904         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1905         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1906 }
1907
1908 /*
1909  * RX control handlers
1910  */
1911 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1912 {
1913         u8 offset = rt2x00dev->lna_gain;
1914         u8 lna;
1915
1916         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1917         switch (lna) {
1918         case 3:
1919                 offset += 90;
1920                 break;
1921         case 2:
1922                 offset += 74;
1923                 break;
1924         case 1:
1925                 offset += 64;
1926                 break;
1927         default:
1928                 return 0;
1929         }
1930
1931         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1932                 if (lna == 3 || lna == 2)
1933                         offset += 10;
1934         }
1935
1936         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1937 }
1938
1939 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1940                                 struct rxdone_entry_desc *rxdesc)
1941 {
1942         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1943         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1944         u32 word0;
1945         u32 word1;
1946
1947         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1948         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1949
1950         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1951                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1952
1953         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1954                 rxdesc->cipher =
1955                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1956                 rxdesc->cipher_status =
1957                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1958         }
1959
1960         if (rxdesc->cipher != CIPHER_NONE) {
1961                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv);
1962                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->eiv);
1963                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1964
1965                 /*
1966                  * Hardware has stripped IV/EIV data from 802.11 frame during
1967                  * decryption. It has provided the data seperately but rt2x00lib
1968                  * should decide if it should be reinserted.
1969                  */
1970                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1971
1972                 /*
1973                  * FIXME: Legacy driver indicates that the frame does
1974                  * contain the Michael Mic. Unfortunately, in rt2x00
1975                  * the MIC seems to be missing completely...
1976                  */
1977                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1978
1979                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1980                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1981                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1982                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1983         }
1984
1985         /*
1986          * Obtain the status about this packet.
1987          * When frame was received with an OFDM bitrate,
1988          * the signal is the PLCP value. If it was received with
1989          * a CCK bitrate the signal is the rate in 100kbit/s.
1990          */
1991         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1992         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
1993         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1994
1995         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1996                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1997         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1998                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1999 }
2000
2001 /*
2002  * Interrupt functions.
2003  */
2004 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2005 {
2006         struct data_queue *queue;
2007         struct queue_entry *entry;
2008         struct queue_entry *entry_done;
2009         struct queue_entry_priv_pci *entry_priv;
2010         struct txdone_entry_desc txdesc;
2011         u32 word;
2012         u32 reg;
2013         u32 old_reg;
2014         int type;
2015         int index;
2016
2017         /*
2018          * During each loop we will compare the freshly read
2019          * STA_CSR4 register value with the value read from
2020          * the previous loop. If the 2 values are equal then
2021          * we should stop processing because the chance it
2022          * quite big that the device has been unplugged and
2023          * we risk going into an endless loop.
2024          */
2025         old_reg = 0;
2026
2027         while (1) {
2028                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2029                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2030                         break;
2031
2032                 if (old_reg == reg)
2033                         break;
2034                 old_reg = reg;
2035
2036                 /*
2037                  * Skip this entry when it contains an invalid
2038                  * queue identication number.
2039                  */
2040                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2041                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2042                 if (unlikely(!queue))
2043                         continue;
2044
2045                 /*
2046                  * Skip this entry when it contains an invalid
2047                  * index number.
2048                  */
2049                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2050                 if (unlikely(index >= queue->limit))
2051                         continue;
2052
2053                 entry = &queue->entries[index];
2054                 entry_priv = entry->priv_data;
2055                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2056
2057                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2058                     !rt2x00_get_field32(word, TXD_W0_VALID))
2059                         return;
2060
2061                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2062                 while (entry != entry_done) {
2063                         /* Catch up.
2064                          * Just report any entries we missed as failed.
2065                          */
2066                         WARNING(rt2x00dev,
2067                                 "TX status report missed for entry %d\n",
2068                                 entry_done->entry_idx);
2069
2070                         txdesc.flags = 0;
2071                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2072                         txdesc.retry = 0;
2073
2074                         rt2x00lib_txdone(entry_done, &txdesc);
2075                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2076                 }
2077
2078                 /*
2079                  * Obtain the status about this packet.
2080                  */
2081                 txdesc.flags = 0;
2082                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2083                 case 0: /* Success, maybe with retry */
2084                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2085                         break;
2086                 case 6: /* Failure, excessive retries */
2087                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2088                         /* Don't break, this is a failed frame! */
2089                 default: /* Failure */
2090                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2091                 }
2092                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2093
2094                 rt2x00lib_txdone(entry, &txdesc);
2095         }
2096 }
2097
2098 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2099 {
2100         struct rt2x00_dev *rt2x00dev = dev_instance;
2101         u32 reg_mcu;
2102         u32 reg;
2103
2104         /*
2105          * Get the interrupt sources & saved to local variable.
2106          * Write register value back to clear pending interrupts.
2107          */
2108         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2109         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2110
2111         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2112         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2113
2114         if (!reg && !reg_mcu)
2115                 return IRQ_NONE;
2116
2117         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
2118                 return IRQ_HANDLED;
2119
2120         /*
2121          * Handle interrupts, walk through all bits
2122          * and run the tasks, the bits are checked in order of
2123          * priority.
2124          */
2125
2126         /*
2127          * 1 - Rx ring done interrupt.
2128          */
2129         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2130                 rt2x00pci_rxdone(rt2x00dev);
2131
2132         /*
2133          * 2 - Tx ring done interrupt.
2134          */
2135         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2136                 rt61pci_txdone(rt2x00dev);
2137
2138         /*
2139          * 3 - Handle MCU command done.
2140          */
2141         if (reg_mcu)
2142                 rt2x00pci_register_write(rt2x00dev,
2143                                          M2H_CMD_DONE_CSR, 0xffffffff);
2144
2145         return IRQ_HANDLED;
2146 }
2147
2148 /*
2149  * Device probe functions.
2150  */
2151 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2152 {
2153         struct eeprom_93cx6 eeprom;
2154         u32 reg;
2155         u16 word;
2156         u8 *mac;
2157         s8 value;
2158
2159         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2160
2161         eeprom.data = rt2x00dev;
2162         eeprom.register_read = rt61pci_eepromregister_read;
2163         eeprom.register_write = rt61pci_eepromregister_write;
2164         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2165             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2166         eeprom.reg_data_in = 0;
2167         eeprom.reg_data_out = 0;
2168         eeprom.reg_data_clock = 0;
2169         eeprom.reg_chip_select = 0;
2170
2171         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2172                                EEPROM_SIZE / sizeof(u16));
2173
2174         /*
2175          * Start validation of the data that has been read.
2176          */
2177         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2178         if (!is_valid_ether_addr(mac)) {
2179                 DECLARE_MAC_BUF(macbuf);
2180
2181                 random_ether_addr(mac);
2182                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2183         }
2184
2185         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2186         if (word == 0xffff) {
2187                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2188                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2189                                    ANTENNA_B);
2190                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2191                                    ANTENNA_B);
2192                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2193                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2194                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2195                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2196                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2197                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2198         }
2199
2200         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2201         if (word == 0xffff) {
2202                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2203                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2204                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2205                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2206                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2207                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2208                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2209                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2210         }
2211
2212         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2213         if (word == 0xffff) {
2214                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2215                                    LED_MODE_DEFAULT);
2216                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2217                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2218         }
2219
2220         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2221         if (word == 0xffff) {
2222                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2223                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2224                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2225                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2226         }
2227
2228         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2229         if (word == 0xffff) {
2230                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2231                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2232                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2233                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2234         } else {
2235                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2236                 if (value < -10 || value > 10)
2237                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2238                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2239                 if (value < -10 || value > 10)
2240                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2241                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2242         }
2243
2244         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2245         if (word == 0xffff) {
2246                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2247                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2248                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2249                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2250         } else {
2251                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2252                 if (value < -10 || value > 10)
2253                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2254                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2255                 if (value < -10 || value > 10)
2256                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2257                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2258         }
2259
2260         return 0;
2261 }
2262
2263 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2264 {
2265         u32 reg;
2266         u16 value;
2267         u16 eeprom;
2268         u16 device;
2269
2270         /*
2271          * Read EEPROM word for configuration.
2272          */
2273         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2274
2275         /*
2276          * Identify RF chipset.
2277          * To determine the RT chip we have to read the
2278          * PCI header of the device.
2279          */
2280         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2281                              PCI_CONFIG_HEADER_DEVICE, &device);
2282         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2283         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2284         rt2x00_set_chip(rt2x00dev, device, value, reg);
2285
2286         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2287             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2288             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2289             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2290                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2291                 return -ENODEV;
2292         }
2293
2294         /*
2295          * Determine number of antenna's.
2296          */
2297         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2298                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2299
2300         /*
2301          * Identify default antenna configuration.
2302          */
2303         rt2x00dev->default_ant.tx =
2304             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2305         rt2x00dev->default_ant.rx =
2306             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2307
2308         /*
2309          * Read the Frame type.
2310          */
2311         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2312                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2313
2314         /*
2315          * Detect if this device has an hardware controlled radio.
2316          */
2317 #ifdef CONFIG_RT61PCI_RFKILL
2318         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2319                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2320 #endif /* CONFIG_RT61PCI_RFKILL */
2321
2322         /*
2323          * Read frequency offset and RF programming sequence.
2324          */
2325         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2326         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2327                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2328
2329         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2330
2331         /*
2332          * Read external LNA informations.
2333          */
2334         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2335
2336         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2337                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2338         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2339                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2340
2341         /*
2342          * When working with a RF2529 chip without double antenna
2343          * the antenna settings should be gathered from the NIC
2344          * eeprom word.
2345          */
2346         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2347             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2348                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2349                 case 0:
2350                         rt2x00dev->default_ant.tx = ANTENNA_B;
2351                         rt2x00dev->default_ant.rx = ANTENNA_A;
2352                         break;
2353                 case 1:
2354                         rt2x00dev->default_ant.tx = ANTENNA_B;
2355                         rt2x00dev->default_ant.rx = ANTENNA_B;
2356                         break;
2357                 case 2:
2358                         rt2x00dev->default_ant.tx = ANTENNA_A;
2359                         rt2x00dev->default_ant.rx = ANTENNA_A;
2360                         break;
2361                 case 3:
2362                         rt2x00dev->default_ant.tx = ANTENNA_A;
2363                         rt2x00dev->default_ant.rx = ANTENNA_B;
2364                         break;
2365                 }
2366
2367                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2368                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2369                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2370                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2371         }
2372
2373         /*
2374          * Store led settings, for correct led behaviour.
2375          * If the eeprom value is invalid,
2376          * switch to default led mode.
2377          */
2378 #ifdef CONFIG_RT61PCI_LEDS
2379         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2380         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2381
2382         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2383         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2384         if (value == LED_MODE_SIGNAL_STRENGTH)
2385                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2386                                  LED_TYPE_QUALITY);
2387
2388         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2389         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2390                            rt2x00_get_field16(eeprom,
2391                                               EEPROM_LED_POLARITY_GPIO_0));
2392         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2393                            rt2x00_get_field16(eeprom,
2394                                               EEPROM_LED_POLARITY_GPIO_1));
2395         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2396                            rt2x00_get_field16(eeprom,
2397                                               EEPROM_LED_POLARITY_GPIO_2));
2398         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2399                            rt2x00_get_field16(eeprom,
2400                                               EEPROM_LED_POLARITY_GPIO_3));
2401         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2402                            rt2x00_get_field16(eeprom,
2403                                               EEPROM_LED_POLARITY_GPIO_4));
2404         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2405                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2406         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2407                            rt2x00_get_field16(eeprom,
2408                                               EEPROM_LED_POLARITY_RDY_G));
2409         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2410                            rt2x00_get_field16(eeprom,
2411                                               EEPROM_LED_POLARITY_RDY_A));
2412 #endif /* CONFIG_RT61PCI_LEDS */
2413
2414         return 0;
2415 }
2416
2417 /*
2418  * RF value list for RF5225 & RF5325
2419  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2420  */
2421 static const struct rf_channel rf_vals_noseq[] = {
2422         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2423         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2424         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2425         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2426         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2427         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2428         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2429         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2430         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2431         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2432         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2433         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2434         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2435         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2436
2437         /* 802.11 UNI / HyperLan 2 */
2438         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2439         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2440         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2441         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2442         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2443         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2444         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2445         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2446
2447         /* 802.11 HyperLan 2 */
2448         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2449         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2450         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2451         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2452         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2453         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2454         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2455         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2456         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2457         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2458
2459         /* 802.11 UNII */
2460         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2461         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2462         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2463         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2464         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2465         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2466
2467         /* MMAC(Japan)J52 ch 34,38,42,46 */
2468         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2469         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2470         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2471         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2472 };
2473
2474 /*
2475  * RF value list for RF5225 & RF5325
2476  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2477  */
2478 static const struct rf_channel rf_vals_seq[] = {
2479         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2480         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2481         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2482         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2483         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2484         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2485         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2486         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2487         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2488         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2489         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2490         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2491         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2492         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2493
2494         /* 802.11 UNI / HyperLan 2 */
2495         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2496         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2497         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2498         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2499         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2500         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2501         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2502         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2503
2504         /* 802.11 HyperLan 2 */
2505         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2506         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2507         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2508         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2509         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2510         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2511         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2512         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2513         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2514         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2515
2516         /* 802.11 UNII */
2517         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2518         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2519         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2520         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2521         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2522         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2523
2524         /* MMAC(Japan)J52 ch 34,38,42,46 */
2525         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2526         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2527         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2528         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2529 };
2530
2531 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2532 {
2533         struct hw_mode_spec *spec = &rt2x00dev->spec;
2534         struct channel_info *info;
2535         char *tx_power;
2536         unsigned int i;
2537
2538         /*
2539          * Initialize all hw fields.
2540          */
2541         rt2x00dev->hw->flags =
2542             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2543             IEEE80211_HW_SIGNAL_DBM;
2544         rt2x00dev->hw->extra_tx_headroom = 0;
2545
2546         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2547         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2548                                 rt2x00_eeprom_addr(rt2x00dev,
2549                                                    EEPROM_MAC_ADDR_0));
2550
2551         /*
2552          * Initialize hw_mode information.
2553          */
2554         spec->supported_bands = SUPPORT_BAND_2GHZ;
2555         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2556
2557         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2558                 spec->num_channels = 14;
2559                 spec->channels = rf_vals_noseq;
2560         } else {
2561                 spec->num_channels = 14;
2562                 spec->channels = rf_vals_seq;
2563         }
2564
2565         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2566             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2567                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2568                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2569         }
2570
2571         /*
2572          * Create channel information array
2573          */
2574         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2575         if (!info)
2576                 return -ENOMEM;
2577
2578         spec->channels_info = info;
2579
2580         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2581         for (i = 0; i < 14; i++)
2582                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2583
2584         if (spec->num_channels > 14) {
2585                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2586                 for (i = 14; i < spec->num_channels; i++)
2587                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2588         }
2589
2590         return 0;
2591 }
2592
2593 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2594 {
2595         int retval;
2596
2597         /*
2598          * Allocate eeprom data.
2599          */
2600         retval = rt61pci_validate_eeprom(rt2x00dev);
2601         if (retval)
2602                 return retval;
2603
2604         retval = rt61pci_init_eeprom(rt2x00dev);
2605         if (retval)
2606                 return retval;
2607
2608         /*
2609          * Initialize hw specifications.
2610          */
2611         retval = rt61pci_probe_hw_mode(rt2x00dev);
2612         if (retval)
2613                 return retval;
2614
2615         /*
2616          * This device requires firmware and DMA mapped skbs.
2617          */
2618         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2619         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2620         __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2621
2622         /*
2623          * Set the rssi offset.
2624          */
2625         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2626
2627         return 0;
2628 }
2629
2630 /*
2631  * IEEE80211 stack callback functions.
2632  */
2633 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2634                                    u32 short_retry, u32 long_retry)
2635 {
2636         struct rt2x00_dev *rt2x00dev = hw->priv;
2637         u32 reg;
2638
2639         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2640         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2641         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2642         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2643
2644         return 0;
2645 }
2646
2647 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2648 {
2649         struct rt2x00_dev *rt2x00dev = hw->priv;
2650         u64 tsf;
2651         u32 reg;
2652
2653         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2654         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2655         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2656         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2657
2658         return tsf;
2659 }
2660
2661 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2662         .tx                     = rt2x00mac_tx,
2663         .start                  = rt2x00mac_start,
2664         .stop                   = rt2x00mac_stop,
2665         .add_interface          = rt2x00mac_add_interface,
2666         .remove_interface       = rt2x00mac_remove_interface,
2667         .config                 = rt2x00mac_config,
2668         .config_interface       = rt2x00mac_config_interface,
2669         .configure_filter       = rt2x00mac_configure_filter,
2670         .set_key                = rt2x00mac_set_key,
2671         .get_stats              = rt2x00mac_get_stats,
2672         .set_retry_limit        = rt61pci_set_retry_limit,
2673         .bss_info_changed       = rt2x00mac_bss_info_changed,
2674         .conf_tx                = rt2x00mac_conf_tx,
2675         .get_tx_stats           = rt2x00mac_get_tx_stats,
2676         .get_tsf                = rt61pci_get_tsf,
2677 };
2678
2679 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2680         .irq_handler            = rt61pci_interrupt,
2681         .probe_hw               = rt61pci_probe_hw,
2682         .get_firmware_name      = rt61pci_get_firmware_name,
2683         .get_firmware_crc       = rt61pci_get_firmware_crc,
2684         .load_firmware          = rt61pci_load_firmware,
2685         .initialize             = rt2x00pci_initialize,
2686         .uninitialize           = rt2x00pci_uninitialize,
2687         .init_rxentry           = rt61pci_init_rxentry,
2688         .init_txentry           = rt61pci_init_txentry,
2689         .set_device_state       = rt61pci_set_device_state,
2690         .rfkill_poll            = rt61pci_rfkill_poll,
2691         .link_stats             = rt61pci_link_stats,
2692         .reset_tuner            = rt61pci_reset_tuner,
2693         .link_tuner             = rt61pci_link_tuner,
2694         .write_tx_desc          = rt61pci_write_tx_desc,
2695         .write_tx_data          = rt2x00pci_write_tx_data,
2696         .write_beacon           = rt61pci_write_beacon,
2697         .kick_tx_queue          = rt61pci_kick_tx_queue,
2698         .fill_rxdone            = rt61pci_fill_rxdone,
2699         .config_shared_key      = rt61pci_config_shared_key,
2700         .config_pairwise_key    = rt61pci_config_pairwise_key,
2701         .config_filter          = rt61pci_config_filter,
2702         .config_intf            = rt61pci_config_intf,
2703         .config_erp             = rt61pci_config_erp,
2704         .config                 = rt61pci_config,
2705 };
2706
2707 static const struct data_queue_desc rt61pci_queue_rx = {
2708         .entry_num              = RX_ENTRIES,
2709         .data_size              = DATA_FRAME_SIZE,
2710         .desc_size              = RXD_DESC_SIZE,
2711         .priv_size              = sizeof(struct queue_entry_priv_pci),
2712 };
2713
2714 static const struct data_queue_desc rt61pci_queue_tx = {
2715         .entry_num              = TX_ENTRIES,
2716         .data_size              = DATA_FRAME_SIZE,
2717         .desc_size              = TXD_DESC_SIZE,
2718         .priv_size              = sizeof(struct queue_entry_priv_pci),
2719 };
2720
2721 static const struct data_queue_desc rt61pci_queue_bcn = {
2722         .entry_num              = 4 * BEACON_ENTRIES,
2723         .data_size              = 0, /* No DMA required for beacons */
2724         .desc_size              = TXINFO_SIZE,
2725         .priv_size              = sizeof(struct queue_entry_priv_pci),
2726 };
2727
2728 static const struct rt2x00_ops rt61pci_ops = {
2729         .name           = KBUILD_MODNAME,
2730         .max_sta_intf   = 1,
2731         .max_ap_intf    = 4,
2732         .eeprom_size    = EEPROM_SIZE,
2733         .rf_size        = RF_SIZE,
2734         .tx_queues      = NUM_TX_QUEUES,
2735         .rx             = &rt61pci_queue_rx,
2736         .tx             = &rt61pci_queue_tx,
2737         .bcn            = &rt61pci_queue_bcn,
2738         .lib            = &rt61pci_rt2x00_ops,
2739         .hw             = &rt61pci_mac80211_ops,
2740 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2741         .debugfs        = &rt61pci_rt2x00debug,
2742 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2743 };
2744
2745 /*
2746  * RT61pci module information.
2747  */
2748 static struct pci_device_id rt61pci_device_table[] = {
2749         /* RT2561s */
2750         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2751         /* RT2561 v2 */
2752         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2753         /* RT2661 */
2754         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2755         { 0, }
2756 };
2757
2758 MODULE_AUTHOR(DRV_PROJECT);
2759 MODULE_VERSION(DRV_VERSION);
2760 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2761 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2762                         "PCI & PCMCIA chipset based cards");
2763 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2764 MODULE_FIRMWARE(FIRMWARE_RT2561);
2765 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2766 MODULE_FIRMWARE(FIRMWARE_RT2661);
2767 MODULE_LICENSE("GPL");
2768
2769 static struct pci_driver rt61pci_driver = {
2770         .name           = KBUILD_MODNAME,
2771         .id_table       = rt61pci_device_table,
2772         .probe          = rt2x00pci_probe,
2773         .remove         = __devexit_p(rt2x00pci_remove),
2774         .suspend        = rt2x00pci_suspend,
2775         .resume         = rt2x00pci_resume,
2776 };
2777
2778 static int __init rt61pci_init(void)
2779 {
2780         return pci_register_driver(&rt61pci_driver);
2781 }
2782
2783 static void __exit rt61pci_exit(void)
2784 {
2785         pci_unregister_driver(&rt61pci_driver);
2786 }
2787
2788 module_init(rt61pci_init);
2789 module_exit(rt61pci_exit);