SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
 126                                     const unsigned int word, const u8 value)
 127 {
 128         rt2800usb_bbp_write(rt2x00dev, word, value);
 129 }
 130
 131 static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 132                                    const unsigned int word, u8 *value)
 133 {
 134         rt2800usb_bbp_read(rt2x00dev, word, value);
 135 }
 136
 137 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 138                                   const unsigned int word, const u8 value)
 139 {
 140         u32 reg;
 141
 142         mutex_lock(&rt2x00dev->csr_mutex);
 143
 144         /*
 145          * Wait until the RFCSR becomes available, afterwards we
 146          * can safely write the new data into the register.
 147          */
 148         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 149                 reg = 0;
 150                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 151                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 152                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 153                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 154
 155                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 156         }
 157
 158         mutex_unlock(&rt2x00dev->csr_mutex);
 159 }
 160
 161 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 162                                  const unsigned int word, u8 *value)
 163 {
 164         u32 reg;
 165
 166         mutex_lock(&rt2x00dev->csr_mutex);
 167
 168         /*
 169          * Wait until the RFCSR becomes available, afterwards we
 170          * can safely write the read request into the register.
 171          * After the data has been written, we wait until hardware
 172          * returns the correct value, if at any time the register
 173          * doesn't become available in time, reg will be 0xffffffff
 174          * which means we return 0xff to the caller.
 175          */
 176         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 177                 reg = 0;
 178                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 179                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 180                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 181
 182                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 183
 184                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 185         }
 186
 187         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 188
 189         mutex_unlock(&rt2x00dev->csr_mutex);
 190 }
 191
 192 static inline void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 193                                       const unsigned int word, const u8 value)
 194 {
 195         rt2800usb_rfcsr_write(rt2x00dev, word, value);
 196 }
 197
 198 static inline void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 199                                      const unsigned int word, u8 *value)
 200 {
 201         rt2800usb_rfcsr_read(rt2x00dev, word, value);
 202 }
 203
 204 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 205                                const unsigned int word, const u32 value)
 206 {
 207         u32 reg;
 208
 209         mutex_lock(&rt2x00dev->csr_mutex);
 210
 211         /*
 212          * Wait until the RF becomes available, afterwards we
 213          * can safely write the new data into the register.
 214          */
 215         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 216                 reg = 0;
 217                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 218                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 219                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 220                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 221
 222                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 223                 rt2x00_rf_write(rt2x00dev, word, value);
 224         }
 225
 226         mutex_unlock(&rt2x00dev->csr_mutex);
 227 }
 228
 229 static inline void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 230                                    const unsigned int word, const u32 value)
 231 {
 232         rt2800usb_rf_write(rt2x00dev, word, value);
 233 }
 234
 235 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 236                                   const u8 command, const u8 token,
 237                                   const u8 arg0, const u8 arg1)
 238 {
 239         u32 reg;
 240
 241         mutex_lock(&rt2x00dev->csr_mutex);
 242
 243         /*
 244          * Wait until the MCU becomes available, afterwards we
 245          * can safely write the new data into the register.
 246          */
 247         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 248                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 249                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 250                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 251                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 252                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 253
 254                 reg = 0;
 255                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 256                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 257         }
 258
 259         mutex_unlock(&rt2x00dev->csr_mutex);
 260 }
 261
 262 static inline void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 263                                       const u8 command, const u8 token,
 264                                       const u8 arg0, const u8 arg1)
 265 {
 266         rt2800usb_mcu_request(rt2x00dev, command, token, arg0, arg1);
 267 }
 268
 269 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 270 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 271         .owner  = THIS_MODULE,
 272         .csr    = {
 273                 .read           = rt2800_register_read,
 274                 .write          = rt2800_register_write,
 275                 .flags          = RT2X00DEBUGFS_OFFSET,
 276                 .word_base      = CSR_REG_BASE,
 277                 .word_size      = sizeof(u32),
 278                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 279         },
 280         .eeprom = {
 281                 .read           = rt2x00_eeprom_read,
 282                 .write          = rt2x00_eeprom_write,
 283                 .word_base      = EEPROM_BASE,
 284                 .word_size      = sizeof(u16),
 285                 .word_count     = EEPROM_SIZE / sizeof(u16),
 286         },
 287         .bbp    = {
 288                 .read           = rt2800_bbp_read,
 289                 .write          = rt2800_bbp_write,
 290                 .word_base      = BBP_BASE,
 291                 .word_size      = sizeof(u8),
 292                 .word_count     = BBP_SIZE / sizeof(u8),
 293         },
 294         .rf     = {
 295                 .read           = rt2x00_rf_read,
 296                 .write          = rt2800_rf_write,
 297                 .word_base      = RF_BASE,
 298                 .word_size      = sizeof(u32),
 299                 .word_count     = RF_SIZE / sizeof(u32),
 300         },
 301 };
 302 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 303
 304 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 305 {
 306         u32 reg;
 307
 308         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 309         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 310 }
 311
 312 #ifdef CONFIG_RT2X00_LIB_LEDS
 313 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 314                                      enum led_brightness brightness)
 315 {
 316         struct rt2x00_led *led =
 317             container_of(led_cdev, struct rt2x00_led, led_dev);
 318         unsigned int enabled = brightness != LED_OFF;
 319         unsigned int bg_mode =
 320             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 321         unsigned int polarity =
 322                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 323                                    EEPROM_FREQ_LED_POLARITY);
 324         unsigned int ledmode =
 325                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 326                                    EEPROM_FREQ_LED_MODE);
 327
 328         if (led->type == LED_TYPE_RADIO) {
 329                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 330                                       enabled ? 0x20 : 0);
 331         } else if (led->type == LED_TYPE_ASSOC) {
 332                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 333                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 334         } else if (led->type == LED_TYPE_QUALITY) {
 335                 /*
 336                  * The brightness is divided into 6 levels (0 - 5),
 337                  * The specs tell us the following levels:
 338                  *      0, 1 ,3, 7, 15, 31
 339                  * to determine the level in a simple way we can simply
 340                  * work with bitshifting:
 341                  *      (1 << level) - 1
 342                  */
 343                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 344                                       (1 << brightness / (LED_FULL / 6)) - 1,
 345                                       polarity);
 346         }
 347 }
 348
 349 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 350                                unsigned long *delay_on,
 351                                unsigned long *delay_off)
 352 {
 353         struct rt2x00_led *led =
 354             container_of(led_cdev, struct rt2x00_led, led_dev);
 355         u32 reg;
 356
 357         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 358         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 359         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 360         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 361         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 362         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 363         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 364         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 365         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 366
 367         return 0;
 368 }
 369
 370 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 371                                struct rt2x00_led *led,
 372                                enum led_type type)
 373 {
 374         led->rt2x00dev = rt2x00dev;
 375         led->type = type;
 376         led->led_dev.brightness_set = rt2800usb_brightness_set;
 377         led->led_dev.blink_set = rt2800usb_blink_set;
 378         led->flags = LED_INITIALIZED;
 379 }
 380 #endif /* CONFIG_RT2X00_LIB_LEDS */
 381
 382 /*
 383  * Configuration handlers.
 384  */
 385 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 386                                        struct rt2x00lib_crypto *crypto,
 387                                        struct ieee80211_key_conf *key)
 388 {
 389         struct mac_wcid_entry wcid_entry;
 390         struct mac_iveiv_entry iveiv_entry;
 391         u32 offset;
 392         u32 reg;
 393
 394         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 395
 396         rt2800_register_read(rt2x00dev, offset, &reg);
 397         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 398                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 399         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 400                            (crypto->cmd == SET_KEY) * crypto->cipher);
 401         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 402                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 403         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 404         rt2800_register_write(rt2x00dev, offset, reg);
 405
 406         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 407
 408         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 409         if ((crypto->cipher == CIPHER_TKIP) ||
 410             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 411             (crypto->cipher == CIPHER_AES))
 412                 iveiv_entry.iv[3] |= 0x20;
 413         iveiv_entry.iv[3] |= key->keyidx << 6;
 414         rt2800_register_multiwrite(rt2x00dev, offset,
 415                                       &iveiv_entry, sizeof(iveiv_entry));
 416
 417         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 418
 419         memset(&wcid_entry, 0, sizeof(wcid_entry));
 420         if (crypto->cmd == SET_KEY)
 421                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 422         rt2800_register_multiwrite(rt2x00dev, offset,
 423                                       &wcid_entry, sizeof(wcid_entry));
 424 }
 425
 426 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 427                                        struct rt2x00lib_crypto *crypto,
 428                                        struct ieee80211_key_conf *key)
 429 {
 430         struct hw_key_entry key_entry;
 431         struct rt2x00_field32 field;
 432         u32 offset;
 433         u32 reg;
 434
 435         if (crypto->cmd == SET_KEY) {
 436                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 437
 438                 memcpy(key_entry.key, crypto->key,
 439                        sizeof(key_entry.key));
 440                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 441                        sizeof(key_entry.tx_mic));
 442                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 443                        sizeof(key_entry.rx_mic));
 444
 445                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 446                 rt2800_register_multiwrite(rt2x00dev, offset,
 447                                               &key_entry, sizeof(key_entry));
 448         }
 449
 450         /*
 451          * The cipher types are stored over multiple registers
 452          * starting with SHARED_KEY_MODE_BASE each word will have
 453          * 32 bits and contains the cipher types for 2 bssidx each.
 454          * Using the correct defines correctly will cause overhead,
 455          * so just calculate the correct offset.
 456          */
 457         field.bit_offset = 4 * (key->hw_key_idx % 8);
 458         field.bit_mask = 0x7 << field.bit_offset;
 459
 460         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 461
 462         rt2800_register_read(rt2x00dev, offset, &reg);
 463         rt2x00_set_field32(&reg, field,
 464                            (crypto->cmd == SET_KEY) * crypto->cipher);
 465         rt2800_register_write(rt2x00dev, offset, reg);
 466
 467         /*
 468          * Update WCID information
 469          */
 470         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 471
 472         return 0;
 473 }
 474
 475 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 476                                          struct rt2x00lib_crypto *crypto,
 477                                          struct ieee80211_key_conf *key)
 478 {
 479         struct hw_key_entry key_entry;
 480         u32 offset;
 481
 482         if (crypto->cmd == SET_KEY) {
 483                 /*
 484                  * 1 pairwise key is possible per AID, this means that the AID
 485                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 486                  * last possible shared key entry.
 487                  */
 488                 if (crypto->aid > (256 - 32))
 489                         return -ENOSPC;
 490
 491                 key->hw_key_idx = 32 + crypto->aid;
 492
 493                 memcpy(key_entry.key, crypto->key,
 494                        sizeof(key_entry.key));
 495                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 496                        sizeof(key_entry.tx_mic));
 497                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 498                        sizeof(key_entry.rx_mic));
 499
 500                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 501                 rt2800_register_multiwrite(rt2x00dev, offset,
 502                                               &key_entry, sizeof(key_entry));
 503         }
 504
 505         /*
 506          * Update WCID information
 507          */
 508         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 509
 510         return 0;
 511 }
 512
 513 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 514                                     const unsigned int filter_flags)
 515 {
 516         u32 reg;
 517
 518         /*
 519          * Start configuration steps.
 520          * Note that the version error will always be dropped
 521          * and broadcast frames will always be accepted since
 522          * there is no filter for it at this time.
 523          */
 524         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 526                            !(filter_flags & FIF_FCSFAIL));
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 528                            !(filter_flags & FIF_PLCPFAIL));
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 530                            !(filter_flags & FIF_PROMISC_IN_BSS));
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 534                            !(filter_flags & FIF_ALLMULTI));
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 538                            !(filter_flags & FIF_CONTROL));
 539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 542                            !(filter_flags & FIF_CONTROL));
 543         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 544                            !(filter_flags & FIF_CONTROL));
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 546                            !(filter_flags & FIF_CONTROL));
 547         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 548                            !(filter_flags & FIF_PSPOLL));
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 551         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 552                            !(filter_flags & FIF_CONTROL));
 553         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 554 }
 555
 556 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 557                                   struct rt2x00_intf *intf,
 558                                   struct rt2x00intf_conf *conf,
 559                                   const unsigned int flags)
 560 {
 561         unsigned int beacon_base;
 562         u32 reg;
 563
 564         if (flags & CONFIG_UPDATE_TYPE) {
 565                 /*
 566                  * Clear current synchronisation setup.
 567                  * For the Beacon base registers we only need to clear
 568                  * the first byte since that byte contains the VALID and OWNER
 569                  * bits which (when set to 0) will invalidate the entire beacon.
 570                  */
 571                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 572                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 573
 574                 /*
 575                  * Enable synchronisation.
 576                  */
 577                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 578                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 579                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 580                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 581                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 582         }
 583
 584         if (flags & CONFIG_UPDATE_MAC) {
 585                 reg = le32_to_cpu(conf->mac[1]);
 586                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 587                 conf->mac[1] = cpu_to_le32(reg);
 588
 589                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 590                                               conf->mac, sizeof(conf->mac));
 591         }
 592
 593         if (flags & CONFIG_UPDATE_BSSID) {
 594                 reg = le32_to_cpu(conf->bssid[1]);
 595                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 596                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 597                 conf->bssid[1] = cpu_to_le32(reg);
 598
 599                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 600                                               conf->bssid, sizeof(conf->bssid));
 601         }
 602 }
 603
 604 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 605                                  struct rt2x00lib_erp *erp)
 606 {
 607         u32 reg;
 608
 609         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 610         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 611         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 612
 613         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 614         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 615                            !!erp->short_preamble);
 616         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 617                            !!erp->short_preamble);
 618         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 619
 620         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 621         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 622                            erp->cts_protection ? 2 : 0);
 623         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 624
 625         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 626                                  erp->basic_rates);
 627         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 628
 629         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 630         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 631         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 632         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 633
 634         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 635         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 636         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 637         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 638         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 639         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 640         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 641
 642         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 643         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 644                            erp->beacon_int * 16);
 645         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 646 }
 647
 648 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 649                                  struct antenna_setup *ant)
 650 {
 651         u8 r1;
 652         u8 r3;
 653
 654         rt2800_bbp_read(rt2x00dev, 1, &r1);
 655         rt2800_bbp_read(rt2x00dev, 3, &r3);
 656
 657         /*
 658          * Configure the TX antenna.
 659          */
 660         switch ((int)ant->tx) {
 661         case 1:
 662                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 663                 break;
 664         case 2:
 665                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 666                 break;
 667         case 3:
 668                 /* Do nothing */
 669                 break;
 670         }
 671
 672         /*
 673          * Configure the RX antenna.
 674          */
 675         switch ((int)ant->rx) {
 676         case 1:
 677                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 678                 break;
 679         case 2:
 680                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 681                 break;
 682         case 3:
 683                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 684                 break;
 685         }
 686
 687         rt2800_bbp_write(rt2x00dev, 3, r3);
 688         rt2800_bbp_write(rt2x00dev, 1, r1);
 689 }
 690
 691 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 692                                       struct rt2x00lib_conf *libconf)
 693 {
 694         u16 eeprom;
 695         short lna_gain;
 696
 697         if (libconf->rf.channel <= 14) {
 698                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 699                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 700         } else if (libconf->rf.channel <= 64) {
 701                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 702                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 703         } else if (libconf->rf.channel <= 128) {
 704                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 705                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 706         } else {
 707                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 708                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 709         }
 710
 711         rt2x00dev->lna_gain = lna_gain;
 712 }
 713
 714 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 715                                           struct ieee80211_conf *conf,
 716                                           struct rf_channel *rf,
 717                                           struct channel_info *info)
 718 {
 719         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 720
 721         if (rt2x00dev->default_ant.tx == 1)
 722                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 723
 724         if (rt2x00dev->default_ant.rx == 1) {
 725                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 726                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 727         } else if (rt2x00dev->default_ant.rx == 2)
 728                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 729
 730         if (rf->channel > 14) {
 731                 /*
 732                  * When TX power is below 0, we should increase it by 7 to
 733                  * make it a positive value (Minumum value is -7).
 734                  * However this means that values between 0 and 7 have
 735                  * double meaning, and we should set a 7DBm boost flag.
 736                  */
 737                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 738                                    (info->tx_power1 >= 0));
 739
 740                 if (info->tx_power1 < 0)
 741                         info->tx_power1 += 7;
 742
 743                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 744                                    TXPOWER_A_TO_DEV(info->tx_power1));
 745
 746                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 747                                    (info->tx_power2 >= 0));
 748
 749                 if (info->tx_power2 < 0)
 750                         info->tx_power2 += 7;
 751
 752                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 753                                    TXPOWER_A_TO_DEV(info->tx_power2));
 754         } else {
 755                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 756                                    TXPOWER_G_TO_DEV(info->tx_power1));
 757                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 758                                    TXPOWER_G_TO_DEV(info->tx_power2));
 759         }
 760
 761         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 762
 763         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 764         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 765         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 766         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 767
 768         udelay(200);
 769
 770         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 771         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 772         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 773         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 774
 775         udelay(200);
 776
 777         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 778         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 779         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 780         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 781 }
 782
 783 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 784                                           struct ieee80211_conf *conf,
 785                                           struct rf_channel *rf,
 786                                           struct channel_info *info)
 787 {
 788         u8 rfcsr;
 789
 790         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 791         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
 792
 793         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 794         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 795         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 796
 797         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 798         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 799                           TXPOWER_G_TO_DEV(info->tx_power1));
 800         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 801
 802         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 803         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 804         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 805
 806         rt2800_rfcsr_write(rt2x00dev, 24,
 807                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 808
 809         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 810         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 811         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 812 }
 813
 814 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 815                                      struct ieee80211_conf *conf,
 816                                      struct rf_channel *rf,
 817                                      struct channel_info *info)
 818 {
 819         u32 reg;
 820         unsigned int tx_pin;
 821         u8 bbp;
 822
 823         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 824                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 825         else
 826                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 827
 828         /*
 829          * Change BBP settings
 830          */
 831         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 832         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 833         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 834         rt2800_bbp_write(rt2x00dev, 86, 0);
 835
 836         if (rf->channel <= 14) {
 837                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 838                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 839                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 840                 } else {
 841                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 842                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 843                 }
 844         } else {
 845                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 846
 847                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 848                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 849                 else
 850                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 851         }
 852
 853         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 854         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 855         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 856         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 857         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 858
 859         tx_pin = 0;
 860
 861         /* Turn on unused PA or LNA when not using 1T or 1R */
 862         if (rt2x00dev->default_ant.tx != 1) {
 863                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 864                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 865         }
 866
 867         /* Turn on unused PA or LNA when not using 1T or 1R */
 868         if (rt2x00dev->default_ant.rx != 1) {
 869                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 870                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 871         }
 872
 873         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 874         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 875         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 876         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 877         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 878         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 879
 880         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 881
 882         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 883         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 884         rt2800_bbp_write(rt2x00dev, 4, bbp);
 885
 886         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 887         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 888         rt2800_bbp_write(rt2x00dev, 3, bbp);
 889
 890         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 891                 if (conf_is_ht40(conf)) {
 892                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 893                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 894                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 895                 } else {
 896                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 897                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 898                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 899                 }
 900         }
 901
 902         msleep(1);
 903 }
 904
 905 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 906                                      const int txpower)
 907 {
 908         u32 reg;
 909         u32 value = TXPOWER_G_TO_DEV(txpower);
 910         u8 r1;
 911
 912         rt2800_bbp_read(rt2x00dev, 1, &r1);
 913         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 914         rt2800_bbp_write(rt2x00dev, 1, r1);
 915
 916         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 922         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 923         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 925         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 926
 927         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 936         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 937
 938         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 947         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 948
 949         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 955         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 958         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 959
 960         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 964         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 965         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 966 }
 967
 968 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 969                                          struct rt2x00lib_conf *libconf)
 970 {
 971         u32 reg;
 972
 973         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 974         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 975                            libconf->conf->short_frame_max_tx_count);
 976         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 977                            libconf->conf->long_frame_max_tx_count);
 978         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 979         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 980         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 981         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 982         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 983 }
 984
 985 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 986                                 struct rt2x00lib_conf *libconf)
 987 {
 988         enum dev_state state =
 989             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 990                 STATE_SLEEP : STATE_AWAKE;
 991         u32 reg;
 992
 993         if (state == STATE_SLEEP) {
 994                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 995
 996                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 997                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 998                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 999                                    libconf->conf->listen_interval - 1);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1001                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1002
1003                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1004         } else {
1005                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1006
1007                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1008                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1009                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1011                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1012         }
1013 }
1014
1015 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1016                              struct rt2x00lib_conf *libconf,
1017                              const unsigned int flags)
1018 {
1019         /* Always recalculate LNA gain before changing configuration */
1020         rt2800usb_config_lna_gain(rt2x00dev, libconf);
1021
1022         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1023                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1024                                          &libconf->rf, &libconf->channel);
1025         if (flags & IEEE80211_CONF_CHANGE_POWER)
1026                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1027         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1028                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1029         if (flags & IEEE80211_CONF_CHANGE_PS)
1030                 rt2800usb_config_ps(rt2x00dev, libconf);
1031 }
1032
1033 /*
1034  * Link tuning
1035  */
1036 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1037                                  struct link_qual *qual)
1038 {
1039         u32 reg;
1040
1041         /*
1042          * Update FCS error count from register.
1043          */
1044         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1045         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1046 }
1047
1048 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1049 {
1050         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1051                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1052                         return 0x1c + (2 * rt2x00dev->lna_gain);
1053                 else
1054                         return 0x2e + rt2x00dev->lna_gain;
1055         }
1056
1057         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1058                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1059         else
1060                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1061 }
1062
1063 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1064                                      struct link_qual *qual, u8 vgc_level)
1065 {
1066         if (qual->vgc_level != vgc_level) {
1067                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1068                 qual->vgc_level = vgc_level;
1069                 qual->vgc_level_reg = vgc_level;
1070         }
1071 }
1072
1073 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1074                                   struct link_qual *qual)
1075 {
1076         rt2800usb_set_vgc(rt2x00dev, qual,
1077                           rt2800usb_get_default_vgc(rt2x00dev));
1078 }
1079
1080 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1081                                  struct link_qual *qual, const u32 count)
1082 {
1083         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1084                 return;
1085
1086         /*
1087          * When RSSI is better then -80 increase VGC level with 0x10
1088          */
1089         rt2800usb_set_vgc(rt2x00dev, qual,
1090                           rt2800usb_get_default_vgc(rt2x00dev) +
1091                           ((qual->rssi > -80) * 0x10));
1092 }
1093
1094 /*
1095  * Firmware functions
1096  */
1097 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1098 {
1099         return FIRMWARE_RT2870;
1100 }
1101
1102 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1103 {
1104         u16 fw_crc;
1105         u16 crc;
1106
1107         /*
1108          * The last 2 bytes in the firmware array are the crc checksum itself,
1109          * this means that we should never pass those 2 bytes to the crc
1110          * algorithm.
1111          */
1112         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1113
1114         /*
1115          * Use the crc ccitt algorithm.
1116          * This will return the same value as the legacy driver which
1117          * used bit ordering reversion on the both the firmware bytes
1118          * before input input as well as on the final output.
1119          * Obviously using crc ccitt directly is much more efficient.
1120          */
1121         crc = crc_ccitt(~0, data, len - 2);
1122
1123         /*
1124          * There is a small difference between the crc-itu-t + bitrev and
1125          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1126          * will be swapped, use swab16 to convert the crc to the correct
1127          * value.
1128          */
1129         crc = swab16(crc);
1130
1131         return fw_crc == crc;
1132 }
1133
1134 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1135                                     const u8 *data, const size_t len)
1136 {
1137         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1138         size_t offset = 0;
1139
1140         /*
1141          * Firmware files:
1142          * There are 2 variations of the rt2870 firmware.
1143          * a) size: 4kb
1144          * b) size: 8kb
1145          * Note that (b) contains 2 seperate firmware blobs of 4k
1146          * within the file. The first blob is the same firmware as (a),
1147          * but the second blob is for the additional chipsets.
1148          */
1149         if (len != 4096 && len != 8192)
1150                 return FW_BAD_LENGTH;
1151
1152         /*
1153          * Check if we need the upper 4kb firmware data or not.
1154          */
1155         if ((len == 4096) &&
1156             (chipset != 0x2860) &&
1157             (chipset != 0x2872) &&
1158             (chipset != 0x3070))
1159                 return FW_BAD_VERSION;
1160
1161         /*
1162          * 8kb firmware files must be checked as if it were
1163          * 2 seperate firmware files.
1164          */
1165         while (offset < len) {
1166                 if (!rt2800usb_check_crc(data + offset, 4096))
1167                         return FW_BAD_CRC;
1168
1169                 offset += 4096;
1170         }
1171
1172         return FW_OK;
1173 }
1174
1175 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1176                                    const u8 *data, const size_t len)
1177 {
1178         unsigned int i;
1179         int status;
1180         u32 reg;
1181         u32 offset;
1182         u32 length;
1183         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1184
1185         /*
1186          * Check which section of the firmware we need.
1187          */
1188         if ((chipset == 0x2860) ||
1189             (chipset == 0x2872) ||
1190             (chipset == 0x3070)) {
1191                 offset = 0;
1192                 length = 4096;
1193         } else {
1194                 offset = 4096;
1195                 length = 4096;
1196         }
1197
1198         /*
1199          * Wait for stable hardware.
1200          */
1201         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1202                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1203                 if (reg && reg != ~0)
1204                         break;
1205                 msleep(1);
1206         }
1207
1208         if (i == REGISTER_BUSY_COUNT) {
1209                 ERROR(rt2x00dev, "Unstable hardware.\n");
1210                 return -EBUSY;
1211         }
1212
1213         /*
1214          * Write firmware to device.
1215          */
1216         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1217                                             USB_VENDOR_REQUEST_OUT,
1218                                             FIRMWARE_IMAGE_BASE,
1219                                             data + offset, length,
1220                                             REGISTER_TIMEOUT32(length));
1221
1222         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1223         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1224
1225         /*
1226          * Send firmware request to device to load firmware,
1227          * we need to specify a long timeout time.
1228          */
1229         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1230                                              0, USB_MODE_FIRMWARE,
1231                                              REGISTER_TIMEOUT_FIRMWARE);
1232         if (status < 0) {
1233                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1234                 return status;
1235         }
1236
1237         msleep(10);
1238         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1239
1240         /*
1241          * Send signal to firmware during boot time.
1242          */
1243         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1244
1245         if ((chipset == 0x3070) ||
1246             (chipset == 0x3071) ||
1247             (chipset == 0x3572)) {
1248                 udelay(200);
1249                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1250                 udelay(10);
1251         }
1252
1253         /*
1254          * Wait for device to stabilize.
1255          */
1256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1257                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1258                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1259                         break;
1260                 msleep(1);
1261         }
1262
1263         if (i == REGISTER_BUSY_COUNT) {
1264                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1265                 return -EBUSY;
1266         }
1267
1268         /*
1269          * Initialize firmware.
1270          */
1271         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1272         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1273         msleep(1);
1274
1275         return 0;
1276 }
1277
1278 /*
1279  * Initialization functions.
1280  */
1281 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1282 {
1283         u32 reg;
1284         unsigned int i;
1285
1286         /*
1287          * Wait untill BBP and RF are ready.
1288          */
1289         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1290                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1291                 if (reg && reg != ~0)
1292                         break;
1293                 msleep(1);
1294         }
1295
1296         if (i == REGISTER_BUSY_COUNT) {
1297                 ERROR(rt2x00dev, "Unstable hardware.\n");
1298                 return -EBUSY;
1299         }
1300
1301         rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1302         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1303
1304         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1305         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1306         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1307         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1308
1309         rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1310
1311         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1312                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1313
1314         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1315
1316         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1317         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1318         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1319         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1320         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1321         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1322
1323         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1324         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1325         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1326         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1327         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1328         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1329
1330         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1331         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1332
1333         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1334
1335         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1336         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1337         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1338         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1339         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1340         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1341         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1342         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1343
1344         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1345                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1346                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1347                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1348         } else {
1349                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1350                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1351         }
1352
1353         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1354         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1355         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1356         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1357         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1358         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1359         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1360         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1361         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1362         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1363
1364         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1365         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1366         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1367         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1368
1369         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1370         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1371         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1372             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1373                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1374         else
1375                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1376         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1377         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1378         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1379
1380         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1381
1382         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1383         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1384         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1385         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1386         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1387         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1388         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1389
1390         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1391         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1392         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1393         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1394         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1395         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1396         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1397         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1398         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1399         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1400         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1401
1402         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1403         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1404         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1405         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1406         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1407         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1408         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1409         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1410         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1411         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1412         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1413
1414         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1415         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1416         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1417         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1418         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1419         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1420         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1421         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1422         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1423         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1424         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1425
1426         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1427         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1428         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1429         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1430         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1431         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1432         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1433         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1434         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1435         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1436         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1437
1438         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1439         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1440         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1441         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1442         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1443         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1444         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1445         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1446         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1447         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1448         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1449
1450         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1451         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1452         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1453         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1454         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1455         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1456         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1457         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1458         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1459         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1460         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1461
1462         rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1463
1464         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1465         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1466         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1467         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1468         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1469         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1470         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1471         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1472         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1473         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1474         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1475
1476         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1477         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1478
1479         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1480         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1481         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1482                            IEEE80211_MAX_RTS_THRESHOLD);
1483         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1484         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1485
1486         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1487         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1488
1489         /*
1490          * ASIC will keep garbage value after boot, clear encryption keys.
1491          */
1492         for (i = 0; i < 4; i++)
1493                 rt2800_register_write(rt2x00dev,
1494                                          SHARED_KEY_MODE_ENTRY(i), 0);
1495
1496         for (i = 0; i < 256; i++) {
1497                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1498                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1499                                               wcid, sizeof(wcid));
1500
1501                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1502                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1503         }
1504
1505         /*
1506          * Clear all beacons
1507          * For the Beacon base registers we only need to clear
1508          * the first byte since that byte contains the VALID and OWNER
1509          * bits which (when set to 0) will invalidate the entire beacon.
1510          */
1511         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1512         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1513         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1514         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1515         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1516         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1517         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1518         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1519
1520         rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1521         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1522         rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1523
1524         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1525         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1526         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1527         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1528         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1529         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1530         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1531         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1532         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1533         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1534
1535         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1536         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1537         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1538         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1539         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1540         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1541         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1542         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1543         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1544         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1545
1546         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1547         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1548         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1549         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1550         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1551         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1552         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1553         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1554         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1555         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1556
1557         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1558         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1559         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1560         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1561         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1562         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1563
1564         /*
1565          * We must clear the error counters.
1566          * These registers are cleared on read,
1567          * so we may pass a useless variable to store the value.
1568          */
1569         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1570         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1571         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1572         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1573         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1574         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1575
1576         return 0;
1577 }
1578
1579 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1580 {
1581         unsigned int i;
1582         u32 reg;
1583
1584         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1585                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1586                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1587                         return 0;
1588
1589                 udelay(REGISTER_BUSY_DELAY);
1590         }
1591
1592         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1593         return -EACCES;
1594 }
1595
1596 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1597 {
1598         unsigned int i;
1599         u8 value;
1600
1601         /*
1602          * BBP was enabled after firmware was loaded,
1603          * but we need to reactivate it now.
1604          */
1605         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1606         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1607         msleep(1);
1608
1609         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1610                 rt2800_bbp_read(rt2x00dev, 0, &value);
1611                 if ((value != 0xff) && (value != 0x00))
1612                         return 0;
1613                 udelay(REGISTER_BUSY_DELAY);
1614         }
1615
1616         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1617         return -EACCES;
1618 }
1619
1620 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1621 {
1622         unsigned int i;
1623         u16 eeprom;
1624         u8 reg_id;
1625         u8 value;
1626
1627         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1628                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1629                 return -EACCES;
1630
1631         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1632         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1633         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1634         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1635         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1636         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1637         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1638         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1639         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1640         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1641         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1642         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1643         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1644         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1645
1646         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1647                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1648                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1649         }
1650
1651         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1652                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1653         }
1654
1655         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1656                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1657                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1658                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1659         }
1660
1661         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1663
1664                 if (eeprom != 0xffff && eeprom != 0x0000) {
1665                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1666                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1667                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1668                 }
1669         }
1670
1671         return 0;
1672 }
1673
1674 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1675                                    bool bw40, u8 rfcsr24, u8 filter_target)
1676 {
1677         unsigned int i;
1678         u8 bbp;
1679         u8 rfcsr;
1680         u8 passband;
1681         u8 stopband;
1682         u8 overtuned = 0;
1683
1684         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1685
1686         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1687         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1688         rt2800_bbp_write(rt2x00dev, 4, bbp);
1689
1690         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1691         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1692         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1693
1694         /*
1695          * Set power & frequency of passband test tone
1696          */
1697         rt2800_bbp_write(rt2x00dev, 24, 0);
1698
1699         for (i = 0; i < 100; i++) {
1700                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1701                 msleep(1);
1702
1703                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1704                 if (passband)
1705                         break;
1706         }
1707
1708         /*
1709          * Set power & frequency of stopband test tone
1710          */
1711         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1712
1713         for (i = 0; i < 100; i++) {
1714                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1715                 msleep(1);
1716
1717                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1718
1719                 if ((passband - stopband) <= filter_target) {
1720                         rfcsr24++;
1721                         overtuned += ((passband - stopband) == filter_target);
1722                 } else
1723                         break;
1724
1725                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1726         }
1727
1728         rfcsr24 -= !!overtuned;
1729
1730         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1731         return rfcsr24;
1732 }
1733
1734 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1735 {
1736         u8 rfcsr;
1737         u8 bbp;
1738
1739         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1740                 return 0;
1741
1742         /*
1743          * Init RF calibration.
1744          */
1745         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1746         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1747         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1748         msleep(1);
1749         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1750         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1751
1752         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1753         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1754         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1755         rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1756         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1757         rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1758         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1759         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1760         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1761         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1762         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1763         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1764         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1765         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1766         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1767         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1768         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1769         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1770         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1771         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1772
1773         /*
1774          * Set RX Filter calibration for 20MHz and 40MHz
1775          */
1776         rt2x00dev->calibration[0] =
1777             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1778         rt2x00dev->calibration[1] =
1779             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1780
1781         /*
1782          * Set back to initial state
1783          */
1784         rt2800_bbp_write(rt2x00dev, 24, 0);
1785
1786         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1787         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1788         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1789
1790         /*
1791          * set BBP back to BW20
1792          */
1793         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1794         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1795         rt2800_bbp_write(rt2x00dev, 4, bbp);
1796
1797         return 0;
1798 }
1799
1800 /*
1801  * Device state switch handlers.
1802  */
1803 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1804                                 enum dev_state state)
1805 {
1806         u32 reg;
1807
1808         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1809         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1810                            (state == STATE_RADIO_RX_ON) ||
1811                            (state == STATE_RADIO_RX_ON_LINK));
1812         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1813 }
1814
1815 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1816 {
1817         unsigned int i;
1818         u32 reg;
1819
1820         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1821                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1822                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1823                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1824                         return 0;
1825
1826                 msleep(1);
1827         }
1828
1829         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1830         return -EACCES;
1831 }
1832
1833 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1834 {
1835         u32 reg;
1836         u16 word;
1837
1838         /*
1839          * Initialize all registers.
1840          */
1841         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1842                      rt2800usb_init_registers(rt2x00dev) ||
1843                      rt2800usb_init_bbp(rt2x00dev) ||
1844                      rt2800usb_init_rfcsr(rt2x00dev)))
1845                 return -EIO;
1846
1847         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1848         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1849         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1850
1851         udelay(50);
1852
1853         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1854         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1855         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1856         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1857         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1858
1859
1860         rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1861         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1862         /* Don't use bulk in aggregation when working with USB 1.1 */
1863         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1864                            (rt2x00dev->rx->usb_maxpacket == 512));
1865         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1866         /*
1867          * Total room for RX frames in kilobytes, PBF might still exceed
1868          * this limit so reduce the number to prevent errors.
1869          */
1870         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1871                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1872         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1873         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1874         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1875
1876         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1877         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1878         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1879         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1880
1881         /*
1882          * Initialize LED control
1883          */
1884         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1885         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1886                               word & 0xff, (word >> 8) & 0xff);
1887
1888         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1889         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1890                               word & 0xff, (word >> 8) & 0xff);
1891
1892         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1893         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1894                               word & 0xff, (word >> 8) & 0xff);
1895
1896         return 0;
1897 }
1898
1899 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1900 {
1901         u32 reg;
1902
1903         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1904         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1905         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1906         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1907
1908         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1909         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1910         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1911
1912         /* Wait for DMA, ignore error */
1913         rt2800usb_wait_wpdma_ready(rt2x00dev);
1914
1915         rt2x00usb_disable_radio(rt2x00dev);
1916 }
1917
1918 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1919                                enum dev_state state)
1920 {
1921         if (state == STATE_AWAKE)
1922                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1923         else
1924                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1925
1926         return 0;
1927 }
1928
1929 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1930                                       enum dev_state state)
1931 {
1932         int retval = 0;
1933
1934         switch (state) {
1935         case STATE_RADIO_ON:
1936                 /*
1937                  * Before the radio can be enabled, the device first has
1938                  * to be woken up. After that it needs a bit of time
1939                  * to be fully awake and then the radio can be enabled.
1940                  */
1941                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1942                 msleep(1);
1943                 retval = rt2800usb_enable_radio(rt2x00dev);
1944                 break;
1945         case STATE_RADIO_OFF:
1946                 /*
1947                  * After the radio has been disabled, the device should
1948                  * be put to sleep for powersaving.
1949                  */
1950                 rt2800usb_disable_radio(rt2x00dev);
1951                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1952                 break;
1953         case STATE_RADIO_RX_ON:
1954         case STATE_RADIO_RX_ON_LINK:
1955         case STATE_RADIO_RX_OFF:
1956         case STATE_RADIO_RX_OFF_LINK:
1957                 rt2800usb_toggle_rx(rt2x00dev, state);
1958                 break;
1959         case STATE_RADIO_IRQ_ON:
1960         case STATE_RADIO_IRQ_OFF:
1961                 /* No support, but no error either */
1962                 break;
1963         case STATE_DEEP_SLEEP:
1964         case STATE_SLEEP:
1965         case STATE_STANDBY:
1966         case STATE_AWAKE:
1967                 retval = rt2800usb_set_state(rt2x00dev, state);
1968                 break;
1969         default:
1970                 retval = -ENOTSUPP;
1971                 break;
1972         }
1973
1974         if (unlikely(retval))
1975                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1976                       state, retval);
1977
1978         return retval;
1979 }
1980
1981 /*
1982  * TX descriptor initialization
1983  */
1984 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1985                                     struct sk_buff *skb,
1986                                     struct txentry_desc *txdesc)
1987 {
1988         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1989         __le32 *txi = skbdesc->desc;
1990         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1991         u32 word;
1992
1993         /*
1994          * Initialize TX Info descriptor
1995          */
1996         rt2x00_desc_read(txwi, 0, &word);
1997         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1998                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1999         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2000         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2001         rt2x00_set_field32(&word, TXWI_W0_TS,
2002                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2003         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2004                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2005         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2006         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2007         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2008         rt2x00_set_field32(&word, TXWI_W0_BW,
2009                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2010         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2011                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2012         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2013         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2014         rt2x00_desc_write(txwi, 0, word);
2015
2016         rt2x00_desc_read(txwi, 1, &word);
2017         rt2x00_set_field32(&word, TXWI_W1_ACK,
2018                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2019         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2020                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2021         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2022         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2023                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2024                            txdesc->key_idx : 0xff);
2025         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2026                            skb->len - txdesc->l2pad);
2027         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2028                            skbdesc->entry->queue->qid + 1);
2029         rt2x00_desc_write(txwi, 1, word);
2030
2031         /*
2032          * Always write 0 to IV/EIV fields, hardware will insert the IV
2033          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2034          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2035          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2036          * crypto entry in the registers should be used to encrypt the frame.
2037          */
2038         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2039         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2040
2041         /*
2042          * Initialize TX descriptor
2043          */
2044         rt2x00_desc_read(txi, 0, &word);
2045         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2046                            skb->len + TXWI_DESC_SIZE);
2047         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2048                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2049         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2050         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2051         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2052         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2053                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2054         rt2x00_desc_write(txi, 0, word);
2055 }
2056
2057 /*
2058  * TX data initialization
2059  */
2060 static void rt2800usb_write_beacon(struct queue_entry *entry)
2061 {
2062         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2063         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2064         unsigned int beacon_base;
2065         u32 reg;
2066
2067         /*
2068          * Add the descriptor in front of the skb.
2069          */
2070         skb_push(entry->skb, entry->queue->desc_size);
2071         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2072         skbdesc->desc = entry->skb->data;
2073
2074         /*
2075          * Disable beaconing while we are reloading the beacon data,
2076          * otherwise we might be sending out invalid data.
2077          */
2078         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2079         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2080         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2081
2082         /*
2083          * Write entire beacon with descriptor to register.
2084          */
2085         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2086         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2087                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2088                                             entry->skb->data, entry->skb->len,
2089                                             REGISTER_TIMEOUT32(entry->skb->len));
2090
2091         /*
2092          * Clean up the beacon skb.
2093          */
2094         dev_kfree_skb(entry->skb);
2095         entry->skb = NULL;
2096 }
2097
2098 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2099 {
2100         int length;
2101
2102         /*
2103          * The length _must_ include 4 bytes padding,
2104          * it should always be multiple of 4,
2105          * but it must _not_ be a multiple of the USB packet size.
2106          */
2107         length = roundup(entry->skb->len + 4, 4);
2108         length += (4 * !(length % entry->queue->usb_maxpacket));
2109
2110         return length;
2111 }
2112
2113 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2114                                     const enum data_queue_qid queue)
2115 {
2116         u32 reg;
2117
2118         if (queue != QID_BEACON) {
2119                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2120                 return;
2121         }
2122
2123         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2124         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2125                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2126                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2127                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2128                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2129         }
2130 }
2131
2132 /*
2133  * RX control handlers
2134  */
2135 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2136                                   struct rxdone_entry_desc *rxdesc)
2137 {
2138         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2139         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2140         __le32 *rxd = (__le32 *)entry->skb->data;
2141         __le32 *rxwi;
2142         u32 rxd0;
2143         u32 rxwi0;
2144         u32 rxwi1;
2145         u32 rxwi2;
2146         u32 rxwi3;
2147
2148         /*
2149          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2150          * moving of frame data in rt2x00usb.
2151          */
2152         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2153         rxd = (__le32 *)skbdesc->desc;
2154         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2155
2156         /*
2157          * It is now safe to read the descriptor on all architectures.
2158          */
2159         rt2x00_desc_read(rxd, 0, &rxd0);
2160         rt2x00_desc_read(rxwi, 0, &rxwi0);
2161         rt2x00_desc_read(rxwi, 1, &rxwi1);
2162         rt2x00_desc_read(rxwi, 2, &rxwi2);
2163         rt2x00_desc_read(rxwi, 3, &rxwi3);
2164
2165         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2166                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2167
2168         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2169                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2170                 rxdesc->cipher_status =
2171                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2172         }
2173
2174         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2175                 /*
2176                  * Hardware has stripped IV/EIV data from 802.11 frame during
2177                  * decryption. Unfortunately the descriptor doesn't contain
2178                  * any fields with the EIV/IV data either, so they can't
2179                  * be restored by rt2x00lib.
2180                  */
2181                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2182
2183                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2184                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2185                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2186                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2187         }
2188
2189         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2190                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2191
2192         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2193                 rxdesc->dev_flags |= RXDONE_L2PAD;
2194                 skbdesc->flags |= SKBDESC_L2_PADDED;
2195         }
2196
2197         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2198                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2199
2200         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2201                 rxdesc->flags |= RX_FLAG_40MHZ;
2202
2203         /*
2204          * Detect RX rate, always use MCS as signal type.
2205          */
2206         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2207         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2208         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2209
2210         /*
2211          * Mask of 0x8 bit to remove the short preamble flag.
2212          */
2213         if (rxdesc->rate_mode == RATE_MODE_CCK)
2214                 rxdesc->signal &= ~0x8;
2215
2216         rxdesc->rssi =
2217             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2218              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2219
2220         rxdesc->noise =
2221             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2222              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2223
2224         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2225
2226         /*
2227          * Remove RXWI descriptor from start of buffer.
2228          */
2229         skb_pull(entry->skb, skbdesc->desc_len);
2230         skb_trim(entry->skb, rxdesc->size);
2231 }
2232
2233 /*
2234  * Device probe functions.
2235  */
2236 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2237 {
2238         u16 word;
2239         u8 *mac;
2240         u8 default_lna_gain;
2241
2242         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2243
2244         /*
2245          * Start validation of the data that has been read.
2246          */
2247         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2248         if (!is_valid_ether_addr(mac)) {
2249                 random_ether_addr(mac);
2250                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2251         }
2252
2253         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2254         if (word == 0xffff) {
2255                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2256                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2257                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2258                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2259                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2260         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2261                 /*
2262                  * There is a max of 2 RX streams for RT2870 series
2263                  */
2264                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2265                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2266                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2267         }
2268
2269         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2270         if (word == 0xffff) {
2271                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2272                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2273                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2274                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2275                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2276                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2277                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2278                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2279                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2280                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2281                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2282                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2283         }
2284
2285         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2286         if ((word & 0x00ff) == 0x00ff) {
2287                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2288                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2289                                    LED_MODE_TXRX_ACTIVITY);
2290                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2291                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2292                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2293                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2294                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2295                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2296         }
2297
2298         /*
2299          * During the LNA validation we are going to use
2300          * lna0 as correct value. Note that EEPROM_LNA
2301          * is never validated.
2302          */
2303         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2304         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2305
2306         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2307         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2308                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2309         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2310                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2311         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2312
2313         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2314         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2315                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2316         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2317             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2318                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2319                                    default_lna_gain);
2320         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2321
2322         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2323         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2324                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2325         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2326                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2327         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2328
2329         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2330         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2331                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2332         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2333             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2334                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2335                                    default_lna_gain);
2336         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2337
2338         return 0;
2339 }
2340
2341 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2342 {
2343         u32 reg;
2344         u16 value;
2345         u16 eeprom;
2346
2347         /*
2348          * Read EEPROM word for configuration.
2349          */
2350         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2351
2352         /*
2353          * Identify RF chipset.
2354          */
2355         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2356         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2357         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2358
2359         /*
2360          * The check for rt2860 is not a typo, some rt2870 hardware
2361          * identifies itself as rt2860 in the CSR register.
2362          */
2363         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2364             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2365             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2366             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2367                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2368                 return -ENODEV;
2369         }
2370
2371         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2372             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2373             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2374             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2375             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2376             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2377                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2378                 return -ENODEV;
2379         }
2380
2381         /*
2382          * Identify default antenna configuration.
2383          */
2384         rt2x00dev->default_ant.tx =
2385             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2386         rt2x00dev->default_ant.rx =
2387             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2388
2389         /*
2390          * Read frequency offset and RF programming sequence.
2391          */
2392         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2393         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2394
2395         /*
2396          * Read external LNA informations.
2397          */
2398         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2399
2400         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2401                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2402         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2403                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2404
2405         /*
2406          * Detect if this device has an hardware controlled radio.
2407          */
2408         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2409                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2410
2411         /*
2412          * Store led settings, for correct led behaviour.
2413          */
2414 #ifdef CONFIG_RT2X00_LIB_LEDS
2415         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2416         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2417         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2418
2419         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2420                            &rt2x00dev->led_mcu_reg);
2421 #endif /* CONFIG_RT2X00_LIB_LEDS */
2422
2423         return 0;
2424 }
2425
2426 /*
2427  * RF value list for rt2870
2428  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2429  */
2430 static const struct rf_channel rf_vals[] = {
2431         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2432         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2433         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2434         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2435         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2436         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2437         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2438         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2439         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2440         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2441         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2442         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2443         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2444         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2445
2446         /* 802.11 UNI / HyperLan 2 */
2447         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2448         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2449         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2450         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2451         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2452         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2453         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2454         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2455         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2456         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2457         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2458         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2459
2460         /* 802.11 HyperLan 2 */
2461         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2462         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2463         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2464         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2465         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2466         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2467         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2468         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2469         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2470         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2471         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2472         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2473         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2474         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2475         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2476         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2477
2478         /* 802.11 UNII */
2479         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2480         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2481         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2482         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2483         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2484         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2485         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2486         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2487         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2488         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2489         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2490
2491         /* 802.11 Japan */
2492         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2493         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2494         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2495         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2496         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2497         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2498         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2499 };
2500
2501 /*
2502  * RF value list for rt3070
2503  * Supports: 2.4 GHz
2504  */
2505 static const struct rf_channel rf_vals_3070[] = {
2506         {1,  241, 2, 2 },
2507         {2,  241, 2, 7 },
2508         {3,  242, 2, 2 },
2509         {4,  242, 2, 7 },
2510         {5,  243, 2, 2 },
2511         {6,  243, 2, 7 },
2512         {7,  244, 2, 2 },
2513         {8,  244, 2, 7 },
2514         {9,  245, 2, 2 },
2515         {10, 245, 2, 7 },
2516         {11, 246, 2, 2 },
2517         {12, 246, 2, 7 },
2518         {13, 247, 2, 2 },
2519         {14, 248, 2, 4 },
2520 };
2521
2522 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2523 {
2524         struct hw_mode_spec *spec = &rt2x00dev->spec;
2525         struct channel_info *info;
2526         char *tx_power1;
2527         char *tx_power2;
2528         unsigned int i;
2529         u16 eeprom;
2530
2531         /*
2532          * Initialize all hw fields.
2533          */
2534         rt2x00dev->hw->flags =
2535             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2536             IEEE80211_HW_SIGNAL_DBM |
2537             IEEE80211_HW_SUPPORTS_PS |
2538             IEEE80211_HW_PS_NULLFUNC_STACK;
2539         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2540
2541         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2542         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2543                                 rt2x00_eeprom_addr(rt2x00dev,
2544                                                    EEPROM_MAC_ADDR_0));
2545
2546         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2547
2548         /*
2549          * Initialize HT information.
2550          */
2551         spec->ht.ht_supported = true;
2552         spec->ht.cap =
2553             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2554             IEEE80211_HT_CAP_GRN_FLD |
2555             IEEE80211_HT_CAP_SGI_20 |
2556             IEEE80211_HT_CAP_SGI_40 |
2557             IEEE80211_HT_CAP_TX_STBC |
2558             IEEE80211_HT_CAP_RX_STBC |
2559             IEEE80211_HT_CAP_PSMP_SUPPORT;
2560         spec->ht.ampdu_factor = 3;
2561         spec->ht.ampdu_density = 4;
2562         spec->ht.mcs.tx_params =
2563             IEEE80211_HT_MCS_TX_DEFINED |
2564             IEEE80211_HT_MCS_TX_RX_DIFF |
2565             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2566                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2567
2568         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2569         case 3:
2570                 spec->ht.mcs.rx_mask[2] = 0xff;
2571         case 2:
2572                 spec->ht.mcs.rx_mask[1] = 0xff;
2573         case 1:
2574                 spec->ht.mcs.rx_mask[0] = 0xff;
2575                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2576                 break;
2577         }
2578
2579         /*
2580          * Initialize hw_mode information.
2581          */
2582         spec->supported_bands = SUPPORT_BAND_2GHZ;
2583         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2584
2585         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2586             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2587                 spec->num_channels = 14;
2588                 spec->channels = rf_vals;
2589         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2590                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2591                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2592                 spec->num_channels = ARRAY_SIZE(rf_vals);
2593                 spec->channels = rf_vals;
2594         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2595                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2596                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2597                 spec->channels = rf_vals_3070;
2598         }
2599
2600         /*
2601          * Create channel information array
2602          */
2603         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2604         if (!info)
2605                 return -ENOMEM;
2606
2607         spec->channels_info = info;
2608
2609         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2610         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2611
2612         for (i = 0; i < 14; i++) {
2613                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2614                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2615         }
2616
2617         if (spec->num_channels > 14) {
2618                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2619                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2620
2621                 for (i = 14; i < spec->num_channels; i++) {
2622                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2623                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2624                 }
2625         }
2626
2627         return 0;
2628 }
2629
2630 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2631 {
2632         int retval;
2633
2634         /*
2635          * Allocate eeprom data.
2636          */
2637         retval = rt2800usb_validate_eeprom(rt2x00dev);
2638         if (retval)
2639                 return retval;
2640
2641         retval = rt2800usb_init_eeprom(rt2x00dev);
2642         if (retval)
2643                 return retval;
2644
2645         /*
2646          * Initialize hw specifications.
2647          */
2648         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2649         if (retval)
2650                 return retval;
2651
2652         /*
2653          * This device has multiple filters for control frames
2654          * and has a separate filter for PS Poll frames.
2655          */
2656         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2657         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2658
2659         /*
2660          * This device requires firmware.
2661          */
2662         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2663         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2664         if (!modparam_nohwcrypt)
2665                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2666
2667         /*
2668          * Set the rssi offset.
2669          */
2670         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2671
2672         return 0;
2673 }
2674
2675 /*
2676  * IEEE80211 stack callback functions.
2677  */
2678 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2679                                    u32 *iv32, u16 *iv16)
2680 {
2681         struct rt2x00_dev *rt2x00dev = hw->priv;
2682         struct mac_iveiv_entry iveiv_entry;
2683         u32 offset;
2684
2685         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2686         rt2800_register_multiread(rt2x00dev, offset,
2687                                       &iveiv_entry, sizeof(iveiv_entry));
2688
2689         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2690         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2691 }
2692
2693 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2694 {
2695         struct rt2x00_dev *rt2x00dev = hw->priv;
2696         u32 reg;
2697         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2698
2699         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2700         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2701         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2702
2703         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2704         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2705         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2706
2707         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2708         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2709         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2710
2711         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2712         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2713         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2714
2715         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2716         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2717         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2718
2719         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2720         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2721         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2722
2723         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2724         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2725         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2726
2727         return 0;
2728 }
2729
2730 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2731                              const struct ieee80211_tx_queue_params *params)
2732 {
2733         struct rt2x00_dev *rt2x00dev = hw->priv;
2734         struct data_queue *queue;
2735         struct rt2x00_field32 field;
2736         int retval;
2737         u32 reg;
2738         u32 offset;
2739
2740         /*
2741          * First pass the configuration through rt2x00lib, that will
2742          * update the queue settings and validate the input. After that
2743          * we are free to update the registers based on the value
2744          * in the queue parameter.
2745          */
2746         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2747         if (retval)
2748                 return retval;
2749
2750         /*
2751          * We only need to perform additional register initialization
2752          * for WMM queues/
2753          */
2754         if (queue_idx >= 4)
2755                 return 0;
2756
2757         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2758
2759         /* Update WMM TXOP register */
2760         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2761         field.bit_offset = (queue_idx & 1) * 16;
2762         field.bit_mask = 0xffff << field.bit_offset;
2763
2764         rt2800_register_read(rt2x00dev, offset, &reg);
2765         rt2x00_set_field32(&reg, field, queue->txop);
2766         rt2800_register_write(rt2x00dev, offset, reg);
2767
2768         /* Update WMM registers */
2769         field.bit_offset = queue_idx * 4;
2770         field.bit_mask = 0xf << field.bit_offset;
2771
2772         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2773         rt2x00_set_field32(&reg, field, queue->aifs);
2774         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2775
2776         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2777         rt2x00_set_field32(&reg, field, queue->cw_min);
2778         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2779
2780         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2781         rt2x00_set_field32(&reg, field, queue->cw_max);
2782         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2783
2784         /* Update EDCA registers */
2785         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2786
2787         rt2800_register_read(rt2x00dev, offset, &reg);
2788         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2789         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2790         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2791         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2792         rt2800_register_write(rt2x00dev, offset, reg);
2793
2794         return 0;
2795 }
2796
2797 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2798 {
2799         struct rt2x00_dev *rt2x00dev = hw->priv;
2800         u64 tsf;
2801         u32 reg;
2802
2803         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2804         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2805         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2806         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2807
2808         return tsf;
2809 }
2810
2811 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2812         .tx                     = rt2x00mac_tx,
2813         .start                  = rt2x00mac_start,
2814         .stop                   = rt2x00mac_stop,
2815         .add_interface          = rt2x00mac_add_interface,
2816         .remove_interface       = rt2x00mac_remove_interface,
2817         .config                 = rt2x00mac_config,
2818         .configure_filter       = rt2x00mac_configure_filter,
2819         .set_tim                = rt2x00mac_set_tim,
2820         .set_key                = rt2x00mac_set_key,
2821         .get_stats              = rt2x00mac_get_stats,
2822         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2823         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2824         .bss_info_changed       = rt2x00mac_bss_info_changed,
2825         .conf_tx                = rt2800usb_conf_tx,
2826         .get_tx_stats           = rt2x00mac_get_tx_stats,
2827         .get_tsf                = rt2800usb_get_tsf,
2828         .rfkill_poll            = rt2x00mac_rfkill_poll,
2829 };
2830
2831 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2832         .probe_hw               = rt2800usb_probe_hw,
2833         .get_firmware_name      = rt2800usb_get_firmware_name,
2834         .check_firmware         = rt2800usb_check_firmware,
2835         .load_firmware          = rt2800usb_load_firmware,
2836         .initialize             = rt2x00usb_initialize,
2837         .uninitialize           = rt2x00usb_uninitialize,
2838         .clear_entry            = rt2x00usb_clear_entry,
2839         .set_device_state       = rt2800usb_set_device_state,
2840         .rfkill_poll            = rt2800usb_rfkill_poll,
2841         .link_stats             = rt2800usb_link_stats,
2842         .reset_tuner            = rt2800usb_reset_tuner,
2843         .link_tuner             = rt2800usb_link_tuner,
2844         .write_tx_desc          = rt2800usb_write_tx_desc,
2845         .write_tx_data          = rt2x00usb_write_tx_data,
2846         .write_beacon           = rt2800usb_write_beacon,
2847         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2848         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2849         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2850         .fill_rxdone            = rt2800usb_fill_rxdone,
2851         .config_shared_key      = rt2800usb_config_shared_key,
2852         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2853         .config_filter          = rt2800usb_config_filter,
2854         .config_intf            = rt2800usb_config_intf,
2855         .config_erp             = rt2800usb_config_erp,
2856         .config_ant             = rt2800usb_config_ant,
2857         .config                 = rt2800usb_config,
2858 };
2859
2860 static const struct data_queue_desc rt2800usb_queue_rx = {
2861         .entry_num              = RX_ENTRIES,
2862         .data_size              = AGGREGATION_SIZE,
2863         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2864         .priv_size              = sizeof(struct queue_entry_priv_usb),
2865 };
2866
2867 static const struct data_queue_desc rt2800usb_queue_tx = {
2868         .entry_num              = TX_ENTRIES,
2869         .data_size              = AGGREGATION_SIZE,
2870         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2871         .priv_size              = sizeof(struct queue_entry_priv_usb),
2872 };
2873
2874 static const struct data_queue_desc rt2800usb_queue_bcn = {
2875         .entry_num              = 8 * BEACON_ENTRIES,
2876         .data_size              = MGMT_FRAME_SIZE,
2877         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2878         .priv_size              = sizeof(struct queue_entry_priv_usb),
2879 };
2880
2881 static const struct rt2x00_ops rt2800usb_ops = {
2882         .name           = KBUILD_MODNAME,
2883         .max_sta_intf   = 1,
2884         .max_ap_intf    = 8,
2885         .eeprom_size    = EEPROM_SIZE,
2886         .rf_size        = RF_SIZE,
2887         .tx_queues      = NUM_TX_QUEUES,
2888         .rx             = &rt2800usb_queue_rx,
2889         .tx             = &rt2800usb_queue_tx,
2890         .bcn            = &rt2800usb_queue_bcn,
2891         .lib            = &rt2800usb_rt2x00_ops,
2892         .hw             = &rt2800usb_mac80211_ops,
2893 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2894         .debugfs        = &rt2800usb_rt2x00debug,
2895 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2896 };
2897
2898 /*
2899  * rt2800usb module information.
2900  */
2901 static struct usb_device_id rt2800usb_device_table[] = {
2902         /* Abocom */
2903         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2906         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2908         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         /* AirTies */
2910         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2911         /* Amigo */
2912         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         /* Amit */
2915         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         /* ASUS */
2917         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2922         /* AzureWave */
2923         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         /* Belkin */
2928         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2929         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2931         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         /* Buffalo */
2933         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         /* Conceptronic */
2936         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2937         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2940         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2941         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2943         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         /* Corega */
2947         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2950         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         /* D-Link */
2953         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2954         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2956         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2961         /* Edimax */
2962         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         /* Encore */
2966         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2967         /* EnGenius */
2968         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         /* Gemtek */
2975         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         /* Gigabyte */
2977         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2979         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         /* Hawking */
2981         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2982         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2983         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         /* I-O DATA */
2986         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2987         /* LevelOne */
2988         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2989         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Linksys */
2991         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2993         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         /* Logitec */
2995         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         /* Motorola */
2999         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
3001         /* Ovislink */
3002         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3003         /* Pegatron */
3004         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
3005         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         /* Philips */
3008         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         /* Planex */
3010         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         /* Qcom */
3014         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         /* Quanta */
3016         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
3017         /* Ralink */
3018         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
3019         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
3020         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
3022         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
3024         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3026         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         /* Samsung */
3028         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3029         /* Siemens */
3030         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         /* Sitecom */
3032         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3034         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3036         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3037         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3038         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3039         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3040         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3041         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3042         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3043         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3044         /* SMC */
3045         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3046         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3047         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3048         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3049         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3050         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3051         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3052         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3053         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3054         /* Sparklan */
3055         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3056         /* Sweex */
3057         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3058         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3059         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3060         /* U-Media*/
3061         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3062         /* ZCOM */
3063         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3064         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3065         /* Zinwell */
3066         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3067         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3068         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3069         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3070         /* Zyxel */
3071         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3072         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3073         { 0, }
3074 };
3075
3076 MODULE_AUTHOR(DRV_PROJECT);
3077 MODULE_VERSION(DRV_VERSION);
3078 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3079 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3080 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3081 MODULE_FIRMWARE(FIRMWARE_RT2870);
3082 MODULE_LICENSE("GPL");
3083
3084 static struct usb_driver rt2800usb_driver = {
3085         .name           = KBUILD_MODNAME,
3086         .id_table       = rt2800usb_device_table,
3087         .probe          = rt2x00usb_probe,
3088         .disconnect     = rt2x00usb_disconnect,
3089         .suspend        = rt2x00usb_suspend,
3090         .resume         = rt2x00usb_resume,
3091 };
3092
3093 static int __init rt2800usb_init(void)
3094 {
3095         return usb_register(&rt2800usb_driver);
3096 }
3097
3098 static void __exit rt2800usb_exit(void)
3099 {
3100         usb_deregister(&rt2800usb_driver);
3101 }
3102
3103 module_init(rt2800usb_init);
3104 module_exit(rt2800usb_exit);