SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   4
   5         Based on the original rt2800pci.c and rt2800usb.c.
   6           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   7           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   8           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   9           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13           <http://rt2x00.serialmonkey.com>
  14
  15         This program is free software; you can redistribute it and/or modify
  16         it under the terms of the GNU General Public License as published by
  17         the Free Software Foundation; either version 2 of the License, or
  18         (at your option) any later version.
  19
  20         This program is distributed in the hope that it will be useful,
  21         but WITHOUT ANY WARRANTY; without even the implied warranty of
  22         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23         GNU General Public License for more details.
  24
  25         You should have received a copy of the GNU General Public License
  26         along with this program; if not, write to the
  27         Free Software Foundation, Inc.,
  28         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /*
  32         Module: rt2800lib
  33         Abstract: rt2800 generic device routines.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  42 #include "rt2x00usb.h"
  43 #endif
  44 #include "rt2800lib.h"
  45 #include "rt2800.h"
  46 #include "rt2800usb.h"
  47
  48 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  49 MODULE_DESCRIPTION("rt2800 library");
  50 MODULE_LICENSE("GPL");
  51
  52 /*
  53  * Register access.
  54  * All access to the CSR registers will go through the methods
  55  * rt2800_register_read and rt2800_register_write.
  56  * BBP and RF register require indirect register access,
  57  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  58  * These indirect registers work with busy bits,
  59  * and we will try maximal REGISTER_BUSY_COUNT times to access
  60  * the register while taking a REGISTER_BUSY_DELAY us delay
  61  * between each attampt. When the busy bit is still set at that time,
  62  * the access attempt is considered to have failed,
  63  * and we will print an error.
  64  * The _lock versions must be used if you already hold the csr_mutex
  65  */
  66 #define WAIT_FOR_BBP(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  68 #define WAIT_FOR_RFCSR(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  70 #define WAIT_FOR_RF(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  72 #define WAIT_FOR_MCU(__dev, __reg) \
  73         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  74                             H2M_MAILBOX_CSR_OWNER, (__reg))
  75
  76 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  77 {
  78         /* check for rt2872 on SoC */
  79         if (!rt2x00_is_soc(rt2x00dev) ||
  80             !rt2x00_rt(rt2x00dev, RT2872))
  81                 return false;
  82
  83         /* we know for sure that these rf chipsets are used on rt305x boards */
  84         if (rt2x00_rf(rt2x00dev, RF3020) ||
  85             rt2x00_rf(rt2x00dev, RF3021) ||
  86             rt2x00_rf(rt2x00dev, RF3022))
  87                 return true;
  88
  89         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  90         return false;
  91 }
  92
  93 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  94                              const unsigned int word, const u8 value)
  95 {
  96         u32 reg;
  97
  98         mutex_lock(&rt2x00dev->csr_mutex);
  99
 100         /*
 101          * Wait until the BBP becomes available, afterwards we
 102          * can safely write the new data into the register.
 103          */
 104         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 105                 reg = 0;
 106                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 107                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 108                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 109                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 110                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 111                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 112
 113                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 114         }
 115
 116         mutex_unlock(&rt2x00dev->csr_mutex);
 117 }
 118
 119 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 120                             const unsigned int word, u8 *value)
 121 {
 122         u32 reg;
 123
 124         mutex_lock(&rt2x00dev->csr_mutex);
 125
 126         /*
 127          * Wait until the BBP becomes available, afterwards we
 128          * can safely write the read request into the register.
 129          * After the data has been written, we wait until hardware
 130          * returns the correct value, if at any time the register
 131          * doesn't become available in time, reg will be 0xffffffff
 132          * which means we return 0xff to the caller.
 133          */
 134         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 135                 reg = 0;
 136                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 137                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 138                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 139                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 140                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 141
 142                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 143
 144                 WAIT_FOR_BBP(rt2x00dev, &reg);
 145         }
 146
 147         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 148
 149         mutex_unlock(&rt2x00dev->csr_mutex);
 150 }
 151
 152 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 153                                const unsigned int word, const u8 value)
 154 {
 155         u32 reg;
 156
 157         mutex_lock(&rt2x00dev->csr_mutex);
 158
 159         /*
 160          * Wait until the RFCSR becomes available, afterwards we
 161          * can safely write the new data into the register.
 162          */
 163         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 164                 reg = 0;
 165                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 167                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 168                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 169
 170                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 171         }
 172
 173         mutex_unlock(&rt2x00dev->csr_mutex);
 174 }
 175
 176 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 177                               const unsigned int word, u8 *value)
 178 {
 179         u32 reg;
 180
 181         mutex_lock(&rt2x00dev->csr_mutex);
 182
 183         /*
 184          * Wait until the RFCSR becomes available, afterwards we
 185          * can safely write the read request into the register.
 186          * After the data has been written, we wait until hardware
 187          * returns the correct value, if at any time the register
 188          * doesn't become available in time, reg will be 0xffffffff
 189          * which means we return 0xff to the caller.
 190          */
 191         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 192                 reg = 0;
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 194                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 195                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 196
 197                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 198
 199                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 200         }
 201
 202         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 203
 204         mutex_unlock(&rt2x00dev->csr_mutex);
 205 }
 206
 207 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 208                             const unsigned int word, const u32 value)
 209 {
 210         u32 reg;
 211
 212         mutex_lock(&rt2x00dev->csr_mutex);
 213
 214         /*
 215          * Wait until the RF becomes available, afterwards we
 216          * can safely write the new data into the register.
 217          */
 218         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 219                 reg = 0;
 220                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 221                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 222                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 223                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 224
 225                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 226                 rt2x00_rf_write(rt2x00dev, word, value);
 227         }
 228
 229         mutex_unlock(&rt2x00dev->csr_mutex);
 230 }
 231
 232 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 233                         const u8 command, const u8 token,
 234                         const u8 arg0, const u8 arg1)
 235 {
 236         u32 reg;
 237
 238         /*
 239          * SOC devices don't support MCU requests.
 240          */
 241         if (rt2x00_is_soc(rt2x00dev))
 242                 return;
 243
 244         mutex_lock(&rt2x00dev->csr_mutex);
 245
 246         /*
 247          * Wait until the MCU becomes available, afterwards we
 248          * can safely write the new data into the register.
 249          */
 250         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 251                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 252                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 253                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 254                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 255                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 256
 257                 reg = 0;
 258                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 259                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 260         }
 261
 262         mutex_unlock(&rt2x00dev->csr_mutex);
 263 }
 264 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 265
 266 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 267 {
 268         unsigned int i;
 269         u32 reg;
 270
 271         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 272                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 273                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 274                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 275                         return 0;
 276
 277                 msleep(1);
 278         }
 279
 280         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 281         return -EACCES;
 282 }
 283 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 284
 285 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 286 const struct rt2x00debug rt2800_rt2x00debug = {
 287         .owner  = THIS_MODULE,
 288         .csr    = {
 289                 .read           = rt2800_register_read,
 290                 .write          = rt2800_register_write,
 291                 .flags          = RT2X00DEBUGFS_OFFSET,
 292                 .word_base      = CSR_REG_BASE,
 293                 .word_size      = sizeof(u32),
 294                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 295         },
 296         .eeprom = {
 297                 .read           = rt2x00_eeprom_read,
 298                 .write          = rt2x00_eeprom_write,
 299                 .word_base      = EEPROM_BASE,
 300                 .word_size      = sizeof(u16),
 301                 .word_count     = EEPROM_SIZE / sizeof(u16),
 302         },
 303         .bbp    = {
 304                 .read           = rt2800_bbp_read,
 305                 .write          = rt2800_bbp_write,
 306                 .word_base      = BBP_BASE,
 307                 .word_size      = sizeof(u8),
 308                 .word_count     = BBP_SIZE / sizeof(u8),
 309         },
 310         .rf     = {
 311                 .read           = rt2x00_rf_read,
 312                 .write          = rt2800_rf_write,
 313                 .word_base      = RF_BASE,
 314                 .word_size      = sizeof(u32),
 315                 .word_count     = RF_SIZE / sizeof(u32),
 316         },
 317 };
 318 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 319 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 320
 321 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 322 {
 323         u32 reg;
 324
 325         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 326         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 327 }
 328 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 329
 330 #ifdef CONFIG_RT2X00_LIB_LEDS
 331 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 332                                   enum led_brightness brightness)
 333 {
 334         struct rt2x00_led *led =
 335             container_of(led_cdev, struct rt2x00_led, led_dev);
 336         unsigned int enabled = brightness != LED_OFF;
 337         unsigned int bg_mode =
 338             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 339         unsigned int polarity =
 340                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 341                                    EEPROM_FREQ_LED_POLARITY);
 342         unsigned int ledmode =
 343                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 344                                    EEPROM_FREQ_LED_MODE);
 345
 346         if (led->type == LED_TYPE_RADIO) {
 347                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 348                                       enabled ? 0x20 : 0);
 349         } else if (led->type == LED_TYPE_ASSOC) {
 350                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 351                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 352         } else if (led->type == LED_TYPE_QUALITY) {
 353                 /*
 354                  * The brightness is divided into 6 levels (0 - 5),
 355                  * The specs tell us the following levels:
 356                  *      0, 1 ,3, 7, 15, 31
 357                  * to determine the level in a simple way we can simply
 358                  * work with bitshifting:
 359                  *      (1 << level) - 1
 360                  */
 361                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 362                                       (1 << brightness / (LED_FULL / 6)) - 1,
 363                                       polarity);
 364         }
 365 }
 366
 367 static int rt2800_blink_set(struct led_classdev *led_cdev,
 368                             unsigned long *delay_on, unsigned long *delay_off)
 369 {
 370         struct rt2x00_led *led =
 371             container_of(led_cdev, struct rt2x00_led, led_dev);
 372         u32 reg;
 373
 374         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 375         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 376         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 377         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 378
 379         return 0;
 380 }
 381
 382 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 383                      struct rt2x00_led *led, enum led_type type)
 384 {
 385         led->rt2x00dev = rt2x00dev;
 386         led->type = type;
 387         led->led_dev.brightness_set = rt2800_brightness_set;
 388         led->led_dev.blink_set = rt2800_blink_set;
 389         led->flags = LED_INITIALIZED;
 390 }
 391 #endif /* CONFIG_RT2X00_LIB_LEDS */
 392
 393 /*
 394  * Configuration handlers.
 395  */
 396 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 397                                     struct rt2x00lib_crypto *crypto,
 398                                     struct ieee80211_key_conf *key)
 399 {
 400         struct mac_wcid_entry wcid_entry;
 401         struct mac_iveiv_entry iveiv_entry;
 402         u32 offset;
 403         u32 reg;
 404
 405         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 406
 407         rt2800_register_read(rt2x00dev, offset, &reg);
 408         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 409                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 410         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 411                            (crypto->cmd == SET_KEY) * crypto->cipher);
 412         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 413                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 414         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 415         rt2800_register_write(rt2x00dev, offset, reg);
 416
 417         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 418
 419         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 420         if ((crypto->cipher == CIPHER_TKIP) ||
 421             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 422             (crypto->cipher == CIPHER_AES))
 423                 iveiv_entry.iv[3] |= 0x20;
 424         iveiv_entry.iv[3] |= key->keyidx << 6;
 425         rt2800_register_multiwrite(rt2x00dev, offset,
 426                                       &iveiv_entry, sizeof(iveiv_entry));
 427
 428         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 429
 430         memset(&wcid_entry, 0, sizeof(wcid_entry));
 431         if (crypto->cmd == SET_KEY)
 432                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 433         rt2800_register_multiwrite(rt2x00dev, offset,
 434                                       &wcid_entry, sizeof(wcid_entry));
 435 }
 436
 437 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 438                              struct rt2x00lib_crypto *crypto,
 439                              struct ieee80211_key_conf *key)
 440 {
 441         struct hw_key_entry key_entry;
 442         struct rt2x00_field32 field;
 443         u32 offset;
 444         u32 reg;
 445
 446         if (crypto->cmd == SET_KEY) {
 447                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 448
 449                 memcpy(key_entry.key, crypto->key,
 450                        sizeof(key_entry.key));
 451                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 452                        sizeof(key_entry.tx_mic));
 453                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 454                        sizeof(key_entry.rx_mic));
 455
 456                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 457                 rt2800_register_multiwrite(rt2x00dev, offset,
 458                                               &key_entry, sizeof(key_entry));
 459         }
 460
 461         /*
 462          * The cipher types are stored over multiple registers
 463          * starting with SHARED_KEY_MODE_BASE each word will have
 464          * 32 bits and contains the cipher types for 2 bssidx each.
 465          * Using the correct defines correctly will cause overhead,
 466          * so just calculate the correct offset.
 467          */
 468         field.bit_offset = 4 * (key->hw_key_idx % 8);
 469         field.bit_mask = 0x7 << field.bit_offset;
 470
 471         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 472
 473         rt2800_register_read(rt2x00dev, offset, &reg);
 474         rt2x00_set_field32(&reg, field,
 475                            (crypto->cmd == SET_KEY) * crypto->cipher);
 476         rt2800_register_write(rt2x00dev, offset, reg);
 477
 478         /*
 479          * Update WCID information
 480          */
 481         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 482
 483         return 0;
 484 }
 485 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 486
 487 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 488                                struct rt2x00lib_crypto *crypto,
 489                                struct ieee80211_key_conf *key)
 490 {
 491         struct hw_key_entry key_entry;
 492         u32 offset;
 493
 494         if (crypto->cmd == SET_KEY) {
 495                 /*
 496                  * 1 pairwise key is possible per AID, this means that the AID
 497                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 498                  * last possible shared key entry.
 499                  */
 500                 if (crypto->aid > (256 - 32))
 501                         return -ENOSPC;
 502
 503                 key->hw_key_idx = 32 + crypto->aid;
 504
 505                 memcpy(key_entry.key, crypto->key,
 506                        sizeof(key_entry.key));
 507                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 508                        sizeof(key_entry.tx_mic));
 509                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 510                        sizeof(key_entry.rx_mic));
 511
 512                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 513                 rt2800_register_multiwrite(rt2x00dev, offset,
 514                                               &key_entry, sizeof(key_entry));
 515         }
 516
 517         /*
 518          * Update WCID information
 519          */
 520         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 521
 522         return 0;
 523 }
 524 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 525
 526 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 527                           const unsigned int filter_flags)
 528 {
 529         u32 reg;
 530
 531         /*
 532          * Start configuration steps.
 533          * Note that the version error will always be dropped
 534          * and broadcast frames will always be accepted since
 535          * there is no filter for it at this time.
 536          */
 537         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 538         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 539                            !(filter_flags & FIF_FCSFAIL));
 540         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 541                            !(filter_flags & FIF_PLCPFAIL));
 542         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 543                            !(filter_flags & FIF_PROMISC_IN_BSS));
 544         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 545         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 546         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 547                            !(filter_flags & FIF_ALLMULTI));
 548         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 549         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 550         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 551                            !(filter_flags & FIF_CONTROL));
 552         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 553                            !(filter_flags & FIF_CONTROL));
 554         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 555                            !(filter_flags & FIF_CONTROL));
 556         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 557                            !(filter_flags & FIF_CONTROL));
 558         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 559                            !(filter_flags & FIF_CONTROL));
 560         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 561                            !(filter_flags & FIF_PSPOLL));
 562         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 563         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 564         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 565                            !(filter_flags & FIF_CONTROL));
 566         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 567 }
 568 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 569
 570 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 571                         struct rt2x00intf_conf *conf, const unsigned int flags)
 572 {
 573         unsigned int beacon_base;
 574         u32 reg;
 575
 576         if (flags & CONFIG_UPDATE_TYPE) {
 577                 /*
 578                  * Clear current synchronisation setup.
 579                  * For the Beacon base registers we only need to clear
 580                  * the first byte since that byte contains the VALID and OWNER
 581                  * bits which (when set to 0) will invalidate the entire beacon.
 582                  */
 583                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 584                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 585
 586                 /*
 587                  * Enable synchronisation.
 588                  */
 589                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 590                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 591                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 592                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
 593                                    (conf->sync == TSF_SYNC_BEACON));
 594                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 595         }
 596
 597         if (flags & CONFIG_UPDATE_MAC) {
 598                 reg = le32_to_cpu(conf->mac[1]);
 599                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 600                 conf->mac[1] = cpu_to_le32(reg);
 601
 602                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 603                                               conf->mac, sizeof(conf->mac));
 604         }
 605
 606         if (flags & CONFIG_UPDATE_BSSID) {
 607                 reg = le32_to_cpu(conf->bssid[1]);
 608                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 609                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 610                 conf->bssid[1] = cpu_to_le32(reg);
 611
 612                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 613                                               conf->bssid, sizeof(conf->bssid));
 614         }
 615 }
 616 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 617
 618 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 619 {
 620         u32 reg;
 621
 622         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 623         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 624                            !!erp->short_preamble);
 625         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 626                            !!erp->short_preamble);
 627         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 628
 629         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 630         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 631                            erp->cts_protection ? 2 : 0);
 632         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 633
 634         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 635                                  erp->basic_rates);
 636         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 637
 638         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 639         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 640         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 641
 642         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 643         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 644         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 645         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 646         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 647
 648         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 649         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 650                            erp->beacon_int * 16);
 651         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 652 }
 653 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 654
 655 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 656 {
 657         u8 r1;
 658         u8 r3;
 659
 660         rt2800_bbp_read(rt2x00dev, 1, &r1);
 661         rt2800_bbp_read(rt2x00dev, 3, &r3);
 662
 663         /*
 664          * Configure the TX antenna.
 665          */
 666         switch ((int)ant->tx) {
 667         case 1:
 668                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 669                 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
 670                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 671                 break;
 672         case 2:
 673                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 674                 break;
 675         case 3:
 676                 /* Do nothing */
 677                 break;
 678         }
 679
 680         /*
 681          * Configure the RX antenna.
 682          */
 683         switch ((int)ant->rx) {
 684         case 1:
 685                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 686                 break;
 687         case 2:
 688                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 689                 break;
 690         case 3:
 691                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 692                 break;
 693         }
 694
 695         rt2800_bbp_write(rt2x00dev, 3, r3);
 696         rt2800_bbp_write(rt2x00dev, 1, r1);
 697 }
 698 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 699
 700 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 701                                    struct rt2x00lib_conf *libconf)
 702 {
 703         u16 eeprom;
 704         short lna_gain;
 705
 706         if (libconf->rf.channel <= 14) {
 707                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 708                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 709         } else if (libconf->rf.channel <= 64) {
 710                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 711                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 712         } else if (libconf->rf.channel <= 128) {
 713                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 714                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 715         } else {
 716                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 717                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 718         }
 719
 720         rt2x00dev->lna_gain = lna_gain;
 721 }
 722
 723 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 724                                          struct ieee80211_conf *conf,
 725                                          struct rf_channel *rf,
 726                                          struct channel_info *info)
 727 {
 728         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 729
 730         if (rt2x00dev->default_ant.tx == 1)
 731                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 732
 733         if (rt2x00dev->default_ant.rx == 1) {
 734                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 735                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 736         } else if (rt2x00dev->default_ant.rx == 2)
 737                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 738
 739         if (rf->channel > 14) {
 740                 /*
 741                  * When TX power is below 0, we should increase it by 7 to
 742                  * make it a positive value (Minumum value is -7).
 743                  * However this means that values between 0 and 7 have
 744                  * double meaning, and we should set a 7DBm boost flag.
 745                  */
 746                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 747                                    (info->tx_power1 >= 0));
 748
 749                 if (info->tx_power1 < 0)
 750                         info->tx_power1 += 7;
 751
 752                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 753                                    TXPOWER_A_TO_DEV(info->tx_power1));
 754
 755                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 756                                    (info->tx_power2 >= 0));
 757
 758                 if (info->tx_power2 < 0)
 759                         info->tx_power2 += 7;
 760
 761                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 762                                    TXPOWER_A_TO_DEV(info->tx_power2));
 763         } else {
 764                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 765                                    TXPOWER_G_TO_DEV(info->tx_power1));
 766                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 767                                    TXPOWER_G_TO_DEV(info->tx_power2));
 768         }
 769
 770         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 771
 772         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 773         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 774         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 775         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 776
 777         udelay(200);
 778
 779         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 780         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 781         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 782         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 783
 784         udelay(200);
 785
 786         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 787         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 788         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 789         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 790 }
 791
 792 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
 793                                          struct ieee80211_conf *conf,
 794                                          struct rf_channel *rf,
 795                                          struct channel_info *info)
 796 {
 797         u8 rfcsr;
 798
 799         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 800         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 801
 802         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 803         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
 804         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 805
 806         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 807         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 808                           TXPOWER_G_TO_DEV(info->tx_power1));
 809         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 810
 811         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
 812         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
 813                           TXPOWER_G_TO_DEV(info->tx_power2));
 814         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
 815
 816         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 817         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 818         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 819
 820         rt2800_rfcsr_write(rt2x00dev, 24,
 821                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 822
 823         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
 824         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 825         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 826 }
 827
 828 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 829                                   struct ieee80211_conf *conf,
 830                                   struct rf_channel *rf,
 831                                   struct channel_info *info)
 832 {
 833         u32 reg;
 834         unsigned int tx_pin;
 835         u8 bbp;
 836
 837         if (rt2x00_rf(rt2x00dev, RF2020) ||
 838             rt2x00_rf(rt2x00dev, RF3020) ||
 839             rt2x00_rf(rt2x00dev, RF3021) ||
 840             rt2x00_rf(rt2x00dev, RF3022))
 841                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
 842         else
 843                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 844
 845         /*
 846          * Change BBP settings
 847          */
 848         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 849         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 850         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 851         rt2800_bbp_write(rt2x00dev, 86, 0);
 852
 853         if (rf->channel <= 14) {
 854                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 855                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 856                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 857                 } else {
 858                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 859                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 860                 }
 861         } else {
 862                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 863
 864                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 865                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 866                 else
 867                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 868         }
 869
 870         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 871         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
 872         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 873         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 874         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 875
 876         tx_pin = 0;
 877
 878         /* Turn on unused PA or LNA when not using 1T or 1R */
 879         if (rt2x00dev->default_ant.tx != 1) {
 880                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 881                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 882         }
 883
 884         /* Turn on unused PA or LNA when not using 1T or 1R */
 885         if (rt2x00dev->default_ant.rx != 1) {
 886                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 887                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 888         }
 889
 890         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 891         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 892         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 893         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 894         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 895         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 896
 897         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 898
 899         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 900         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 901         rt2800_bbp_write(rt2x00dev, 4, bbp);
 902
 903         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 904         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
 905         rt2800_bbp_write(rt2x00dev, 3, bbp);
 906
 907         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
 908                 if (conf_is_ht40(conf)) {
 909                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 910                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 911                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 912                 } else {
 913                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 914                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 915                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 916                 }
 917         }
 918
 919         msleep(1);
 920 }
 921
 922 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 923                                   const int txpower)
 924 {
 925         u32 reg;
 926         u32 value = TXPOWER_G_TO_DEV(txpower);
 927         u8 r1;
 928
 929         rt2800_bbp_read(rt2x00dev, 1, &r1);
 930         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 931         rt2800_bbp_write(rt2x00dev, 1, r1);
 932
 933         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 938         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 939         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 942         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 943
 944         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 948         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 949         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 950         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 953         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 954
 955         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 956         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 957         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 958         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 959         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 960         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 961         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 962         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 963         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 964         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 965
 966         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 967         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 968         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 969         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 970         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 971         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 972         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 973         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 974         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 975         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 976
 977         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 978         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 979         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 980         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 981         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 982         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 983 }
 984
 985 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 986                                       struct rt2x00lib_conf *libconf)
 987 {
 988         u32 reg;
 989
 990         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 991         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 992                            libconf->conf->short_frame_max_tx_count);
 993         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 994                            libconf->conf->long_frame_max_tx_count);
 995         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 996 }
 997
 998 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 999                              struct rt2x00lib_conf *libconf)
1000 {
1001         enum dev_state state =
1002             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1003                 STATE_SLEEP : STATE_AWAKE;
1004         u32 reg;
1005
1006         if (state == STATE_SLEEP) {
1007                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1008
1009                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1010                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1011                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1012                                    libconf->conf->listen_interval - 1);
1013                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1014                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1015
1016                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017         } else {
1018                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1019                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1020                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1021                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1022                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1023
1024                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1025         }
1026 }
1027
1028 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1029                    struct rt2x00lib_conf *libconf,
1030                    const unsigned int flags)
1031 {
1032         /* Always recalculate LNA gain before changing configuration */
1033         rt2800_config_lna_gain(rt2x00dev, libconf);
1034
1035         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1036                 rt2800_config_channel(rt2x00dev, libconf->conf,
1037                                       &libconf->rf, &libconf->channel);
1038         if (flags & IEEE80211_CONF_CHANGE_POWER)
1039                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1040         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1041                 rt2800_config_retry_limit(rt2x00dev, libconf);
1042         if (flags & IEEE80211_CONF_CHANGE_PS)
1043                 rt2800_config_ps(rt2x00dev, libconf);
1044 }
1045 EXPORT_SYMBOL_GPL(rt2800_config);
1046
1047 /*
1048  * Link tuning
1049  */
1050 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1051 {
1052         u32 reg;
1053
1054         /*
1055          * Update FCS error count from register.
1056          */
1057         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1058         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1059 }
1060 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1061
1062 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063 {
1064         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1066                     rt2x00_rt(rt2x00dev, RT3071) ||
1067                     rt2x00_rt(rt2x00dev, RT3090) ||
1068                     rt2x00_rt(rt2x00dev, RT3390))
1069                         return 0x1c + (2 * rt2x00dev->lna_gain);
1070                 else
1071                         return 0x2e + rt2x00dev->lna_gain;
1072         }
1073
1074         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1075                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1076         else
1077                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1078 }
1079
1080 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1081                                   struct link_qual *qual, u8 vgc_level)
1082 {
1083         if (qual->vgc_level != vgc_level) {
1084                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1085                 qual->vgc_level = vgc_level;
1086                 qual->vgc_level_reg = vgc_level;
1087         }
1088 }
1089
1090 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1091 {
1092         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1093 }
1094 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1095
1096 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1097                        const u32 count)
1098 {
1099         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1100                 return;
1101
1102         /*
1103          * When RSSI is better then -80 increase VGC level with 0x10
1104          */
1105         rt2800_set_vgc(rt2x00dev, qual,
1106                        rt2800_get_default_vgc(rt2x00dev) +
1107                        ((qual->rssi > -80) * 0x10));
1108 }
1109 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1110
1111 /*
1112  * Initialization functions.
1113  */
1114 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115 {
1116         u32 reg;
1117         u16 eeprom;
1118         unsigned int i;
1119
1120         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1121         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1122         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1123         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1124         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1125         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1126         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1127
1128         if (rt2x00_is_usb(rt2x00dev)) {
1129                 /*
1130                  * Wait until BBP and RF are ready.
1131                  */
1132                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1133                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1134                         if (reg && reg != ~0)
1135                                 break;
1136                         msleep(1);
1137                 }
1138
1139                 if (i == REGISTER_BUSY_COUNT) {
1140                         ERROR(rt2x00dev, "Unstable hardware.\n");
1141                         return -EBUSY;
1142                 }
1143
1144                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1145                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1146                                       reg & ~0x00002000);
1147         } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1148                 /*
1149                  * Reset DMA indexes
1150                  */
1151                 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1152                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1153                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1154                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1155                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1156                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1157                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1158                 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1159                 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1160
1161                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1162                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1163
1164                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1165         }
1166
1167         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1168         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1169         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1170         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1171
1172         if (rt2x00_is_usb(rt2x00dev)) {
1173                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1174 #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
1175                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1176                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1177 #endif
1178         }
1179
1180         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1181
1182         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1183         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1184         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1185         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1186         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1187         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1188
1189         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1190         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1191         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1192         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1193         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1194         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1195
1196         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1197         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1198
1199         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1200
1201         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1202         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1203         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1204         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1205         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1206         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1207         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1208         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1209
1210         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1211
1212         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1213         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1214         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1215         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1216
1217         if (rt2x00_rt(rt2x00dev, RT3071) ||
1218             rt2x00_rt(rt2x00dev, RT3090) ||
1219             rt2x00_rt(rt2x00dev, RT3390)) {
1220                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1221                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1222                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1223                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1224                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1225                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1226                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1227                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1228                                                       0x0000002c);
1229                         else
1230                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1231                                                       0x0000000f);
1232                 } else {
1233                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1234                 }
1235                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1236         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1237                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1238
1239                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1240                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1241                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1242                 } else {
1243                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1244                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1245                 }
1246         } else {
1247                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1248                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1249         }
1250
1251         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1252         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1253         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1254         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1255         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1256         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1257         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1258         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1259         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1260         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1261
1262         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1263         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1264         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1265         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1266         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1267
1268         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1269         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1270         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1271             rt2x00_rt(rt2x00dev, RT2883) ||
1272             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1273                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1274         else
1275                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1276         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1277         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1278         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1279
1280         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1281         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1282         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1283         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1284         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1285         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1286         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1287         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1288         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1289
1290         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1291
1292         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1293         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1294         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1295         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1296         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1297         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1298         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1299         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1300
1301         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1302         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1303         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1304         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1305         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1306         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1307         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1308         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1309         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1310
1311         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1312         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1313         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1314         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1315         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1316         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1317         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1318         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1319         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1320         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1321         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1322         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1323
1324         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1325         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1326         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1327         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1328         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1329         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1330         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1331         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1332         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1333         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1334         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1335         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1336
1337         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1338         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1339         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1340         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1341         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1342         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1343         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1344         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1345         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1346         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1347         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1348         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1349
1350         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1351         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1352         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1353                            !rt2x00_is_usb(rt2x00dev));
1354         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1355         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1356         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1357         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1358         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1359         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1360         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1361         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1362         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1363
1364         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1365         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1366         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1367         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1368         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1369         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1370         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1372         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1373         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1374         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1375         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1376
1377         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1378         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1379         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1380         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1381         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1382         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1383         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1384         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1385         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1386         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1387         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1388         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1389
1390         if (rt2x00_is_usb(rt2x00dev)) {
1391                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1392
1393                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1394                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1395                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1396                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1397                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1398                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1399                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1400                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1401                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1402                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1403                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1404         }
1405
1406         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1407         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1408
1409         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1410         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1411         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1412                            IEEE80211_MAX_RTS_THRESHOLD);
1413         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1414         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1415
1416         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1417
1418         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1419         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1420         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1421         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1422         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1423         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1424         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1425
1426         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1427
1428         /*
1429          * ASIC will keep garbage value after boot, clear encryption keys.
1430          */
1431         for (i = 0; i < 4; i++)
1432                 rt2800_register_write(rt2x00dev,
1433                                          SHARED_KEY_MODE_ENTRY(i), 0);
1434
1435         for (i = 0; i < 256; i++) {
1436                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1437                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1438                                               wcid, sizeof(wcid));
1439
1440                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1441                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1442         }
1443
1444         /*
1445          * Clear all beacons
1446          * For the Beacon base registers we only need to clear
1447          * the first byte since that byte contains the VALID and OWNER
1448          * bits which (when set to 0) will invalidate the entire beacon.
1449          */
1450         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1451         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1452         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1453         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1454         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1455         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1456         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1457         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1458
1459         if (rt2x00_is_usb(rt2x00dev)) {
1460                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1461                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1462                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1463         }
1464
1465         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1466         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1467         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1468         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1469         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1470         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1471         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1472         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1473         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1474         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1475
1476         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1477         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1478         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1479         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1480         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1481         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1482         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1483         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1484         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1485         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1486
1487         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1488         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1489         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1490         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1491         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1492         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1493         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1494         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1495         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1496         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1497
1498         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1499         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1500         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1501         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1502         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1503         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1504
1505         /*
1506          * We must clear the error counters.
1507          * These registers are cleared on read,
1508          * so we may pass a useless variable to store the value.
1509          */
1510         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1511         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1512         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1513         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1514         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1515         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1516
1517         return 0;
1518 }
1519 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1520
1521 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1522 {
1523         unsigned int i;
1524         u32 reg;
1525
1526         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1527                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1528                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1529                         return 0;
1530
1531                 udelay(REGISTER_BUSY_DELAY);
1532         }
1533
1534         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1535         return -EACCES;
1536 }
1537
1538 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1539 {
1540         unsigned int i;
1541         u8 value;
1542
1543         /*
1544          * BBP was enabled after firmware was loaded,
1545          * but we need to reactivate it now.
1546          */
1547         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1548         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1549         msleep(1);
1550
1551         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1552                 rt2800_bbp_read(rt2x00dev, 0, &value);
1553                 if ((value != 0xff) && (value != 0x00))
1554                         return 0;
1555                 udelay(REGISTER_BUSY_DELAY);
1556         }
1557
1558         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1559         return -EACCES;
1560 }
1561
1562 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1563 {
1564         unsigned int i;
1565         u16 eeprom;
1566         u8 reg_id;
1567         u8 value;
1568
1569         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1570                      rt2800_wait_bbp_ready(rt2x00dev)))
1571                 return -EACCES;
1572
1573         if (rt2800_is_305x_soc(rt2x00dev))
1574                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1575
1576         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1577         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1578
1579         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1580                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1581                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1582         } else {
1583                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1584                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1585         }
1586
1587         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1588
1589         if (rt2x00_rt(rt2x00dev, RT3070) ||
1590             rt2x00_rt(rt2x00dev, RT3071) ||
1591             rt2x00_rt(rt2x00dev, RT3090) ||
1592             rt2x00_rt(rt2x00dev, RT3390)) {
1593                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1594                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1595                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1596         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1597                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1598                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1599         } else {
1600                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1601         }
1602
1603         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1604         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1605
1606         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1607             rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1608                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1609         else
1610                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1611
1612         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1613         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1614         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1615
1616         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1617             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1618             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1619             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1620             rt2800_is_305x_soc(rt2x00dev))
1621                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1622         else
1623                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1624
1625         if (rt2800_is_305x_soc(rt2x00dev))
1626                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1627         else
1628                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1629         rt2800_bbp_write(rt2x00dev, 106, 0x35);
1630
1631         if (rt2x00_rt(rt2x00dev, RT3071) ||
1632             rt2x00_rt(rt2x00dev, RT3090) ||
1633             rt2x00_rt(rt2x00dev, RT3390)) {
1634                 rt2800_bbp_read(rt2x00dev, 138, &value);
1635
1636                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1637                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1638                         value |= 0x20;
1639                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1640                         value &= ~0x02;
1641
1642                 rt2800_bbp_write(rt2x00dev, 138, value);
1643         }
1644
1645
1646         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1647                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1648
1649                 if (eeprom != 0xffff && eeprom != 0x0000) {
1650                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1651                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1652                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1653                 }
1654         }
1655
1656         return 0;
1657 }
1658 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1659
1660 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1661                                 bool bw40, u8 rfcsr24, u8 filter_target)
1662 {
1663         unsigned int i;
1664         u8 bbp;
1665         u8 rfcsr;
1666         u8 passband;
1667         u8 stopband;
1668         u8 overtuned = 0;
1669
1670         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1671
1672         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1673         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1674         rt2800_bbp_write(rt2x00dev, 4, bbp);
1675
1676         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1677         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1678         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1679
1680         /*
1681          * Set power & frequency of passband test tone
1682          */
1683         rt2800_bbp_write(rt2x00dev, 24, 0);
1684
1685         for (i = 0; i < 100; i++) {
1686                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1687                 msleep(1);
1688
1689                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1690                 if (passband)
1691                         break;
1692         }
1693
1694         /*
1695          * Set power & frequency of stopband test tone
1696          */
1697         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1698
1699         for (i = 0; i < 100; i++) {
1700                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1701                 msleep(1);
1702
1703                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1704
1705                 if ((passband - stopband) <= filter_target) {
1706                         rfcsr24++;
1707                         overtuned += ((passband - stopband) == filter_target);
1708                 } else
1709                         break;
1710
1711                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1712         }
1713
1714         rfcsr24 -= !!overtuned;
1715
1716         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1717         return rfcsr24;
1718 }
1719
1720 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1721 {
1722         u8 rfcsr;
1723         u8 bbp;
1724         u32 reg;
1725         u16 eeprom;
1726
1727         if (!rt2x00_rt(rt2x00dev, RT3070) &&
1728             !rt2x00_rt(rt2x00dev, RT3071) &&
1729             !rt2x00_rt(rt2x00dev, RT3090) &&
1730             !rt2x00_rt(rt2x00dev, RT3390) &&
1731             !rt2800_is_305x_soc(rt2x00dev))
1732                 return 0;
1733
1734         /*
1735          * Init RF calibration.
1736          */
1737         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1738         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1739         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1740         msleep(1);
1741         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1742         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1743
1744         if (rt2x00_rt(rt2x00dev, RT3070) ||
1745             rt2x00_rt(rt2x00dev, RT3071) ||
1746             rt2x00_rt(rt2x00dev, RT3090)) {
1747                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1748                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1749                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1750                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1751                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1752                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1753                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1754                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1755                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1756                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1757                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1758                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1759                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1760                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1761                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1762                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1763                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1764                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1765                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1766         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1767                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1768                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1769                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1770                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1771                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1772                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1773                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1774                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1775                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1776                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1777                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1778                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1779                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1780                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1781                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1782                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1783                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1784                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1785                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1786                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1787                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1788                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1789                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1790                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1791                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1792                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1793                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1794                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1795                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1796                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1797                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1798                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1799         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1800                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1801                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1802                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1803                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1804                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1805                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1806                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1807                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1808                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1809                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1810                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1811                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1812                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1813                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1814                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1815                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1816                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1817                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1818                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1819                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1820                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1821                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1822                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1823                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1824                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1825                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1826                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1827                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1828                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1829                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1830                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1831                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1832                 return 0;
1833         }
1834
1835         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1836                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1837                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1838                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1839                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1840         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1841                    rt2x00_rt(rt2x00dev, RT3090)) {
1842                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1843                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1844                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1845
1846                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1847
1848                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1849                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1850                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1851                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1852                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1853                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1854                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1855                         else
1856                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1857                 }
1858                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1859         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1860                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1861                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1862                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1863         }
1864
1865         /*
1866          * Set RX Filter calibration for 20MHz and 40MHz
1867          */
1868         if (rt2x00_rt(rt2x00dev, RT3070)) {
1869                 rt2x00dev->calibration[0] =
1870                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1871                 rt2x00dev->calibration[1] =
1872                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1873         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1874                    rt2x00_rt(rt2x00dev, RT3090) ||
1875                    rt2x00_rt(rt2x00dev, RT3390)) {
1876                 rt2x00dev->calibration[0] =
1877                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1878                 rt2x00dev->calibration[1] =
1879                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1880         }
1881
1882         /*
1883          * Set back to initial state
1884          */
1885         rt2800_bbp_write(rt2x00dev, 24, 0);
1886
1887         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1888         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1889         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1890
1891         /*
1892          * set BBP back to BW20
1893          */
1894         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1895         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1896         rt2800_bbp_write(rt2x00dev, 4, bbp);
1897
1898         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1899             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1900             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1901             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1902                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1903
1904         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1905         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1906         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1907
1908         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1909         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1910         if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1911             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1912             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1913                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1914                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1915                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1916         }
1917         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1918         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1919                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1920                                   rt2x00_get_field16(eeprom,
1921                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
1922         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1923
1924         if (rt2x00_rt(rt2x00dev, RT3090)) {
1925                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1926
1927                 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1928                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1929                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1930                 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1931                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1932
1933                 rt2800_bbp_write(rt2x00dev, 138, bbp);
1934         }
1935
1936         if (rt2x00_rt(rt2x00dev, RT3071) ||
1937             rt2x00_rt(rt2x00dev, RT3090) ||
1938             rt2x00_rt(rt2x00dev, RT3390)) {
1939                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1940                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1941                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1942                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1943                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1944                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1945                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1946
1947                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1948                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1949                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1950
1951                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1952                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1953                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1954
1955                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1956                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1957                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1958         }
1959
1960         if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1961                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1962                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1963                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1964                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1965                 else
1966                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1967                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1968                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1969                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1970                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1971         }
1972
1973         return 0;
1974 }
1975 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1976
1977 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1978 {
1979         u32 reg;
1980
1981         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1982
1983         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1984 }
1985 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1986
1987 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1988 {
1989         u32 reg;
1990
1991         mutex_lock(&rt2x00dev->csr_mutex);
1992
1993         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
1994         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1995         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1996         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1997         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
1998
1999         /* Wait until the EEPROM has been loaded */
2000         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2001
2002         /* Apparently the data is read from end to start */
2003         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2004                                         (u32 *)&rt2x00dev->eeprom[i]);
2005         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2006                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2007         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2008                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2009         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2010                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2011
2012         mutex_unlock(&rt2x00dev->csr_mutex);
2013 }
2014
2015 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2016 {
2017         unsigned int i;
2018
2019         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2020                 rt2800_efuse_read(rt2x00dev, i);
2021 }
2022 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2023
2024 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2025 {
2026         u16 word;
2027         u8 *mac;
2028         u8 default_lna_gain;
2029
2030         /*
2031          * Start validation of the data that has been read.
2032          */
2033         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2034         if (!is_valid_ether_addr(mac)) {
2035                 random_ether_addr(mac);
2036                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2037         }
2038
2039         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2040         if (word == 0xffff) {
2041                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2042                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2043                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2044                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2045                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2046         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2047                    rt2x00_rt(rt2x00dev, RT2870) ||
2048                    rt2x00_rt(rt2x00dev, RT2872)) {
2049                 /*
2050                  * There is a max of 2 RX streams for RT28x0 series
2051                  */
2052                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2053                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2054                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2055         }
2056
2057         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2058         if (word == 0xffff) {
2059                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2060                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2061                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2062                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2063                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2064                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2065                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2066                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2067                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2068                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2069                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2070                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2071         }
2072
2073         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2074         if ((word & 0x00ff) == 0x00ff) {
2075                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2076                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2077                                    LED_MODE_TXRX_ACTIVITY);
2078                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2079                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2080                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2081                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2082                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2083                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2084         }
2085
2086         /*
2087          * During the LNA validation we are going to use
2088          * lna0 as correct value. Note that EEPROM_LNA
2089          * is never validated.
2090          */
2091         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2092         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2093
2094         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2095         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2096                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2097         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2098                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2099         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2100
2101         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2102         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2103                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2104         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2105             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2106                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2107                                    default_lna_gain);
2108         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2109
2110         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2111         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2112                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2113         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2114                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2115         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2116
2117         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2118         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2119                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2120         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2121             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2122                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2123                                    default_lna_gain);
2124         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2125
2126         return 0;
2127 }
2128 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2129
2130 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2131 {
2132         u32 reg;
2133         u16 value;
2134         u16 eeprom;
2135
2136         /*
2137          * Read EEPROM word for configuration.
2138          */
2139         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2140
2141         /*
2142          * Identify RF chipset.
2143          */
2144         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2145         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2146
2147         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2148                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2149
2150         if (!rt2x00_rt(rt2x00dev, RT2860) &&
2151             !rt2x00_rt(rt2x00dev, RT2870) &&
2152             !rt2x00_rt(rt2x00dev, RT2872) &&
2153             !rt2x00_rt(rt2x00dev, RT2883) &&
2154             !rt2x00_rt(rt2x00dev, RT3070) &&
2155             !rt2x00_rt(rt2x00dev, RT3071) &&
2156             !rt2x00_rt(rt2x00dev, RT3090) &&
2157             !rt2x00_rt(rt2x00dev, RT3390) &&
2158             !rt2x00_rt(rt2x00dev, RT3572)) {
2159                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2160                 return -ENODEV;
2161         }
2162
2163         if (!rt2x00_rf(rt2x00dev, RF2820) &&
2164             !rt2x00_rf(rt2x00dev, RF2850) &&
2165             !rt2x00_rf(rt2x00dev, RF2720) &&
2166             !rt2x00_rf(rt2x00dev, RF2750) &&
2167             !rt2x00_rf(rt2x00dev, RF3020) &&
2168             !rt2x00_rf(rt2x00dev, RF2020) &&
2169             !rt2x00_rf(rt2x00dev, RF3021) &&
2170             !rt2x00_rf(rt2x00dev, RF3022) &&
2171             !rt2x00_rf(rt2x00dev, RF3052)) {
2172                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2173                 return -ENODEV;
2174         }
2175
2176         /*
2177          * Identify default antenna configuration.
2178          */
2179         rt2x00dev->default_ant.tx =
2180             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2181         rt2x00dev->default_ant.rx =
2182             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2183
2184         /*
2185          * Read frequency offset and RF programming sequence.
2186          */
2187         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2188         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2189
2190         /*
2191          * Read external LNA informations.
2192          */
2193         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2194
2195         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2196                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2197         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2198                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2199
2200         /*
2201          * Detect if this device has an hardware controlled radio.
2202          */
2203         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2204                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2205
2206         /*
2207          * Store led settings, for correct led behaviour.
2208          */
2209 #ifdef CONFIG_RT2X00_LIB_LEDS
2210         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2211         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2212         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2213
2214         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2215 #endif /* CONFIG_RT2X00_LIB_LEDS */
2216
2217         return 0;
2218 }
2219 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
2220
2221 /*
2222  * RF value list for rt28x0
2223  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2224  */
2225 static const struct rf_channel rf_vals[] = {
2226         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2227         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2228         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2229         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2230         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2231         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2232         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2233         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2234         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2235         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2236         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2237         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2238         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2239         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2240
2241         /* 802.11 UNI / HyperLan 2 */
2242         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2243         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2244         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2245         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2246         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2247         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2248         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2249         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2250         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2251         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2252         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2253         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2254
2255         /* 802.11 HyperLan 2 */
2256         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2257         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2258         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2259         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2260         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2261         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2262         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2263         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2264         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2265         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2266         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2267         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2268         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2269         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2270         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2271         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2272
2273         /* 802.11 UNII */
2274         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2275         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2276         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2277         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2278         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2279         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2280         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2281         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2282         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2283         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2284         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2285
2286         /* 802.11 Japan */
2287         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2288         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2289         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2290         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2291         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2292         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2293         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2294 };
2295
2296 /*
2297  * RF value list for rt3070
2298  * Supports: 2.4 GHz
2299  */
2300 static const struct rf_channel rf_vals_302x[] = {
2301         {1,  241, 2, 2 },
2302         {2,  241, 2, 7 },
2303         {3,  242, 2, 2 },
2304         {4,  242, 2, 7 },
2305         {5,  243, 2, 2 },
2306         {6,  243, 2, 7 },
2307         {7,  244, 2, 2 },
2308         {8,  244, 2, 7 },
2309         {9,  245, 2, 2 },
2310         {10, 245, 2, 7 },
2311         {11, 246, 2, 2 },
2312         {12, 246, 2, 7 },
2313         {13, 247, 2, 2 },
2314         {14, 248, 2, 4 },
2315 };
2316
2317 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2318 {
2319         struct hw_mode_spec *spec = &rt2x00dev->spec;
2320         struct channel_info *info;
2321         char *tx_power1;
2322         char *tx_power2;
2323         unsigned int i;
2324         u16 eeprom;
2325
2326         /*
2327          * Disable powersaving as default on PCI devices.
2328          */
2329         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
2330                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2331
2332         /*
2333          * Initialize all hw fields.
2334          */
2335         rt2x00dev->hw->flags =
2336             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2337             IEEE80211_HW_SIGNAL_DBM |
2338             IEEE80211_HW_SUPPORTS_PS |
2339             IEEE80211_HW_PS_NULLFUNC_STACK;
2340
2341         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2342         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2343                                 rt2x00_eeprom_addr(rt2x00dev,
2344                                                    EEPROM_MAC_ADDR_0));
2345
2346         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2347
2348         /*
2349          * Initialize hw_mode information.
2350          */
2351         spec->supported_bands = SUPPORT_BAND_2GHZ;
2352         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2353
2354         if (rt2x00_rf(rt2x00dev, RF2820) ||
2355             rt2x00_rf(rt2x00dev, RF2720) ||
2356             rt2x00_rf(rt2x00dev, RF3052)) {
2357                 spec->num_channels = 14;
2358                 spec->channels = rf_vals;
2359         } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
2360                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2361                 spec->num_channels = ARRAY_SIZE(rf_vals);
2362                 spec->channels = rf_vals;
2363         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
2364                    rt2x00_rf(rt2x00dev, RF2020) ||
2365                    rt2x00_rf(rt2x00dev, RF3021) ||
2366                    rt2x00_rf(rt2x00dev, RF3022)) {
2367                 spec->num_channels = ARRAY_SIZE(rf_vals_302x);
2368                 spec->channels = rf_vals_302x;
2369         }
2370
2371         /*
2372          * Initialize HT information.
2373          */
2374         if (!rt2x00_rf(rt2x00dev, RF2020))
2375                 spec->ht.ht_supported = true;
2376         else
2377                 spec->ht.ht_supported = false;
2378
2379         /*
2380          * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2381          * reception problems with HT40 capable 11n APs
2382          */
2383         spec->ht.cap =
2384             IEEE80211_HT_CAP_GRN_FLD |
2385             IEEE80211_HT_CAP_SGI_20 |
2386             IEEE80211_HT_CAP_SGI_40 |
2387             IEEE80211_HT_CAP_TX_STBC |
2388             IEEE80211_HT_CAP_RX_STBC;
2389         spec->ht.ampdu_factor = 3;
2390         spec->ht.ampdu_density = 4;
2391         spec->ht.mcs.tx_params =
2392             IEEE80211_HT_MCS_TX_DEFINED |
2393             IEEE80211_HT_MCS_TX_RX_DIFF |
2394             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2395                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2396
2397         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2398         case 3:
2399                 spec->ht.mcs.rx_mask[2] = 0xff;
2400         case 2:
2401                 spec->ht.mcs.rx_mask[1] = 0xff;
2402         case 1:
2403                 spec->ht.mcs.rx_mask[0] = 0xff;
2404                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2405                 break;
2406         }
2407
2408         /*
2409          * Create channel information array
2410          */
2411         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2412         if (!info)
2413                 return -ENOMEM;
2414
2415         spec->channels_info = info;
2416
2417         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2418         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2419
2420         for (i = 0; i < 14; i++) {
2421                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2422                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2423         }
2424
2425         if (spec->num_channels > 14) {
2426                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2427                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2428
2429                 for (i = 14; i < spec->num_channels; i++) {
2430                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2431                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2432                 }
2433         }
2434
2435         return 0;
2436 }
2437 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2438
2439 /*
2440  * IEEE80211 stack callback functions.
2441  */
2442 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2443                                 u32 *iv32, u16 *iv16)
2444 {
2445         struct rt2x00_dev *rt2x00dev = hw->priv;
2446         struct mac_iveiv_entry iveiv_entry;
2447         u32 offset;
2448
2449         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2450         rt2800_register_multiread(rt2x00dev, offset,
2451                                       &iveiv_entry, sizeof(iveiv_entry));
2452
2453         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
2454         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
2455 }
2456
2457 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2458 {
2459         struct rt2x00_dev *rt2x00dev = hw->priv;
2460         u32 reg;
2461         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2462
2463         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2464         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2465         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2466
2467         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2468         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2469         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2470
2471         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2472         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2473         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2474
2475         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2476         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2477         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2478
2479         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2480         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2481         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2482
2483         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2484         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2485         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2486
2487         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2488         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2489         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2490
2491         return 0;
2492 }
2493
2494 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2495                           const struct ieee80211_tx_queue_params *params)
2496 {
2497         struct rt2x00_dev *rt2x00dev = hw->priv;
2498         struct data_queue *queue;
2499         struct rt2x00_field32 field;
2500         int retval;
2501         u32 reg;
2502         u32 offset;
2503
2504         /*
2505          * First pass the configuration through rt2x00lib, that will
2506          * update the queue settings and validate the input. After that
2507          * we are free to update the registers based on the value
2508          * in the queue parameter.
2509          */
2510         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2511         if (retval)
2512                 return retval;
2513
2514         /*
2515          * We only need to perform additional register initialization
2516          * for WMM queues/
2517          */
2518         if (queue_idx >= 4)
2519                 return 0;
2520
2521         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2522
2523         /* Update WMM TXOP register */
2524         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2525         field.bit_offset = (queue_idx & 1) * 16;
2526         field.bit_mask = 0xffff << field.bit_offset;
2527
2528         rt2800_register_read(rt2x00dev, offset, &reg);
2529         rt2x00_set_field32(&reg, field, queue->txop);
2530         rt2800_register_write(rt2x00dev, offset, reg);
2531
2532         /* Update WMM registers */
2533         field.bit_offset = queue_idx * 4;
2534         field.bit_mask = 0xf << field.bit_offset;
2535
2536         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2537         rt2x00_set_field32(&reg, field, queue->aifs);
2538         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2539
2540         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2541         rt2x00_set_field32(&reg, field, queue->cw_min);
2542         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2543
2544         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2545         rt2x00_set_field32(&reg, field, queue->cw_max);
2546         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2547
2548         /* Update EDCA registers */
2549         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2550
2551         rt2800_register_read(rt2x00dev, offset, &reg);
2552         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2553         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2554         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2555         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2556         rt2800_register_write(rt2x00dev, offset, reg);
2557
2558         return 0;
2559 }
2560
2561 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2562 {
2563         struct rt2x00_dev *rt2x00dev = hw->priv;
2564         u64 tsf;
2565         u32 reg;
2566
2567         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2568         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2569         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2570         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2571
2572         return tsf;
2573 }
2574
2575 const struct ieee80211_ops rt2800_mac80211_ops = {
2576         .tx                     = rt2x00mac_tx,
2577         .start                  = rt2x00mac_start,
2578         .stop                   = rt2x00mac_stop,
2579         .add_interface          = rt2x00mac_add_interface,
2580         .remove_interface       = rt2x00mac_remove_interface,
2581         .config                 = rt2x00mac_config,
2582         .configure_filter       = rt2x00mac_configure_filter,
2583         .set_tim                = rt2x00mac_set_tim,
2584         .set_key                = rt2x00mac_set_key,
2585         .get_stats              = rt2x00mac_get_stats,
2586         .get_tkip_seq           = rt2800_get_tkip_seq,
2587         .set_rts_threshold      = rt2800_set_rts_threshold,
2588         .bss_info_changed       = rt2x00mac_bss_info_changed,
2589         .conf_tx                = rt2800_conf_tx,
2590         .get_tsf                = rt2800_get_tsf,
2591         .rfkill_poll            = rt2x00mac_rfkill_poll,
2592 };
2593 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);