SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/p54/p54pci.c

   1
   2 /*
   3  * Linux device driver for PCI based Prism54
   4  *
   5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
   6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
   7  *
   8  * Based on the islsm (softmac prism54) driver, which is:
   9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/pci.h>
  18 #include <linux/firmware.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/delay.h>
  21 #include <linux/completion.h>
  22 #include <net/mac80211.h>
  23
  24 #include "p54.h"
  25 #include "lmac.h"
  26 #include "p54pci.h"
  27
  28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  30 MODULE_LICENSE("GPL");
  31 MODULE_ALIAS("prism54pci");
  32 MODULE_FIRMWARE("isl3886pci");
  33
  34 static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  35         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  36         { PCI_DEVICE(0x1260, 0x3890) },
  37         /* 3COM 3CRWE154G72 Wireless LAN adapter */
  38         { PCI_DEVICE(0x10b7, 0x6001) },
  39         /* Intersil PRISM Indigo Wireless LAN adapter */
  40         { PCI_DEVICE(0x1260, 0x3877) },
  41         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  42         { PCI_DEVICE(0x1260, 0x3886) },
  43         { },
  44 };
  45
  46 MODULE_DEVICE_TABLE(pci, p54p_table);
  47
  48 static int p54p_upload_firmware(struct ieee80211_hw *dev)
  49 {
  50         struct p54p_priv *priv = dev->priv;
  51         __le32 reg;
  52         int err;
  53         __le32 *data;
  54         u32 remains, left, device_addr;
  55
  56         P54P_WRITE(int_enable, cpu_to_le32(0));
  57         P54P_READ(int_enable);
  58         udelay(10);
  59
  60         reg = P54P_READ(ctrl_stat);
  61         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  63         P54P_WRITE(ctrl_stat, reg);
  64         P54P_READ(ctrl_stat);
  65         udelay(10);
  66
  67         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  68         P54P_WRITE(ctrl_stat, reg);
  69         wmb();
  70         udelay(10);
  71
  72         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  73         P54P_WRITE(ctrl_stat, reg);
  74         wmb();
  75
  76         /* wait for the firmware to reset properly */
  77         mdelay(10);
  78
  79         err = p54_parse_firmware(dev, priv->firmware);
  80         if (err)
  81                 return err;
  82
  83         if (priv->common.fw_interface != FW_LM86) {
  84                 dev_err(&priv->pdev->dev, "wrong firmware, "
  85                         "please get a LM86(PCI) firmware a try again.\n");
  86                 return -EINVAL;
  87         }
  88
  89         data = (__le32 *) priv->firmware->data;
  90         remains = priv->firmware->size;
  91         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  92         while (remains) {
  93                 u32 i = 0;
  94                 left = min((u32)0x1000, remains);
  95                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  96                 P54P_READ(int_enable);
  97
  98                 device_addr += 0x1000;
  99                 while (i < left) {
 100                         P54P_WRITE(direct_mem_win[i], *data++);
 101                         i += sizeof(u32);
 102                 }
 103
 104                 remains -= left;
 105                 P54P_READ(int_enable);
 106         }
 107
 108         reg = P54P_READ(ctrl_stat);
 109         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
 110         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 111         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
 112         P54P_WRITE(ctrl_stat, reg);
 113         P54P_READ(ctrl_stat);
 114         udelay(10);
 115
 116         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
 117         P54P_WRITE(ctrl_stat, reg);
 118         wmb();
 119         udelay(10);
 120
 121         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
 122         P54P_WRITE(ctrl_stat, reg);
 123         wmb();
 124         udelay(10);
 125
 126         /* wait for the firmware to boot properly */
 127         mdelay(100);
 128
 129         return 0;
 130 }
 131
 132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
 133         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 134         struct sk_buff **rx_buf)
 135 {
 136         struct p54p_priv *priv = dev->priv;
 137         struct p54p_ring_control *ring_control = priv->ring_control;
 138         u32 limit, idx, i;
 139
 140         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
 141         limit = idx;
 142         limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
 143         limit = ring_limit - limit;
 144
 145         i = idx % ring_limit;
 146         while (limit-- > 1) {
 147                 struct p54p_desc *desc = &ring[i];
 148
 149                 if (!desc->host_addr) {
 150                         struct sk_buff *skb;
 151                         dma_addr_t mapping;
 152                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
 153                         if (!skb)
 154                                 break;
 155
 156                         mapping = pci_map_single(priv->pdev,
 157                                                  skb_tail_pointer(skb),
 158                                                  priv->common.rx_mtu + 32,
 159                                                  PCI_DMA_FROMDEVICE);
 160                         desc->host_addr = cpu_to_le32(mapping);
 161                         desc->device_addr = 0;  // FIXME: necessary?
 162                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 163                         desc->flags = 0;
 164                         rx_buf[i] = skb;
 165                 }
 166
 167                 i++;
 168                 idx++;
 169                 i %= ring_limit;
 170         }
 171
 172         wmb();
 173         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
 174 }
 175
 176 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
 177         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 178         struct sk_buff **rx_buf)
 179 {
 180         struct p54p_priv *priv = dev->priv;
 181         struct p54p_ring_control *ring_control = priv->ring_control;
 182         struct p54p_desc *desc;
 183         u32 idx, i;
 184
 185         i = (*index) % ring_limit;
 186         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
 187         idx %= ring_limit;
 188         while (i != idx) {
 189                 u16 len;
 190                 struct sk_buff *skb;
 191                 desc = &ring[i];
 192                 len = le16_to_cpu(desc->len);
 193                 skb = rx_buf[i];
 194
 195                 if (!skb) {
 196                         i++;
 197                         i %= ring_limit;
 198                         continue;
 199                 }
 200                 skb_put(skb, len);
 201
 202                 if (p54_rx(dev, skb)) {
 203                         pci_unmap_single(priv->pdev,
 204                                          le32_to_cpu(desc->host_addr),
 205                                          priv->common.rx_mtu + 32,
 206                                          PCI_DMA_FROMDEVICE);
 207                         rx_buf[i] = NULL;
 208                         desc->host_addr = 0;
 209                 } else {
 210                         skb_trim(skb, 0);
 211                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
 212                 }
 213
 214                 i++;
 215                 i %= ring_limit;
 216         }
 217
 218         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
 219 }
 220
 221 /* caller must hold priv->lock */
 222 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
 223         int ring_index, struct p54p_desc *ring, u32 ring_limit,
 224         void **tx_buf)
 225 {
 226         struct p54p_priv *priv = dev->priv;
 227         struct p54p_ring_control *ring_control = priv->ring_control;
 228         struct p54p_desc *desc;
 229         u32 idx, i;
 230
 231         i = (*index) % ring_limit;
 232         (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
 233         idx %= ring_limit;
 234
 235         while (i != idx) {
 236                 desc = &ring[i];
 237                 if (tx_buf[i])
 238                         if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
 239                                 p54_free_skb(dev, tx_buf[i]);
 240                 tx_buf[i] = NULL;
 241
 242                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
 243                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
 244
 245                 desc->host_addr = 0;
 246                 desc->device_addr = 0;
 247                 desc->len = 0;
 248                 desc->flags = 0;
 249
 250                 i++;
 251                 i %= ring_limit;
 252         }
 253 }
 254
 255 static void p54p_rx_tasklet(unsigned long dev_id)
 256 {
 257         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
 258         struct p54p_priv *priv = dev->priv;
 259         struct p54p_ring_control *ring_control = priv->ring_control;
 260
 261         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
 262                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
 263
 264         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
 265                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
 266
 267         wmb();
 268         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 269 }
 270
 271 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
 272 {
 273         struct ieee80211_hw *dev = dev_id;
 274         struct p54p_priv *priv = dev->priv;
 275         struct p54p_ring_control *ring_control = priv->ring_control;
 276         __le32 reg;
 277
 278         spin_lock(&priv->lock);
 279         reg = P54P_READ(int_ident);
 280         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
 281                 spin_unlock(&priv->lock);
 282                 return IRQ_HANDLED;
 283         }
 284
 285         P54P_WRITE(int_ack, reg);
 286
 287         reg &= P54P_READ(int_enable);
 288
 289         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
 290                 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
 291                                    3, ring_control->tx_mgmt,
 292                                    ARRAY_SIZE(ring_control->tx_mgmt),
 293                                    priv->tx_buf_mgmt);
 294
 295                 p54p_check_tx_ring(dev, &priv->tx_idx_data,
 296                                    1, ring_control->tx_data,
 297                                    ARRAY_SIZE(ring_control->tx_data),
 298                                    priv->tx_buf_data);
 299
 300                 tasklet_schedule(&priv->rx_tasklet);
 301
 302         } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
 303                 complete(&priv->boot_comp);
 304
 305         spin_unlock(&priv->lock);
 306
 307         return reg ? IRQ_HANDLED : IRQ_NONE;
 308 }
 309
 310 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
 311 {
 312         struct p54p_priv *priv = dev->priv;
 313         struct p54p_ring_control *ring_control = priv->ring_control;
 314         unsigned long flags;
 315         struct p54p_desc *desc;
 316         dma_addr_t mapping;
 317         u32 device_idx, idx, i;
 318
 319         spin_lock_irqsave(&priv->lock, flags);
 320
 321         device_idx = le32_to_cpu(ring_control->device_idx[1]);
 322         idx = le32_to_cpu(ring_control->host_idx[1]);
 323         i = idx % ARRAY_SIZE(ring_control->tx_data);
 324
 325         priv->tx_buf_data[i] = skb;
 326         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
 327                                  PCI_DMA_TODEVICE);
 328         desc = &ring_control->tx_data[i];
 329         desc->host_addr = cpu_to_le32(mapping);
 330         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
 331         desc->len = cpu_to_le16(skb->len);
 332         desc->flags = 0;
 333
 334         wmb();
 335         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
 336         spin_unlock_irqrestore(&priv->lock, flags);
 337
 338         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 339         P54P_READ(dev_int);
 340 }
 341
 342 static void p54p_stop(struct ieee80211_hw *dev)
 343 {
 344         struct p54p_priv *priv = dev->priv;
 345         struct p54p_ring_control *ring_control = priv->ring_control;
 346         unsigned int i;
 347         struct p54p_desc *desc;
 348
 349         tasklet_kill(&priv->rx_tasklet);
 350
 351         P54P_WRITE(int_enable, cpu_to_le32(0));
 352         P54P_READ(int_enable);
 353         udelay(10);
 354
 355         free_irq(priv->pdev->irq, dev);
 356
 357         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 358
 359         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
 360                 desc = &ring_control->rx_data[i];
 361                 if (desc->host_addr)
 362                         pci_unmap_single(priv->pdev,
 363                                          le32_to_cpu(desc->host_addr),
 364                                          priv->common.rx_mtu + 32,
 365                                          PCI_DMA_FROMDEVICE);
 366                 kfree_skb(priv->rx_buf_data[i]);
 367                 priv->rx_buf_data[i] = NULL;
 368         }
 369
 370         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
 371                 desc = &ring_control->rx_mgmt[i];
 372                 if (desc->host_addr)
 373                         pci_unmap_single(priv->pdev,
 374                                          le32_to_cpu(desc->host_addr),
 375                                          priv->common.rx_mtu + 32,
 376                                          PCI_DMA_FROMDEVICE);
 377                 kfree_skb(priv->rx_buf_mgmt[i]);
 378                 priv->rx_buf_mgmt[i] = NULL;
 379         }
 380
 381         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
 382                 desc = &ring_control->tx_data[i];
 383                 if (desc->host_addr)
 384                         pci_unmap_single(priv->pdev,
 385                                          le32_to_cpu(desc->host_addr),
 386                                          le16_to_cpu(desc->len),
 387                                          PCI_DMA_TODEVICE);
 388
 389                 p54_free_skb(dev, priv->tx_buf_data[i]);
 390                 priv->tx_buf_data[i] = NULL;
 391         }
 392
 393         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
 394                 desc = &ring_control->tx_mgmt[i];
 395                 if (desc->host_addr)
 396                         pci_unmap_single(priv->pdev,
 397                                          le32_to_cpu(desc->host_addr),
 398                                          le16_to_cpu(desc->len),
 399                                          PCI_DMA_TODEVICE);
 400
 401                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
 402                 priv->tx_buf_mgmt[i] = NULL;
 403         }
 404
 405         memset(ring_control, 0, sizeof(*ring_control));
 406 }
 407
 408 static int p54p_open(struct ieee80211_hw *dev)
 409 {
 410         struct p54p_priv *priv = dev->priv;
 411         int err;
 412
 413         init_completion(&priv->boot_comp);
 414         err = request_irq(priv->pdev->irq, p54p_interrupt,
 415                           IRQF_SHARED, "p54pci", dev);
 416         if (err) {
 417                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
 418                 return err;
 419         }
 420
 421         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
 422         err = p54p_upload_firmware(dev);
 423         if (err) {
 424                 free_irq(priv->pdev->irq, dev);
 425                 return err;
 426         }
 427         priv->rx_idx_data = priv->tx_idx_data = 0;
 428         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
 429
 430         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
 431                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
 432
 433         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
 434                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
 435
 436         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
 437         P54P_READ(ring_control_base);
 438         wmb();
 439         udelay(10);
 440
 441         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
 442         P54P_READ(int_enable);
 443         wmb();
 444         udelay(10);
 445
 446         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
 447         P54P_READ(dev_int);
 448
 449         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
 450                 printk(KERN_ERR "%s: Cannot boot firmware!\n",
 451                        wiphy_name(dev->wiphy));
 452                 p54p_stop(dev);
 453                 return -ETIMEDOUT;
 454         }
 455
 456         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
 457         P54P_READ(int_enable);
 458         wmb();
 459         udelay(10);
 460
 461         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
 462         P54P_READ(dev_int);
 463         wmb();
 464         udelay(10);
 465
 466         return 0;
 467 }
 468
 469 static int __devinit p54p_probe(struct pci_dev *pdev,
 470                                 const struct pci_device_id *id)
 471 {
 472         struct p54p_priv *priv;
 473         struct ieee80211_hw *dev;
 474         unsigned long mem_addr, mem_len;
 475         int err;
 476
 477         err = pci_enable_device(pdev);
 478         if (err) {
 479                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
 480                 return err;
 481         }
 482
 483         mem_addr = pci_resource_start(pdev, 0);
 484         mem_len = pci_resource_len(pdev, 0);
 485         if (mem_len < sizeof(struct p54p_csr)) {
 486                 dev_err(&pdev->dev, "Too short PCI resources\n");
 487                 goto err_disable_dev;
 488         }
 489
 490         err = pci_request_regions(pdev, "p54pci");
 491         if (err) {
 492                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
 493                 goto err_disable_dev;
 494         }
 495
 496         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
 497             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
 498                 dev_err(&pdev->dev, "No suitable DMA available\n");
 499                 goto err_free_reg;
 500         }
 501
 502         pci_set_master(pdev);
 503         pci_try_set_mwi(pdev);
 504
 505         pci_write_config_byte(pdev, 0x40, 0);
 506         pci_write_config_byte(pdev, 0x41, 0);
 507
 508         dev = p54_init_common(sizeof(*priv));
 509         if (!dev) {
 510                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
 511                 err = -ENOMEM;
 512                 goto err_free_reg;
 513         }
 514
 515         priv = dev->priv;
 516         priv->pdev = pdev;
 517
 518         SET_IEEE80211_DEV(dev, &pdev->dev);
 519         pci_set_drvdata(pdev, dev);
 520
 521         priv->map = ioremap(mem_addr, mem_len);
 522         if (!priv->map) {
 523                 dev_err(&pdev->dev, "Cannot map device memory\n");
 524                 err = -ENOMEM;
 525                 goto err_free_dev;
 526         }
 527
 528         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
 529                                                   &priv->ring_control_dma);
 530         if (!priv->ring_control) {
 531                 dev_err(&pdev->dev, "Cannot allocate rings\n");
 532                 err = -ENOMEM;
 533                 goto err_iounmap;
 534         }
 535         priv->common.open = p54p_open;
 536         priv->common.stop = p54p_stop;
 537         priv->common.tx = p54p_tx;
 538
 539         spin_lock_init(&priv->lock);
 540         tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
 541
 542         err = request_firmware(&priv->firmware, "isl3886pci",
 543                                &priv->pdev->dev);
 544         if (err) {
 545                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
 546                 err = request_firmware(&priv->firmware, "isl3886",
 547                                        &priv->pdev->dev);
 548                 if (err)
 549                         goto err_free_common;
 550         }
 551
 552         err = p54p_open(dev);
 553         if (err)
 554                 goto err_free_common;
 555         err = p54_read_eeprom(dev);
 556         p54p_stop(dev);
 557         if (err)
 558                 goto err_free_common;
 559
 560         err = p54_register_common(dev, &pdev->dev);
 561         if (err)
 562                 goto err_free_common;
 563
 564         return 0;
 565
 566  err_free_common:
 567         release_firmware(priv->firmware);
 568         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 569                             priv->ring_control, priv->ring_control_dma);
 570
 571  err_iounmap:
 572         iounmap(priv->map);
 573
 574  err_free_dev:
 575         pci_set_drvdata(pdev, NULL);
 576         p54_free_common(dev);
 577
 578  err_free_reg:
 579         pci_release_regions(pdev);
 580  err_disable_dev:
 581         pci_disable_device(pdev);
 582         return err;
 583 }
 584
 585 static void __devexit p54p_remove(struct pci_dev *pdev)
 586 {
 587         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 588         struct p54p_priv *priv;
 589
 590         if (!dev)
 591                 return;
 592
 593         p54_unregister_common(dev);
 594         priv = dev->priv;
 595         release_firmware(priv->firmware);
 596         pci_free_consistent(pdev, sizeof(*priv->ring_control),
 597                             priv->ring_control, priv->ring_control_dma);
 598         iounmap(priv->map);
 599         pci_release_regions(pdev);
 600         pci_disable_device(pdev);
 601         p54_free_common(dev);
 602 }
 603
 604 #ifdef CONFIG_PM
 605 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
 606 {
 607         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 608         struct p54p_priv *priv = dev->priv;
 609
 610         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 611                 ieee80211_stop_queues(dev);
 612                 p54p_stop(dev);
 613         }
 614
 615         pci_save_state(pdev);
 616         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 617         return 0;
 618 }
 619
 620 static int p54p_resume(struct pci_dev *pdev)
 621 {
 622         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
 623         struct p54p_priv *priv = dev->priv;
 624
 625         pci_set_power_state(pdev, PCI_D0);
 626         pci_restore_state(pdev);
 627
 628         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
 629                 p54p_open(dev);
 630                 ieee80211_wake_queues(dev);
 631         }
 632
 633         return 0;
 634 }
 635 #endif /* CONFIG_PM */
 636
 637 static struct pci_driver p54p_driver = {
 638         .name           = "p54pci",
 639         .id_table       = p54p_table,
 640         .probe          = p54p_probe,
 641         .remove         = __devexit_p(p54p_remove),
 642 #ifdef CONFIG_PM
 643         .suspend        = p54p_suspend,
 644         .resume         = p54p_resume,
 645 #endif /* CONFIG_PM */
 646 };
 647
 648 static int __init p54p_init(void)
 649 {
 650         return pci_register_driver(&p54p_driver);
 651 }
 652
 653 static void __exit p54p_exit(void)
 654 {
 655         pci_unregister_driver(&p54p_driver);
 656 }
 657
 658 module_init(p54p_init);
 659 module_exit(p54p_exit);