2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
91 struct mwl8k_device_info {
95 struct rxd_ops *rxd_ops;
99 struct mwl8k_rx_queue {
102 /* hw receives here */
105 /* refill descs here */
112 DECLARE_PCI_UNMAP_ADDR(dma)
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
120 /* sw appends here */
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
126 struct sk_buff **skb;
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
135 struct firmware *ucode;
141 struct ieee80211_hw *hw;
143 struct pci_dev *pdev;
145 struct mwl8k_device_info *device_info;
147 struct rxd_ops *rxd_ops;
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
156 struct completion *hostcmd_wait;
158 /* lock held over TX and TX reap */
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
164 struct ieee80211_vif *vif;
166 struct ieee80211_channel *current_channel;
168 /* power management status cookie from firmware */
170 dma_addr_t cookie_dma;
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
191 bool radio_short_preamble;
192 bool sniffer_enabled;
195 /* XXX need to convert this to handle multiple interfaces */
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
206 struct work_struct finalize_join_worker;
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
212 /* Per interface specific private data */
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
220 /* BSSID of AP or IBSS */
222 u8 mac_addr[ETH_ALEN];
224 /* Index into station database. Returned by UPDATE_STADB. */
227 /* Non AMPDU sequence number assigned by driver */
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
330 snprintf(buf, bufsize, "0x%x", cmd);
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
352 release_firmware(*fw);
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
366 /* release current image */
368 mwl8k_release_fw(fw);
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
376 struct mwl8k_device_info *di = priv->device_info;
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
403 struct mwl8k_cmd_pkt {
409 } __attribute__((packed));
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
417 void __iomem *regs = priv->regs;
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
448 return loops ? 0 : -ETIMEDOUT;
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
454 struct mwl8k_cmd_pkt *cmd;
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
468 int block_size = length > 256 ? 256 : length;
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
479 length -= block_size;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
499 buffer = kmalloc(1024, GFP_KERNEL);
506 while (may_continue > 0) {
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
514 done += prev_block_size;
515 length -= prev_block_size;
518 if (block_size > 1024 || block_size > length) {
528 if (block_size == 0) {
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
543 if (!rc && length != 0)
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
596 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
597 if (ready_code == MWL8K_FWAP_READY) {
600 } else if (ready_code == MWL8K_FWSTA_READY) {
609 return loops ? 0 : -ETIMEDOUT;
614 * Defines shared between transmission and reception.
616 /* HT control fields for firmware */
621 } __attribute__((packed));
623 /* Firmware Station database operations */
624 #define MWL8K_STA_DB_ADD_ENTRY 0
625 #define MWL8K_STA_DB_MODIFY_ENTRY 1
626 #define MWL8K_STA_DB_DEL_ENTRY 2
627 #define MWL8K_STA_DB_FLUSH 3
629 /* Peer Entry flags - used to define the type of the peer node */
630 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
632 struct peer_capability_info {
633 /* Peer type - AP vs. STA. */
636 /* Basic 802.11 capabilities from assoc resp. */
639 /* Set if peer supports 802.11n high throughput (HT). */
642 /* Valid if HT is supported. */
644 __u8 extended_ht_caps;
645 struct ewc_ht_info ewc_info;
647 /* Legacy rate table. Intersection of our rates and peer rates. */
648 __u8 legacy_rates[12];
650 /* HT rate table. Intersection of our rates and peer rates. */
654 /* If set, interoperability mode, no proprietary extensions. */
658 __le16 amsdu_enabled;
659 } __attribute__((packed));
661 /* DMA header used by firmware and hardware. */
662 struct mwl8k_dma_data {
664 struct ieee80211_hdr wh;
666 } __attribute__((packed));
668 /* Routines to add/remove DMA header from skb. */
669 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
671 struct mwl8k_dma_data *tr;
674 tr = (struct mwl8k_dma_data *)skb->data;
675 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
677 if (hdrlen != sizeof(tr->wh)) {
678 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
679 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
680 *((__le16 *)(tr->data - 2)) = qos;
682 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
686 if (hdrlen != sizeof(*tr))
687 skb_pull(skb, sizeof(*tr) - hdrlen);
690 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
692 struct ieee80211_hdr *wh;
694 struct mwl8k_dma_data *tr;
697 * Add a firmware DMA header; the firmware requires that we
698 * present a 2-byte payload length followed by a 4-address
699 * header (without QoS field), followed (optionally) by any
700 * WEP/ExtIV header (but only filled in for CCMP).
702 wh = (struct ieee80211_hdr *)skb->data;
704 hdrlen = ieee80211_hdrlen(wh->frame_control);
705 if (hdrlen != sizeof(*tr))
706 skb_push(skb, sizeof(*tr) - hdrlen);
708 if (ieee80211_is_data_qos(wh->frame_control))
711 tr = (struct mwl8k_dma_data *)skb->data;
713 memmove(&tr->wh, wh, hdrlen);
714 if (hdrlen != sizeof(tr->wh))
715 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
718 * Firmware length is the length of the fully formed "802.11
719 * payload". That is, everything except for the 802.11 header.
720 * This includes all crypto material including the MIC.
722 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
727 * Packet reception for 88w8366.
729 struct mwl8k_rxd_8366 {
733 __le32 pkt_phys_addr;
734 __le32 next_rxd_phys_addr;
738 __le32 hw_noise_floor_info;
745 } __attribute__((packed));
747 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
748 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
749 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
751 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
753 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
755 struct mwl8k_rxd_8366 *rxd = _rxd;
757 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
758 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
761 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
763 struct mwl8k_rxd_8366 *rxd = _rxd;
765 rxd->pkt_len = cpu_to_le16(len);
766 rxd->pkt_phys_addr = cpu_to_le32(addr);
772 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
775 struct mwl8k_rxd_8366 *rxd = _rxd;
777 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
781 memset(status, 0, sizeof(*status));
783 status->signal = -rxd->rssi;
784 status->noise = -rxd->noise_floor;
786 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
787 status->flag |= RX_FLAG_HT;
788 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
789 status->flag |= RX_FLAG_40MHZ;
790 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
794 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
795 if (mwl8k_rates[i].hw_value == rxd->rate) {
796 status->rate_idx = i;
802 status->band = IEEE80211_BAND_2GHZ;
803 status->freq = ieee80211_channel_to_frequency(rxd->channel);
805 *qos = rxd->qos_control;
807 return le16_to_cpu(rxd->pkt_len);
810 static struct rxd_ops rxd_8366_ops = {
811 .rxd_size = sizeof(struct mwl8k_rxd_8366),
812 .rxd_init = mwl8k_rxd_8366_init,
813 .rxd_refill = mwl8k_rxd_8366_refill,
814 .rxd_process = mwl8k_rxd_8366_process,
818 * Packet reception for 88w8687.
820 struct mwl8k_rxd_8687 {
824 __le32 pkt_phys_addr;
825 __le32 next_rxd_phys_addr;
835 } __attribute__((packed));
837 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
838 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
839 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
840 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
841 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
842 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
844 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
846 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
848 struct mwl8k_rxd_8687 *rxd = _rxd;
850 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
851 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
854 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
856 struct mwl8k_rxd_8687 *rxd = _rxd;
858 rxd->pkt_len = cpu_to_le16(len);
859 rxd->pkt_phys_addr = cpu_to_le32(addr);
865 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
868 struct mwl8k_rxd_8687 *rxd = _rxd;
871 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
875 rate_info = le16_to_cpu(rxd->rate_info);
877 memset(status, 0, sizeof(*status));
879 status->signal = -rxd->rssi;
880 status->noise = -rxd->noise_level;
881 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
882 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
884 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
885 status->flag |= RX_FLAG_SHORTPRE;
886 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
887 status->flag |= RX_FLAG_40MHZ;
888 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
889 status->flag |= RX_FLAG_SHORT_GI;
890 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
891 status->flag |= RX_FLAG_HT;
893 status->band = IEEE80211_BAND_2GHZ;
894 status->freq = ieee80211_channel_to_frequency(rxd->channel);
896 *qos = rxd->qos_control;
898 return le16_to_cpu(rxd->pkt_len);
901 static struct rxd_ops rxd_8687_ops = {
902 .rxd_size = sizeof(struct mwl8k_rxd_8687),
903 .rxd_init = mwl8k_rxd_8687_init,
904 .rxd_refill = mwl8k_rxd_8687_refill,
905 .rxd_process = mwl8k_rxd_8687_process,
909 #define MWL8K_RX_DESCS 256
910 #define MWL8K_RX_MAXSZ 3800
912 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
914 struct mwl8k_priv *priv = hw->priv;
915 struct mwl8k_rx_queue *rxq = priv->rxq + index;
923 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
925 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
926 if (rxq->rxd == NULL) {
927 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
928 wiphy_name(hw->wiphy));
931 memset(rxq->rxd, 0, size);
933 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
934 if (rxq->buf == NULL) {
935 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
936 wiphy_name(hw->wiphy));
937 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
940 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
942 for (i = 0; i < MWL8K_RX_DESCS; i++) {
946 dma_addr_t next_dma_addr;
948 desc_size = priv->rxd_ops->rxd_size;
949 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
952 if (nexti == MWL8K_RX_DESCS)
954 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
956 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
962 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
964 struct mwl8k_priv *priv = hw->priv;
965 struct mwl8k_rx_queue *rxq = priv->rxq + index;
969 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
975 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
979 addr = pci_map_single(priv->pdev, skb->data,
980 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
984 if (rxq->tail == MWL8K_RX_DESCS)
986 rxq->buf[rx].skb = skb;
987 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
989 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
990 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
998 /* Must be called only when the card's reception is completely halted */
999 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1001 struct mwl8k_priv *priv = hw->priv;
1002 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1005 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1006 if (rxq->buf[i].skb != NULL) {
1007 pci_unmap_single(priv->pdev,
1008 pci_unmap_addr(&rxq->buf[i], dma),
1009 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1010 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1012 kfree_skb(rxq->buf[i].skb);
1013 rxq->buf[i].skb = NULL;
1020 pci_free_consistent(priv->pdev,
1021 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1022 rxq->rxd, rxq->rxd_dma);
1028 * Scan a list of BSSIDs to process for finalize join.
1029 * Allows for extension to process multiple BSSIDs.
1032 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1034 return priv->capture_beacon &&
1035 ieee80211_is_beacon(wh->frame_control) &&
1036 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1039 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1040 struct sk_buff *skb)
1042 struct mwl8k_priv *priv = hw->priv;
1044 priv->capture_beacon = false;
1045 memset(priv->capture_bssid, 0, ETH_ALEN);
1048 * Use GFP_ATOMIC as rxq_process is called from
1049 * the primary interrupt handler, memory allocation call
1052 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1053 if (priv->beacon_skb != NULL)
1054 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1057 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1059 struct mwl8k_priv *priv = hw->priv;
1060 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1064 while (rxq->rxd_count && limit--) {
1065 struct sk_buff *skb;
1068 struct ieee80211_rx_status status;
1071 skb = rxq->buf[rxq->head].skb;
1075 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1077 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1081 rxq->buf[rxq->head].skb = NULL;
1083 pci_unmap_single(priv->pdev,
1084 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1085 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1086 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1089 if (rxq->head == MWL8K_RX_DESCS)
1094 skb_put(skb, pkt_len);
1095 mwl8k_remove_dma_header(skb, qos);
1098 * Check for a pending join operation. Save a
1099 * copy of the beacon and schedule a tasklet to
1100 * send a FINALIZE_JOIN command to the firmware.
1102 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1103 mwl8k_save_beacon(hw, skb);
1105 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1106 ieee80211_rx_irqsafe(hw, skb);
1116 * Packet transmission.
1119 #define MWL8K_TXD_STATUS_OK 0x00000001
1120 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1121 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1122 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1123 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1125 #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1126 #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1127 #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1128 #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1129 #define MWL8K_QOS_EOSP 0x0010
1131 struct mwl8k_tx_desc {
1136 __le32 pkt_phys_addr;
1138 __u8 dest_MAC_addr[ETH_ALEN];
1139 __le32 next_txd_phys_addr;
1144 } __attribute__((packed));
1146 #define MWL8K_TX_DESCS 128
1148 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1150 struct mwl8k_priv *priv = hw->priv;
1151 struct mwl8k_tx_queue *txq = priv->txq + index;
1155 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1156 txq->stats.limit = MWL8K_TX_DESCS;
1160 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1162 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1163 if (txq->txd == NULL) {
1164 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1165 wiphy_name(hw->wiphy));
1168 memset(txq->txd, 0, size);
1170 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1171 if (txq->skb == NULL) {
1172 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1173 wiphy_name(hw->wiphy));
1174 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1177 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1179 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1180 struct mwl8k_tx_desc *tx_desc;
1183 tx_desc = txq->txd + i;
1184 nexti = (i + 1) % MWL8K_TX_DESCS;
1186 tx_desc->status = 0;
1187 tx_desc->next_txd_phys_addr =
1188 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1194 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1196 iowrite32(MWL8K_H2A_INT_PPA_READY,
1197 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1198 iowrite32(MWL8K_H2A_INT_DUMMY,
1199 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1200 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1203 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1205 struct mwl8k_priv *priv = hw->priv;
1208 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1209 struct mwl8k_tx_queue *txq = priv->txq + i;
1215 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1216 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1219 status = le32_to_cpu(tx_desc->status);
1220 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1225 if (tx_desc->pkt_len == 0)
1229 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1230 "fw_owned=%d drv_owned=%d unused=%d\n",
1231 wiphy_name(hw->wiphy), i,
1232 txq->stats.len, txq->head, txq->tail,
1233 fw_owned, drv_owned, unused);
1238 * Must be called with priv->fw_mutex held and tx queues stopped.
1240 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1242 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1244 struct mwl8k_priv *priv = hw->priv;
1245 DECLARE_COMPLETION_ONSTACK(tx_wait);
1252 * The TX queues are stopped at this point, so this test
1253 * doesn't need to take ->tx_lock.
1255 if (!priv->pending_tx_pkts)
1261 spin_lock_bh(&priv->tx_lock);
1262 priv->tx_wait = &tx_wait;
1265 unsigned long timeout;
1267 oldcount = priv->pending_tx_pkts;
1269 spin_unlock_bh(&priv->tx_lock);
1270 timeout = wait_for_completion_timeout(&tx_wait,
1271 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1272 spin_lock_bh(&priv->tx_lock);
1275 WARN_ON(priv->pending_tx_pkts);
1277 printk(KERN_NOTICE "%s: tx rings drained\n",
1278 wiphy_name(hw->wiphy));
1283 if (priv->pending_tx_pkts < oldcount) {
1284 printk(KERN_NOTICE "%s: timeout waiting for tx "
1285 "rings to drain (%d -> %d pkts), retrying\n",
1286 wiphy_name(hw->wiphy), oldcount,
1287 priv->pending_tx_pkts);
1292 priv->tx_wait = NULL;
1294 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1295 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1296 mwl8k_dump_tx_rings(hw);
1300 spin_unlock_bh(&priv->tx_lock);
1305 #define MWL8K_TXD_SUCCESS(status) \
1306 ((status) & (MWL8K_TXD_STATUS_OK | \
1307 MWL8K_TXD_STATUS_OK_RETRY | \
1308 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1310 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1312 struct mwl8k_priv *priv = hw->priv;
1313 struct mwl8k_tx_queue *txq = priv->txq + index;
1316 while (txq->stats.len > 0) {
1318 struct mwl8k_tx_desc *tx_desc;
1321 struct sk_buff *skb;
1322 struct ieee80211_tx_info *info;
1326 tx_desc = txq->txd + tx;
1328 status = le32_to_cpu(tx_desc->status);
1330 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1334 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1337 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1338 BUG_ON(txq->stats.len == 0);
1340 priv->pending_tx_pkts--;
1342 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1343 size = le16_to_cpu(tx_desc->pkt_len);
1345 txq->skb[tx] = NULL;
1347 BUG_ON(skb == NULL);
1348 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1350 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1352 /* Mark descriptor as unused */
1353 tx_desc->pkt_phys_addr = 0;
1354 tx_desc->pkt_len = 0;
1356 info = IEEE80211_SKB_CB(skb);
1357 ieee80211_tx_info_clear_status(info);
1358 if (MWL8K_TXD_SUCCESS(status))
1359 info->flags |= IEEE80211_TX_STAT_ACK;
1361 ieee80211_tx_status_irqsafe(hw, skb);
1366 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1367 ieee80211_wake_queue(hw, index);
1370 /* must be called only when the card's transmit is completely halted */
1371 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1373 struct mwl8k_priv *priv = hw->priv;
1374 struct mwl8k_tx_queue *txq = priv->txq + index;
1376 mwl8k_txq_reclaim(hw, index, 1);
1381 pci_free_consistent(priv->pdev,
1382 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1383 txq->txd, txq->txd_dma);
1388 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1390 struct mwl8k_priv *priv = hw->priv;
1391 struct ieee80211_tx_info *tx_info;
1392 struct mwl8k_vif *mwl8k_vif;
1393 struct ieee80211_hdr *wh;
1394 struct mwl8k_tx_queue *txq;
1395 struct mwl8k_tx_desc *tx;
1401 wh = (struct ieee80211_hdr *)skb->data;
1402 if (ieee80211_is_data_qos(wh->frame_control))
1403 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1407 mwl8k_add_dma_header(skb);
1408 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1410 tx_info = IEEE80211_SKB_CB(skb);
1411 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1413 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1414 u16 seqno = mwl8k_vif->seqno;
1416 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1417 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1418 mwl8k_vif->seqno = seqno++ % 4096;
1421 /* Setup firmware control bit fields for each frame type. */
1424 if (ieee80211_is_mgmt(wh->frame_control) ||
1425 ieee80211_is_ctl(wh->frame_control)) {
1427 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1428 } else if (ieee80211_is_data(wh->frame_control)) {
1430 if (is_multicast_ether_addr(wh->addr1))
1431 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1433 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1434 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1435 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1437 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1440 dma = pci_map_single(priv->pdev, skb->data,
1441 skb->len, PCI_DMA_TODEVICE);
1443 if (pci_dma_mapping_error(priv->pdev, dma)) {
1444 printk(KERN_DEBUG "%s: failed to dma map skb, "
1445 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1447 return NETDEV_TX_OK;
1450 spin_lock_bh(&priv->tx_lock);
1452 txq = priv->txq + index;
1454 BUG_ON(txq->skb[txq->tail] != NULL);
1455 txq->skb[txq->tail] = skb;
1457 tx = txq->txd + txq->tail;
1458 tx->data_rate = txdatarate;
1459 tx->tx_priority = index;
1460 tx->qos_control = cpu_to_le16(qos);
1461 tx->pkt_phys_addr = cpu_to_le32(dma);
1462 tx->pkt_len = cpu_to_le16(skb->len);
1464 tx->peer_id = mwl8k_vif->peer_id;
1466 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1470 priv->pending_tx_pkts++;
1473 if (txq->tail == MWL8K_TX_DESCS)
1476 if (txq->head == txq->tail)
1477 ieee80211_stop_queue(hw, index);
1479 mwl8k_tx_start(priv);
1481 spin_unlock_bh(&priv->tx_lock);
1483 return NETDEV_TX_OK;
1490 * We have the following requirements for issuing firmware commands:
1491 * - Some commands require that the packet transmit path is idle when
1492 * the command is issued. (For simplicity, we'll just quiesce the
1493 * transmit path for every command.)
1494 * - There are certain sequences of commands that need to be issued to
1495 * the hardware sequentially, with no other intervening commands.
1497 * This leads to an implementation of a "firmware lock" as a mutex that
1498 * can be taken recursively, and which is taken by both the low-level
1499 * command submission function (mwl8k_post_cmd) as well as any users of
1500 * that function that require issuing of an atomic sequence of commands,
1501 * and quiesces the transmit path whenever it's taken.
1503 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1505 struct mwl8k_priv *priv = hw->priv;
1507 if (priv->fw_mutex_owner != current) {
1510 mutex_lock(&priv->fw_mutex);
1511 ieee80211_stop_queues(hw);
1513 rc = mwl8k_tx_wait_empty(hw);
1515 ieee80211_wake_queues(hw);
1516 mutex_unlock(&priv->fw_mutex);
1521 priv->fw_mutex_owner = current;
1524 priv->fw_mutex_depth++;
1529 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1531 struct mwl8k_priv *priv = hw->priv;
1533 if (!--priv->fw_mutex_depth) {
1534 ieee80211_wake_queues(hw);
1535 priv->fw_mutex_owner = NULL;
1536 mutex_unlock(&priv->fw_mutex);
1542 * Command processing.
1545 /* Timeout firmware commands after 10s */
1546 #define MWL8K_CMD_TIMEOUT_MS 10000
1548 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1550 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1551 struct mwl8k_priv *priv = hw->priv;
1552 void __iomem *regs = priv->regs;
1553 dma_addr_t dma_addr;
1554 unsigned int dma_size;
1556 unsigned long timeout = 0;
1559 cmd->result = 0xffff;
1560 dma_size = le16_to_cpu(cmd->length);
1561 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1562 PCI_DMA_BIDIRECTIONAL);
1563 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1566 rc = mwl8k_fw_lock(hw);
1568 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1569 PCI_DMA_BIDIRECTIONAL);
1573 priv->hostcmd_wait = &cmd_wait;
1574 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1575 iowrite32(MWL8K_H2A_INT_DOORBELL,
1576 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1577 iowrite32(MWL8K_H2A_INT_DUMMY,
1578 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1580 timeout = wait_for_completion_timeout(&cmd_wait,
1581 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1583 priv->hostcmd_wait = NULL;
1585 mwl8k_fw_unlock(hw);
1587 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1588 PCI_DMA_BIDIRECTIONAL);
1591 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1592 wiphy_name(hw->wiphy),
1593 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1594 MWL8K_CMD_TIMEOUT_MS);
1599 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1601 rc = cmd->result ? -EINVAL : 0;
1603 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1604 wiphy_name(hw->wiphy),
1605 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1606 le16_to_cpu(cmd->result));
1608 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1609 wiphy_name(hw->wiphy),
1610 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1618 * CMD_GET_HW_SPEC (STA version).
1620 struct mwl8k_cmd_get_hw_spec_sta {
1621 struct mwl8k_cmd_pkt header;
1623 __u8 host_interface;
1625 __u8 perm_addr[ETH_ALEN];
1630 __u8 mcs_bitmap[16];
1631 __le32 rx_queue_ptr;
1632 __le32 num_tx_queues;
1633 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1635 __le32 num_tx_desc_per_queue;
1637 } __attribute__((packed));
1639 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1641 struct mwl8k_priv *priv = hw->priv;
1642 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1646 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1650 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1651 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1653 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1654 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1655 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1656 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1657 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1658 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1659 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1660 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1662 rc = mwl8k_post_cmd(hw, &cmd->header);
1665 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1666 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1667 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1668 priv->hw_rev = cmd->hw_rev;
1676 * CMD_GET_HW_SPEC (AP version).
1678 struct mwl8k_cmd_get_hw_spec_ap {
1679 struct mwl8k_cmd_pkt header;
1681 __u8 host_interface;
1684 __u8 perm_addr[ETH_ALEN];
1695 } __attribute__((packed));
1697 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1699 struct mwl8k_priv *priv = hw->priv;
1700 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1703 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1707 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1708 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1710 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1711 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1713 rc = mwl8k_post_cmd(hw, &cmd->header);
1718 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1719 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1720 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1721 priv->hw_rev = cmd->hw_rev;
1723 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1724 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1726 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1727 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1729 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1730 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1732 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1733 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1735 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1736 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1738 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1739 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1749 struct mwl8k_cmd_set_hw_spec {
1750 struct mwl8k_cmd_pkt header;
1752 __u8 host_interface;
1754 __u8 perm_addr[ETH_ALEN];
1759 __le32 rx_queue_ptr;
1760 __le32 num_tx_queues;
1761 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1763 __le32 num_tx_desc_per_queue;
1765 } __attribute__((packed));
1767 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1769 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1771 struct mwl8k_priv *priv = hw->priv;
1772 struct mwl8k_cmd_set_hw_spec *cmd;
1776 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1780 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1781 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1783 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1784 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1785 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1786 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1787 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1788 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1789 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1790 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1792 rc = mwl8k_post_cmd(hw, &cmd->header);
1799 * CMD_MAC_MULTICAST_ADR.
1801 struct mwl8k_cmd_mac_multicast_adr {
1802 struct mwl8k_cmd_pkt header;
1805 __u8 addr[0][ETH_ALEN];
1808 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1809 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1810 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1811 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1813 static struct mwl8k_cmd_pkt *
1814 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1815 int mc_count, struct dev_addr_list *mclist)
1817 struct mwl8k_priv *priv = hw->priv;
1818 struct mwl8k_cmd_mac_multicast_adr *cmd;
1821 if (allmulti || mc_count > priv->num_mcaddrs) {
1826 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1828 cmd = kzalloc(size, GFP_ATOMIC);
1832 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1833 cmd->header.length = cpu_to_le16(size);
1834 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1835 MWL8K_ENABLE_RX_BROADCAST);
1838 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1839 } else if (mc_count) {
1842 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1843 cmd->numaddr = cpu_to_le16(mc_count);
1844 for (i = 0; i < mc_count && mclist; i++) {
1845 if (mclist->da_addrlen != ETH_ALEN) {
1849 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1850 mclist = mclist->next;
1854 return &cmd->header;
1860 struct mwl8k_cmd_get_stat {
1861 struct mwl8k_cmd_pkt header;
1863 } __attribute__((packed));
1865 #define MWL8K_STAT_ACK_FAILURE 9
1866 #define MWL8K_STAT_RTS_FAILURE 12
1867 #define MWL8K_STAT_FCS_ERROR 24
1868 #define MWL8K_STAT_RTS_SUCCESS 11
1870 static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1871 struct ieee80211_low_level_stats *stats)
1873 struct mwl8k_cmd_get_stat *cmd;
1876 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1880 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1881 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1883 rc = mwl8k_post_cmd(hw, &cmd->header);
1885 stats->dot11ACKFailureCount =
1886 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1887 stats->dot11RTSFailureCount =
1888 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1889 stats->dot11FCSErrorCount =
1890 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1891 stats->dot11RTSSuccessCount =
1892 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1900 * CMD_RADIO_CONTROL.
1902 struct mwl8k_cmd_radio_control {
1903 struct mwl8k_cmd_pkt header;
1907 } __attribute__((packed));
1910 mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1912 struct mwl8k_priv *priv = hw->priv;
1913 struct mwl8k_cmd_radio_control *cmd;
1916 if (enable == priv->radio_on && !force)
1919 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1923 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1924 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1925 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1926 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1927 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1929 rc = mwl8k_post_cmd(hw, &cmd->header);
1933 priv->radio_on = enable;
1938 static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
1940 return mwl8k_cmd_radio_control(hw, 0, 0);
1943 static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
1945 return mwl8k_cmd_radio_control(hw, 1, 0);
1949 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1951 struct mwl8k_priv *priv = hw->priv;
1953 priv->radio_short_preamble = short_preamble;
1955 return mwl8k_cmd_radio_control(hw, 1, 1);
1961 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1963 struct mwl8k_cmd_rf_tx_power {
1964 struct mwl8k_cmd_pkt header;
1966 __le16 support_level;
1967 __le16 current_level;
1969 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1970 } __attribute__((packed));
1972 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1974 struct mwl8k_cmd_rf_tx_power *cmd;
1977 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1981 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1982 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1983 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1984 cmd->support_level = cpu_to_le16(dBm);
1986 rc = mwl8k_post_cmd(hw, &cmd->header);
1995 struct mwl8k_cmd_rf_antenna {
1996 struct mwl8k_cmd_pkt header;
1999 } __attribute__((packed));
2001 #define MWL8K_RF_ANTENNA_RX 1
2002 #define MWL8K_RF_ANTENNA_TX 2
2005 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2007 struct mwl8k_cmd_rf_antenna *cmd;
2010 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2014 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2015 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2016 cmd->antenna = cpu_to_le16(antenna);
2017 cmd->mode = cpu_to_le16(mask);
2019 rc = mwl8k_post_cmd(hw, &cmd->header);
2028 struct mwl8k_cmd_set_pre_scan {
2029 struct mwl8k_cmd_pkt header;
2030 } __attribute__((packed));
2032 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2034 struct mwl8k_cmd_set_pre_scan *cmd;
2037 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2041 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2042 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2044 rc = mwl8k_post_cmd(hw, &cmd->header);
2051 * CMD_SET_POST_SCAN.
2053 struct mwl8k_cmd_set_post_scan {
2054 struct mwl8k_cmd_pkt header;
2056 __u8 bssid[ETH_ALEN];
2057 } __attribute__((packed));
2060 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2062 struct mwl8k_cmd_set_post_scan *cmd;
2065 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2069 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2070 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2072 memcpy(cmd->bssid, mac, ETH_ALEN);
2074 rc = mwl8k_post_cmd(hw, &cmd->header);
2081 * CMD_SET_RF_CHANNEL.
2083 struct mwl8k_cmd_set_rf_channel {
2084 struct mwl8k_cmd_pkt header;
2086 __u8 current_channel;
2087 __le32 channel_flags;
2088 } __attribute__((packed));
2090 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2091 struct ieee80211_channel *channel)
2093 struct mwl8k_cmd_set_rf_channel *cmd;
2096 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2100 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2101 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2102 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2103 cmd->current_channel = channel->hw_value;
2104 if (channel->band == IEEE80211_BAND_2GHZ)
2105 cmd->channel_flags = cpu_to_le32(0x00000081);
2107 cmd->channel_flags = cpu_to_le32(0x00000000);
2109 rc = mwl8k_post_cmd(hw, &cmd->header);
2118 #define MWL8K_FRAME_PROT_DISABLED 0x00
2119 #define MWL8K_FRAME_PROT_11G 0x07
2120 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2121 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2123 struct mwl8k_cmd_update_set_aid {
2124 struct mwl8k_cmd_pkt header;
2127 /* AP's MAC address (BSSID) */
2128 __u8 bssid[ETH_ALEN];
2129 __le16 protection_mode;
2130 __u8 supp_rates[14];
2131 } __attribute__((packed));
2134 mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2136 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2137 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2138 struct mwl8k_cmd_update_set_aid *cmd;
2142 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2146 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2147 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2148 cmd->aid = cpu_to_le16(info->aid);
2150 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2152 if (info->use_cts_prot) {
2153 prot_mode = MWL8K_FRAME_PROT_11G;
2155 switch (info->ht_operation_mode &
2156 IEEE80211_HT_OP_MODE_PROTECTION) {
2157 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2158 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2160 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2161 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2164 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2168 cmd->protection_mode = cpu_to_le16(prot_mode);
2170 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2172 rc = mwl8k_post_cmd(hw, &cmd->header);
2181 struct mwl8k_cmd_set_rate {
2182 struct mwl8k_cmd_pkt header;
2183 __u8 legacy_rates[14];
2185 /* Bitmap for supported MCS codes. */
2188 } __attribute__((packed));
2191 mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2193 struct mwl8k_cmd_set_rate *cmd;
2196 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2200 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2201 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2202 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2204 rc = mwl8k_post_cmd(hw, &cmd->header);
2211 * CMD_FINALIZE_JOIN.
2213 #define MWL8K_FJ_BEACON_MAXLEN 128
2215 struct mwl8k_cmd_finalize_join {
2216 struct mwl8k_cmd_pkt header;
2217 __le32 sleep_interval; /* Number of beacon periods to sleep */
2218 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2219 } __attribute__((packed));
2221 static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2222 int framelen, int dtim)
2224 struct mwl8k_cmd_finalize_join *cmd;
2225 struct ieee80211_mgmt *payload = frame;
2229 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2233 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2234 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2235 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2237 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2238 if (payload_len < 0)
2240 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2241 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2243 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2245 rc = mwl8k_post_cmd(hw, &cmd->header);
2252 * CMD_SET_RTS_THRESHOLD.
2254 struct mwl8k_cmd_set_rts_threshold {
2255 struct mwl8k_cmd_pkt header;
2258 } __attribute__((packed));
2260 static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2261 u16 action, u16 threshold)
2263 struct mwl8k_cmd_set_rts_threshold *cmd;
2266 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2270 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2271 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2272 cmd->action = cpu_to_le16(action);
2273 cmd->threshold = cpu_to_le16(threshold);
2275 rc = mwl8k_post_cmd(hw, &cmd->header);
2284 struct mwl8k_cmd_set_slot {
2285 struct mwl8k_cmd_pkt header;
2288 } __attribute__((packed));
2290 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2292 struct mwl8k_cmd_set_slot *cmd;
2295 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2299 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2300 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2301 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2302 cmd->short_slot = short_slot_time;
2304 rc = mwl8k_post_cmd(hw, &cmd->header);
2311 * CMD_SET_EDCA_PARAMS.
2313 struct mwl8k_cmd_set_edca_params {
2314 struct mwl8k_cmd_pkt header;
2316 /* See MWL8K_SET_EDCA_XXX below */
2319 /* TX opportunity in units of 32 us */
2324 /* Log exponent of max contention period: 0...15 */
2327 /* Log exponent of min contention period: 0...15 */
2330 /* Adaptive interframe spacing in units of 32us */
2333 /* TX queue to configure */
2337 /* Log exponent of max contention period: 0...15 */
2340 /* Log exponent of min contention period: 0...15 */
2343 /* Adaptive interframe spacing in units of 32us */
2346 /* TX queue to configure */
2350 } __attribute__((packed));
2352 #define MWL8K_SET_EDCA_CW 0x01
2353 #define MWL8K_SET_EDCA_TXOP 0x02
2354 #define MWL8K_SET_EDCA_AIFS 0x04
2356 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2357 MWL8K_SET_EDCA_TXOP | \
2358 MWL8K_SET_EDCA_AIFS)
2361 mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2362 __u16 cw_min, __u16 cw_max,
2363 __u8 aifs, __u16 txop)
2365 struct mwl8k_priv *priv = hw->priv;
2366 struct mwl8k_cmd_set_edca_params *cmd;
2369 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2374 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2377 qnum ^= !(qnum >> 1);
2379 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2380 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2381 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2382 cmd->txop = cpu_to_le16(txop);
2384 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2385 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2386 cmd->ap.aifs = aifs;
2389 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2390 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2391 cmd->sta.aifs = aifs;
2392 cmd->sta.txq = qnum;
2395 rc = mwl8k_post_cmd(hw, &cmd->header);
2404 struct mwl8k_cmd_set_wmm_mode {
2405 struct mwl8k_cmd_pkt header;
2407 } __attribute__((packed));
2409 static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
2411 struct mwl8k_priv *priv = hw->priv;
2412 struct mwl8k_cmd_set_wmm_mode *cmd;
2415 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2419 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2420 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2421 cmd->action = cpu_to_le16(!!enable);
2423 rc = mwl8k_post_cmd(hw, &cmd->header);
2427 priv->wmm_enabled = enable;
2435 struct mwl8k_cmd_mimo_config {
2436 struct mwl8k_cmd_pkt header;
2438 __u8 rx_antenna_map;
2439 __u8 tx_antenna_map;
2440 } __attribute__((packed));
2442 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2444 struct mwl8k_cmd_mimo_config *cmd;
2447 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2451 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2452 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2453 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2454 cmd->rx_antenna_map = rx;
2455 cmd->tx_antenna_map = tx;
2457 rc = mwl8k_post_cmd(hw, &cmd->header);
2464 * CMD_USE_FIXED_RATE.
2466 #define MWL8K_RATE_TABLE_SIZE 8
2467 #define MWL8K_UCAST_RATE 0
2468 #define MWL8K_USE_AUTO_RATE 0x0002
2470 struct mwl8k_rate_entry {
2471 /* Set to 1 if HT rate, 0 if legacy. */
2474 /* Set to 1 to use retry_count field. */
2475 __le32 enable_retry;
2477 /* Specified legacy rate or MCS. */
2480 /* Number of allowed retries. */
2482 } __attribute__((packed));
2484 struct mwl8k_rate_table {
2485 /* 1 to allow specified rate and below */
2486 __le32 allow_rate_drop;
2488 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2489 } __attribute__((packed));
2491 struct mwl8k_cmd_use_fixed_rate {
2492 struct mwl8k_cmd_pkt header;
2494 struct mwl8k_rate_table rate_table;
2496 /* Unicast, Broadcast or Multicast */
2500 } __attribute__((packed));
2502 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2503 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2505 struct mwl8k_cmd_use_fixed_rate *cmd;
2509 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2513 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2514 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2516 cmd->action = cpu_to_le32(action);
2517 cmd->rate_type = cpu_to_le32(rate_type);
2519 if (rate_table != NULL) {
2521 * Copy over each field manually so that endian
2522 * conversion can be done.
2524 cmd->rate_table.allow_rate_drop =
2525 cpu_to_le32(rate_table->allow_rate_drop);
2526 cmd->rate_table.num_rates =
2527 cpu_to_le32(rate_table->num_rates);
2529 for (count = 0; count < rate_table->num_rates; count++) {
2530 struct mwl8k_rate_entry *dst =
2531 &cmd->rate_table.rate_entry[count];
2532 struct mwl8k_rate_entry *src =
2533 &rate_table->rate_entry[count];
2535 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2536 dst->enable_retry = cpu_to_le32(src->enable_retry);
2537 dst->rate = cpu_to_le32(src->rate);
2538 dst->retry_count = cpu_to_le32(src->retry_count);
2542 rc = mwl8k_post_cmd(hw, &cmd->header);
2549 * CMD_ENABLE_SNIFFER.
2551 struct mwl8k_cmd_enable_sniffer {
2552 struct mwl8k_cmd_pkt header;
2554 } __attribute__((packed));
2556 static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2558 struct mwl8k_cmd_enable_sniffer *cmd;
2561 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2565 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2566 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2567 cmd->action = cpu_to_le32(!!enable);
2569 rc = mwl8k_post_cmd(hw, &cmd->header);
2578 struct mwl8k_cmd_set_mac_addr {
2579 struct mwl8k_cmd_pkt header;
2583 __u8 mac_addr[ETH_ALEN];
2585 __u8 mac_addr[ETH_ALEN];
2587 } __attribute__((packed));
2589 static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2591 struct mwl8k_priv *priv = hw->priv;
2592 struct mwl8k_cmd_set_mac_addr *cmd;
2595 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2599 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2600 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2602 cmd->mbss.mac_type = 0;
2603 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2605 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2608 rc = mwl8k_post_cmd(hw, &cmd->header);
2615 * CMD_SET_RATEADAPT_MODE.
2617 struct mwl8k_cmd_set_rate_adapt_mode {
2618 struct mwl8k_cmd_pkt header;
2621 } __attribute__((packed));
2623 static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2625 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2628 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2632 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2633 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2634 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2635 cmd->mode = cpu_to_le16(mode);
2637 rc = mwl8k_post_cmd(hw, &cmd->header);
2646 struct mwl8k_cmd_update_stadb {
2647 struct mwl8k_cmd_pkt header;
2649 /* See STADB_ACTION_TYPE */
2652 /* Peer MAC address */
2653 __u8 peer_addr[ETH_ALEN];
2657 /* Peer info - valid during add/update. */
2658 struct peer_capability_info peer_info;
2659 } __attribute__((packed));
2661 static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw,
2662 struct ieee80211_vif *vif, __u32 action)
2664 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2665 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2666 struct mwl8k_cmd_update_stadb *cmd;
2667 struct peer_capability_info *peer_info;
2670 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2674 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2675 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2677 cmd->action = cpu_to_le32(action);
2678 peer_info = &cmd->peer_info;
2679 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2682 case MWL8K_STA_DB_ADD_ENTRY:
2683 case MWL8K_STA_DB_MODIFY_ENTRY:
2684 /* Build peer_info block */
2685 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2686 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2687 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2688 sizeof(mwl8k_rateids));
2689 peer_info->interop = 1;
2690 peer_info->amsdu_enabled = 0;
2692 rc = mwl8k_post_cmd(hw, &cmd->header);
2694 mv_vif->peer_id = peer_info->station_id;
2698 case MWL8K_STA_DB_DEL_ENTRY:
2699 case MWL8K_STA_DB_FLUSH:
2701 rc = mwl8k_post_cmd(hw, &cmd->header);
2703 mv_vif->peer_id = 0;
2713 * Interrupt handling.
2715 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2717 struct ieee80211_hw *hw = dev_id;
2718 struct mwl8k_priv *priv = hw->priv;
2721 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2722 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2727 if (status & MWL8K_A2H_INT_TX_DONE)
2728 tasklet_schedule(&priv->tx_reclaim_task);
2730 if (status & MWL8K_A2H_INT_RX_READY) {
2731 while (rxq_process(hw, 0, 1))
2732 rxq_refill(hw, 0, 1);
2735 if (status & MWL8K_A2H_INT_OPC_DONE) {
2736 if (priv->hostcmd_wait != NULL)
2737 complete(priv->hostcmd_wait);
2740 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2741 if (!mutex_is_locked(&priv->fw_mutex) &&
2742 priv->radio_on && priv->pending_tx_pkts)
2743 mwl8k_tx_start(priv);
2751 * Core driver operations.
2753 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2755 struct mwl8k_priv *priv = hw->priv;
2756 int index = skb_get_queue_mapping(skb);
2759 if (priv->current_channel == NULL) {
2760 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2761 "disabled\n", wiphy_name(hw->wiphy));
2763 return NETDEV_TX_OK;
2766 rc = mwl8k_txq_xmit(hw, index, skb);
2771 static int mwl8k_start(struct ieee80211_hw *hw)
2773 struct mwl8k_priv *priv = hw->priv;
2776 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2777 IRQF_SHARED, MWL8K_NAME, hw);
2779 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2780 wiphy_name(hw->wiphy));
2784 /* Enable tx reclaim tasklet */
2785 tasklet_enable(&priv->tx_reclaim_task);
2787 /* Enable interrupts */
2788 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2790 rc = mwl8k_fw_lock(hw);
2792 rc = mwl8k_cmd_radio_enable(hw);
2796 rc = mwl8k_cmd_enable_sniffer(hw, 0);
2799 rc = mwl8k_cmd_set_pre_scan(hw);
2802 rc = mwl8k_cmd_set_post_scan(hw,
2803 "\x00\x00\x00\x00\x00\x00");
2807 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
2810 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
2812 mwl8k_fw_unlock(hw);
2816 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2817 free_irq(priv->pdev->irq, hw);
2818 tasklet_disable(&priv->tx_reclaim_task);
2824 static void mwl8k_stop(struct ieee80211_hw *hw)
2826 struct mwl8k_priv *priv = hw->priv;
2829 mwl8k_cmd_radio_disable(hw);
2831 ieee80211_stop_queues(hw);
2833 /* Disable interrupts */
2834 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2835 free_irq(priv->pdev->irq, hw);
2837 /* Stop finalize join worker */
2838 cancel_work_sync(&priv->finalize_join_worker);
2839 if (priv->beacon_skb != NULL)
2840 dev_kfree_skb(priv->beacon_skb);
2842 /* Stop tx reclaim tasklet */
2843 tasklet_disable(&priv->tx_reclaim_task);
2845 /* Return all skbs to mac80211 */
2846 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2847 mwl8k_txq_reclaim(hw, i, 1);
2850 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2851 struct ieee80211_if_init_conf *conf)
2853 struct mwl8k_priv *priv = hw->priv;
2854 struct mwl8k_vif *mwl8k_vif;
2857 * We only support one active interface at a time.
2859 if (priv->vif != NULL)
2863 * We only support managed interfaces for now.
2865 if (conf->type != NL80211_IFTYPE_STATION)
2869 * Reject interface creation if sniffer mode is active, as
2870 * STA operation is mutually exclusive with hardware sniffer
2873 if (priv->sniffer_enabled) {
2874 printk(KERN_INFO "%s: unable to create STA "
2875 "interface due to sniffer mode being enabled\n",
2876 wiphy_name(hw->wiphy));
2880 /* Clean out driver private area */
2881 mwl8k_vif = MWL8K_VIF(conf->vif);
2882 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2884 /* Set and save the mac address */
2885 mwl8k_cmd_set_mac_addr(hw, conf->mac_addr);
2886 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2888 /* Back pointer to parent config block */
2889 mwl8k_vif->priv = priv;
2891 /* Set Initial sequence number to zero */
2892 mwl8k_vif->seqno = 0;
2894 priv->vif = conf->vif;
2895 priv->current_channel = NULL;
2900 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2901 struct ieee80211_if_init_conf *conf)
2903 struct mwl8k_priv *priv = hw->priv;
2905 if (priv->vif == NULL)
2908 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2913 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2915 struct ieee80211_conf *conf = &hw->conf;
2916 struct mwl8k_priv *priv = hw->priv;
2919 if (conf->flags & IEEE80211_CONF_IDLE) {
2920 mwl8k_cmd_radio_disable(hw);
2921 priv->current_channel = NULL;
2925 rc = mwl8k_fw_lock(hw);
2929 rc = mwl8k_cmd_radio_enable(hw);
2933 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2937 priv->current_channel = conf->channel;
2939 if (conf->power_level > 18)
2940 conf->power_level = 18;
2941 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
2946 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2948 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2950 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2954 mwl8k_fw_unlock(hw);
2959 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2960 struct ieee80211_vif *vif,
2961 struct ieee80211_bss_conf *info,
2964 struct mwl8k_priv *priv = hw->priv;
2965 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2968 if ((changed & BSS_CHANGED_ASSOC) == 0)
2971 priv->capture_beacon = false;
2973 rc = mwl8k_fw_lock(hw);
2978 memcpy(&mwl8k_vif->bss_info, info,
2979 sizeof(struct ieee80211_bss_conf));
2981 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2984 rc = mwl8k_cmd_set_rate(hw, vif);
2988 /* Turn on rate adaptation */
2989 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2990 MWL8K_UCAST_RATE, NULL);
2994 /* Set radio preamble */
2995 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3000 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3004 /* Update peer rate info */
3005 rc = mwl8k_cmd_update_stadb(hw, vif,
3006 MWL8K_STA_DB_MODIFY_ENTRY);
3011 rc = mwl8k_cmd_set_aid(hw, vif);
3016 * Finalize the join. Tell rx handler to process
3017 * next beacon from our BSSID.
3019 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3020 priv->capture_beacon = true;
3022 rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3023 memset(&mwl8k_vif->bss_info, 0,
3024 sizeof(struct ieee80211_bss_conf));
3025 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3029 mwl8k_fw_unlock(hw);
3032 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3033 int mc_count, struct dev_addr_list *mclist)
3035 struct mwl8k_cmd_pkt *cmd;
3038 * Synthesize and return a command packet that programs the
3039 * hardware multicast address filter. At this point we don't
3040 * know whether FIF_ALLMULTI is being requested, but if it is,
3041 * we'll end up throwing this packet away and creating a new
3042 * one in mwl8k_configure_filter().
3044 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3046 return (unsigned long)cmd;
3050 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3051 unsigned int changed_flags,
3052 unsigned int *total_flags)
3054 struct mwl8k_priv *priv = hw->priv;
3057 * Hardware sniffer mode is mutually exclusive with STA
3058 * operation, so refuse to enable sniffer mode if a STA
3059 * interface is active.
3061 if (priv->vif != NULL) {
3062 if (net_ratelimit())
3063 printk(KERN_INFO "%s: not enabling sniffer "
3064 "mode because STA interface is active\n",
3065 wiphy_name(hw->wiphy));
3069 if (!priv->sniffer_enabled) {
3070 if (mwl8k_cmd_enable_sniffer(hw, 1))
3072 priv->sniffer_enabled = true;
3075 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3076 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3082 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3083 unsigned int changed_flags,
3084 unsigned int *total_flags,
3087 struct mwl8k_priv *priv = hw->priv;
3088 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3091 * AP firmware doesn't allow fine-grained control over
3092 * the receive filter.
3095 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3101 * Enable hardware sniffer mode if FIF_CONTROL or
3102 * FIF_OTHER_BSS is requested.
3104 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3105 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3110 /* Clear unsupported feature flags */
3111 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3113 if (mwl8k_fw_lock(hw))
3116 if (priv->sniffer_enabled) {
3117 mwl8k_cmd_enable_sniffer(hw, 0);
3118 priv->sniffer_enabled = false;
3121 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3122 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3124 * Disable the BSS filter.
3126 mwl8k_cmd_set_pre_scan(hw);
3131 * Enable the BSS filter.
3133 * If there is an active STA interface, use that
3134 * interface's BSSID, otherwise use a dummy one
3135 * (where the OUI part needs to be nonzero for
3136 * the BSSID to be accepted by POST_SCAN).
3138 bssid = "\x01\x00\x00\x00\x00\x00";
3139 if (priv->vif != NULL)
3140 bssid = MWL8K_VIF(priv->vif)->bssid;
3142 mwl8k_cmd_set_post_scan(hw, bssid);
3147 * If FIF_ALLMULTI is being requested, throw away the command
3148 * packet that ->prepare_multicast() built and replace it with
3149 * a command packet that enables reception of all multicast
3152 if (*total_flags & FIF_ALLMULTI) {
3154 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3158 mwl8k_post_cmd(hw, cmd);
3162 mwl8k_fw_unlock(hw);
3165 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3167 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
3170 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3171 const struct ieee80211_tx_queue_params *params)
3173 struct mwl8k_priv *priv = hw->priv;
3176 rc = mwl8k_fw_lock(hw);
3178 if (!priv->wmm_enabled)
3179 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
3182 rc = mwl8k_cmd_set_edca_params(hw, queue,
3188 mwl8k_fw_unlock(hw);
3194 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3195 struct ieee80211_tx_queue_stats *stats)
3197 struct mwl8k_priv *priv = hw->priv;
3198 struct mwl8k_tx_queue *txq;
3201 spin_lock_bh(&priv->tx_lock);
3202 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3203 txq = priv->txq + index;
3204 memcpy(&stats[index], &txq->stats,
3205 sizeof(struct ieee80211_tx_queue_stats));
3207 spin_unlock_bh(&priv->tx_lock);
3212 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3213 struct ieee80211_low_level_stats *stats)
3215 return mwl8k_cmd_get_stat(hw, stats);
3218 static const struct ieee80211_ops mwl8k_ops = {
3220 .start = mwl8k_start,
3222 .add_interface = mwl8k_add_interface,
3223 .remove_interface = mwl8k_remove_interface,
3224 .config = mwl8k_config,
3225 .bss_info_changed = mwl8k_bss_info_changed,
3226 .prepare_multicast = mwl8k_prepare_multicast,
3227 .configure_filter = mwl8k_configure_filter,
3228 .set_rts_threshold = mwl8k_set_rts_threshold,
3229 .conf_tx = mwl8k_conf_tx,
3230 .get_tx_stats = mwl8k_get_tx_stats,
3231 .get_stats = mwl8k_get_stats,
3234 static void mwl8k_tx_reclaim_handler(unsigned long data)
3237 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3238 struct mwl8k_priv *priv = hw->priv;
3240 spin_lock_bh(&priv->tx_lock);
3241 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3242 mwl8k_txq_reclaim(hw, i, 0);
3244 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3245 complete(priv->tx_wait);
3246 priv->tx_wait = NULL;
3248 spin_unlock_bh(&priv->tx_lock);
3251 static void mwl8k_finalize_join_worker(struct work_struct *work)
3253 struct mwl8k_priv *priv =
3254 container_of(work, struct mwl8k_priv, finalize_join_worker);
3255 struct sk_buff *skb = priv->beacon_skb;
3256 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3258 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim);
3261 priv->beacon_skb = NULL;
3269 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3271 .part_name = "88w8687",
3272 .helper_image = "mwl8k/helper_8687.fw",
3273 .fw_image = "mwl8k/fmimage_8687.fw",
3274 .rxd_ops = &rxd_8687_ops,
3275 .modes = BIT(NL80211_IFTYPE_STATION),
3278 .part_name = "88w8366",
3279 .helper_image = "mwl8k/helper_8366.fw",
3280 .fw_image = "mwl8k/fmimage_8366.fw",
3281 .rxd_ops = &rxd_8366_ops,
3286 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3287 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3288 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3289 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3292 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3294 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3295 const struct pci_device_id *id)
3297 static int printed_version = 0;
3298 struct ieee80211_hw *hw;
3299 struct mwl8k_priv *priv;
3303 if (!printed_version) {
3304 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3305 printed_version = 1;
3308 rc = pci_enable_device(pdev);
3310 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3315 rc = pci_request_regions(pdev, MWL8K_NAME);
3317 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3319 goto err_disable_device;
3322 pci_set_master(pdev);
3324 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3326 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3334 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3335 priv->rxd_ops = priv->device_info->rxd_ops;
3336 priv->sniffer_enabled = false;
3337 priv->wmm_enabled = false;
3338 priv->pending_tx_pkts = 0;
3340 SET_IEEE80211_DEV(hw, &pdev->dev);
3341 pci_set_drvdata(pdev, hw);
3343 priv->sram = pci_iomap(pdev, 0, 0x10000);
3344 if (priv->sram == NULL) {
3345 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3346 wiphy_name(hw->wiphy));
3351 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3352 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3354 priv->regs = pci_iomap(pdev, 1, 0x10000);
3355 if (priv->regs == NULL) {
3356 priv->regs = pci_iomap(pdev, 2, 0x10000);
3357 if (priv->regs == NULL) {
3358 printk(KERN_ERR "%s: Cannot map device registers\n",
3359 wiphy_name(hw->wiphy));
3364 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3365 priv->band.band = IEEE80211_BAND_2GHZ;
3366 priv->band.channels = priv->channels;
3367 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3368 priv->band.bitrates = priv->rates;
3369 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3372 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3373 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3376 * Extra headroom is the size of the required DMA header
3377 * minus the size of the smallest 802.11 frame (CTS frame).
3379 hw->extra_tx_headroom =
3380 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3382 hw->channel_change_time = 10;
3384 hw->queues = MWL8K_TX_QUEUES;
3386 hw->wiphy->interface_modes = priv->device_info->modes;
3388 /* Set rssi and noise values to dBm */
3389 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3390 hw->vif_data_size = sizeof(struct mwl8k_vif);
3393 /* Set default radio state and preamble */
3395 priv->radio_short_preamble = 0;
3397 /* Finalize join worker */
3398 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3400 /* TX reclaim tasklet */
3401 tasklet_init(&priv->tx_reclaim_task,
3402 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3403 tasklet_disable(&priv->tx_reclaim_task);
3405 /* Power management cookie */
3406 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3407 if (priv->cookie == NULL)
3410 rc = mwl8k_rxq_init(hw, 0);
3413 rxq_refill(hw, 0, INT_MAX);
3415 mutex_init(&priv->fw_mutex);
3416 priv->fw_mutex_owner = NULL;
3417 priv->fw_mutex_depth = 0;
3418 priv->hostcmd_wait = NULL;
3420 spin_lock_init(&priv->tx_lock);
3422 priv->tx_wait = NULL;
3424 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3425 rc = mwl8k_txq_init(hw, i);
3427 goto err_free_queues;
3430 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3431 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3432 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3433 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3435 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3436 IRQF_SHARED, MWL8K_NAME, hw);
3438 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3439 wiphy_name(hw->wiphy));
3440 goto err_free_queues;
3443 /* Reset firmware and hardware */
3444 mwl8k_hw_reset(priv);
3446 /* Ask userland hotplug daemon for the device firmware */
3447 rc = mwl8k_request_firmware(priv);
3449 printk(KERN_ERR "%s: Firmware files not found\n",
3450 wiphy_name(hw->wiphy));
3454 /* Load firmware into hardware */
3455 rc = mwl8k_load_firmware(hw);
3457 printk(KERN_ERR "%s: Cannot start firmware\n",
3458 wiphy_name(hw->wiphy));
3459 goto err_stop_firmware;
3462 /* Reclaim memory once firmware is successfully loaded */
3463 mwl8k_release_firmware(priv);
3466 * Temporarily enable interrupts. Initial firmware host
3467 * commands use interrupts and avoids polling. Disable
3468 * interrupts when done.
3470 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3472 /* Get config data, mac addrs etc */
3474 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3476 rc = mwl8k_cmd_set_hw_spec(hw);
3478 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3481 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3482 wiphy_name(hw->wiphy));
3483 goto err_stop_firmware;
3486 /* Turn radio off */
3487 rc = mwl8k_cmd_radio_disable(hw);
3489 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3490 goto err_stop_firmware;
3493 /* Clear MAC address */
3494 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3496 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3497 wiphy_name(hw->wiphy));
3498 goto err_stop_firmware;
3501 /* Disable interrupts */
3502 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3503 free_irq(priv->pdev->irq, hw);
3505 rc = ieee80211_register_hw(hw);
3507 printk(KERN_ERR "%s: Cannot register device\n",
3508 wiphy_name(hw->wiphy));
3509 goto err_stop_firmware;
3512 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3513 wiphy_name(hw->wiphy), priv->device_info->part_name,
3514 priv->hw_rev, hw->wiphy->perm_addr,
3515 priv->ap_fw ? "AP" : "STA",
3516 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3517 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3522 mwl8k_hw_reset(priv);
3523 mwl8k_release_firmware(priv);
3526 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3527 free_irq(priv->pdev->irq, hw);
3530 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3531 mwl8k_txq_deinit(hw, i);
3532 mwl8k_rxq_deinit(hw, 0);
3535 if (priv->cookie != NULL)
3536 pci_free_consistent(priv->pdev, 4,
3537 priv->cookie, priv->cookie_dma);
3539 if (priv->regs != NULL)
3540 pci_iounmap(pdev, priv->regs);
3542 if (priv->sram != NULL)
3543 pci_iounmap(pdev, priv->sram);
3545 pci_set_drvdata(pdev, NULL);
3546 ieee80211_free_hw(hw);
3549 pci_release_regions(pdev);
3552 pci_disable_device(pdev);
3557 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3559 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3562 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3564 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3565 struct mwl8k_priv *priv;
3572 ieee80211_stop_queues(hw);
3574 ieee80211_unregister_hw(hw);
3576 /* Remove tx reclaim tasklet */
3577 tasklet_kill(&priv->tx_reclaim_task);
3580 mwl8k_hw_reset(priv);
3582 /* Return all skbs to mac80211 */
3583 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3584 mwl8k_txq_reclaim(hw, i, 1);
3586 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3587 mwl8k_txq_deinit(hw, i);
3589 mwl8k_rxq_deinit(hw, 0);
3591 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3593 pci_iounmap(pdev, priv->regs);
3594 pci_iounmap(pdev, priv->sram);
3595 pci_set_drvdata(pdev, NULL);
3596 ieee80211_free_hw(hw);
3597 pci_release_regions(pdev);
3598 pci_disable_device(pdev);
3601 static struct pci_driver mwl8k_driver = {
3603 .id_table = mwl8k_pci_id_table,
3604 .probe = mwl8k_probe,
3605 .remove = __devexit_p(mwl8k_remove),
3606 .shutdown = __devexit_p(mwl8k_shutdown),
3609 static int __init mwl8k_init(void)
3611 return pci_register_driver(&mwl8k_driver);
3614 static void __exit mwl8k_exit(void)
3616 pci_unregister_driver(&mwl8k_driver);
3619 module_init(mwl8k_init);
3620 module_exit(mwl8k_exit);
3622 MODULE_DESCRIPTION(MWL8K_DESC);
3623 MODULE_VERSION(MWL8K_VERSION);
3624 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3625 MODULE_LICENSE("GPL");