SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-eeprom.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *****************************************************************************/
  62
  63
  64 #include <linux/kernel.h>
  65 #include <linux/module.h>
  66 #include <linux/init.h>
  67
  68 #include <net/mac80211.h>
  69
  70 #include "iwl-commands.h"
  71 #include "iwl-dev.h"
  72 #include "iwl-core.h"
  73 #include "iwl-debug.h"
  74 #include "iwl-eeprom.h"
  75 #include "iwl-io.h"
  76
  77 /************************** EEPROM BANDS ****************************
  78  *
  79  * The iwl_eeprom_band definitions below provide the mapping from the
  80  * EEPROM contents to the specific channel number supported for each
  81  * band.
  82  *
  83  * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
  84  * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  85  * The specific geography and calibration information for that channel
  86  * is contained in the eeprom map itself.
  87  *
  88  * During init, we copy the eeprom information and channel map
  89  * information into priv->channel_info_24/52 and priv->channel_map_24/52
  90  *
  91  * channel_map_24/52 provides the index in the channel_info array for a
  92  * given channel.  We have to have two separate maps as there is channel
  93  * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  94  * band_2
  95  *
  96  * A value of 0xff stored in the channel_map indicates that the channel
  97  * is not supported by the hardware at all.
  98  *
  99  * A value of 0xfe in the channel_map indicates that the channel is not
 100  * valid for Tx with the current hardware.  This means that
 101  * while the system can tune and receive on a given channel, it may not
 102  * be able to associate or transmit any frames on that
 103  * channel.  There is no corresponding channel information for that
 104  * entry.
 105  *
 106  *********************************************************************/
 107
 108 /* 2.4 GHz */
 109 const u8 iwl_eeprom_band_1[14] = {
 110         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 111 };
 112
 113 /* 5.2 GHz bands */
 114 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
 115         183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
 116 };
 117
 118 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
 119         34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 120 };
 121
 122 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
 123         100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 124 };
 125
 126 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
 127         145, 149, 153, 157, 161, 165
 128 };
 129
 130 static const u8 iwl_eeprom_band_6[] = {       /* 2.4 ht40 channel */
 131         1, 2, 3, 4, 5, 6, 7
 132 };
 133
 134 static const u8 iwl_eeprom_band_7[] = {       /* 5.2 ht40 channel */
 135         36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
 136 };
 137
 138 /**
 139  * struct iwl_txpwr_section: eeprom section information
 140  * @offset: indirect address into eeprom image
 141  * @count: number of "struct iwl_eeprom_enhanced_txpwr" in this section
 142  * @band: band type for the section
 143  * @is_common - true: common section, false: channel section
 144  * @is_cck - true: cck section, false: not cck section
 145  * @is_ht_40 - true: all channel in the section are HT40 channel,
 146  *             false: legacy or HT 20 MHz
 147  *             ignore if it is common section
 148  * @iwl_eeprom_section_channel: channel array in the section,
 149  *             ignore if common section
 150  */
 151 struct iwl_txpwr_section {
 152         u32 offset;
 153         u8 count;
 154         enum ieee80211_band band;
 155         bool is_common;
 156         bool is_cck;
 157         bool is_ht40;
 158         u8 iwl_eeprom_section_channel[EEPROM_MAX_TXPOWER_SECTION_ELEMENTS];
 159 };
 160
 161 /**
 162  * section 1 - 3 are regulatory tx power apply to all channels based on
 163  *    modulation: CCK, OFDM
 164  *    Band: 2.4GHz, 5.2GHz
 165  * section 4 - 10 are regulatory tx power apply to specified channels
 166  *    For example:
 167  *      1L - Channel 1 Legacy
 168  *      1HT - Channel 1 HT
 169  *      (1,+1) - Channel 1 HT40 "_above_"
 170  *
 171  * Section 1: all CCK channels
 172  * Section 2: all 2.4 GHz OFDM (Legacy, HT and HT40) channels
 173  * Section 3: all 5.2 GHz OFDM (Legacy, HT and HT40) channels
 174  * Section 4: 2.4 GHz 20MHz channels: 1L, 1HT, 2L, 2HT, 10L, 10HT, 11L, 11HT
 175  * Section 5: 2.4 GHz 40MHz channels: (1,+1) (2,+1) (6,+1) (7,+1) (9,+1)
 176  * Section 6: 5.2 GHz 20MHz channels: 36L, 64L, 100L, 36HT, 64HT, 100HT
 177  * Section 7: 5.2 GHz 40MHz channels: (36,+1) (60,+1) (100,+1)
 178  * Section 8: 2.4 GHz channel: 13L, 13HT
 179  * Section 9: 2.4 GHz channel: 140L, 140HT
 180  * Section 10: 2.4 GHz 40MHz channels: (132,+1)  (44,+1)
 181  *
 182  */
 183 static const struct iwl_txpwr_section enhinfo[] = {
 184         { EEPROM_LB_CCK_20_COMMON, 1, IEEE80211_BAND_2GHZ, true, true, false },
 185         { EEPROM_LB_OFDM_COMMON, 3, IEEE80211_BAND_2GHZ, true, false, false },
 186         { EEPROM_HB_OFDM_COMMON, 3, IEEE80211_BAND_5GHZ, true, false, false },
 187         { EEPROM_LB_OFDM_20_BAND, 8, IEEE80211_BAND_2GHZ,
 188                 false, false, false,
 189                 {1, 1, 2, 2, 10, 10, 11, 11 } },
 190         { EEPROM_LB_OFDM_HT40_BAND, 5, IEEE80211_BAND_2GHZ,
 191                 false, false, true,
 192                 { 1, 2, 6, 7, 9 } },
 193         { EEPROM_HB_OFDM_20_BAND, 6, IEEE80211_BAND_5GHZ,
 194                 false, false, false,
 195                 { 36, 64, 100, 36, 64, 100 } },
 196         { EEPROM_HB_OFDM_HT40_BAND, 3, IEEE80211_BAND_5GHZ,
 197                 false, false, true,
 198                 { 36, 60, 100 } },
 199         { EEPROM_LB_OFDM_20_CHANNEL_13, 2, IEEE80211_BAND_2GHZ,
 200                 false, false, false,
 201                 { 13, 13 } },
 202         { EEPROM_HB_OFDM_20_CHANNEL_140, 2, IEEE80211_BAND_5GHZ,
 203                 false, false, false,
 204                 { 140, 140 } },
 205         { EEPROM_HB_OFDM_HT40_BAND_1, 2, IEEE80211_BAND_5GHZ,
 206                 false, false, true,
 207                 { 132, 44 } },
 208 };
 209
 210 /******************************************************************************
 211  *
 212  * EEPROM related functions
 213  *
 214 ******************************************************************************/
 215
 216 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
 217 {
 218         u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
 219         int ret = 0;
 220
 221         IWL_DEBUG_INFO(priv, "EEPROM signature=0x%08x\n", gp);
 222         switch (gp) {
 223         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
 224                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
 225                         IWL_ERR(priv, "EEPROM with bad signature: 0x%08x\n",
 226                                 gp);
 227                         ret = -ENOENT;
 228                 }
 229                 break;
 230         case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
 231         case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
 232                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
 233                         IWL_ERR(priv, "OTP with bad signature: 0x%08x\n", gp);
 234                         ret = -ENOENT;
 235                 }
 236                 break;
 237         case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
 238         default:
 239                 IWL_ERR(priv, "bad EEPROM/OTP signature, type=%s, "
 240                         "EEPROM_GP=0x%08x\n",
 241                         (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
 242                         ? "OTP" : "EEPROM", gp);
 243                 ret = -ENOENT;
 244                 break;
 245         }
 246         return ret;
 247 }
 248 EXPORT_SYMBOL(iwlcore_eeprom_verify_signature);
 249
 250 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
 251 {
 252         u32 otpgp;
 253
 254         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 255         if (mode == IWL_OTP_ACCESS_ABSOLUTE)
 256                 iwl_clear_bit(priv, CSR_OTP_GP_REG,
 257                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 258         else
 259                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 260                                 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
 261 }
 262
 263 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
 264 {
 265         u32 otpgp;
 266         int nvm_type;
 267
 268         /* OTP only valid for CP/PP and after */
 269         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 270         case CSR_HW_REV_TYPE_NONE:
 271                 IWL_ERR(priv, "Unknown hardware type\n");
 272                 return -ENOENT;
 273         case CSR_HW_REV_TYPE_3945:
 274         case CSR_HW_REV_TYPE_4965:
 275         case CSR_HW_REV_TYPE_5300:
 276         case CSR_HW_REV_TYPE_5350:
 277         case CSR_HW_REV_TYPE_5100:
 278         case CSR_HW_REV_TYPE_5150:
 279                 nvm_type = NVM_DEVICE_TYPE_EEPROM;
 280                 break;
 281         default:
 282                 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 283                 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
 284                         nvm_type = NVM_DEVICE_TYPE_OTP;
 285                 else
 286                         nvm_type = NVM_DEVICE_TYPE_EEPROM;
 287                 break;
 288         }
 289         return  nvm_type;
 290 }
 291
 292 /*
 293  * The device's EEPROM semaphore prevents conflicts between driver and uCode
 294  * when accessing the EEPROM; each access is a series of pulses to/from the
 295  * EEPROM chip, not a single event, so even reads could conflict if they
 296  * weren't arbitrated by the semaphore.
 297  */
 298 int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
 299 {
 300         u16 count;
 301         int ret;
 302
 303         for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
 304                 /* Request semaphore */
 305                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 306                             CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 307
 308                 /* See if we got it */
 309                 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
 310                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 311                                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
 312                                 EEPROM_SEM_TIMEOUT);
 313                 if (ret >= 0) {
 314                         IWL_DEBUG_IO(priv, "Acquired semaphore after %d tries.\n",
 315                                 count+1);
 316                         return ret;
 317                 }
 318         }
 319
 320         return ret;
 321 }
 322 EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore);
 323
 324 void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
 325 {
 326         iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
 327                 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
 328
 329 }
 330 EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
 331
 332 const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 333 {
 334         BUG_ON(offset >= priv->cfg->eeprom_size);
 335         return &priv->eeprom[offset];
 336 }
 337 EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
 338
 339 static int iwl_init_otp_access(struct iwl_priv *priv)
 340 {
 341         int ret;
 342
 343         /* Enable 40MHz radio clock */
 344         _iwl_write32(priv, CSR_GP_CNTRL,
 345                      _iwl_read32(priv, CSR_GP_CNTRL) |
 346                      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 347
 348         /* wait for clock to be ready */
 349         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
 350                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 351                                   CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 352                                   25000);
 353         if (ret < 0)
 354                 IWL_ERR(priv, "Time out access OTP\n");
 355         else {
 356                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
 357                                   APMG_PS_CTRL_VAL_RESET_REQ);
 358                 udelay(5);
 359                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
 360                                     APMG_PS_CTRL_VAL_RESET_REQ);
 361
 362                 /*
 363                  * CSR auto clock gate disable bit -
 364                  * this is only applicable for HW with OTP shadow RAM
 365                  */
 366                 if (priv->cfg->shadow_ram_support)
 367                         iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG,
 368                                 CSR_RESET_LINK_PWR_MGMT_DISABLED);
 369         }
 370         return ret;
 371 }
 372
 373 static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, u16 *eeprom_data)
 374 {
 375         int ret = 0;
 376         u32 r;
 377         u32 otpgp;
 378
 379         _iwl_write32(priv, CSR_EEPROM_REG,
 380                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 381         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 382                                   CSR_EEPROM_REG_READ_VALID_MSK,
 383                                   CSR_EEPROM_REG_READ_VALID_MSK,
 384                                   IWL_EEPROM_ACCESS_TIMEOUT);
 385         if (ret < 0) {
 386                 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
 387                 return ret;
 388         }
 389         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 390         /* check for ECC errors: */
 391         otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
 392         if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
 393                 /* stop in this case */
 394                 /* set the uncorrectable OTP ECC bit for acknowledgement */
 395                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 396                         CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 397                 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
 398                 return -EINVAL;
 399         }
 400         if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
 401                 /* continue in this case */
 402                 /* set the correctable OTP ECC bit for acknowledgement */
 403                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 404                                 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
 405                 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
 406         }
 407         *eeprom_data = le16_to_cpu((__force __le16)(r >> 16));
 408         return 0;
 409 }
 410
 411 /*
 412  * iwl_is_otp_empty: check for empty OTP
 413  */
 414 static bool iwl_is_otp_empty(struct iwl_priv *priv)
 415 {
 416         u16 next_link_addr = 0, link_value;
 417         bool is_empty = false;
 418
 419         /* locate the beginning of OTP link list */
 420         if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
 421                 if (!link_value) {
 422                         IWL_ERR(priv, "OTP is empty\n");
 423                         is_empty = true;
 424                 }
 425         } else {
 426                 IWL_ERR(priv, "Unable to read first block of OTP list.\n");
 427                 is_empty = true;
 428         }
 429
 430         return is_empty;
 431 }
 432
 433
 434 /*
 435  * iwl_find_otp_image: find EEPROM image in OTP
 436  *   finding the OTP block that contains the EEPROM image.
 437  *   the last valid block on the link list (the block _before_ the last block)
 438  *   is the block we should read and used to configure the device.
 439  *   If all the available OTP blocks are full, the last block will be the block
 440  *   we should read and used to configure the device.
 441  *   only perform this operation if shadow RAM is disabled
 442  */
 443 static int iwl_find_otp_image(struct iwl_priv *priv,
 444                                         u16 *validblockaddr)
 445 {
 446         u16 next_link_addr = 0, link_value = 0, valid_addr;
 447         int usedblocks = 0;
 448
 449         /* set addressing mode to absolute to traverse the link list */
 450         iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
 451
 452         /* checking for empty OTP or error */
 453         if (iwl_is_otp_empty(priv))
 454                 return -EINVAL;
 455
 456         /*
 457          * start traverse link list
 458          * until reach the max number of OTP blocks
 459          * different devices have different number of OTP blocks
 460          */
 461         do {
 462                 /* save current valid block address
 463                  * check for more block on the link list
 464                  */
 465                 valid_addr = next_link_addr;
 466                 next_link_addr = link_value * sizeof(u16);
 467                 IWL_DEBUG_INFO(priv, "OTP blocks %d addr 0x%x\n",
 468                                usedblocks, next_link_addr);
 469                 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
 470                         return -EINVAL;
 471                 if (!link_value) {
 472                         /*
 473                          * reach the end of link list, return success and
 474                          * set address point to the starting address
 475                          * of the image
 476                          */
 477                         *validblockaddr = valid_addr;
 478                         /* skip first 2 bytes (link list pointer) */
 479                         *validblockaddr += 2;
 480                         return 0;
 481                 }
 482                 /* more in the link list, continue */
 483                 usedblocks++;
 484         } while (usedblocks <= priv->cfg->max_ll_items);
 485
 486         /* OTP has no valid blocks */
 487         IWL_DEBUG_INFO(priv, "OTP has no valid blocks\n");
 488         return -EINVAL;
 489 }
 490
 491 /**
 492  * iwl_eeprom_init - read EEPROM contents
 493  *
 494  * Load the EEPROM contents from adapter into priv->eeprom
 495  *
 496  * NOTE:  This routine uses the non-debug IO access functions.
 497  */
 498 int iwl_eeprom_init(struct iwl_priv *priv)
 499 {
 500         u16 *e;
 501         u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
 502         int sz;
 503         int ret;
 504         u16 addr;
 505         u16 validblockaddr = 0;
 506         u16 cache_addr = 0;
 507
 508         priv->nvm_device_type = iwlcore_get_nvm_type(priv);
 509         if (priv->nvm_device_type == -ENOENT)
 510                 return -ENOENT;
 511         /* allocate eeprom */
 512         IWL_DEBUG_INFO(priv, "NVM size = %d\n", priv->cfg->eeprom_size);
 513         sz = priv->cfg->eeprom_size;
 514         priv->eeprom = kzalloc(sz, GFP_KERNEL);
 515         if (!priv->eeprom) {
 516                 ret = -ENOMEM;
 517                 goto alloc_err;
 518         }
 519         e = (u16 *)priv->eeprom;
 520
 521         ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv);
 522         if (ret < 0) {
 523                 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
 524                 ret = -ENOENT;
 525                 goto err;
 526         }
 527
 528         /* Make sure driver (instead of uCode) is allowed to read EEPROM */
 529         ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
 530         if (ret < 0) {
 531                 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
 532                 ret = -ENOENT;
 533                 goto err;
 534         }
 535         if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
 536
 537                 /* OTP reads require powered-up chip */
 538                 priv->cfg->ops->lib->apm_ops.init(priv);
 539
 540                 ret = iwl_init_otp_access(priv);
 541                 if (ret) {
 542                         IWL_ERR(priv, "Failed to initialize OTP access.\n");
 543                         ret = -ENOENT;
 544                         goto done;
 545                 }
 546                 _iwl_write32(priv, CSR_EEPROM_GP,
 547                              iwl_read32(priv, CSR_EEPROM_GP) &
 548                              ~CSR_EEPROM_GP_IF_OWNER_MSK);
 549
 550                 iwl_set_bit(priv, CSR_OTP_GP_REG,
 551                              CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
 552                              CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
 553                 /* traversing the linked list if no shadow ram supported */
 554                 if (!priv->cfg->shadow_ram_support) {
 555                         if (iwl_find_otp_image(priv, &validblockaddr)) {
 556                                 ret = -ENOENT;
 557                                 goto done;
 558                         }
 559                 }
 560                 for (addr = validblockaddr; addr < validblockaddr + sz;
 561                      addr += sizeof(u16)) {
 562                         u16 eeprom_data;
 563
 564                         ret = iwl_read_otp_word(priv, addr, &eeprom_data);
 565                         if (ret)
 566                                 goto done;
 567                         e[cache_addr / 2] = eeprom_data;
 568                         cache_addr += sizeof(u16);
 569                 }
 570
 571                 /*
 572                  * Now that OTP reads are complete, reset chip to save
 573                  *   power until we load uCode during "up".
 574                  */
 575                 priv->cfg->ops->lib->apm_ops.stop(priv);
 576
 577         } else {
 578                 /* eeprom is an array of 16bit values */
 579                 for (addr = 0; addr < sz; addr += sizeof(u16)) {
 580                         u32 r;
 581
 582                         _iwl_write32(priv, CSR_EEPROM_REG,
 583                                      CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
 584
 585                         ret = iwl_poll_bit(priv, CSR_EEPROM_REG,
 586                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 587                                                   CSR_EEPROM_REG_READ_VALID_MSK,
 588                                                   IWL_EEPROM_ACCESS_TIMEOUT);
 589                         if (ret < 0) {
 590                                 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
 591                                 goto done;
 592                         }
 593                         r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
 594                         e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
 595                 }
 596         }
 597         ret = 0;
 598 done:
 599         priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
 600 err:
 601         if (ret)
 602                 iwl_eeprom_free(priv);
 603 alloc_err:
 604         return ret;
 605 }
 606 EXPORT_SYMBOL(iwl_eeprom_init);
 607
 608 void iwl_eeprom_free(struct iwl_priv *priv)
 609 {
 610         kfree(priv->eeprom);
 611         priv->eeprom = NULL;
 612 }
 613 EXPORT_SYMBOL(iwl_eeprom_free);
 614
 615 int iwl_eeprom_check_version(struct iwl_priv *priv)
 616 {
 617         u16 eeprom_ver;
 618         u16 calib_ver;
 619
 620         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
 621         calib_ver = priv->cfg->ops->lib->eeprom_ops.calib_version(priv);
 622
 623         if (eeprom_ver < priv->cfg->eeprom_ver ||
 624             calib_ver < priv->cfg->eeprom_calib_ver)
 625                 goto err;
 626
 627         return 0;
 628 err:
 629         IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
 630                   eeprom_ver, priv->cfg->eeprom_ver,
 631                   calib_ver,  priv->cfg->eeprom_calib_ver);
 632         return -EINVAL;
 633
 634 }
 635 EXPORT_SYMBOL(iwl_eeprom_check_version);
 636
 637 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
 638 {
 639         return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
 640 }
 641 EXPORT_SYMBOL(iwl_eeprom_query_addr);
 642
 643 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
 644 {
 645         if (!priv->eeprom)
 646                 return 0;
 647         return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
 648 }
 649 EXPORT_SYMBOL(iwl_eeprom_query16);
 650
 651 void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
 652 {
 653         const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv,
 654                                         EEPROM_MAC_ADDRESS);
 655         memcpy(mac, addr, ETH_ALEN);
 656 }
 657 EXPORT_SYMBOL(iwl_eeprom_get_mac);
 658
 659 static void iwl_init_band_reference(const struct iwl_priv *priv,
 660                         int eep_band, int *eeprom_ch_count,
 661                         const struct iwl_eeprom_channel **eeprom_ch_info,
 662                         const u8 **eeprom_ch_index)
 663 {
 664         u32 offset = priv->cfg->ops->lib->
 665                         eeprom_ops.regulatory_bands[eep_band - 1];
 666         switch (eep_band) {
 667         case 1:         /* 2.4GHz band */
 668                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
 669                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 670                                 iwl_eeprom_query_addr(priv, offset);
 671                 *eeprom_ch_index = iwl_eeprom_band_1;
 672                 break;
 673         case 2:         /* 4.9GHz band */
 674                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
 675                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 676                                 iwl_eeprom_query_addr(priv, offset);
 677                 *eeprom_ch_index = iwl_eeprom_band_2;
 678                 break;
 679         case 3:         /* 5.2GHz band */
 680                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
 681                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 682                                 iwl_eeprom_query_addr(priv, offset);
 683                 *eeprom_ch_index = iwl_eeprom_band_3;
 684                 break;
 685         case 4:         /* 5.5GHz band */
 686                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
 687                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 688                                 iwl_eeprom_query_addr(priv, offset);
 689                 *eeprom_ch_index = iwl_eeprom_band_4;
 690                 break;
 691         case 5:         /* 5.7GHz band */
 692                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
 693                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 694                                 iwl_eeprom_query_addr(priv, offset);
 695                 *eeprom_ch_index = iwl_eeprom_band_5;
 696                 break;
 697         case 6:         /* 2.4GHz ht40 channels */
 698                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
 699                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 700                                 iwl_eeprom_query_addr(priv, offset);
 701                 *eeprom_ch_index = iwl_eeprom_band_6;
 702                 break;
 703         case 7:         /* 5 GHz ht40 channels */
 704                 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
 705                 *eeprom_ch_info = (struct iwl_eeprom_channel *)
 706                                 iwl_eeprom_query_addr(priv, offset);
 707                 *eeprom_ch_index = iwl_eeprom_band_7;
 708                 break;
 709         default:
 710                 BUG();
 711                 return;
 712         }
 713 }
 714
 715 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
 716                             ? # x " " : "")
 717
 718 /**
 719  * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
 720  *
 721  * Does not set up a command, or touch hardware.
 722  */
 723 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
 724                               enum ieee80211_band band, u16 channel,
 725                               const struct iwl_eeprom_channel *eeprom_ch,
 726                               u8 clear_ht40_extension_channel)
 727 {
 728         struct iwl_channel_info *ch_info;
 729
 730         ch_info = (struct iwl_channel_info *)
 731                         iwl_get_channel_info(priv, band, channel);
 732
 733         if (!is_channel_valid(ch_info))
 734                 return -1;
 735
 736         IWL_DEBUG_INFO(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
 737                         " Ad-Hoc %ssupported\n",
 738                         ch_info->channel,
 739                         is_channel_a_band(ch_info) ?
 740                         "5.2" : "2.4",
 741                         CHECK_AND_PRINT(IBSS),
 742                         CHECK_AND_PRINT(ACTIVE),
 743                         CHECK_AND_PRINT(RADAR),
 744                         CHECK_AND_PRINT(WIDE),
 745                         CHECK_AND_PRINT(DFS),
 746                         eeprom_ch->flags,
 747                         eeprom_ch->max_power_avg,
 748                         ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
 749                          && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
 750                         "" : "not ");
 751
 752         ch_info->ht40_eeprom = *eeprom_ch;
 753         ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
 754         ch_info->ht40_flags = eeprom_ch->flags;
 755         ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
 756
 757         return 0;
 758 }
 759
 760 /**
 761  * iwl_get_max_txpower_avg - get the highest tx power from all chains.
 762  *     find the highest tx power from all chains for the channel
 763  */
 764 static s8 iwl_get_max_txpower_avg(struct iwl_priv *priv,
 765                 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower, int element)
 766 {
 767         s8 max_txpower_avg = 0; /* (dBm) */
 768
 769         IWL_DEBUG_INFO(priv, "%d - "
 770                         "chain_a: %d dB chain_b: %d dB "
 771                         "chain_c: %d dB mimo2: %d dB mimo3: %d dB\n",
 772                         element,
 773                         enhanced_txpower[element].chain_a_max >> 1,
 774                         enhanced_txpower[element].chain_b_max >> 1,
 775                         enhanced_txpower[element].chain_c_max >> 1,
 776                         enhanced_txpower[element].mimo2_max >> 1,
 777                         enhanced_txpower[element].mimo3_max >> 1);
 778         /* Take the highest tx power from any valid chains */
 779         if ((priv->cfg->valid_tx_ant & ANT_A) &&
 780             (enhanced_txpower[element].chain_a_max > max_txpower_avg))
 781                 max_txpower_avg = enhanced_txpower[element].chain_a_max;
 782         if ((priv->cfg->valid_tx_ant & ANT_B) &&
 783             (enhanced_txpower[element].chain_b_max > max_txpower_avg))
 784                 max_txpower_avg = enhanced_txpower[element].chain_b_max;
 785         if ((priv->cfg->valid_tx_ant & ANT_C) &&
 786             (enhanced_txpower[element].chain_c_max > max_txpower_avg))
 787                 max_txpower_avg = enhanced_txpower[element].chain_c_max;
 788         if (((priv->cfg->valid_tx_ant == ANT_AB) |
 789             (priv->cfg->valid_tx_ant == ANT_BC) |
 790             (priv->cfg->valid_tx_ant == ANT_AC)) &&
 791             (enhanced_txpower[element].mimo2_max > max_txpower_avg))
 792                 max_txpower_avg =  enhanced_txpower[element].mimo2_max;
 793         if ((priv->cfg->valid_tx_ant == ANT_ABC) &&
 794             (enhanced_txpower[element].mimo3_max > max_txpower_avg))
 795                 max_txpower_avg = enhanced_txpower[element].mimo3_max;
 796
 797         /* max. tx power in EEPROM is in 1/2 dBm format
 798          * convert from 1/2 dBm to dBm
 799          */
 800         return max_txpower_avg >> 1;
 801 }
 802
 803 /**
 804  * iwl_update_common_txpower: update channel tx power
 805  *     update tx power per band based on EEPROM enhanced tx power info.
 806  */
 807 static s8 iwl_update_common_txpower(struct iwl_priv *priv,
 808                 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
 809                 int section, int element)
 810 {
 811         struct iwl_channel_info *ch_info;
 812         int ch;
 813         bool is_ht40 = false;
 814         s8 max_txpower_avg; /* (dBm) */
 815
 816         /* it is common section, contain all type (Legacy, HT and HT40)
 817          * based on the element in the section to determine
 818          * is it HT 40 or not
 819          */
 820         if (element == EEPROM_TXPOWER_COMMON_HT40_INDEX)
 821                 is_ht40 = true;
 822         max_txpower_avg =
 823                 iwl_get_max_txpower_avg(priv, enhanced_txpower, element);
 824         ch_info = priv->channel_info;
 825
 826         for (ch = 0; ch < priv->channel_count; ch++) {
 827                 /* find matching band and update tx power if needed */
 828                 if ((ch_info->band == enhinfo[section].band) &&
 829                     (ch_info->max_power_avg < max_txpower_avg) && (!is_ht40)) {
 830                         /* Update regulatory-based run-time data */
 831                         ch_info->max_power_avg = ch_info->curr_txpow =
 832                             max_txpower_avg;
 833                         ch_info->scan_power = max_txpower_avg;
 834                 }
 835                 if ((ch_info->band == enhinfo[section].band) && is_ht40 &&
 836                     ch_info->ht40_max_power_avg &&
 837                     (ch_info->ht40_max_power_avg < max_txpower_avg)) {
 838                         /* Update regulatory-based run-time data */
 839                         ch_info->ht40_max_power_avg = max_txpower_avg;
 840                 }
 841                 ch_info++;
 842         }
 843         return max_txpower_avg;
 844 }
 845
 846 /**
 847  * iwl_update_channel_txpower: update channel tx power
 848  *      update channel tx power based on EEPROM enhanced tx power info.
 849  */
 850 static s8 iwl_update_channel_txpower(struct iwl_priv *priv,
 851                 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
 852                 int section, int element)
 853 {
 854         struct iwl_channel_info *ch_info;
 855         int ch;
 856         u8 channel;
 857         s8 max_txpower_avg; /* (dBm) */
 858
 859         channel = enhinfo[section].iwl_eeprom_section_channel[element];
 860         max_txpower_avg =
 861                 iwl_get_max_txpower_avg(priv, enhanced_txpower, element);
 862
 863         ch_info = priv->channel_info;
 864         for (ch = 0; ch < priv->channel_count; ch++) {
 865                 /* find matching channel and update tx power if needed */
 866                 if (ch_info->channel == channel) {
 867                         if ((ch_info->max_power_avg < max_txpower_avg) &&
 868                             (!enhinfo[section].is_ht40)) {
 869                                 /* Update regulatory-based run-time data */
 870                                 ch_info->max_power_avg = max_txpower_avg;
 871                                 ch_info->curr_txpow = max_txpower_avg;
 872                                 ch_info->scan_power = max_txpower_avg;
 873                         }
 874                         if ((enhinfo[section].is_ht40) &&
 875                             (ch_info->ht40_max_power_avg) &&
 876                             (ch_info->ht40_max_power_avg < max_txpower_avg)) {
 877                                 /* Update regulatory-based run-time data */
 878                                 ch_info->ht40_max_power_avg = max_txpower_avg;
 879                         }
 880                         break;
 881                 }
 882                 ch_info++;
 883         }
 884         return max_txpower_avg;
 885 }
 886
 887 /**
 888  * iwlcore_eeprom_enhanced_txpower: process enhanced tx power info
 889  */
 890 void iwlcore_eeprom_enhanced_txpower(struct iwl_priv *priv)
 891 {
 892         int eeprom_section_count = 0;
 893         int section, element;
 894         struct iwl_eeprom_enhanced_txpwr *enhanced_txpower;
 895         u32 offset;
 896         s8 max_txpower_avg; /* (dBm) */
 897
 898         /* Loop through all the sections
 899          * adjust bands and channel's max tx power
 900          * Set the tx_power_user_lmt to the highest power
 901          * supported by any channels and chains
 902          */
 903         for (section = 0; section < ARRAY_SIZE(enhinfo); section++) {
 904                 eeprom_section_count = enhinfo[section].count;
 905                 offset = enhinfo[section].offset;
 906                 enhanced_txpower = (struct iwl_eeprom_enhanced_txpwr *)
 907                                 iwl_eeprom_query_addr(priv, offset);
 908
 909                 /*
 910                  * check for valid entry -
 911                  * different version of EEPROM might contain different set
 912                  * of enhanced tx power table
 913                  * always check for valid entry before process
 914                  * the information
 915                  */
 916                 if (!enhanced_txpower->common || enhanced_txpower->reserved)
 917                         continue;
 918
 919                 for (element = 0; element < eeprom_section_count; element++) {
 920                         if (enhinfo[section].is_common)
 921                                 max_txpower_avg =
 922                                         iwl_update_common_txpower(priv,
 923                                         enhanced_txpower, section, element);
 924                         else
 925                                 max_txpower_avg =
 926                                         iwl_update_channel_txpower(priv,
 927                                         enhanced_txpower, section, element);
 928
 929                         /* Update the tx_power_user_lmt to the highest power
 930                          * supported by any channel */
 931                         if (max_txpower_avg > priv->tx_power_user_lmt)
 932                                 priv->tx_power_user_lmt = max_txpower_avg;
 933                 }
 934         }
 935 }
 936 EXPORT_SYMBOL(iwlcore_eeprom_enhanced_txpower);
 937
 938 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
 939                             ? # x " " : "")
 940
 941 /**
 942  * iwl_init_channel_map - Set up driver's info for all possible channels
 943  */
 944 int iwl_init_channel_map(struct iwl_priv *priv)
 945 {
 946         int eeprom_ch_count = 0;
 947         const u8 *eeprom_ch_index = NULL;
 948         const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
 949         int band, ch;
 950         struct iwl_channel_info *ch_info;
 951
 952         if (priv->channel_count) {
 953                 IWL_DEBUG_INFO(priv, "Channel map already initialized.\n");
 954                 return 0;
 955         }
 956
 957         IWL_DEBUG_INFO(priv, "Initializing regulatory info from EEPROM\n");
 958
 959         priv->channel_count =
 960             ARRAY_SIZE(iwl_eeprom_band_1) +
 961             ARRAY_SIZE(iwl_eeprom_band_2) +
 962             ARRAY_SIZE(iwl_eeprom_band_3) +
 963             ARRAY_SIZE(iwl_eeprom_band_4) +
 964             ARRAY_SIZE(iwl_eeprom_band_5);
 965
 966         IWL_DEBUG_INFO(priv, "Parsing data for %d channels.\n", priv->channel_count);
 967
 968         priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
 969                                      priv->channel_count, GFP_KERNEL);
 970         if (!priv->channel_info) {
 971                 IWL_ERR(priv, "Could not allocate channel_info\n");
 972                 priv->channel_count = 0;
 973                 return -ENOMEM;
 974         }
 975
 976         ch_info = priv->channel_info;
 977
 978         /* Loop through the 5 EEPROM bands adding them in order to the
 979          * channel map we maintain (that contains additional information than
 980          * what just in the EEPROM) */
 981         for (band = 1; band <= 5; band++) {
 982
 983                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
 984                                         &eeprom_ch_info, &eeprom_ch_index);
 985
 986                 /* Loop through each band adding each of the channels */
 987                 for (ch = 0; ch < eeprom_ch_count; ch++) {
 988                         ch_info->channel = eeprom_ch_index[ch];
 989                         ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
 990                             IEEE80211_BAND_5GHZ;
 991
 992                         /* permanently store EEPROM's channel regulatory flags
 993                          *   and max power in channel info database. */
 994                         ch_info->eeprom = eeprom_ch_info[ch];
 995
 996                         /* Copy the run-time flags so they are there even on
 997                          * invalid channels */
 998                         ch_info->flags = eeprom_ch_info[ch].flags;
 999                         /* First write that ht40 is not enabled, and then enable
1000                          * one by one */
1001                         ch_info->ht40_extension_channel =
1002                                         IEEE80211_CHAN_NO_HT40;
1003
1004                         if (!(is_channel_valid(ch_info))) {
1005                                 IWL_DEBUG_INFO(priv, "Ch. %d Flags %x [%sGHz] - "
1006                                                "No traffic\n",
1007                                                ch_info->channel,
1008                                                ch_info->flags,
1009                                                is_channel_a_band(ch_info) ?
1010                                                "5.2" : "2.4");
1011                                 ch_info++;
1012                                 continue;
1013                         }
1014
1015                         /* Initialize regulatory-based run-time data */
1016                         ch_info->max_power_avg = ch_info->curr_txpow =
1017                             eeprom_ch_info[ch].max_power_avg;
1018                         ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
1019                         ch_info->min_power = 0;
1020
1021                         IWL_DEBUG_INFO(priv, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
1022                                        " Ad-Hoc %ssupported\n",
1023                                        ch_info->channel,
1024                                        is_channel_a_band(ch_info) ?
1025                                        "5.2" : "2.4",
1026                                        CHECK_AND_PRINT_I(VALID),
1027                                        CHECK_AND_PRINT_I(IBSS),
1028                                        CHECK_AND_PRINT_I(ACTIVE),
1029                                        CHECK_AND_PRINT_I(RADAR),
1030                                        CHECK_AND_PRINT_I(WIDE),
1031                                        CHECK_AND_PRINT_I(DFS),
1032                                        eeprom_ch_info[ch].flags,
1033                                        eeprom_ch_info[ch].max_power_avg,
1034                                        ((eeprom_ch_info[ch].
1035                                          flags & EEPROM_CHANNEL_IBSS)
1036                                         && !(eeprom_ch_info[ch].
1037                                              flags & EEPROM_CHANNEL_RADAR))
1038                                        ? "" : "not ");
1039
1040                         /* Set the tx_power_user_lmt to the highest power
1041                          * supported by any channel */
1042                         if (eeprom_ch_info[ch].max_power_avg >
1043                                                 priv->tx_power_user_lmt)
1044                                 priv->tx_power_user_lmt =
1045                                     eeprom_ch_info[ch].max_power_avg;
1046
1047                         ch_info++;
1048                 }
1049         }
1050
1051         /* Check if we do have HT40 channels */
1052         if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
1053             EEPROM_REGULATORY_BAND_NO_HT40 &&
1054             priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
1055             EEPROM_REGULATORY_BAND_NO_HT40)
1056                 return 0;
1057
1058         /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1059         for (band = 6; band <= 7; band++) {
1060                 enum ieee80211_band ieeeband;
1061
1062                 iwl_init_band_reference(priv, band, &eeprom_ch_count,
1063                                         &eeprom_ch_info, &eeprom_ch_index);
1064
1065                 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1066                 ieeeband =
1067                         (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1068
1069                 /* Loop through each band adding each of the channels */
1070                 for (ch = 0; ch < eeprom_ch_count; ch++) {
1071                         /* Set up driver's info for lower half */
1072                         iwl_mod_ht40_chan_info(priv, ieeeband,
1073                                                 eeprom_ch_index[ch],
1074                                                 &eeprom_ch_info[ch],
1075                                                 IEEE80211_CHAN_NO_HT40PLUS);
1076
1077                         /* Set up driver's info for upper half */
1078                         iwl_mod_ht40_chan_info(priv, ieeeband,
1079                                                 eeprom_ch_index[ch] + 4,
1080                                                 &eeprom_ch_info[ch],
1081                                                 IEEE80211_CHAN_NO_HT40MINUS);
1082                 }
1083         }
1084
1085         /* for newer device (6000 series and up)
1086          * EEPROM contain enhanced tx power information
1087          * driver need to process addition information
1088          * to determine the max channel tx power limits
1089          */
1090         if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower)
1091                 priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv);
1092
1093         return 0;
1094 }
1095 EXPORT_SYMBOL(iwl_init_channel_map);
1096
1097 /*
1098  * iwl_free_channel_map - undo allocations in iwl_init_channel_map
1099  */
1100 void iwl_free_channel_map(struct iwl_priv *priv)
1101 {
1102         kfree(priv->channel_info);
1103         priv->channel_count = 0;
1104 }
1105 EXPORT_SYMBOL(iwl_free_channel_map);
1106
1107 /**
1108  * iwl_get_channel_info - Find driver's private channel info
1109  *
1110  * Based on band and channel number.
1111  */
1112 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
1113                                         enum ieee80211_band band, u16 channel)
1114 {
1115         int i;
1116
1117         switch (band) {
1118         case IEEE80211_BAND_5GHZ:
1119                 for (i = 14; i < priv->channel_count; i++) {
1120                         if (priv->channel_info[i].channel == channel)
1121                                 return &priv->channel_info[i];
1122                 }
1123                 break;
1124         case IEEE80211_BAND_2GHZ:
1125                 if (channel >= 1 && channel <= 14)
1126                         return &priv->channel_info[channel - 1];
1127                 break;
1128         default:
1129                 BUG();
1130         }
1131
1132         return NULL;
1133 }
1134 EXPORT_SYMBOL(iwl_get_channel_info);
1135