SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46 #include "iwl-6000-hw.h"
  47
  48 /* Highest firmware API version supported */
  49 #define IWL5000_UCODE_API_MAX 1
  50 #define IWL5150_UCODE_API_MAX 1
  51
  52 /* Lowest firmware API version supported */
  53 #define IWL5000_UCODE_API_MIN 1
  54 #define IWL5150_UCODE_API_MIN 1
  55
  56 #define IWL5000_FW_PRE "iwlwifi-5000-"
  57 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  58 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  59
  60 #define IWL5150_FW_PRE "iwlwifi-5150-"
  61 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  62 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  63
  64 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  65         IWL_TX_FIFO_AC3,
  66         IWL_TX_FIFO_AC2,
  67         IWL_TX_FIFO_AC1,
  68         IWL_TX_FIFO_AC0,
  69         IWL50_CMD_FIFO_NUM,
  70         IWL_TX_FIFO_HCCA_1,
  71         IWL_TX_FIFO_HCCA_2
  72 };
  73
  74 /* FIXME: same implementation as 4965 */
  75 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  76 {
  77         unsigned long flags;
  78
  79         spin_lock_irqsave(&priv->lock, flags);
  80
  81         /* set stop master bit */
  82         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  83
  84         iwl_poll_direct_bit(priv, CSR_RESET,
  85                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  86
  87         spin_unlock_irqrestore(&priv->lock, flags);
  88         IWL_DEBUG_INFO(priv, "stop master\n");
  89
  90         return 0;
  91 }
  92
  93
  94 static int iwl5000_apm_init(struct iwl_priv *priv)
  95 {
  96         int ret = 0;
  97
  98         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  99                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 100
 101         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 102         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 103                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 104
 105         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 106         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 107
 108         /* enable HAP INTA to move device L1a -> L0s */
 109         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 110                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 111
 112         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 113
 114         /* set "initialization complete" bit to move adapter
 115          * D0U* --> D0A* state */
 116         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 117
 118         /* wait for clock stabilization */
 119         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 120                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 121         if (ret < 0) {
 122                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 123                 return ret;
 124         }
 125
 126         ret = iwl_grab_nic_access(priv);
 127         if (ret)
 128                 return ret;
 129
 130         /* enable DMA */
 131         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 132
 133         udelay(20);
 134
 135         /* disable L1-Active */
 136         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 137                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 138
 139         iwl_release_nic_access(priv);
 140
 141         return ret;
 142 }
 143
 144 /* FIXME: this is identical to 4965 */
 145 static void iwl5000_apm_stop(struct iwl_priv *priv)
 146 {
 147         unsigned long flags;
 148
 149         iwl5000_apm_stop_master(priv);
 150
 151         spin_lock_irqsave(&priv->lock, flags);
 152
 153         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 154
 155         udelay(10);
 156
 157         /* clear "init complete"  move adapter D0A* --> D0U state */
 158         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 159
 160         spin_unlock_irqrestore(&priv->lock, flags);
 161 }
 162
 163
 164 static int iwl5000_apm_reset(struct iwl_priv *priv)
 165 {
 166         int ret = 0;
 167         unsigned long flags;
 168
 169         iwl5000_apm_stop_master(priv);
 170
 171         spin_lock_irqsave(&priv->lock, flags);
 172
 173         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 174
 175         udelay(10);
 176
 177
 178         /* FIXME: put here L1A -L0S w/a */
 179
 180         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 181
 182         /* set "initialization complete" bit to move adapter
 183          * D0U* --> D0A* state */
 184         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 185
 186         /* wait for clock stabilization */
 187         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 188                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 189         if (ret < 0) {
 190                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 191                 goto out;
 192         }
 193
 194         ret = iwl_grab_nic_access(priv);
 195         if (ret)
 196                 goto out;
 197
 198         /* enable DMA */
 199         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 200
 201         udelay(20);
 202
 203         /* disable L1-Active */
 204         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 205                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 206
 207         iwl_release_nic_access(priv);
 208
 209 out:
 210         spin_unlock_irqrestore(&priv->lock, flags);
 211
 212         return ret;
 213 }
 214
 215
 216 static void iwl5000_nic_config(struct iwl_priv *priv)
 217 {
 218         unsigned long flags;
 219         u16 radio_cfg;
 220         u16 link;
 221
 222         spin_lock_irqsave(&priv->lock, flags);
 223
 224         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 225
 226         /* L1 is enabled by BIOS */
 227         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 228                 /* disable L0S disabled L1A enabled */
 229                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 230         else
 231                 /* L0S enabled L1A disabled */
 232                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 233
 234         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 235
 236         /* write radio config values to register */
 237         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 238                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 239                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 240                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 241                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 242
 243         /* set CSR_HW_CONFIG_REG for uCode use */
 244         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 245                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 246                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 247
 248         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 249          * (PCIe power is lost before PERST# is asserted),
 250          * causing ME FW to lose ownership and not being able to obtain it back.
 251          */
 252         iwl_grab_nic_access(priv);
 253         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 254                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 255                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 256         iwl_release_nic_access(priv);
 257
 258         spin_unlock_irqrestore(&priv->lock, flags);
 259 }
 260
 261
 262
 263 /*
 264  * EEPROM
 265  */
 266 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 267 {
 268         u16 offset = 0;
 269
 270         if ((address & INDIRECT_ADDRESS) == 0)
 271                 return address;
 272
 273         switch (address & INDIRECT_TYPE_MSK) {
 274         case INDIRECT_HOST:
 275                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 276                 break;
 277         case INDIRECT_GENERAL:
 278                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 279                 break;
 280         case INDIRECT_REGULATORY:
 281                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 282                 break;
 283         case INDIRECT_CALIBRATION:
 284                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 285                 break;
 286         case INDIRECT_PROCESS_ADJST:
 287                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 288                 break;
 289         case INDIRECT_OTHERS:
 290                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 291                 break;
 292         default:
 293                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 294                 address & INDIRECT_TYPE_MSK);
 295                 break;
 296         }
 297
 298         /* translate the offset from words to byte */
 299         return (address & ADDRESS_MSK) + (offset << 1);
 300 }
 301
 302 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 303 {
 304         struct iwl_eeprom_calib_hdr {
 305                 u8 version;
 306                 u8 pa_type;
 307                 u16 voltage;
 308         } *hdr;
 309
 310         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 311                                                         EEPROM_5000_CALIB_ALL);
 312         return hdr->version;
 313
 314 }
 315
 316 static void iwl5000_gain_computation(struct iwl_priv *priv,
 317                 u32 average_noise[NUM_RX_CHAINS],
 318                 u16 min_average_noise_antenna_i,
 319                 u32 min_average_noise)
 320 {
 321         int i;
 322         s32 delta_g;
 323         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 324
 325         /* Find Gain Code for the antennas B and C */
 326         for (i = 1; i < NUM_RX_CHAINS; i++) {
 327                 if ((data->disconn_array[i])) {
 328                         data->delta_gain_code[i] = 0;
 329                         continue;
 330                 }
 331                 delta_g = (1000 * ((s32)average_noise[0] -
 332                         (s32)average_noise[i])) / 1500;
 333                 /* bound gain by 2 bits value max, 3rd bit is sign */
 334                 data->delta_gain_code[i] =
 335                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 336
 337                 if (delta_g < 0)
 338                         /* set negative sign */
 339                         data->delta_gain_code[i] |= (1 << 2);
 340         }
 341
 342         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 343                         data->delta_gain_code[1], data->delta_gain_code[2]);
 344
 345         if (!data->radio_write) {
 346                 struct iwl_calib_chain_noise_gain_cmd cmd;
 347
 348                 memset(&cmd, 0, sizeof(cmd));
 349
 350                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 351                 cmd.hdr.first_group = 0;
 352                 cmd.hdr.groups_num = 1;
 353                 cmd.hdr.data_valid = 1;
 354                 cmd.delta_gain_1 = data->delta_gain_code[1];
 355                 cmd.delta_gain_2 = data->delta_gain_code[2];
 356                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 357                         sizeof(cmd), &cmd, NULL);
 358
 359                 data->radio_write = 1;
 360                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 361         }
 362
 363         data->chain_noise_a = 0;
 364         data->chain_noise_b = 0;
 365         data->chain_noise_c = 0;
 366         data->chain_signal_a = 0;
 367         data->chain_signal_b = 0;
 368         data->chain_signal_c = 0;
 369         data->beacon_count = 0;
 370 }
 371
 372 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 373 {
 374         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 375         int ret;
 376
 377         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 378                 struct iwl_calib_chain_noise_reset_cmd cmd;
 379                 memset(&cmd, 0, sizeof(cmd));
 380
 381                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 382                 cmd.hdr.first_group = 0;
 383                 cmd.hdr.groups_num = 1;
 384                 cmd.hdr.data_valid = 1;
 385                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 386                                         sizeof(cmd), &cmd);
 387                 if (ret)
 388                         IWL_ERR(priv,
 389                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 390                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 391                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 392         }
 393 }
 394
 395 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 396                         __le32 *tx_flags)
 397 {
 398         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 399             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 400                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 401         else
 402                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 403 }
 404
 405 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 406         .min_nrg_cck = 95,
 407         .max_nrg_cck = 0,
 408         .auto_corr_min_ofdm = 90,
 409         .auto_corr_min_ofdm_mrc = 170,
 410         .auto_corr_min_ofdm_x1 = 120,
 411         .auto_corr_min_ofdm_mrc_x1 = 240,
 412
 413         .auto_corr_max_ofdm = 120,
 414         .auto_corr_max_ofdm_mrc = 210,
 415         .auto_corr_max_ofdm_x1 = 155,
 416         .auto_corr_max_ofdm_mrc_x1 = 290,
 417
 418         .auto_corr_min_cck = 125,
 419         .auto_corr_max_cck = 200,
 420         .auto_corr_min_cck_mrc = 170,
 421         .auto_corr_max_cck_mrc = 400,
 422         .nrg_th_cck = 95,
 423         .nrg_th_ofdm = 95,
 424 };
 425
 426 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 427                                            size_t offset)
 428 {
 429         u32 address = eeprom_indirect_address(priv, offset);
 430         BUG_ON(address >= priv->cfg->eeprom_size);
 431         return &priv->eeprom[address];
 432 }
 433
 434 static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv)
 435 {
 436         const s32 volt2temp_coef = -5;
 437         u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv,
 438                                                 EEPROM_5000_TEMPERATURE);
 439         /* offset =  temperate -  voltage / coef */
 440         s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef;
 441         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset;
 442         return threshold * volt2temp_coef;
 443 }
 444
 445 /*
 446  *  Calibration
 447  */
 448 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 449 {
 450         struct iwl_calib_xtal_freq_cmd cmd;
 451         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 452
 453         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 454         cmd.hdr.first_group = 0;
 455         cmd.hdr.groups_num = 1;
 456         cmd.hdr.data_valid = 1;
 457         cmd.cap_pin1 = (u8)xtal_calib[0];
 458         cmd.cap_pin2 = (u8)xtal_calib[1];
 459         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 460                              (u8 *)&cmd, sizeof(cmd));
 461 }
 462
 463 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 464 {
 465         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 466         struct iwl_host_cmd cmd = {
 467                 .id = CALIBRATION_CFG_CMD,
 468                 .len = sizeof(struct iwl_calib_cfg_cmd),
 469                 .data = &calib_cfg_cmd,
 470         };
 471
 472         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 473         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 474         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 475         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 476         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 477
 478         return iwl_send_cmd(priv, &cmd);
 479 }
 480
 481 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 482                              struct iwl_rx_mem_buffer *rxb)
 483 {
 484         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 485         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 486         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 487         int index;
 488
 489         /* reduce the size of the length field itself */
 490         len -= 4;
 491
 492         /* Define the order in which the results will be sent to the runtime
 493          * uCode. iwl_send_calib_results sends them in a row according to their
 494          * index. We sort them here */
 495         switch (hdr->op_code) {
 496         case IWL_PHY_CALIBRATE_DC_CMD:
 497                 index = IWL_CALIB_DC;
 498                 break;
 499         case IWL_PHY_CALIBRATE_LO_CMD:
 500                 index = IWL_CALIB_LO;
 501                 break;
 502         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 503                 index = IWL_CALIB_TX_IQ;
 504                 break;
 505         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 506                 index = IWL_CALIB_TX_IQ_PERD;
 507                 break;
 508         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 509                 index = IWL_CALIB_BASE_BAND;
 510                 break;
 511         default:
 512                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 513                           hdr->op_code);
 514                 return;
 515         }
 516         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 517 }
 518
 519 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 520                                struct iwl_rx_mem_buffer *rxb)
 521 {
 522         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 523         queue_work(priv->workqueue, &priv->restart);
 524 }
 525
 526 /*
 527  * ucode
 528  */
 529 static int iwl5000_load_section(struct iwl_priv *priv,
 530                                 struct fw_desc *image,
 531                                 u32 dst_addr)
 532 {
 533         int ret = 0;
 534         unsigned long flags;
 535
 536         dma_addr_t phy_addr = image->p_addr;
 537         u32 byte_cnt = image->len;
 538
 539         spin_lock_irqsave(&priv->lock, flags);
 540         ret = iwl_grab_nic_access(priv);
 541         if (ret) {
 542                 spin_unlock_irqrestore(&priv->lock, flags);
 543                 return ret;
 544         }
 545
 546         iwl_write_direct32(priv,
 547                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 548                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 549
 550         iwl_write_direct32(priv,
 551                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 552
 553         iwl_write_direct32(priv,
 554                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 555                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 556
 557         iwl_write_direct32(priv,
 558                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 559                 (iwl_get_dma_hi_addr(phy_addr)
 560                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 561
 562         iwl_write_direct32(priv,
 563                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 564                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 565                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 566                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 567
 568         iwl_write_direct32(priv,
 569                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 570                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 571                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 572                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 573
 574         iwl_release_nic_access(priv);
 575         spin_unlock_irqrestore(&priv->lock, flags);
 576         return 0;
 577 }
 578
 579 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 580                 struct fw_desc *inst_image,
 581                 struct fw_desc *data_image)
 582 {
 583         int ret = 0;
 584
 585         ret = iwl5000_load_section(priv, inst_image,
 586                                    IWL50_RTC_INST_LOWER_BOUND);
 587         if (ret)
 588                 return ret;
 589
 590         IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
 591         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 592                                         priv->ucode_write_complete, 5 * HZ);
 593         if (ret == -ERESTARTSYS) {
 594                 IWL_ERR(priv, "Could not load the INST uCode section due "
 595                         "to interrupt\n");
 596                 return ret;
 597         }
 598         if (!ret) {
 599                 IWL_ERR(priv, "Could not load the INST uCode section\n");
 600                 return -ETIMEDOUT;
 601         }
 602
 603         priv->ucode_write_complete = 0;
 604
 605         ret = iwl5000_load_section(
 606                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 607         if (ret)
 608                 return ret;
 609
 610         IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
 611
 612         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 613                                 priv->ucode_write_complete, 5 * HZ);
 614         if (ret == -ERESTARTSYS) {
 615                 IWL_ERR(priv, "Could not load the INST uCode section due "
 616                         "to interrupt\n");
 617                 return ret;
 618         } else if (!ret) {
 619                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
 620                 return -ETIMEDOUT;
 621         } else
 622                 ret = 0;
 623
 624         priv->ucode_write_complete = 0;
 625
 626         return ret;
 627 }
 628
 629 static int iwl5000_load_ucode(struct iwl_priv *priv)
 630 {
 631         int ret = 0;
 632
 633         /* check whether init ucode should be loaded, or rather runtime ucode */
 634         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 635                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 636                 ret = iwl5000_load_given_ucode(priv,
 637                         &priv->ucode_init, &priv->ucode_init_data);
 638                 if (!ret) {
 639                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 640                         priv->ucode_type = UCODE_INIT;
 641                 }
 642         } else {
 643                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 644                         "Loading runtime ucode...\n");
 645                 ret = iwl5000_load_given_ucode(priv,
 646                         &priv->ucode_code, &priv->ucode_data);
 647                 if (!ret) {
 648                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 649                         priv->ucode_type = UCODE_RT;
 650                 }
 651         }
 652
 653         return ret;
 654 }
 655
 656 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 657 {
 658         int ret = 0;
 659
 660         /* Check alive response for "valid" sign from uCode */
 661         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 662                 /* We had an error bringing up the hardware, so take it
 663                  * all the way back down so we can try again */
 664                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 665                 goto restart;
 666         }
 667
 668         /* initialize uCode was loaded... verify inst image.
 669          * This is a paranoid check, because we would not have gotten the
 670          * "initialize" alive if code weren't properly loaded.  */
 671         if (iwl_verify_ucode(priv)) {
 672                 /* Runtime instruction load was bad;
 673                  * take it all the way back down so we can try again */
 674                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 675                 goto restart;
 676         }
 677
 678         iwl_clear_stations_table(priv);
 679         ret = priv->cfg->ops->lib->alive_notify(priv);
 680         if (ret) {
 681                 IWL_WARN(priv,
 682                         "Could not complete ALIVE transition: %d\n", ret);
 683                 goto restart;
 684         }
 685
 686         iwl5000_send_calib_cfg(priv);
 687         return;
 688
 689 restart:
 690         /* real restart (first load init_ucode) */
 691         queue_work(priv->workqueue, &priv->restart);
 692 }
 693
 694 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 695                                 int txq_id, u32 index)
 696 {
 697         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 698                         (index & 0xff) | (txq_id << 8));
 699         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 700 }
 701
 702 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 703                                         struct iwl_tx_queue *txq,
 704                                         int tx_fifo_id, int scd_retry)
 705 {
 706         int txq_id = txq->q.id;
 707         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 708
 709         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 710                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 711                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 712                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 713                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 714
 715         txq->sched_retry = scd_retry;
 716
 717         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 718                        active ? "Activate" : "Deactivate",
 719                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 720 }
 721
 722 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 723 {
 724         struct iwl_wimax_coex_cmd coex_cmd;
 725
 726         memset(&coex_cmd, 0, sizeof(coex_cmd));
 727
 728         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 729                                 sizeof(coex_cmd), &coex_cmd);
 730 }
 731
 732 static int iwl5000_alive_notify(struct iwl_priv *priv)
 733 {
 734         u32 a;
 735         unsigned long flags;
 736         int ret;
 737         int i, chan;
 738         u32 reg_val;
 739
 740         spin_lock_irqsave(&priv->lock, flags);
 741
 742         ret = iwl_grab_nic_access(priv);
 743         if (ret) {
 744                 spin_unlock_irqrestore(&priv->lock, flags);
 745                 return ret;
 746         }
 747
 748         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 749         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 750         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 751                 a += 4)
 752                 iwl_write_targ_mem(priv, a, 0);
 753         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 754                 a += 4)
 755                 iwl_write_targ_mem(priv, a, 0);
 756         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 757                 iwl_write_targ_mem(priv, a, 0);
 758
 759         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 760                        priv->scd_bc_tbls.dma >> 10);
 761
 762         /* Enable DMA channel */
 763         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 764                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 765                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 766                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 767
 768         /* Update FH chicken bits */
 769         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 770         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 771                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 772
 773         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 774                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 775         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 776
 777         /* initiate the queues */
 778         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 779                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 780                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 781                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 782                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 783                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 784                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 785                                 sizeof(u32),
 786                                 ((SCD_WIN_SIZE <<
 787                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 788                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 789                                 ((SCD_FRAME_LIMIT <<
 790                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 791                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 792         }
 793
 794         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 795                         IWL_MASK(0, priv->hw_params.max_txq_num));
 796
 797         /* Activate all Tx DMA/FIFO channels */
 798         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 799
 800         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 801
 802         /* map qos queues to fifos one-to-one */
 803         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 804                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 805                 iwl_txq_ctx_activate(priv, i);
 806                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 807         }
 808         /* TODO - need to initialize those FIFOs inside the loop above,
 809          * not only mark them as active */
 810         iwl_txq_ctx_activate(priv, 4);
 811         iwl_txq_ctx_activate(priv, 7);
 812         iwl_txq_ctx_activate(priv, 8);
 813         iwl_txq_ctx_activate(priv, 9);
 814
 815         iwl_release_nic_access(priv);
 816         spin_unlock_irqrestore(&priv->lock, flags);
 817
 818
 819         iwl5000_send_wimax_coex(priv);
 820
 821         iwl5000_set_Xtal_calib(priv);
 822         iwl_send_calib_results(priv);
 823
 824         return 0;
 825 }
 826
 827 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 828 {
 829         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 830             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 831                 IWL_ERR(priv,
 832                         "invalid queues_num, should be between %d and %d\n",
 833                         IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 834                 return -EINVAL;
 835         }
 836
 837         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 838         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 839         priv->hw_params.scd_bc_tbls_size =
 840                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 841         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 842         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 843         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 844
 845         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 846         case CSR_HW_REV_TYPE_6x00:
 847         case CSR_HW_REV_TYPE_6x50:
 848                 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
 849                 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
 850                 break;
 851         default:
 852                 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 853                 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 854         }
 855
 856         priv->hw_params.max_bsm_size = 0;
 857         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 858                                         BIT(IEEE80211_BAND_5GHZ);
 859         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 860
 861         priv->hw_params.sens = &iwl5000_sensitivity;
 862
 863         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 864         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 865         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 866         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 867
 868         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 869         case CSR_HW_REV_TYPE_5150:
 870                 /* 5150 wants in Kelvin */
 871                 priv->hw_params.ct_kill_threshold =
 872                                 iwl5150_get_ct_threshold(priv);
 873                 break;
 874         default:
 875                 /* all others want Celsius */
 876                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 877                 break;
 878         }
 879
 880         /* Set initial calibration set */
 881         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 882         case CSR_HW_REV_TYPE_5150:
 883                 priv->hw_params.calib_init_cfg =
 884                         BIT(IWL_CALIB_DC)               |
 885                         BIT(IWL_CALIB_LO)               |
 886                         BIT(IWL_CALIB_TX_IQ)            |
 887                         BIT(IWL_CALIB_BASE_BAND);
 888
 889                 break;
 890         default:
 891                 priv->hw_params.calib_init_cfg =
 892                         BIT(IWL_CALIB_XTAL)             |
 893                         BIT(IWL_CALIB_LO)               |
 894                         BIT(IWL_CALIB_TX_IQ)            |
 895                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 896                         BIT(IWL_CALIB_BASE_BAND);
 897                 break;
 898         }
 899
 900
 901         return 0;
 902 }
 903
 904 /**
 905  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 906  */
 907 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 908                                             struct iwl_tx_queue *txq,
 909                                             u16 byte_cnt)
 910 {
 911         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 912         int write_ptr = txq->q.write_ptr;
 913         int txq_id = txq->q.id;
 914         u8 sec_ctl = 0;
 915         u8 sta_id = 0;
 916         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 917         __le16 bc_ent;
 918
 919         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 920
 921         if (txq_id != IWL_CMD_QUEUE_NUM) {
 922                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 923                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 924
 925                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 926                 case TX_CMD_SEC_CCM:
 927                         len += CCMP_MIC_LEN;
 928                         break;
 929                 case TX_CMD_SEC_TKIP:
 930                         len += TKIP_ICV_LEN;
 931                         break;
 932                 case TX_CMD_SEC_WEP:
 933                         len += WEP_IV_LEN + WEP_ICV_LEN;
 934                         break;
 935                 }
 936         }
 937
 938         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 939
 940         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 941
 942         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 943                 scd_bc_tbl[txq_id].
 944                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 945 }
 946
 947 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 948                                            struct iwl_tx_queue *txq)
 949 {
 950         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 951         int txq_id = txq->q.id;
 952         int read_ptr = txq->q.read_ptr;
 953         u8 sta_id = 0;
 954         __le16 bc_ent;
 955
 956         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 957
 958         if (txq_id != IWL_CMD_QUEUE_NUM)
 959                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 960
 961         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 962         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 963
 964         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 965                 scd_bc_tbl[txq_id].
 966                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 967 }
 968
 969 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 970                                         u16 txq_id)
 971 {
 972         u32 tbl_dw_addr;
 973         u32 tbl_dw;
 974         u16 scd_q2ratid;
 975
 976         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 977
 978         tbl_dw_addr = priv->scd_base_addr +
 979                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 980
 981         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 982
 983         if (txq_id & 0x1)
 984                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 985         else
 986                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 987
 988         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 989
 990         return 0;
 991 }
 992 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 993 {
 994         /* Simply stop the queue, but don't change any configuration;
 995          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 996         iwl_write_prph(priv,
 997                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 998                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 999                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1000 }
1001
1002 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1003                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1004 {
1005         unsigned long flags;
1006         int ret;
1007         u16 ra_tid;
1008
1009         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1010             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1011                 IWL_WARN(priv,
1012                         "queue number out of range: %d, must be %d to %d\n",
1013                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1014                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1015                 return -EINVAL;
1016         }
1017
1018         ra_tid = BUILD_RAxTID(sta_id, tid);
1019
1020         /* Modify device's station table to Tx this TID */
1021         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1022
1023         spin_lock_irqsave(&priv->lock, flags);
1024         ret = iwl_grab_nic_access(priv);
1025         if (ret) {
1026                 spin_unlock_irqrestore(&priv->lock, flags);
1027                 return ret;
1028         }
1029
1030         /* Stop this Tx queue before configuring it */
1031         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1032
1033         /* Map receiver-address / traffic-ID to this queue */
1034         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1035
1036         /* Set this queue as a chain-building queue */
1037         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1038
1039         /* enable aggregations for the queue */
1040         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1041
1042         /* Place first TFD at index corresponding to start sequence number.
1043          * Assumes that ssn_idx is valid (!= 0xFFF) */
1044         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1045         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1046         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1047
1048         /* Set up Tx window size and frame limit for this queue */
1049         iwl_write_targ_mem(priv, priv->scd_base_addr +
1050                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1051                         sizeof(u32),
1052                         ((SCD_WIN_SIZE <<
1053                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1054                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1055                         ((SCD_FRAME_LIMIT <<
1056                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1057                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1058
1059         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1060
1061         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1062         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1063
1064         iwl_release_nic_access(priv);
1065         spin_unlock_irqrestore(&priv->lock, flags);
1066
1067         return 0;
1068 }
1069
1070 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1071                                    u16 ssn_idx, u8 tx_fifo)
1072 {
1073         int ret;
1074
1075         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1076             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1077                 IWL_WARN(priv,
1078                         "queue number out of range: %d, must be %d to %d\n",
1079                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1080                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1081                 return -EINVAL;
1082         }
1083
1084         ret = iwl_grab_nic_access(priv);
1085         if (ret)
1086                 return ret;
1087
1088         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1089
1090         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1091
1092         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1093         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1094         /* supposes that ssn_idx is valid (!= 0xFFF) */
1095         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1096
1097         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1098         iwl_txq_ctx_deactivate(priv, txq_id);
1099         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1100
1101         iwl_release_nic_access(priv);
1102
1103         return 0;
1104 }
1105
1106 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1107 {
1108         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1109         memcpy(data, cmd, size);
1110         return size;
1111 }
1112
1113
1114 /*
1115  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1116  * must be called under priv->lock and mac access
1117  */
1118 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1119 {
1120         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1121 }
1122
1123
1124 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1125 {
1126         return le32_to_cpup((__le32 *)&tx_resp->status +
1127                             tx_resp->frame_count) & MAX_SN;
1128 }
1129
1130 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1131                                       struct iwl_ht_agg *agg,
1132                                       struct iwl5000_tx_resp *tx_resp,
1133                                       int txq_id, u16 start_idx)
1134 {
1135         u16 status;
1136         struct agg_tx_status *frame_status = &tx_resp->status;
1137         struct ieee80211_tx_info *info = NULL;
1138         struct ieee80211_hdr *hdr = NULL;
1139         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1140         int i, sh, idx;
1141         u16 seq;
1142
1143         if (agg->wait_for_ba)
1144                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1145
1146         agg->frame_count = tx_resp->frame_count;
1147         agg->start_idx = start_idx;
1148         agg->rate_n_flags = rate_n_flags;
1149         agg->bitmap = 0;
1150
1151         /* # frames attempted by Tx command */
1152         if (agg->frame_count == 1) {
1153                 /* Only one frame was attempted; no block-ack will arrive */
1154                 status = le16_to_cpu(frame_status[0].status);
1155                 idx = start_idx;
1156
1157                 /* FIXME: code repetition */
1158                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1159                                    agg->frame_count, agg->start_idx, idx);
1160
1161                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1162                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1163                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1164                 info->flags |= iwl_is_tx_success(status) ?
1165                                         IEEE80211_TX_STAT_ACK : 0;
1166                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1167
1168                 /* FIXME: code repetition end */
1169
1170                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1171                                     status & 0xff, tx_resp->failure_frame);
1172                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1173
1174                 agg->wait_for_ba = 0;
1175         } else {
1176                 /* Two or more frames were attempted; expect block-ack */
1177                 u64 bitmap = 0;
1178                 int start = agg->start_idx;
1179
1180                 /* Construct bit-map of pending frames within Tx window */
1181                 for (i = 0; i < agg->frame_count; i++) {
1182                         u16 sc;
1183                         status = le16_to_cpu(frame_status[i].status);
1184                         seq  = le16_to_cpu(frame_status[i].sequence);
1185                         idx = SEQ_TO_INDEX(seq);
1186                         txq_id = SEQ_TO_QUEUE(seq);
1187
1188                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1189                                       AGG_TX_STATE_ABORT_MSK))
1190                                 continue;
1191
1192                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1193                                            agg->frame_count, txq_id, idx);
1194
1195                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1196
1197                         sc = le16_to_cpu(hdr->seq_ctrl);
1198                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1199                                 IWL_ERR(priv,
1200                                         "BUG_ON idx doesn't match seq control"
1201                                         " idx=%d, seq_idx=%d, seq=%d\n",
1202                                           idx, SEQ_TO_SN(sc),
1203                                           hdr->seq_ctrl);
1204                                 return -1;
1205                         }
1206
1207                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1208                                            i, idx, SEQ_TO_SN(sc));
1209
1210                         sh = idx - start;
1211                         if (sh > 64) {
1212                                 sh = (start - idx) + 0xff;
1213                                 bitmap = bitmap << sh;
1214                                 sh = 0;
1215                                 start = idx;
1216                         } else if (sh < -64)
1217                                 sh  = 0xff - (start - idx);
1218                         else if (sh < 0) {
1219                                 sh = start - idx;
1220                                 start = idx;
1221                                 bitmap = bitmap << sh;
1222                                 sh = 0;
1223                         }
1224                         bitmap |= 1ULL << sh;
1225                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1226                                            start, (unsigned long long)bitmap);
1227                 }
1228
1229                 agg->bitmap = bitmap;
1230                 agg->start_idx = start;
1231                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1232                                    agg->frame_count, agg->start_idx,
1233                                    (unsigned long long)agg->bitmap);
1234
1235                 if (bitmap)
1236                         agg->wait_for_ba = 1;
1237         }
1238         return 0;
1239 }
1240
1241 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1242                                 struct iwl_rx_mem_buffer *rxb)
1243 {
1244         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1245         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1246         int txq_id = SEQ_TO_QUEUE(sequence);
1247         int index = SEQ_TO_INDEX(sequence);
1248         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1249         struct ieee80211_tx_info *info;
1250         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1251         u32  status = le16_to_cpu(tx_resp->status.status);
1252         int tid;
1253         int sta_id;
1254         int freed;
1255
1256         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1257                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1258                           "is out of range [0-%d] %d %d\n", txq_id,
1259                           index, txq->q.n_bd, txq->q.write_ptr,
1260                           txq->q.read_ptr);
1261                 return;
1262         }
1263
1264         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1265         memset(&info->status, 0, sizeof(info->status));
1266
1267         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1268         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1269
1270         if (txq->sched_retry) {
1271                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1272                 struct iwl_ht_agg *agg = NULL;
1273
1274                 agg = &priv->stations[sta_id].tid[tid].agg;
1275
1276                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1277
1278                 /* check if BAR is needed */
1279                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1280                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1281
1282                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1283                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1284                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1285                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1286                                         scd_ssn , index, txq_id, txq->swq_id);
1287
1288                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1289                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1290
1291                         if (priv->mac80211_registered &&
1292                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1293                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1294                                 if (agg->state == IWL_AGG_OFF)
1295                                         ieee80211_wake_queue(priv->hw, txq_id);
1296                                 else
1297                                         ieee80211_wake_queue(priv->hw,
1298                                                              txq->swq_id);
1299                         }
1300                 }
1301         } else {
1302                 BUG_ON(txq_id != txq->swq_id);
1303
1304                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1305                 info->flags |= iwl_is_tx_success(status) ?
1306                                         IEEE80211_TX_STAT_ACK : 0;
1307                 iwl_hwrate_to_tx_control(priv,
1308                                         le32_to_cpu(tx_resp->rate_n_flags),
1309                                         info);
1310
1311                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1312                                    "0x%x retries %d\n",
1313                                    txq_id,
1314                                    iwl_get_tx_fail_reason(status), status,
1315                                    le32_to_cpu(tx_resp->rate_n_flags),
1316                                    tx_resp->failure_frame);
1317
1318                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1319                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1320                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1321
1322                 if (priv->mac80211_registered &&
1323                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1324                         ieee80211_wake_queue(priv->hw, txq_id);
1325         }
1326
1327         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1328                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1329
1330         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1331                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1332 }
1333
1334 /* Currently 5000 is the superset of everything */
1335 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1336 {
1337         return len;
1338 }
1339
1340 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1341 {
1342         /* in 5000 the tx power calibration is done in uCode */
1343         priv->disable_tx_power_cal = 1;
1344 }
1345
1346 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1347 {
1348         /* init calibration handlers */
1349         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1350                                         iwl5000_rx_calib_result;
1351         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1352                                         iwl5000_rx_calib_complete;
1353         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1354 }
1355
1356
1357 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1358 {
1359         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1360                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1361 }
1362
1363 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1364 {
1365         int ret = 0;
1366         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1367         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1368         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1369
1370         if ((rxon1->flags == rxon2->flags) &&
1371             (rxon1->filter_flags == rxon2->filter_flags) &&
1372             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1373             (rxon1->ofdm_ht_single_stream_basic_rates ==
1374              rxon2->ofdm_ht_single_stream_basic_rates) &&
1375             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1376              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1377             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1378              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1379             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1380             (rxon1->rx_chain == rxon2->rx_chain) &&
1381             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1382                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1383                 return 0;
1384         }
1385
1386         rxon_assoc.flags = priv->staging_rxon.flags;
1387         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1388         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1389         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1390         rxon_assoc.reserved1 = 0;
1391         rxon_assoc.reserved2 = 0;
1392         rxon_assoc.reserved3 = 0;
1393         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1394             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1395         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1396             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1397         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1398         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1399                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1400         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1401
1402         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1403                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1404         if (ret)
1405                 return ret;
1406
1407         return ret;
1408 }
1409 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1410 {
1411         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1412
1413         /* half dBm need to multiply */
1414         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1415         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1416         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1417         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1418                                        sizeof(tx_power_cmd), &tx_power_cmd,
1419                                        NULL);
1420 }
1421
1422 static void iwl5000_temperature(struct iwl_priv *priv)
1423 {
1424         /* store temperature from statistics (in Celsius) */
1425         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1426 }
1427
1428 /* Calc max signal level (dBm) among 3 possible receivers */
1429 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1430                              struct iwl_rx_phy_res *rx_resp)
1431 {
1432         /* data from PHY/DSP regarding signal strength, etc.,
1433          *   contents are always there, not configurable by host
1434          */
1435         struct iwl5000_non_cfg_phy *ncphy =
1436                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1437         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1438         u8 agc;
1439
1440         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1441         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1442
1443         /* Find max rssi among 3 possible receivers.
1444          * These values are measured by the digital signal processor (DSP).
1445          * They should stay fairly constant even as the signal strength varies,
1446          *   if the radio's automatic gain control (AGC) is working right.
1447          * AGC value (see below) will provide the "interesting" info.
1448          */
1449         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1450         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1451         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1452         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1453         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1454
1455         max_rssi = max_t(u32, rssi_a, rssi_b);
1456         max_rssi = max_t(u32, max_rssi, rssi_c);
1457
1458         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1459                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1460
1461         /* dBm = max_rssi dB - agc dB - constant.
1462          * Higher AGC (higher radio gain) means lower signal. */
1463         return max_rssi - agc - IWL49_RSSI_OFFSET;
1464 }
1465
1466 static struct iwl_hcmd_ops iwl5000_hcmd = {
1467         .rxon_assoc = iwl5000_send_rxon_assoc,
1468 };
1469
1470 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1471         .get_hcmd_size = iwl5000_get_hcmd_size,
1472         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1473         .gain_computation = iwl5000_gain_computation,
1474         .chain_noise_reset = iwl5000_chain_noise_reset,
1475         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1476         .calc_rssi = iwl5000_calc_rssi,
1477 };
1478
1479 static struct iwl_lib_ops iwl5000_lib = {
1480         .set_hw_params = iwl5000_hw_set_hw_params,
1481         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1482         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1483         .txq_set_sched = iwl5000_txq_set_sched,
1484         .txq_agg_enable = iwl5000_txq_agg_enable,
1485         .txq_agg_disable = iwl5000_txq_agg_disable,
1486         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1487         .txq_free_tfd = iwl_hw_txq_free_tfd,
1488         .txq_init = iwl_hw_tx_queue_init,
1489         .rx_handler_setup = iwl5000_rx_handler_setup,
1490         .setup_deferred_work = iwl5000_setup_deferred_work,
1491         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1492         .load_ucode = iwl5000_load_ucode,
1493         .init_alive_start = iwl5000_init_alive_start,
1494         .alive_notify = iwl5000_alive_notify,
1495         .send_tx_power = iwl5000_send_tx_power,
1496         .temperature = iwl5000_temperature,
1497         .update_chain_flags = iwl_update_chain_flags,
1498         .apm_ops = {
1499                 .init = iwl5000_apm_init,
1500                 .reset = iwl5000_apm_reset,
1501                 .stop = iwl5000_apm_stop,
1502                 .config = iwl5000_nic_config,
1503                 .set_pwr_src = iwl_set_pwr_src,
1504         },
1505         .eeprom_ops = {
1506                 .regulatory_bands = {
1507                         EEPROM_5000_REG_BAND_1_CHANNELS,
1508                         EEPROM_5000_REG_BAND_2_CHANNELS,
1509                         EEPROM_5000_REG_BAND_3_CHANNELS,
1510                         EEPROM_5000_REG_BAND_4_CHANNELS,
1511                         EEPROM_5000_REG_BAND_5_CHANNELS,
1512                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1513                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1514                 },
1515                 .verify_signature  = iwlcore_eeprom_verify_signature,
1516                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1517                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1518                 .calib_version  = iwl5000_eeprom_calib_version,
1519                 .query_addr = iwl5000_eeprom_query_addr,
1520         },
1521 };
1522
1523 struct iwl_ops iwl5000_ops = {
1524         .lib = &iwl5000_lib,
1525         .hcmd = &iwl5000_hcmd,
1526         .utils = &iwl5000_hcmd_utils,
1527 };
1528
1529 struct iwl_mod_params iwl50_mod_params = {
1530         .num_of_queues = IWL50_NUM_QUEUES,
1531         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1532         .amsdu_size_8K = 1,
1533         .restart_fw = 1,
1534         /* the rest are 0 by default */
1535 };
1536
1537
1538 struct iwl_cfg iwl5300_agn_cfg = {
1539         .name = "5300AGN",
1540         .fw_name_pre = IWL5000_FW_PRE,
1541         .ucode_api_max = IWL5000_UCODE_API_MAX,
1542         .ucode_api_min = IWL5000_UCODE_API_MIN,
1543         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1544         .ops = &iwl5000_ops,
1545         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1546         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1547         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1548         .mod_params = &iwl50_mod_params,
1549         .valid_tx_ant = ANT_ABC,
1550         .valid_rx_ant = ANT_ABC,
1551 };
1552
1553 struct iwl_cfg iwl5100_bg_cfg = {
1554         .name = "5100BG",
1555         .fw_name_pre = IWL5000_FW_PRE,
1556         .ucode_api_max = IWL5000_UCODE_API_MAX,
1557         .ucode_api_min = IWL5000_UCODE_API_MIN,
1558         .sku = IWL_SKU_G,
1559         .ops = &iwl5000_ops,
1560         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1561         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1562         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1563         .mod_params = &iwl50_mod_params,
1564         .valid_tx_ant = ANT_B,
1565         .valid_rx_ant = ANT_AB,
1566 };
1567
1568 struct iwl_cfg iwl5100_abg_cfg = {
1569         .name = "5100ABG",
1570         .fw_name_pre = IWL5000_FW_PRE,
1571         .ucode_api_max = IWL5000_UCODE_API_MAX,
1572         .ucode_api_min = IWL5000_UCODE_API_MIN,
1573         .sku = IWL_SKU_A|IWL_SKU_G,
1574         .ops = &iwl5000_ops,
1575         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1576         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1577         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1578         .mod_params = &iwl50_mod_params,
1579         .valid_tx_ant = ANT_B,
1580         .valid_rx_ant = ANT_AB,
1581 };
1582
1583 struct iwl_cfg iwl5100_agn_cfg = {
1584         .name = "5100AGN",
1585         .fw_name_pre = IWL5000_FW_PRE,
1586         .ucode_api_max = IWL5000_UCODE_API_MAX,
1587         .ucode_api_min = IWL5000_UCODE_API_MIN,
1588         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1589         .ops = &iwl5000_ops,
1590         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1591         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1592         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1593         .mod_params = &iwl50_mod_params,
1594         .valid_tx_ant = ANT_B,
1595         .valid_rx_ant = ANT_AB,
1596 };
1597
1598 struct iwl_cfg iwl5350_agn_cfg = {
1599         .name = "5350AGN",
1600         .fw_name_pre = IWL5000_FW_PRE,
1601         .ucode_api_max = IWL5000_UCODE_API_MAX,
1602         .ucode_api_min = IWL5000_UCODE_API_MIN,
1603         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1604         .ops = &iwl5000_ops,
1605         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1606         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1607         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1608         .mod_params = &iwl50_mod_params,
1609         .valid_tx_ant = ANT_ABC,
1610         .valid_rx_ant = ANT_ABC,
1611 };
1612
1613 struct iwl_cfg iwl5150_agn_cfg = {
1614         .name = "5150AGN",
1615         .fw_name_pre = IWL5150_FW_PRE,
1616         .ucode_api_max = IWL5150_UCODE_API_MAX,
1617         .ucode_api_min = IWL5150_UCODE_API_MIN,
1618         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1619         .ops = &iwl5000_ops,
1620         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1621         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1622         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1623         .mod_params = &iwl50_mod_params,
1624         .valid_tx_ant = ANT_A,
1625         .valid_rx_ant = ANT_AB,
1626 };
1627
1628 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1629 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1630
1631 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1632 MODULE_PARM_DESC(disable50,
1633                   "manually disable the 50XX radio (default 0 [radio on])");
1634 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1635 MODULE_PARM_DESC(swcrypto50,
1636                   "using software crypto engine (default 0 [hardware])\n");
1637 module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1638 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1639 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1640 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1641 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1642 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1643 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1644 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1645 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1646 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");