1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
46 #include "iwl-eeprom.h"
47 #include "iwl-helpers.h"
49 #include "iwl-agn-rs.h"
51 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
71 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
86 /* 1 = enable the iwl3945_disable_events() function */
87 #define IWL_EVT_DISABLE (0)
88 #define IWL_EVT_DISABLE_SIZE (1532/32)
91 * iwl3945_disable_events - Disable selected events in uCode event log
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
99 void iwl3945_disable_events(struct iwl_priv *priv)
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
162 ret = iwl_grab_nic_access(priv);
164 IWL_WARN(priv, "Can not read from adapter at this time.\n");
168 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
169 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
170 iwl_release_nic_access(priv);
172 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
173 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
175 ret = iwl_grab_nic_access(priv);
176 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
177 iwl_write_targ_mem(priv,
178 disable_ptr + (i * sizeof(u32)),
181 iwl_release_nic_access(priv);
183 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
184 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
185 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
186 disable_ptr, array_size);
191 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
195 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
196 if (iwl3945_rates[idx].plcp == plcp)
201 #ifdef CONFIG_IWLWIFI_DEBUG
202 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
204 static const char *iwl3945_get_tx_fail_reason(u32 status)
206 switch (status & TX_STATUS_MSK) {
207 case TX_STATUS_SUCCESS:
209 TX_STATUS_ENTRY(SHORT_LIMIT);
210 TX_STATUS_ENTRY(LONG_LIMIT);
211 TX_STATUS_ENTRY(FIFO_UNDERRUN);
212 TX_STATUS_ENTRY(MGMNT_ABORT);
213 TX_STATUS_ENTRY(NEXT_FRAG);
214 TX_STATUS_ENTRY(LIFE_EXPIRE);
215 TX_STATUS_ENTRY(DEST_PS);
216 TX_STATUS_ENTRY(ABORTED);
217 TX_STATUS_ENTRY(BT_RETRY);
218 TX_STATUS_ENTRY(STA_INVALID);
219 TX_STATUS_ENTRY(FRAG_DROPPED);
220 TX_STATUS_ENTRY(TID_DISABLE);
221 TX_STATUS_ENTRY(FRAME_FLUSHED);
222 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
223 TX_STATUS_ENTRY(TX_LOCKED);
224 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
230 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
237 * get ieee prev rate from rate scale table.
238 * for A and B mode we need to overright prev
241 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
243 int next_rate = iwl3945_get_prev_ieee_rate(rate);
245 switch (priv->band) {
246 case IEEE80211_BAND_5GHZ:
247 if (rate == IWL_RATE_12M_INDEX)
248 next_rate = IWL_RATE_9M_INDEX;
249 else if (rate == IWL_RATE_6M_INDEX)
250 next_rate = IWL_RATE_6M_INDEX;
252 case IEEE80211_BAND_2GHZ:
253 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
254 iwl_is_associated(priv)) {
255 if (rate == IWL_RATE_11M_INDEX)
256 next_rate = IWL_RATE_5M_INDEX;
269 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
271 * When FW advances 'R' index, all entries between old and new 'R' index
272 * need to be reclaimed. As result, some free space forms. If there is
273 * enough free space (> low mark), wake the stack that feeds us.
275 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
276 int txq_id, int index)
278 struct iwl_tx_queue *txq = &priv->txq[txq_id];
279 struct iwl_queue *q = &txq->q;
280 struct iwl_tx_info *tx_info;
282 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
284 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
285 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
287 tx_info = &txq->txb[txq->q.read_ptr];
288 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
289 tx_info->skb[0] = NULL;
290 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
293 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
294 (txq_id != IWL_CMD_QUEUE_NUM) &&
295 priv->mac80211_registered)
296 ieee80211_wake_queue(priv->hw, txq_id);
300 * iwl3945_rx_reply_tx - Handle Tx response
302 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
303 struct iwl_rx_mem_buffer *rxb)
305 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
306 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
307 int txq_id = SEQ_TO_QUEUE(sequence);
308 int index = SEQ_TO_INDEX(sequence);
309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
310 struct ieee80211_tx_info *info;
311 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
312 u32 status = le32_to_cpu(tx_resp->status);
316 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
317 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
318 "is out of range [0-%d] %d %d\n", txq_id,
319 index, txq->q.n_bd, txq->q.write_ptr,
324 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
325 ieee80211_tx_info_clear_status(info);
327 /* Fill the MRR chain with some info about on-chip retransmissions */
328 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
329 if (info->band == IEEE80211_BAND_5GHZ)
330 rate_idx -= IWL_FIRST_OFDM_RATE;
332 fail = tx_resp->failure_frame;
334 info->status.rates[0].idx = rate_idx;
335 info->status.rates[0].count = fail + 1; /* add final attempt */
337 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
338 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
339 IEEE80211_TX_STAT_ACK : 0;
341 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
342 txq_id, iwl3945_get_tx_fail_reason(status), status,
343 tx_resp->rate, tx_resp->failure_frame);
345 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
346 iwl3945_tx_queue_reclaim(priv, txq_id, index);
348 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
349 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
354 /*****************************************************************************
356 * Intel PRO/Wireless 3945ABG/BG Network Connection
358 * RX handler implementations
360 *****************************************************************************/
362 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
364 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
365 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
366 (int)sizeof(struct iwl3945_notif_statistics),
367 le32_to_cpu(pkt->len));
369 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
371 iwl3945_led_background(priv);
373 priv->last_statistics_time = jiffies;
376 /******************************************************************************
378 * Misc. internal state and helper functions
380 ******************************************************************************/
381 #ifdef CONFIG_IWLWIFI_DEBUG
384 * iwl3945_report_frame - dump frame to syslog during debug sessions
386 * You may hack this function to show different aspects of received frames,
387 * including selective frame dumps.
388 * group100 parameter selects whether to show 1 out of 100 good frames.
390 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
391 struct iwl_rx_packet *pkt,
392 struct ieee80211_hdr *header, int group100)
395 u32 print_summary = 0;
396 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
412 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
413 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
414 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
415 u8 *data = IWL_RX_DATA(pkt);
418 fc = header->frame_control;
419 seq_ctl = le16_to_cpu(header->seq_ctrl);
422 channel = le16_to_cpu(rx_hdr->channel);
423 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
424 length = le16_to_cpu(rx_hdr->len);
426 /* end-of-frame status and timestamp */
427 status = le32_to_cpu(rx_end->status);
428 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
429 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
430 tsf = le64_to_cpu(rx_end->timestamp);
432 /* signal statistics */
433 rssi = rx_stats->rssi;
435 sig_avg = le16_to_cpu(rx_stats->sig_avg);
436 noise_diff = le16_to_cpu(rx_stats->noise_diff);
438 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
440 /* if data frame is to us and all is good,
441 * (optionally) print summary for only 1 out of every 100 */
442 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
443 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
446 print_summary = 1; /* print each frame */
447 else if (priv->framecnt_to_us < 100) {
448 priv->framecnt_to_us++;
451 priv->framecnt_to_us = 0;
456 /* print summary for all other frames */
466 else if (ieee80211_has_retry(fc))
468 else if (ieee80211_is_assoc_resp(fc))
470 else if (ieee80211_is_reassoc_resp(fc))
472 else if (ieee80211_is_probe_resp(fc)) {
474 print_dump = 1; /* dump frame contents */
475 } else if (ieee80211_is_beacon(fc)) {
477 print_dump = 1; /* dump frame contents */
478 } else if (ieee80211_is_atim(fc))
480 else if (ieee80211_is_auth(fc))
482 else if (ieee80211_is_deauth(fc))
484 else if (ieee80211_is_disassoc(fc))
489 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
493 rate = iwl3945_rates[rate].ieee / 2;
495 /* print frame summary.
496 * MAC addresses show just the last byte (for brevity),
497 * but you can hack it to show more, if you'd like to. */
499 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
500 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
501 title, le16_to_cpu(fc), header->addr1[5],
502 length, rssi, channel, rate);
504 /* src/dst addresses assume managed mode */
505 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
506 "src=0x%02x, rssi=%u, tim=%lu usec, "
507 "phy=0x%02x, chnl=%d\n",
508 title, le16_to_cpu(fc), header->addr1[5],
509 header->addr3[5], rssi,
510 tsf_low - priv->scan_start_tsf,
515 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
518 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
519 struct iwl_rx_packet *pkt,
520 struct ieee80211_hdr *header, int group100)
522 if (priv->debug_level & IWL_DL_RX)
523 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
527 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
528 struct iwl_rx_packet *pkt,
529 struct ieee80211_hdr *header, int group100)
534 /* This is necessary only for a number of statistics, see the caller. */
535 static int iwl3945_is_network_packet(struct iwl_priv *priv,
536 struct ieee80211_hdr *header)
538 /* Filter incoming packets to determine if they are targeted toward
539 * this network, discarding packets coming from ourselves */
540 switch (priv->iw_mode) {
541 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
542 /* packets to our IBSS update information */
543 return !compare_ether_addr(header->addr3, priv->bssid);
544 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
545 /* packets to our IBSS update information */
546 return !compare_ether_addr(header->addr2, priv->bssid);
552 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
553 struct iwl_rx_mem_buffer *rxb,
554 struct ieee80211_rx_status *stats)
556 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
557 #ifdef CONFIG_IWL3945_LEDS
558 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
560 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
561 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
562 short len = le16_to_cpu(rx_hdr->len);
564 /* We received data from the HW, so stop the watchdog */
565 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
566 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
570 /* We only process data packets if the interface is open */
571 if (unlikely(!priv->is_open)) {
572 IWL_DEBUG_DROP_LIMIT(priv,
573 "Dropping packet while interface is not open.\n");
577 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
578 /* Set the size of the skb to the size of the frame */
579 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
581 if (!iwl3945_mod_params.sw_crypto)
582 iwl_set_decrypted_flag(priv,
583 (struct ieee80211_hdr *)rxb->skb->data,
584 le32_to_cpu(rx_end->status), stats);
586 #ifdef CONFIG_IWL3945_LEDS
587 if (ieee80211_is_data(hdr->frame_control))
588 priv->rxtxpackets += len;
590 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
594 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
596 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
597 struct iwl_rx_mem_buffer *rxb)
599 struct ieee80211_hdr *header;
600 struct ieee80211_rx_status rx_status;
601 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
602 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
603 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
604 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
606 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
607 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
611 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
613 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
614 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
615 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
617 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
618 if (rx_status.band == IEEE80211_BAND_5GHZ)
619 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
621 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
622 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
624 /* set the preamble flag if appropriate */
625 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
626 rx_status.flag |= RX_FLAG_SHORTPRE;
628 if ((unlikely(rx_stats->phy_count > 20))) {
629 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
630 rx_stats->phy_count);
634 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
635 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
636 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
642 /* Convert 3945's rssi indicator to dBm */
643 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
645 /* Set default noise value to -127 */
646 if (priv->last_rx_noise == 0)
647 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
649 /* 3945 provides noise info for OFDM frames only.
650 * sig_avg and noise_diff are measured by the 3945's digital signal
651 * processor (DSP), and indicate linear levels of signal level and
652 * distortion/noise within the packet preamble after
653 * automatic gain control (AGC). sig_avg should stay fairly
654 * constant if the radio's AGC is working well.
655 * Since these values are linear (not dB or dBm), linear
656 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
657 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
658 * to obtain noise level in dBm.
659 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
660 if (rx_stats_noise_diff) {
661 snr = rx_stats_sig_avg / rx_stats_noise_diff;
662 rx_status.noise = rx_status.signal -
663 iwl3945_calc_db_from_ratio(snr);
664 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
667 /* If noise info not available, calculate signal quality indicator (%)
668 * using just the dBm signal level. */
670 rx_status.noise = priv->last_rx_noise;
671 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
675 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
676 rx_status.signal, rx_status.noise, rx_status.qual,
677 rx_stats_sig_avg, rx_stats_noise_diff);
679 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
681 network_packet = iwl3945_is_network_packet(priv, header);
683 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
684 network_packet ? '*' : ' ',
685 le16_to_cpu(rx_hdr->channel),
686 rx_status.signal, rx_status.signal,
687 rx_status.noise, rx_status.rate_idx);
689 /* Set "1" to report good data frames in groups of 100 */
690 iwl3945_dbg_report_frame(priv, pkt, header, 1);
692 if (network_packet) {
693 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
694 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
695 priv->last_rx_rssi = rx_status.signal;
696 priv->last_rx_noise = rx_status.noise;
699 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
702 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
703 struct iwl_tx_queue *txq,
704 dma_addr_t addr, u16 len, u8 reset, u8 pad)
708 struct iwl3945_tfd *tfd, *tfd_tmp;
711 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
712 tfd = &tfd_tmp[q->write_ptr];
715 memset(tfd, 0, sizeof(*tfd));
717 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
719 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
720 IWL_ERR(priv, "Error can not send more than %d chunks\n",
725 tfd->tbs[count].addr = cpu_to_le32(addr);
726 tfd->tbs[count].len = cpu_to_le32(len);
730 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
731 TFD_CTL_PAD_SET(pad));
737 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
739 * Does NOT advance any indexes
741 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
743 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
744 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
745 struct pci_dev *dev = priv->pci_dev;
750 if (txq->q.id == IWL_CMD_QUEUE_NUM)
751 /* nothing to cleanup after for host commands */
755 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
756 if (counter > NUM_TFD_CHUNKS) {
757 IWL_ERR(priv, "Too many chunks: %i\n", counter);
758 /* @todo issue fatal error, it is quite serious situation */
762 /* unmap chunks if any */
764 for (i = 1; i < counter; i++) {
765 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
766 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
767 if (txq->txb[txq->q.read_ptr].skb[0]) {
768 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
769 if (txq->txb[txq->q.read_ptr].skb[0]) {
770 /* Can be called from interrupt context */
771 dev_kfree_skb_any(skb);
772 txq->txb[txq->q.read_ptr].skb[0] = NULL;
779 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
781 int i, start = IWL_AP_ID;
782 int ret = IWL_INVALID_STATION;
785 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
786 (priv->iw_mode == NL80211_IFTYPE_AP))
789 if (is_broadcast_ether_addr(addr))
790 return priv->hw_params.bcast_sta_id;
792 spin_lock_irqsave(&priv->sta_lock, flags);
793 for (i = start; i < priv->hw_params.max_stations; i++)
794 if ((priv->stations_39[i].used) &&
796 (priv->stations_39[i].sta.sta.addr, addr))) {
801 IWL_DEBUG_INFO(priv, "can not find STA %pM (total %d)\n",
802 addr, priv->num_stations);
804 spin_unlock_irqrestore(&priv->sta_lock, flags);
809 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
812 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
813 struct ieee80211_tx_info *info,
814 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
816 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
817 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
823 __le16 fc = hdr->frame_control;
824 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
826 rate = iwl3945_rates[rate_index].plcp;
827 tx_flags = tx->tx_flags;
829 /* We need to figure out how to get the sta->supp_rates while
830 * in this running context */
831 rate_mask = IWL_RATES_MASK;
833 if (tx_id >= IWL_CMD_QUEUE_NUM)
838 if (ieee80211_is_probe_resp(fc)) {
839 data_retry_limit = 3;
840 if (data_retry_limit < rts_retry_limit)
841 rts_retry_limit = data_retry_limit;
843 data_retry_limit = IWL_DEFAULT_TX_RETRY;
845 if (priv->data_retry_limit != -1)
846 data_retry_limit = priv->data_retry_limit;
848 if (ieee80211_is_mgmt(fc)) {
849 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
850 case cpu_to_le16(IEEE80211_STYPE_AUTH):
851 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
852 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
853 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
854 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
855 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
856 tx_flags |= TX_CMD_FLG_CTS_MSK;
864 tx->rts_retry_limit = rts_retry_limit;
865 tx->data_retry_limit = data_retry_limit;
867 tx->tx_flags = tx_flags;
871 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
874 tx->supp_rates[1] = (rate_mask & 0xF);
876 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
877 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
878 tx->rate, le32_to_cpu(tx->tx_flags),
879 tx->supp_rates[1], tx->supp_rates[0]);
882 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
884 unsigned long flags_spin;
885 struct iwl3945_station_entry *station;
887 if (sta_id == IWL_INVALID_STATION)
888 return IWL_INVALID_STATION;
890 spin_lock_irqsave(&priv->sta_lock, flags_spin);
891 station = &priv->stations_39[sta_id];
893 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
894 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
895 station->sta.mode = STA_CONTROL_MODIFY_MSK;
897 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
899 iwl_send_add_sta(priv,
900 (struct iwl_addsta_cmd *)&station->sta, flags);
901 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
906 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
911 spin_lock_irqsave(&priv->lock, flags);
912 rc = iwl_grab_nic_access(priv);
914 spin_unlock_irqrestore(&priv->lock, flags);
918 if (src == IWL_PWR_SRC_VAUX) {
921 rc = pci_read_config_dword(priv->pci_dev,
922 PCI_POWER_SOURCE, &val);
923 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
924 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
925 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
926 ~APMG_PS_CTRL_MSK_PWR_SRC);
927 iwl_release_nic_access(priv);
929 iwl_poll_bit(priv, CSR_GPIO_IN,
930 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
931 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
933 iwl_release_nic_access(priv);
935 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
936 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
937 ~APMG_PS_CTRL_MSK_PWR_SRC);
939 iwl_release_nic_access(priv);
940 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
941 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
943 spin_unlock_irqrestore(&priv->lock, flags);
948 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
953 spin_lock_irqsave(&priv->lock, flags);
954 rc = iwl_grab_nic_access(priv);
956 spin_unlock_irqrestore(&priv->lock, flags);
960 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
961 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
962 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
963 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
964 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
965 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
966 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
967 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
968 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
969 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
970 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
971 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
973 /* fake read to flush all prev I/O */
974 iwl_read_direct32(priv, FH39_RSSR_CTRL);
976 iwl_release_nic_access(priv);
977 spin_unlock_irqrestore(&priv->lock, flags);
982 static int iwl3945_tx_reset(struct iwl_priv *priv)
987 spin_lock_irqsave(&priv->lock, flags);
988 rc = iwl_grab_nic_access(priv);
990 spin_unlock_irqrestore(&priv->lock, flags);
995 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
998 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1000 /* all 6 fifo are active */
1001 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1003 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1004 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1005 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1006 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1008 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1011 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1012 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1013 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1014 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1015 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1016 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1017 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1018 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1020 iwl_release_nic_access(priv);
1021 spin_unlock_irqrestore(&priv->lock, flags);
1027 * iwl3945_txq_ctx_reset - Reset TX queue context
1029 * Destroys all DMA structures and initialize them again
1031 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1034 int txq_id, slots_num;
1036 iwl3945_hw_txq_ctx_free(priv);
1039 rc = iwl3945_tx_reset(priv);
1044 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1045 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1046 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1047 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1050 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1058 iwl3945_hw_txq_ctx_free(priv);
1062 static int iwl3945_apm_init(struct iwl_priv *priv)
1066 iwl_power_initialize(priv);
1068 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1069 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1071 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1072 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1073 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1075 /* set "initialization complete" bit to move adapter
1076 * D0U* --> D0A* state */
1077 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1079 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1080 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1082 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1086 ret = iwl_grab_nic_access(priv);
1091 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1092 APMG_CLK_VAL_BSM_CLK_RQT);
1096 /* disable L1-Active */
1097 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1098 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1100 iwl_release_nic_access(priv);
1105 static void iwl3945_nic_config(struct iwl_priv *priv)
1107 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1108 unsigned long flags;
1111 spin_lock_irqsave(&priv->lock, flags);
1113 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1114 IWL_DEBUG_INFO(priv, "RTP type \n");
1115 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1116 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1117 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1118 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1120 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1121 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1122 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1125 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1126 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1127 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1128 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1130 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1132 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1133 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1134 eeprom->board_revision);
1135 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1136 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1138 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1139 eeprom->board_revision);
1140 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1141 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1144 if (eeprom->almgor_m_version <= 1) {
1145 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1146 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1147 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1148 eeprom->almgor_m_version);
1150 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1151 eeprom->almgor_m_version);
1152 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1153 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1155 spin_unlock_irqrestore(&priv->lock, flags);
1157 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1158 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1160 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1161 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1164 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1168 unsigned long flags;
1169 struct iwl_rx_queue *rxq = &priv->rxq;
1171 spin_lock_irqsave(&priv->lock, flags);
1172 priv->cfg->ops->lib->apm_ops.init(priv);
1173 spin_unlock_irqrestore(&priv->lock, flags);
1175 /* Determine HW type */
1176 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1179 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1181 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1185 priv->cfg->ops->lib->apm_ops.config(priv);
1187 /* Allocate the RX queue, or reset if it is already allocated */
1189 rc = iwl_rx_queue_alloc(priv);
1191 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1195 iwl_rx_queue_reset(priv, rxq);
1197 iwl3945_rx_replenish(priv);
1199 iwl3945_rx_init(priv, rxq);
1201 spin_lock_irqsave(&priv->lock, flags);
1203 /* Look at using this instead:
1204 rxq->need_update = 1;
1205 iwl_rx_queue_update_write_ptr(priv, rxq);
1208 rc = iwl_grab_nic_access(priv);
1210 spin_unlock_irqrestore(&priv->lock, flags);
1213 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1214 iwl_release_nic_access(priv);
1216 spin_unlock_irqrestore(&priv->lock, flags);
1218 rc = iwl3945_txq_ctx_reset(priv);
1222 set_bit(STATUS_INIT, &priv->status);
1228 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1230 * Destroy all TX DMA queues and structures
1232 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1237 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1238 iwl_tx_queue_free(priv, txq_id);
1241 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1244 unsigned long flags;
1246 spin_lock_irqsave(&priv->lock, flags);
1247 if (iwl_grab_nic_access(priv)) {
1248 spin_unlock_irqrestore(&priv->lock, flags);
1249 iwl3945_hw_txq_ctx_free(priv);
1254 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1256 /* reset TFD queues */
1257 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1258 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1259 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1260 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1264 iwl_release_nic_access(priv);
1265 spin_unlock_irqrestore(&priv->lock, flags);
1267 iwl3945_hw_txq_ctx_free(priv);
1270 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1273 unsigned long flags;
1275 spin_lock_irqsave(&priv->lock, flags);
1277 /* set stop master bit */
1278 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1280 iwl_poll_direct_bit(priv, CSR_RESET,
1281 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1287 spin_unlock_irqrestore(&priv->lock, flags);
1288 IWL_DEBUG_INFO(priv, "stop master\n");
1293 static void iwl3945_apm_stop(struct iwl_priv *priv)
1295 unsigned long flags;
1297 iwl3945_apm_stop_master(priv);
1299 spin_lock_irqsave(&priv->lock, flags);
1301 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1304 /* clear "init complete" move adapter D0A* --> D0U state */
1305 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1306 spin_unlock_irqrestore(&priv->lock, flags);
1309 static int iwl3945_apm_reset(struct iwl_priv *priv)
1312 unsigned long flags;
1314 iwl3945_apm_stop_master(priv);
1316 spin_lock_irqsave(&priv->lock, flags);
1318 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1321 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1323 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1324 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1326 rc = iwl_grab_nic_access(priv);
1328 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1329 APMG_CLK_VAL_BSM_CLK_RQT);
1331 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1332 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1336 iwl_write_prph(priv, APMG_CLK_EN_REG,
1337 APMG_CLK_VAL_DMA_CLK_RQT |
1338 APMG_CLK_VAL_BSM_CLK_RQT);
1341 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1342 APMG_PS_CTRL_VAL_RESET_REQ);
1344 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1345 APMG_PS_CTRL_VAL_RESET_REQ);
1346 iwl_release_nic_access(priv);
1349 /* Clear the 'host command active' bit... */
1350 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1352 wake_up_interruptible(&priv->wait_command_queue);
1353 spin_unlock_irqrestore(&priv->lock, flags);
1359 * iwl3945_hw_reg_adjust_power_by_temp
1360 * return index delta into power gain settings table
1362 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1364 return (new_reading - old_reading) * (-11) / 100;
1368 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1370 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1372 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1375 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1377 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1381 * iwl3945_hw_reg_txpower_get_temperature
1382 * get the current temperature by reading from NIC
1384 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1386 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1389 temperature = iwl3945_hw_get_temperature(priv);
1391 /* driver's okay range is -260 to +25.
1392 * human readable okay range is 0 to +285 */
1393 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1395 /* handle insane temp reading */
1396 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1397 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1399 /* if really really hot(?),
1400 * substitute the 3rd band/group's temp measured at factory */
1401 if (priv->last_temperature > 100)
1402 temperature = eeprom->groups[2].temperature;
1403 else /* else use most recent "sane" value from driver */
1404 temperature = priv->last_temperature;
1407 return temperature; /* raw, not "human readable" */
1410 /* Adjust Txpower only if temperature variance is greater than threshold.
1412 * Both are lower than older versions' 9 degrees */
1413 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1416 * is_temp_calib_needed - determines if new calibration is needed
1418 * records new temperature in tx_mgr->temperature.
1419 * replaces tx_mgr->last_temperature *only* if calib needed
1420 * (assumes caller will actually do the calibration!). */
1421 static int is_temp_calib_needed(struct iwl_priv *priv)
1425 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1426 temp_diff = priv->temperature - priv->last_temperature;
1428 /* get absolute value */
1429 if (temp_diff < 0) {
1430 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1431 temp_diff = -temp_diff;
1432 } else if (temp_diff == 0)
1433 IWL_DEBUG_POWER(priv, "Same temp,\n");
1435 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1437 /* if we don't need calibration, *don't* update last_temperature */
1438 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1439 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1443 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1445 /* assume that caller will actually do calib ...
1446 * update the "last temperature" value */
1447 priv->last_temperature = priv->temperature;
1451 #define IWL_MAX_GAIN_ENTRIES 78
1452 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1453 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1455 /* radio and DSP power table, each step is 1/2 dB.
1456 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1457 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1459 {251, 127}, /* 2.4 GHz, highest power */
1536 {3, 95} }, /* 2.4 GHz, lowest power */
1538 {251, 127}, /* 5.x GHz, highest power */
1615 {3, 120} } /* 5.x GHz, lowest power */
1618 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1622 if (index >= IWL_MAX_GAIN_ENTRIES)
1623 return IWL_MAX_GAIN_ENTRIES - 1;
1627 /* Kick off thermal recalibration check every 60 seconds */
1628 #define REG_RECALIB_PERIOD (60)
1631 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1633 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1634 * or 6 Mbit (OFDM) rates.
1636 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1637 s32 rate_index, const s8 *clip_pwrs,
1638 struct iwl_channel_info *ch_info,
1641 struct iwl3945_scan_power_info *scan_power_info;
1645 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1647 /* use this channel group's 6Mbit clipping/saturation pwr,
1648 * but cap at regulatory scan power restriction (set during init
1649 * based on eeprom channel data) for this channel. */
1650 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1652 /* further limit to user's max power preference.
1653 * FIXME: Other spectrum management power limitations do not
1654 * seem to apply?? */
1655 power = min(power, priv->tx_power_user_lmt);
1656 scan_power_info->requested_power = power;
1658 /* find difference between new scan *power* and current "normal"
1659 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1660 * current "normal" temperature-compensated Tx power *index* for
1661 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1663 power_index = ch_info->power_info[rate_index].power_table_index
1664 - (power - ch_info->power_info
1665 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1667 /* store reference index that we use when adjusting *all* scan
1668 * powers. So we can accommodate user (all channel) or spectrum
1669 * management (single channel) power changes "between" temperature
1670 * feedback compensation procedures.
1671 * don't force fit this reference index into gain table; it may be a
1672 * negative number. This will help avoid errors when we're at
1673 * the lower bounds (highest gains, for warmest temperatures)
1676 /* don't exceed table bounds for "real" setting */
1677 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1679 scan_power_info->power_table_index = power_index;
1680 scan_power_info->tpc.tx_gain =
1681 power_gain_table[band_index][power_index].tx_gain;
1682 scan_power_info->tpc.dsp_atten =
1683 power_gain_table[band_index][power_index].dsp_atten;
1687 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1689 * Configures power settings for all rates for the current channel,
1690 * using values from channel info struct, and send to NIC
1692 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1695 const struct iwl_channel_info *ch_info = NULL;
1696 struct iwl3945_txpowertable_cmd txpower = {
1697 .channel = priv->active_rxon.channel,
1700 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1701 ch_info = iwl_get_channel_info(priv,
1703 le16_to_cpu(priv->active_rxon.channel));
1706 "Failed to get channel info for channel %d [%d]\n",
1707 le16_to_cpu(priv->active_rxon.channel), priv->band);
1711 if (!is_channel_valid(ch_info)) {
1712 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1713 "non-Tx channel.\n");
1717 /* fill cmd with power settings for all rates for current channel */
1718 /* Fill OFDM rate */
1719 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1720 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1722 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1723 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1725 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1726 le16_to_cpu(txpower.channel),
1728 txpower.power[i].tpc.tx_gain,
1729 txpower.power[i].tpc.dsp_atten,
1730 txpower.power[i].rate);
1732 /* Fill CCK rates */
1733 for (rate_idx = IWL_FIRST_CCK_RATE;
1734 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1735 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1736 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1738 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1739 le16_to_cpu(txpower.channel),
1741 txpower.power[i].tpc.tx_gain,
1742 txpower.power[i].tpc.dsp_atten,
1743 txpower.power[i].rate);
1746 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1747 sizeof(struct iwl3945_txpowertable_cmd),
1753 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1754 * @ch_info: Channel to update. Uses power_info.requested_power.
1756 * Replace requested_power and base_power_index ch_info fields for
1759 * Called if user or spectrum management changes power preferences.
1760 * Takes into account h/w and modulation limitations (clip power).
1762 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1764 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1765 * properly fill out the scan powers, and actual h/w gain settings,
1766 * and send changes to NIC
1768 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1769 struct iwl_channel_info *ch_info)
1771 struct iwl3945_channel_power_info *power_info;
1772 int power_changed = 0;
1774 const s8 *clip_pwrs;
1777 /* Get this chnlgrp's rate-to-max/clip-powers table */
1778 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1780 /* Get this channel's rate-to-current-power settings table */
1781 power_info = ch_info->power_info;
1783 /* update OFDM Txpower settings */
1784 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1785 i++, ++power_info) {
1788 /* limit new power to be no more than h/w capability */
1789 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1790 if (power == power_info->requested_power)
1793 /* find difference between old and new requested powers,
1794 * update base (non-temp-compensated) power index */
1795 delta_idx = (power - power_info->requested_power) * 2;
1796 power_info->base_power_index -= delta_idx;
1798 /* save new requested power value */
1799 power_info->requested_power = power;
1804 /* update CCK Txpower settings, based on OFDM 12M setting ...
1805 * ... all CCK power settings for a given channel are the *same*. */
1806 if (power_changed) {
1808 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1809 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1811 /* do all CCK rates' iwl3945_channel_power_info structures */
1812 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1813 power_info->requested_power = power;
1814 power_info->base_power_index =
1815 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1816 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1825 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1827 * NOTE: Returned power limit may be less (but not more) than requested,
1828 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1829 * (no consideration for h/w clipping limitations).
1831 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1836 /* if we're using TGd limits, use lower of TGd or EEPROM */
1837 if (ch_info->tgd_data.max_power != 0)
1838 max_power = min(ch_info->tgd_data.max_power,
1839 ch_info->eeprom.max_power_avg);
1841 /* else just use EEPROM limits */
1844 max_power = ch_info->eeprom.max_power_avg;
1846 return min(max_power, ch_info->max_power_avg);
1850 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1852 * Compensate txpower settings of *all* channels for temperature.
1853 * This only accounts for the difference between current temperature
1854 * and the factory calibration temperatures, and bases the new settings
1855 * on the channel's base_power_index.
1857 * If RxOn is "associated", this sends the new Txpower to NIC!
1859 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1861 struct iwl_channel_info *ch_info = NULL;
1862 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1864 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1870 int temperature = priv->temperature;
1872 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1873 for (i = 0; i < priv->channel_count; i++) {
1874 ch_info = &priv->channel_info[i];
1875 a_band = is_channel_a_band(ch_info);
1877 /* Get this chnlgrp's factory calibration temperature */
1878 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1881 /* get power index adjustment based on current and factory
1883 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1886 /* set tx power value for all rates, OFDM and CCK */
1887 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1890 ch_info->power_info[rate_index].base_power_index;
1892 /* temperature compensate */
1893 power_idx += delta_index;
1895 /* stay within table range */
1896 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1897 ch_info->power_info[rate_index].
1898 power_table_index = (u8) power_idx;
1899 ch_info->power_info[rate_index].tpc =
1900 power_gain_table[a_band][power_idx];
1903 /* Get this chnlgrp's rate-to-max/clip-powers table */
1904 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1906 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1907 for (scan_tbl_index = 0;
1908 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1909 s32 actual_index = (scan_tbl_index == 0) ?
1910 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1911 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1912 actual_index, clip_pwrs,
1917 /* send Txpower command for current channel to ucode */
1918 return priv->cfg->ops->lib->send_tx_power(priv);
1921 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1923 struct iwl_channel_info *ch_info;
1928 if (priv->tx_power_user_lmt == power) {
1929 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1930 "limit: %ddBm.\n", power);
1934 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1935 priv->tx_power_user_lmt = power;
1937 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1939 for (i = 0; i < priv->channel_count; i++) {
1940 ch_info = &priv->channel_info[i];
1941 a_band = is_channel_a_band(ch_info);
1943 /* find minimum power of all user and regulatory constraints
1944 * (does not consider h/w clipping limitations) */
1945 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1946 max_power = min(power, max_power);
1947 if (max_power != ch_info->curr_txpow) {
1948 ch_info->curr_txpow = max_power;
1950 /* this considers the h/w clipping limitations */
1951 iwl3945_hw_reg_set_new_power(priv, ch_info);
1955 /* update txpower settings for all channels,
1956 * send to NIC if associated. */
1957 is_temp_calib_needed(priv);
1958 iwl3945_hw_reg_comp_txpower_temp(priv);
1963 /* will add 3945 channel switch cmd handling later */
1964 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1970 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1972 * -- reset periodic timer
1973 * -- see if temp has changed enough to warrant re-calibration ... if so:
1974 * -- correct coeffs for temp (can reset temp timer)
1975 * -- save this temp as "last",
1976 * -- send new set of gain settings to NIC
1977 * NOTE: This should continue working, even when we're not associated,
1978 * so we can keep our internal table of scan powers current. */
1979 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1981 /* This will kick in the "brute force"
1982 * iwl3945_hw_reg_comp_txpower_temp() below */
1983 if (!is_temp_calib_needed(priv))
1986 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1987 * This is based *only* on current temperature,
1988 * ignoring any previous power measurements */
1989 iwl3945_hw_reg_comp_txpower_temp(priv);
1992 queue_delayed_work(priv->workqueue,
1993 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1996 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1998 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1999 thermal_periodic.work);
2001 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2004 mutex_lock(&priv->mutex);
2005 iwl3945_reg_txpower_periodic(priv);
2006 mutex_unlock(&priv->mutex);
2010 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2013 * This function is used when initializing channel-info structs.
2015 * NOTE: These channel groups do *NOT* match the bands above!
2016 * These channel groups are based on factory-tested channels;
2017 * on A-band, EEPROM's "group frequency" entries represent the top
2018 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2020 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2021 const struct iwl_channel_info *ch_info)
2023 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2024 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2026 u16 group_index = 0; /* based on factory calib frequencies */
2029 /* Find the group index for the channel ... don't use index 1(?) */
2030 if (is_channel_a_band(ch_info)) {
2031 for (group = 1; group < 5; group++) {
2032 grp_channel = ch_grp[group].group_channel;
2033 if (ch_info->channel <= grp_channel) {
2034 group_index = group;
2038 /* group 4 has a few channels *above* its factory cal freq */
2042 group_index = 0; /* 2.4 GHz, group 0 */
2044 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2050 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2052 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2053 * into radio/DSP gain settings table for requested power.
2055 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2057 s32 setting_index, s32 *new_index)
2059 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2060 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2062 s32 power = 2 * requested_power;
2064 const struct iwl3945_eeprom_txpower_sample *samples;
2069 chnl_grp = &eeprom->groups[setting_index];
2070 samples = chnl_grp->samples;
2071 for (i = 0; i < 5; i++) {
2072 if (power == samples[i].power) {
2073 *new_index = samples[i].gain_index;
2078 if (power > samples[1].power) {
2081 } else if (power > samples[2].power) {
2084 } else if (power > samples[3].power) {
2092 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2093 if (denominator == 0)
2095 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2096 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2097 res = gains0 + (gains1 - gains0) *
2098 ((s32) power - (s32) samples[index0].power) / denominator +
2100 *new_index = res >> 19;
2104 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2108 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2109 const struct iwl3945_eeprom_txpower_group *group;
2111 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2113 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2114 s8 *clip_pwrs; /* table of power levels for each rate */
2115 s8 satur_pwr; /* saturation power for each chnl group */
2116 group = &eeprom->groups[i];
2118 /* sanity check on factory saturation power value */
2119 if (group->saturation_power < 40) {
2120 IWL_WARN(priv, "Error: saturation power is %d, "
2121 "less than minimum expected 40\n",
2122 group->saturation_power);
2127 * Derive requested power levels for each rate, based on
2128 * hardware capabilities (saturation power for band).
2129 * Basic value is 3dB down from saturation, with further
2130 * power reductions for highest 3 data rates. These
2131 * backoffs provide headroom for high rate modulation
2132 * power peaks, without too much distortion (clipping).
2134 /* we'll fill in this array with h/w max power levels */
2135 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2137 /* divide factory saturation power by 2 to find -3dB level */
2138 satur_pwr = (s8) (group->saturation_power >> 1);
2140 /* fill in channel group's nominal powers for each rate */
2141 for (rate_index = 0;
2142 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2143 switch (rate_index) {
2144 case IWL_RATE_36M_INDEX_TABLE:
2145 if (i == 0) /* B/G */
2146 *clip_pwrs = satur_pwr;
2148 *clip_pwrs = satur_pwr - 5;
2150 case IWL_RATE_48M_INDEX_TABLE:
2152 *clip_pwrs = satur_pwr - 7;
2154 *clip_pwrs = satur_pwr - 10;
2156 case IWL_RATE_54M_INDEX_TABLE:
2158 *clip_pwrs = satur_pwr - 9;
2160 *clip_pwrs = satur_pwr - 12;
2163 *clip_pwrs = satur_pwr;
2171 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2173 * Second pass (during init) to set up priv->channel_info
2175 * Set up Tx-power settings in our channel info database for each VALID
2176 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2177 * and current temperature.
2179 * Since this is based on current temperature (at init time), these values may
2180 * not be valid for very long, but it gives us a starting/default point,
2181 * and allows us to active (i.e. using Tx) scan.
2183 * This does *not* write values to NIC, just sets up our internal table.
2185 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2187 struct iwl_channel_info *ch_info = NULL;
2188 struct iwl3945_channel_power_info *pwr_info;
2189 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2193 const s8 *clip_pwrs; /* array of power levels for each rate */
2196 u8 pwr_index, base_pwr_index, a_band;
2200 /* save temperature reference,
2201 * so we can determine next time to calibrate */
2202 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2203 priv->last_temperature = temperature;
2205 iwl3945_hw_reg_init_channel_groups(priv);
2207 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2208 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2210 a_band = is_channel_a_band(ch_info);
2211 if (!is_channel_valid(ch_info))
2214 /* find this channel's channel group (*not* "band") index */
2215 ch_info->group_index =
2216 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2218 /* Get this chnlgrp's rate->max/clip-powers table */
2219 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2221 /* calculate power index *adjustment* value according to
2222 * diff between current temperature and factory temperature */
2223 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2224 eeprom->groups[ch_info->group_index].
2227 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2228 ch_info->channel, delta_index, temperature +
2231 /* set tx power value for all OFDM rates */
2232 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2234 s32 uninitialized_var(power_idx);
2237 /* use channel group's clip-power table,
2238 * but don't exceed channel's max power */
2239 s8 pwr = min(ch_info->max_power_avg,
2240 clip_pwrs[rate_index]);
2242 pwr_info = &ch_info->power_info[rate_index];
2244 /* get base (i.e. at factory-measured temperature)
2245 * power table index for this rate's power */
2246 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2247 ch_info->group_index,
2250 IWL_ERR(priv, "Invalid power index\n");
2253 pwr_info->base_power_index = (u8) power_idx;
2255 /* temperature compensate */
2256 power_idx += delta_index;
2258 /* stay within range of gain table */
2259 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2261 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2262 pwr_info->requested_power = pwr;
2263 pwr_info->power_table_index = (u8) power_idx;
2264 pwr_info->tpc.tx_gain =
2265 power_gain_table[a_band][power_idx].tx_gain;
2266 pwr_info->tpc.dsp_atten =
2267 power_gain_table[a_band][power_idx].dsp_atten;
2270 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2271 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2272 power = pwr_info->requested_power +
2273 IWL_CCK_FROM_OFDM_POWER_DIFF;
2274 pwr_index = pwr_info->power_table_index +
2275 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2276 base_pwr_index = pwr_info->base_power_index +
2277 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2279 /* stay within table range */
2280 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2281 gain = power_gain_table[a_band][pwr_index].tx_gain;
2282 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2284 /* fill each CCK rate's iwl3945_channel_power_info structure
2285 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2286 * NOTE: CCK rates start at end of OFDM rates! */
2287 for (rate_index = 0;
2288 rate_index < IWL_CCK_RATES; rate_index++) {
2289 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2290 pwr_info->requested_power = power;
2291 pwr_info->power_table_index = pwr_index;
2292 pwr_info->base_power_index = base_pwr_index;
2293 pwr_info->tpc.tx_gain = gain;
2294 pwr_info->tpc.dsp_atten = dsp_atten;
2297 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2298 for (scan_tbl_index = 0;
2299 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2300 s32 actual_index = (scan_tbl_index == 0) ?
2301 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2302 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2303 actual_index, clip_pwrs, ch_info, a_band);
2310 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2313 unsigned long flags;
2315 spin_lock_irqsave(&priv->lock, flags);
2316 rc = iwl_grab_nic_access(priv);
2318 spin_unlock_irqrestore(&priv->lock, flags);
2322 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2323 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2324 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2326 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2328 iwl_release_nic_access(priv);
2329 spin_unlock_irqrestore(&priv->lock, flags);
2334 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2337 unsigned long flags;
2338 int txq_id = txq->q.id;
2340 struct iwl3945_shared *shared_data = priv->shared_virt;
2342 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2344 spin_lock_irqsave(&priv->lock, flags);
2345 rc = iwl_grab_nic_access(priv);
2347 spin_unlock_irqrestore(&priv->lock, flags);
2350 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2351 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2353 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2354 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2357 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2358 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2359 iwl_release_nic_access(priv);
2361 /* fake read to flush all prev. writes */
2362 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2363 spin_unlock_irqrestore(&priv->lock, flags);
2371 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2375 return sizeof(struct iwl3945_rxon_cmd);
2376 case POWER_TABLE_CMD:
2377 return sizeof(struct iwl3945_powertable_cmd);
2383 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2385 u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2386 memcpy(data, cmd, size);
2391 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2393 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2395 int rc, i, index, prev_index;
2396 struct iwl3945_rate_scaling_cmd rate_cmd = {
2397 .reserved = {0, 0, 0},
2399 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2401 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2402 index = iwl3945_rates[i].table_rs_index;
2404 table[index].rate_n_flags =
2405 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2406 table[index].try_cnt = priv->retry_rate;
2407 prev_index = iwl3945_get_prev_ieee_rate(i);
2408 table[index].next_rate_index =
2409 iwl3945_rates[prev_index].table_rs_index;
2412 switch (priv->band) {
2413 case IEEE80211_BAND_5GHZ:
2414 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2415 /* If one of the following CCK rates is used,
2416 * have it fall back to the 6M OFDM rate */
2417 for (i = IWL_RATE_1M_INDEX_TABLE;
2418 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2419 table[i].next_rate_index =
2420 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2422 /* Don't fall back to CCK rates */
2423 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2424 IWL_RATE_9M_INDEX_TABLE;
2426 /* Don't drop out of OFDM rates */
2427 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2428 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2431 case IEEE80211_BAND_2GHZ:
2432 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2433 /* If an OFDM rate is used, have it fall back to the
2436 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2437 iwl_is_associated(priv)) {
2439 index = IWL_FIRST_CCK_RATE;
2440 for (i = IWL_RATE_6M_INDEX_TABLE;
2441 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2442 table[i].next_rate_index =
2443 iwl3945_rates[index].table_rs_index;
2445 index = IWL_RATE_11M_INDEX_TABLE;
2446 /* CCK shouldn't fall back to OFDM... */
2447 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2456 /* Update the rate scaling for control frame Tx */
2457 rate_cmd.table_id = 0;
2458 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2463 /* Update the rate scaling for data frame Tx */
2464 rate_cmd.table_id = 1;
2465 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2469 /* Called when initializing driver */
2470 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2472 memset((void *)&priv->hw_params, 0,
2473 sizeof(struct iwl_hw_params));
2476 pci_alloc_consistent(priv->pci_dev,
2477 sizeof(struct iwl3945_shared),
2478 &priv->shared_phys);
2480 if (!priv->shared_virt) {
2481 IWL_ERR(priv, "failed to allocate pci memory\n");
2482 mutex_unlock(&priv->mutex);
2486 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2487 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2488 priv->hw_params.max_pkt_size = 2342;
2489 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2490 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2491 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2492 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2494 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2499 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2500 struct iwl3945_frame *frame, u8 rate)
2502 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2503 unsigned int frame_size;
2505 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2506 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2508 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2509 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2511 frame_size = iwl3945_fill_beacon_frame(priv,
2512 tx_beacon_cmd->frame,
2513 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2515 BUG_ON(frame_size > MAX_MPDU_SIZE);
2516 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2518 tx_beacon_cmd->tx.rate = rate;
2519 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2520 TX_CMD_FLG_TSF_MSK);
2522 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2523 tx_beacon_cmd->tx.supp_rates[0] =
2524 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2526 tx_beacon_cmd->tx.supp_rates[1] =
2527 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2529 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2532 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2534 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2535 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2538 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2540 INIT_DELAYED_WORK(&priv->thermal_periodic,
2541 iwl3945_bg_reg_txpower_periodic);
2544 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2546 cancel_delayed_work(&priv->thermal_periodic);
2549 /* check contents of special bootstrap uCode SRAM */
2550 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2552 __le32 *image = priv->ucode_boot.v_addr;
2553 u32 len = priv->ucode_boot.len;
2557 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2559 /* verify BSM SRAM contents */
2560 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2561 for (reg = BSM_SRAM_LOWER_BOUND;
2562 reg < BSM_SRAM_LOWER_BOUND + len;
2563 reg += sizeof(u32), image++) {
2564 val = iwl_read_prph(priv, reg);
2565 if (val != le32_to_cpu(*image)) {
2566 IWL_ERR(priv, "BSM uCode verification failed at "
2567 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2568 BSM_SRAM_LOWER_BOUND,
2569 reg - BSM_SRAM_LOWER_BOUND, len,
2570 val, le32_to_cpu(*image));
2575 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2581 /******************************************************************************
2583 * EEPROM related functions
2585 ******************************************************************************/
2588 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2589 * embedded controller) as EEPROM reader; each read is a series of pulses
2590 * to/from the EEPROM chip, not a single event, so even reads could conflict
2591 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2592 * simply claims ownership, which should be safe when this function is called
2593 * (i.e. before loading uCode!).
2595 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2597 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2602 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2608 * iwl3945_load_bsm - Load bootstrap instructions
2612 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2613 * in special SRAM that does not power down during RFKILL. When powering back
2614 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2615 * the bootstrap program into the on-board processor, and starts it.
2617 * The bootstrap program loads (via DMA) instructions and data for a new
2618 * program from host DRAM locations indicated by the host driver in the
2619 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2622 * When initializing the NIC, the host driver points the BSM to the
2623 * "initialize" uCode image. This uCode sets up some internal data, then
2624 * notifies host via "initialize alive" that it is complete.
2626 * The host then replaces the BSM_DRAM_* pointer values to point to the
2627 * normal runtime uCode instructions and a backup uCode data cache buffer
2628 * (filled initially with starting data values for the on-board processor),
2629 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2630 * which begins normal operation.
2632 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2633 * the backup data cache in DRAM before SRAM is powered down.
2635 * When powering back up, the BSM loads the bootstrap program. This reloads
2636 * the runtime uCode instructions and the backup data cache into SRAM,
2637 * and re-launches the runtime uCode from where it left off.
2639 static int iwl3945_load_bsm(struct iwl_priv *priv)
2641 __le32 *image = priv->ucode_boot.v_addr;
2642 u32 len = priv->ucode_boot.len;
2652 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2654 /* make sure bootstrap program is no larger than BSM's SRAM size */
2655 if (len > IWL39_MAX_BSM_SIZE)
2658 /* Tell bootstrap uCode where to find the "Initialize" uCode
2659 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2660 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2661 * after the "initialize" uCode has run, to point to
2662 * runtime/protocol instructions and backup data cache. */
2663 pinst = priv->ucode_init.p_addr;
2664 pdata = priv->ucode_init_data.p_addr;
2665 inst_len = priv->ucode_init.len;
2666 data_len = priv->ucode_init_data.len;
2668 rc = iwl_grab_nic_access(priv);
2672 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2673 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2674 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2675 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2677 /* Fill BSM memory with bootstrap instructions */
2678 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2679 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2680 reg_offset += sizeof(u32), image++)
2681 _iwl_write_prph(priv, reg_offset,
2682 le32_to_cpu(*image));
2684 rc = iwl3945_verify_bsm(priv);
2686 iwl_release_nic_access(priv);
2690 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2691 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2692 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2693 IWL39_RTC_INST_LOWER_BOUND);
2694 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2696 /* Load bootstrap code into instruction SRAM now,
2697 * to prepare to load "initialize" uCode */
2698 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2699 BSM_WR_CTRL_REG_BIT_START);
2701 /* Wait for load of bootstrap uCode to finish */
2702 for (i = 0; i < 100; i++) {
2703 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2704 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2709 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2711 IWL_ERR(priv, "BSM write did not complete!\n");
2715 /* Enable future boot loads whenever power management unit triggers it
2716 * (e.g. when powering back up after power-save shutdown) */
2717 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2718 BSM_WR_CTRL_REG_BIT_START_EN);
2720 iwl_release_nic_access(priv);
2725 static struct iwl_lib_ops iwl3945_lib = {
2726 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2727 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2728 .txq_init = iwl3945_hw_tx_queue_init,
2729 .load_ucode = iwl3945_load_bsm,
2731 .init = iwl3945_apm_init,
2732 .reset = iwl3945_apm_reset,
2733 .stop = iwl3945_apm_stop,
2734 .config = iwl3945_nic_config,
2735 .set_pwr_src = iwl3945_set_pwr_src,
2738 .regulatory_bands = {
2739 EEPROM_REGULATORY_BAND_1_CHANNELS,
2740 EEPROM_REGULATORY_BAND_2_CHANNELS,
2741 EEPROM_REGULATORY_BAND_3_CHANNELS,
2742 EEPROM_REGULATORY_BAND_4_CHANNELS,
2743 EEPROM_REGULATORY_BAND_5_CHANNELS,
2744 IWL3945_EEPROM_IMG_SIZE,
2745 IWL3945_EEPROM_IMG_SIZE,
2747 .verify_signature = iwlcore_eeprom_verify_signature,
2748 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2749 .release_semaphore = iwl3945_eeprom_release_semaphore,
2750 .query_addr = iwlcore_eeprom_query_addr,
2752 .send_tx_power = iwl3945_send_tx_power,
2755 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2756 .get_hcmd_size = iwl3945_get_hcmd_size,
2757 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2760 static struct iwl_ops iwl3945_ops = {
2761 .lib = &iwl3945_lib,
2762 .utils = &iwl3945_hcmd_utils,
2765 static struct iwl_cfg iwl3945_bg_cfg = {
2767 .fw_name_pre = IWL3945_FW_PRE,
2768 .ucode_api_max = IWL3945_UCODE_API_MAX,
2769 .ucode_api_min = IWL3945_UCODE_API_MIN,
2771 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2772 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2773 .ops = &iwl3945_ops,
2774 .mod_params = &iwl3945_mod_params
2777 static struct iwl_cfg iwl3945_abg_cfg = {
2779 .fw_name_pre = IWL3945_FW_PRE,
2780 .ucode_api_max = IWL3945_UCODE_API_MAX,
2781 .ucode_api_min = IWL3945_UCODE_API_MIN,
2782 .sku = IWL_SKU_A|IWL_SKU_G,
2783 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2784 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2785 .ops = &iwl3945_ops,
2786 .mod_params = &iwl3945_mod_params
2789 struct pci_device_id iwl3945_hw_card_ids[] = {
2790 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2791 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2792 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2793 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2794 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2795 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2799 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);