SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 /*
 226  * Upload the N-PHY tables.
 227  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 228  */
 229 static void b43_nphy_tables_init(struct b43_wldev *dev)
 230 {
 231         if (dev->phy.rev < 3)
 232                 b43_nphy_rev0_1_2_tables_init(dev);
 233         else
 234                 b43_nphy_rev3plus_tables_init(dev);
 235 }
 236
 237 static void b43_nphy_workarounds(struct b43_wldev *dev)
 238 {
 239         struct b43_phy *phy = &dev->phy;
 240         unsigned int i;
 241
 242         b43_phy_set(dev, B43_NPHY_IQFLIP,
 243                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 244         if (1 /* FIXME band is 2.4GHz */) {
 245                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 246                             B43_NPHY_CLASSCTL_CCKEN);
 247         } else {
 248                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 249                              ~B43_NPHY_CLASSCTL_CCKEN);
 250         }
 251         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 252         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 253
 254         /* Fixup some tables */
 255         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 256         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 257         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 258         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 259         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 260         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 265
 266         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 267         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 268         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 269         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 270
 271         //TODO set RF sequence
 272
 273         /* Set narrowband clip threshold */
 274         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 275         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 276
 277         /* Set wideband clip 2 threshold */
 278         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 279                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 280                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 281         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 282                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 283                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 284
 285         /* Set Clip 2 detect */
 286         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 287                     B43_NPHY_C1_CGAINI_CL2DETECT);
 288         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 289                     B43_NPHY_C2_CGAINI_CL2DETECT);
 290
 291         if (0 /*FIXME*/) {
 292                 /* Set dwell lengths */
 293                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 294                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 295                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 296                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 297
 298                 /* Set gain backoff */
 299                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 300                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 301                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 302                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 303                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 304                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 305
 306                 /* Set HPVGA2 index */
 307                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 308                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 309                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 310                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 311                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 312                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 313
 314                 //FIXME verify that the specs really mean to use autoinc here.
 315                 for (i = 0; i < 3; i++)
 316                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 317         }
 318
 319         /* Set minimum gain value */
 320         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 321                         ~B43_NPHY_C1_MINGAIN,
 322                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 323         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 324                         ~B43_NPHY_C2_MINGAIN,
 325                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 326
 327         if (phy->rev < 2) {
 328                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 329                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 330         }
 331
 332         /* Set phase track alpha and beta */
 333         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 334         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 335         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 336         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 337         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 338         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 342 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 343 {
 344         struct b43_phy_n *nphy = dev->phy.n;
 345         enum ieee80211_band band;
 346         u16 tmp;
 347
 348         if (!enable) {
 349                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 350                                                        B43_NPHY_RFCTL_INTC1);
 351                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 352                                                        B43_NPHY_RFCTL_INTC2);
 353                 band = b43_current_band(dev->wl);
 354                 if (dev->phy.rev >= 3) {
 355                         if (band == IEEE80211_BAND_5GHZ)
 356                                 tmp = 0x600;
 357                         else
 358                                 tmp = 0x480;
 359                 } else {
 360                         if (band == IEEE80211_BAND_5GHZ)
 361                                 tmp = 0x180;
 362                         else
 363                                 tmp = 0x120;
 364                 }
 365                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 366                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 367         } else {
 368                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 369                                 nphy->rfctrl_intc1_save);
 370                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 371                                 nphy->rfctrl_intc2_save);
 372         }
 373 }
 374
 375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 376 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 377 {
 378         struct b43_phy_n *nphy = dev->phy.n;
 379         u16 tmp;
 380         enum ieee80211_band band = b43_current_band(dev->wl);
 381         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 382                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 383
 384         if (dev->phy.rev >= 3) {
 385                 if (ipa) {
 386                         tmp = 4;
 387                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 388                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 389                 }
 390
 391                 tmp = 1;
 392                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 393                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 394         }
 395 }
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 398 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 399 {
 400         u32 tmslow;
 401
 402         if (dev->phy.type != B43_PHYTYPE_N)
 403                 return;
 404
 405         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 406         if (force)
 407                 tmslow |= SSB_TMSLOW_FGC;
 408         else
 409                 tmslow &= ~SSB_TMSLOW_FGC;
 410         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 411 }
 412
 413 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 414 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 415 {
 416         u16 bbcfg;
 417
 418         b43_nphy_bmac_clock_fgc(dev, 1);
 419         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 420         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 421         udelay(1);
 422         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 423         b43_nphy_bmac_clock_fgc(dev, 0);
 424         /* TODO: N PHY Force RF Seq with argument 2 */
 425 }
 426
 427 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 428 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 429                                 u16 samps, u8 time, bool wait)
 430 {
 431         int i;
 432         u16 tmp;
 433
 434         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 435         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 436         if (wait)
 437                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 438         else
 439                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 440
 441         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 442
 443         for (i = 1000; i; i--) {
 444                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 445                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 446                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 447                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 448                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 449                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 450                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 451                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 452
 453                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 454                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 455                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 456                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 457                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 458                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 459                         return;
 460                 }
 461                 udelay(10);
 462         }
 463         memset(est, 0, sizeof(*est));
 464 }
 465
 466 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 467 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 468                                         struct b43_phy_n_iq_comp *pcomp)
 469 {
 470         if (write) {
 471                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 472                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 473                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 474                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 475         } else {
 476                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 477                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 478                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 479                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 480         }
 481 }
 482
 483 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 484 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 485 {
 486         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 487
 488         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 489         if (core == 0) {
 490                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 491                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 492         } else {
 493                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 494                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 495         }
 496         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 497         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 498         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 499         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 500         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 501         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 502         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 503         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 504 }
 505
 506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 507 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 508 {
 509         u8 rxval, txval;
 510         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 511
 512         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 513         if (core == 0) {
 514                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 515                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 516         } else {
 517                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 518                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 519         }
 520         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 521         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 522         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 523         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 524         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 525         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 526         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 527         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 528
 529         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 530         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 531
 532         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 533                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 534         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 535                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 536         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 537                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 538         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 539                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 540
 541         if (core == 0) {
 542                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 543                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 544         } else {
 545                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 546                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 547         }
 548
 549         /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
 550         /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
 551         /* TODO: Call N PHY RF Seq with 0 as argument */
 552
 553         if (core == 0) {
 554                 rxval = 1;
 555                 txval = 8;
 556         } else {
 557                 rxval = 4;
 558                 txval = 2;
 559         }
 560
 561         /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
 562         /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
 563 }
 564
 565 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 566 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 567 {
 568         int i;
 569         s32 iq;
 570         u32 ii;
 571         u32 qq;
 572         int iq_nbits, qq_nbits;
 573         int arsh, brsh;
 574         u16 tmp, a, b;
 575
 576         struct nphy_iq_est est;
 577         struct b43_phy_n_iq_comp old;
 578         struct b43_phy_n_iq_comp new = { };
 579         bool error = false;
 580
 581         if (mask == 0)
 582                 return;
 583
 584         b43_nphy_rx_iq_coeffs(dev, false, &old);
 585         b43_nphy_rx_iq_coeffs(dev, true, &new);
 586         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 587         new = old;
 588
 589         for (i = 0; i < 2; i++) {
 590                 if (i == 0 && (mask & 1)) {
 591                         iq = est.iq0_prod;
 592                         ii = est.i0_pwr;
 593                         qq = est.q0_pwr;
 594                 } else if (i == 1 && (mask & 2)) {
 595                         iq = est.iq1_prod;
 596                         ii = est.i1_pwr;
 597                         qq = est.q1_pwr;
 598                 } else {
 599                         B43_WARN_ON(1);
 600                         continue;
 601                 }
 602
 603                 if (ii + qq < 2) {
 604                         error = true;
 605                         break;
 606                 }
 607
 608                 iq_nbits = fls(abs(iq));
 609                 qq_nbits = fls(qq);
 610
 611                 arsh = iq_nbits - 20;
 612                 if (arsh >= 0) {
 613                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 614                         tmp = ii >> arsh;
 615                 } else {
 616                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 617                         tmp = ii << -arsh;
 618                 }
 619                 if (tmp == 0) {
 620                         error = true;
 621                         break;
 622                 }
 623                 a /= tmp;
 624
 625                 brsh = qq_nbits - 11;
 626                 if (brsh >= 0) {
 627                         b = (qq << (31 - qq_nbits));
 628                         tmp = ii >> brsh;
 629                 } else {
 630                         b = (qq << (31 - qq_nbits));
 631                         tmp = ii << -brsh;
 632                 }
 633                 if (tmp == 0) {
 634                         error = true;
 635                         break;
 636                 }
 637                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 638
 639                 if (i == 0 && (mask & 0x1)) {
 640                         if (dev->phy.rev >= 3) {
 641                                 new.a0 = a & 0x3FF;
 642                                 new.b0 = b & 0x3FF;
 643                         } else {
 644                                 new.a0 = b & 0x3FF;
 645                                 new.b0 = a & 0x3FF;
 646                         }
 647                 } else if (i == 1 && (mask & 0x2)) {
 648                         if (dev->phy.rev >= 3) {
 649                                 new.a1 = a & 0x3FF;
 650                                 new.b1 = b & 0x3FF;
 651                         } else {
 652                                 new.a1 = b & 0x3FF;
 653                                 new.b1 = a & 0x3FF;
 654                         }
 655                 }
 656         }
 657
 658         if (error)
 659                 new = old;
 660
 661         b43_nphy_rx_iq_coeffs(dev, true, &new);
 662 }
 663
 664 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 665 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 666 {
 667         u16 array[4];
 668         int i;
 669
 670         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 671         for (i = 0; i < 4; i++)
 672                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 673
 674         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 675         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 676         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 677         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 678 }
 679
 680 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 681 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 682 {
 683         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 684         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 685 }
 686
 687 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 688 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 689 {
 690         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 691         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 692 }
 693
 694 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 695 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 696 {
 697         u16 tmp;
 698
 699         if (dev->dev->id.revision == 16)
 700                 b43_mac_suspend(dev);
 701
 702         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 703         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 704                 B43_NPHY_CLASSCTL_WAITEDEN);
 705         tmp &= ~mask;
 706         tmp |= (val & mask);
 707         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 708
 709         if (dev->dev->id.revision == 16)
 710                 b43_mac_enable(dev);
 711
 712         return tmp;
 713 }
 714
 715 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 716 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 717 {
 718         struct b43_phy *phy = &dev->phy;
 719         struct b43_phy_n *nphy = phy->n;
 720
 721         if (enable) {
 722                 u16 clip[] = { 0xFFFF, 0xFFFF };
 723                 if (nphy->deaf_count++ == 0) {
 724                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 725                         b43_nphy_classifier(dev, 0x7, 0);
 726                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 727                         b43_nphy_write_clip_detection(dev, clip);
 728                 }
 729                 b43_nphy_reset_cca(dev);
 730         } else {
 731                 if (--nphy->deaf_count == 0) {
 732                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 733                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 734                 }
 735         }
 736 }
 737
 738 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
 739 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
 740 {
 741         struct b43_phy_n *nphy = dev->phy.n;
 742         int i, j;
 743         u32 tmp;
 744         u32 cur_real, cur_imag, real_part, imag_part;
 745
 746         u16 buffer[7];
 747
 748         if (nphy->hang_avoid)
 749                 b43_nphy_stay_in_carrier_search(dev, true);
 750
 751         /* TODO: Read an N PHY Table with ID 15, length 7, offset 80,
 752                 width 16, and data pointer buffer */
 753
 754         for (i = 0; i < 2; i++) {
 755                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
 756                         (buffer[i * 2 + 1] & 0x3FF);
 757                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 758                                 (((i + 26) << 10) | 320));
 759                 for (j = 0; j < 128; j++) {
 760                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 761                                         ((tmp >> 16) & 0xFFFF));
 762                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 763                                         (tmp & 0xFFFF));
 764                 }
 765         }
 766
 767         for (i = 0; i < 2; i++) {
 768                 tmp = buffer[5 + i];
 769                 real_part = (tmp >> 8) & 0xFF;
 770                 imag_part = (tmp & 0xFF);
 771                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 772                                 (((i + 26) << 10) | 448));
 773
 774                 if (dev->phy.rev >= 3) {
 775                         cur_real = real_part;
 776                         cur_imag = imag_part;
 777                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
 778                 }
 779
 780                 for (j = 0; j < 128; j++) {
 781                         if (dev->phy.rev < 3) {
 782                                 cur_real = (real_part * loscale[j] + 128) >> 8;
 783                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
 784                                 tmp = ((cur_real & 0xFF) << 8) |
 785                                         (cur_imag & 0xFF);
 786                         }
 787                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 788                                         ((tmp >> 16) & 0xFFFF));
 789                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 790                                         (tmp & 0xFFFF));
 791                 }
 792         }
 793
 794         if (dev->phy.rev >= 3) {
 795                 b43_shm_write16(dev, B43_SHM_SHARED,
 796                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
 797                 b43_shm_write16(dev, B43_SHM_SHARED,
 798                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
 799         }
 800
 801         if (nphy->hang_avoid)
 802                 b43_nphy_stay_in_carrier_search(dev, false);
 803 }
 804
 805 enum b43_nphy_rf_sequence {
 806         B43_RFSEQ_RX2TX,
 807         B43_RFSEQ_TX2RX,
 808         B43_RFSEQ_RESET2RX,
 809         B43_RFSEQ_UPDATE_GAINH,
 810         B43_RFSEQ_UPDATE_GAINL,
 811         B43_RFSEQ_UPDATE_GAINU,
 812 };
 813
 814 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 815                                        enum b43_nphy_rf_sequence seq)
 816 {
 817         static const u16 trigger[] = {
 818                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 819                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 820                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 821                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 822                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 823                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 824         };
 825         int i;
 826
 827         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 828
 829         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 830                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 831         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 832         for (i = 0; i < 200; i++) {
 833                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 834                         goto ok;
 835                 msleep(1);
 836         }
 837         b43err(dev->wl, "RF sequence status timeout\n");
 838 ok:
 839         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 840                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 841 }
 842
 843 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 844 {
 845         unsigned int i;
 846         u16 val;
 847
 848         val = 0x1E1F;
 849         for (i = 0; i < 14; i++) {
 850                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 851                 val -= 0x202;
 852         }
 853         val = 0x3E3F;
 854         for (i = 0; i < 16; i++) {
 855                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 856                 val -= 0x202;
 857         }
 858         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 859 }
 860
 861 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 862 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 863                                        s8 offset, u8 core, u8 rail, u8 type)
 864 {
 865         u16 tmp;
 866         bool core1or5 = (core == 1) || (core == 5);
 867         bool core2or5 = (core == 2) || (core == 5);
 868
 869         offset = clamp_val(offset, -32, 31);
 870         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 871
 872         if (core1or5 && (rail == 0) && (type == 2))
 873                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 874         if (core1or5 && (rail == 1) && (type == 2))
 875                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 876         if (core2or5 && (rail == 0) && (type == 2))
 877                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 878         if (core2or5 && (rail == 1) && (type == 2))
 879                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 880         if (core1or5 && (rail == 0) && (type == 0))
 881                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 882         if (core1or5 && (rail == 1) && (type == 0))
 883                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 884         if (core2or5 && (rail == 0) && (type == 0))
 885                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 886         if (core2or5 && (rail == 1) && (type == 0))
 887                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 888         if (core1or5 && (rail == 0) && (type == 1))
 889                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 890         if (core1or5 && (rail == 1) && (type == 1))
 891                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 892         if (core2or5 && (rail == 0) && (type == 1))
 893                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 894         if (core2or5 && (rail == 1) && (type == 1))
 895                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 896         if (core1or5 && (rail == 0) && (type == 6))
 897                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 898         if (core1or5 && (rail == 1) && (type == 6))
 899                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 900         if (core2or5 && (rail == 0) && (type == 6))
 901                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 902         if (core2or5 && (rail == 1) && (type == 6))
 903                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 904         if (core1or5 && (rail == 0) && (type == 3))
 905                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 906         if (core1or5 && (rail == 1) && (type == 3))
 907                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 908         if (core2or5 && (rail == 0) && (type == 3))
 909                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 910         if (core2or5 && (rail == 1) && (type == 3))
 911                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 912         if (core1or5 && (type == 4))
 913                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 914         if (core2or5 && (type == 4))
 915                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 916         if (core1or5 && (type == 5))
 917                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 918         if (core2or5 && (type == 5))
 919                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 920 }
 921
 922 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
 923 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 924 {
 925         u16 val;
 926
 927         if (dev->phy.rev >= 3) {
 928                 /* TODO */
 929         } else {
 930                 if (type < 3)
 931                         val = 0;
 932                 else if (type == 6)
 933                         val = 1;
 934                 else if (type == 3)
 935                         val = 2;
 936                 else
 937                         val = 3;
 938
 939                 val = (val << 12) | (val << 14);
 940                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
 941                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
 942
 943                 if (type < 3) {
 944                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
 945                                         (type + 1) << 4);
 946                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
 947                                         (type + 1) << 4);
 948                 }
 949
 950                 /* TODO use some definitions */
 951                 if (code == 0) {
 952                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
 953                         if (type < 3) {
 954                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 955                                                 0xFEC7, 0);
 956                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 957                                                 0xEFDC, 0);
 958                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 959                                                 0xFFFE, 0);
 960                                 udelay(20);
 961                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 962                                                 0xFFFE, 0);
 963                         }
 964                 } else {
 965                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
 966                                         0x3000);
 967                         if (type < 3) {
 968                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 969                                                 0xFEC7, 0x0180);
 970                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 971                                                 0xEFDC, (code << 1 | 0x1021));
 972                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 973                                                 0xFFFE, 0x0001);
 974                                 udelay(20);
 975                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 976                                                 0xFFFE, 0);
 977                         }
 978                 }
 979         }
 980 }
 981
 982 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
 983 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
 984 {
 985         int i;
 986         for (i = 0; i < 2; i++) {
 987                 if (type == 2) {
 988                         if (i == 0) {
 989                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
 990                                                   0xFC, buf[0]);
 991                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
 992                                                   0xFC, buf[1]);
 993                         } else {
 994                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
 995                                                   0xFC, buf[2 * i]);
 996                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
 997                                                   0xFC, buf[2 * i + 1]);
 998                         }
 999                 } else {
1000                         if (i == 0)
1001                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1002                                                   0xF3, buf[0] << 2);
1003                         else
1004                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1005                                                   0xF3, buf[2 * i + 1] << 2);
1006                 }
1007         }
1008 }
1009
1010 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1011 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1012                                 u8 nsamp)
1013 {
1014         int i;
1015         int out;
1016         u16 save_regs_phy[9];
1017         u16 s[2];
1018
1019         if (dev->phy.rev >= 3) {
1020                 save_regs_phy[0] = b43_phy_read(dev,
1021                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1022                 save_regs_phy[1] = b43_phy_read(dev,
1023                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1024                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1025                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1026                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1027                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1028                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1029                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1030         }
1031
1032         b43_nphy_rssi_select(dev, 5, type);
1033
1034         if (dev->phy.rev < 2) {
1035                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1036                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1037         }
1038
1039         for (i = 0; i < 4; i++)
1040                 buf[i] = 0;
1041
1042         for (i = 0; i < nsamp; i++) {
1043                 if (dev->phy.rev < 2) {
1044                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1045                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1046                 } else {
1047                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1048                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1049                 }
1050
1051                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1052                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1053                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1054                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1055         }
1056         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1057                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1058
1059         if (dev->phy.rev < 2)
1060                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1061
1062         if (dev->phy.rev >= 3) {
1063                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1064                                 save_regs_phy[0]);
1065                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1066                                 save_regs_phy[1]);
1067                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1068                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1069                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1070                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1071                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1072                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1073         }
1074
1075         return out;
1076 }
1077
1078 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1079 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1080 {
1081         int i, j;
1082         u8 state[4];
1083         u8 code, val;
1084         u16 class, override;
1085         u8 regs_save_radio[2];
1086         u16 regs_save_phy[2];
1087         s8 offset[4];
1088
1089         u16 clip_state[2];
1090         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1091         s32 results_min[4] = { };
1092         u8 vcm_final[4] = { };
1093         s32 results[4][4] = { };
1094         s32 miniq[4][2] = { };
1095
1096         if (type == 2) {
1097                 code = 0;
1098                 val = 6;
1099         } else if (type < 2) {
1100                 code = 25;
1101                 val = 4;
1102         } else {
1103                 B43_WARN_ON(1);
1104                 return;
1105         }
1106
1107         class = b43_nphy_classifier(dev, 0, 0);
1108         b43_nphy_classifier(dev, 7, 4);
1109         b43_nphy_read_clip_detection(dev, clip_state);
1110         b43_nphy_write_clip_detection(dev, clip_off);
1111
1112         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1113                 override = 0x140;
1114         else
1115                 override = 0x110;
1116
1117         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1118         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1119         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1120         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1121
1122         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1123         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1124         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1125         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1126
1127         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1128         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1129         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1130         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1131         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1132         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1133
1134         b43_nphy_rssi_select(dev, 5, type);
1135         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1136         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1137
1138         for (i = 0; i < 4; i++) {
1139                 u8 tmp[4];
1140                 for (j = 0; j < 4; j++)
1141                         tmp[j] = i;
1142                 if (type != 1)
1143                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1144                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1145                 if (type < 2)
1146                         for (j = 0; j < 2; j++)
1147                                 miniq[i][j] = min(results[i][2 * j],
1148                                                 results[i][2 * j + 1]);
1149         }
1150
1151         for (i = 0; i < 4; i++) {
1152                 s32 mind = 40;
1153                 u8 minvcm = 0;
1154                 s32 minpoll = 249;
1155                 s32 curr;
1156                 for (j = 0; j < 4; j++) {
1157                         if (type == 2)
1158                                 curr = abs(results[j][i]);
1159                         else
1160                                 curr = abs(miniq[j][i / 2] - code * 8);
1161
1162                         if (curr < mind) {
1163                                 mind = curr;
1164                                 minvcm = j;
1165                         }
1166
1167                         if (results[j][i] < minpoll)
1168                                 minpoll = results[j][i];
1169                 }
1170                 results_min[i] = minpoll;
1171                 vcm_final[i] = minvcm;
1172         }
1173
1174         if (type != 1)
1175                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1176
1177         for (i = 0; i < 4; i++) {
1178                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1179
1180                 if (offset[i] < 0)
1181                         offset[i] = -((abs(offset[i]) + 4) / 8);
1182                 else
1183                         offset[i] = (offset[i] + 4) / 8;
1184
1185                 if (results_min[i] == 248)
1186                         offset[i] = code - 32;
1187
1188                 if (i % 2 == 0)
1189                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1190                                                         type);
1191                 else
1192                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1193                                                         type);
1194         }
1195
1196         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1197         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1198
1199         switch (state[2]) {
1200         case 1:
1201                 b43_nphy_rssi_select(dev, 1, 2);
1202                 break;
1203         case 4:
1204                 b43_nphy_rssi_select(dev, 1, 0);
1205                 break;
1206         case 2:
1207                 b43_nphy_rssi_select(dev, 1, 1);
1208                 break;
1209         default:
1210                 b43_nphy_rssi_select(dev, 1, 1);
1211                 break;
1212         }
1213
1214         switch (state[3]) {
1215         case 1:
1216                 b43_nphy_rssi_select(dev, 2, 2);
1217                 break;
1218         case 4:
1219                 b43_nphy_rssi_select(dev, 2, 0);
1220                 break;
1221         default:
1222                 b43_nphy_rssi_select(dev, 2, 1);
1223                 break;
1224         }
1225
1226         b43_nphy_rssi_select(dev, 0, type);
1227
1228         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1229         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1230         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1231         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1232
1233         b43_nphy_classifier(dev, 7, class);
1234         b43_nphy_write_clip_detection(dev, clip_state);
1235 }
1236
1237 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1238 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1239 {
1240         /* TODO */
1241 }
1242
1243 /*
1244  * RSSI Calibration
1245  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1246  */
1247 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1248 {
1249         if (dev->phy.rev >= 3) {
1250                 b43_nphy_rev3_rssi_cal(dev);
1251         } else {
1252                 b43_nphy_rev2_rssi_cal(dev, 2);
1253                 b43_nphy_rev2_rssi_cal(dev, 0);
1254                 b43_nphy_rev2_rssi_cal(dev, 1);
1255         }
1256 }
1257
1258 /*
1259  * Restore RSSI Calibration
1260  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1261  */
1262 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1263 {
1264         struct b43_phy_n *nphy = dev->phy.n;
1265
1266         u16 *rssical_radio_regs = NULL;
1267         u16 *rssical_phy_regs = NULL;
1268
1269         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1270                 if (!nphy->rssical_chanspec_2G)
1271                         return;
1272                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1273                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1274         } else {
1275                 if (!nphy->rssical_chanspec_5G)
1276                         return;
1277                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1278                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1279         }
1280
1281         /* TODO use some definitions */
1282         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1283         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1284
1285         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1286         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1287         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1288         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1289
1290         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1291         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1292         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1293         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1294
1295         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1296         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1297         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1298         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1299 }
1300
1301 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1302 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1303 {
1304         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1305                 if (dev->phy.rev >= 6) {
1306                         /* TODO If the chip is 47162
1307                                 return txpwrctrl_tx_gain_ipa_rev5 */
1308                         return txpwrctrl_tx_gain_ipa_rev6;
1309                 } else if (dev->phy.rev >= 5) {
1310                         return txpwrctrl_tx_gain_ipa_rev5;
1311                 } else {
1312                         return txpwrctrl_tx_gain_ipa;
1313                 }
1314         } else {
1315                 return txpwrctrl_tx_gain_ipa_5g;
1316         }
1317 }
1318
1319 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1320 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1321 {
1322         struct b43_phy_n *nphy = dev->phy.n;
1323         u16 *save = nphy->tx_rx_cal_radio_saveregs;
1324
1325         if (dev->phy.rev >= 3) {
1326                 /* TODO */
1327         } else {
1328                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1329                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1330
1331                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1332                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1333
1334                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1335                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1336
1337                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1338                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1339
1340                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1341                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1342
1343                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1344                     B43_NPHY_BANDCTL_5GHZ)) {
1345                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1346                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1347                 } else {
1348                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1349                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1350                 }
1351
1352                 if (dev->phy.rev < 2) {
1353                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1354                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1355                 } else {
1356                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1357                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1358                 }
1359         }
1360 }
1361
1362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1363 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1364                                         struct nphy_txgains target,
1365                                         struct nphy_iqcal_params *params)
1366 {
1367         int i, j, indx;
1368         u16 gain;
1369
1370         if (dev->phy.rev >= 3) {
1371                 params->txgm = target.txgm[core];
1372                 params->pga = target.pga[core];
1373                 params->pad = target.pad[core];
1374                 params->ipa = target.ipa[core];
1375                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1376                                         (params->pad << 4) | (params->ipa);
1377                 for (j = 0; j < 5; j++)
1378                         params->ncorr[j] = 0x79;
1379         } else {
1380                 gain = (target.pad[core]) | (target.pga[core] << 4) |
1381                         (target.txgm[core] << 8);
1382
1383                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1384                         1 : 0;
1385                 for (i = 0; i < 9; i++)
1386                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
1387                                 break;
1388                 i = min(i, 8);
1389
1390                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1391                 params->pga = tbl_iqcal_gainparams[indx][i][2];
1392                 params->pad = tbl_iqcal_gainparams[indx][i][3];
1393                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1394                                         (params->pad << 2);
1395                 for (j = 0; j < 4; j++)
1396                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1397         }
1398 }
1399
1400 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1401 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1402 {
1403         struct b43_phy_n *nphy = dev->phy.n;
1404         int i;
1405         u16 scale, entry;
1406
1407         u16 tmp = nphy->txcal_bbmult;
1408         if (core == 0)
1409                 tmp >>= 8;
1410         tmp &= 0xff;
1411
1412         for (i = 0; i < 18; i++) {
1413                 scale = (ladder_lo[i].percent * tmp) / 100;
1414                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
1415                 /* TODO: Write an N PHY Table with ID 15, length 1,
1416                         offset i, width 16, and data entry */
1417
1418                 scale = (ladder_iq[i].percent * tmp) / 100;
1419                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
1420                 /* TODO: Write an N PHY Table with ID 15, length 1,
1421                         offset i + 32, width 16, and data entry */
1422         }
1423 }
1424
1425 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1426 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1427 {
1428         struct b43_phy_n *nphy = dev->phy.n;
1429
1430         u16 curr_gain[2];
1431         struct nphy_txgains target;
1432         const u32 *table = NULL;
1433
1434         if (nphy->txpwrctrl == 0) {
1435                 int i;
1436
1437                 if (nphy->hang_avoid)
1438                         b43_nphy_stay_in_carrier_search(dev, true);
1439                 /* TODO: Read an N PHY Table with ID 7, length 2,
1440                         offset 0x110, width 16, and curr_gain */
1441                 if (nphy->hang_avoid)
1442                         b43_nphy_stay_in_carrier_search(dev, false);
1443
1444                 for (i = 0; i < 2; ++i) {
1445                         if (dev->phy.rev >= 3) {
1446                                 target.ipa[i] = curr_gain[i] & 0x000F;
1447                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1448                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1449                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1450                         } else {
1451                                 target.ipa[i] = curr_gain[i] & 0x0003;
1452                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1453                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1454                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1455                         }
1456                 }
1457         } else {
1458                 int i;
1459                 u16 index[2];
1460                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1461                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1462                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1463                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1464                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1465                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1466
1467                 for (i = 0; i < 2; ++i) {
1468                         if (dev->phy.rev >= 3) {
1469                                 enum ieee80211_band band =
1470                                         b43_current_band(dev->wl);
1471
1472                                 if ((nphy->ipa2g_on &&
1473                                      band == IEEE80211_BAND_2GHZ) ||
1474                                     (nphy->ipa5g_on &&
1475                                      band == IEEE80211_BAND_5GHZ)) {
1476                                         table = b43_nphy_get_ipa_gain_table(dev);
1477                                 } else {
1478                                         if (band == IEEE80211_BAND_5GHZ) {
1479                                                 if (dev->phy.rev == 3)
1480                                                         table = b43_ntab_tx_gain_rev3_5ghz;
1481                                                 else if (dev->phy.rev == 4)
1482                                                         table = b43_ntab_tx_gain_rev4_5ghz;
1483                                                 else
1484                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
1485                                         } else {
1486                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
1487                                         }
1488                                 }
1489
1490                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1491                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1492                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1493                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1494                         } else {
1495                                 table = b43_ntab_tx_gain_rev0_1_2;
1496
1497                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1498                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1499                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1500                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1501                         }
1502                 }
1503         }
1504
1505         return target;
1506 }
1507
1508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1509 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1510 {
1511         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1512
1513         if (dev->phy.rev >= 3) {
1514                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1515                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1516                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1517                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1518                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
1519                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1520                         width 16, and data from regs[5] */
1521                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1522                         width 16, and data from regs[6] */
1523                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1524                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1525                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1526                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1527                 b43_nphy_reset_cca(dev);
1528         } else {
1529                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1530                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1531                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1532                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1533                         width 16, and data from regs[3] */
1534                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1535                         width 16, and data from regs[4] */
1536                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1537                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1538         }
1539 }
1540
1541 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1542 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1543 {
1544         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1545         u16 tmp;
1546
1547         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1548         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1549         if (dev->phy.rev >= 3) {
1550                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1551                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1552
1553                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1554                 regs[2] = tmp;
1555                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1556
1557                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1558                 regs[3] = tmp;
1559                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1560
1561                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
1562                 b43_phy_mask(dev, B43_NPHY_BBCFG, ~B43_NPHY_BBCFG_RSTRX);
1563
1564                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 3,
1565                         width 16, and data pointing to tmp */
1566                 regs[5] = tmp;
1567
1568                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1569                         width 16, and data 0 */
1570                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 19,
1571                         width 16, and data pointing to tmp */
1572                 regs[6] = tmp;
1573
1574                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1575                         width 16, and data 0 */
1576                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1577                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1578
1579                 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1580                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1581                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1582
1583                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1584                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1585                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1586                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1587         } else {
1588                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1589                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1590                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1591                 regs[2] = tmp;
1592                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
1593                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 2,
1594                         width 16, and data pointing to tmp */
1595                 regs[3] = tmp;
1596                 tmp |= 0x2000;
1597                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1598                         width 16, and data pointer tmp */
1599                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 18,
1600                         width 16, and data pointer tmp */
1601                 regs[4] = tmp;
1602                 tmp |= 0x2000;
1603                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1604                         width 16, and data pointer tmp */
1605                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1606                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1607                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1608                         tmp = 0x0180;
1609                 else
1610                         tmp = 0x0120;
1611                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1612                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1613         }
1614 }
1615
1616 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1617 static void b43_nphy_restore_cal(struct b43_wldev *dev)
1618 {
1619         struct b43_phy_n *nphy = dev->phy.n;
1620
1621         u16 coef[4];
1622         u16 *loft = NULL;
1623         u16 *table = NULL;
1624
1625         int i;
1626         u16 *txcal_radio_regs = NULL;
1627         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1628
1629         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1630                 if (nphy->iqcal_chanspec_2G == 0)
1631                         return;
1632                 table = nphy->cal_cache.txcal_coeffs_2G;
1633                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1634         } else {
1635                 if (nphy->iqcal_chanspec_5G == 0)
1636                         return;
1637                 table = nphy->cal_cache.txcal_coeffs_5G;
1638                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1639         }
1640
1641         /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1642                 width 16, and data from table */
1643
1644         for (i = 0; i < 4; i++) {
1645                 if (dev->phy.rev >= 3)
1646                         table[i] = coef[i];
1647                 else
1648                         coef[i] = 0;
1649         }
1650
1651         /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1652                 width 16, and data from coef */
1653         /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1654                 width 16 and data from loft */
1655         /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1656                 width 16 and data from loft */
1657
1658         if (dev->phy.rev < 2)
1659                 b43_nphy_tx_iq_workaround(dev);
1660
1661         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1662                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1663                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1664         } else {
1665                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1666                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1667         }
1668
1669         /* TODO use some definitions */
1670         if (dev->phy.rev >= 3) {
1671                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1672                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1673                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1674                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1675                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1676                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1677                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1678                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1679         } else {
1680                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1681                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1682                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1683                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1684         }
1685         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1686 }
1687
1688 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1689 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1690                                 struct nphy_txgains target,
1691                                 bool full, bool mphase)
1692 {
1693         struct b43_phy_n *nphy = dev->phy.n;
1694         int i;
1695         int error = 0;
1696         int freq;
1697         bool avoid = false;
1698         u8 length;
1699         u16 tmp, core, type, count, max, numb, last, cmd;
1700         const u16 *table;
1701         bool phy6or5x;
1702
1703         u16 buffer[11];
1704         u16 diq_start = 0;
1705         u16 save[2];
1706         u16 gain[2];
1707         struct nphy_iqcal_params params[2];
1708         bool updated[2] = { };
1709
1710         b43_nphy_stay_in_carrier_search(dev, true);
1711
1712         if (dev->phy.rev >= 4) {
1713                 avoid = nphy->hang_avoid;
1714                 nphy->hang_avoid = 0;
1715         }
1716
1717         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1718                 width 16, and data pointer save */
1719
1720         for (i = 0; i < 2; i++) {
1721                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
1722                 gain[i] = params[i].cal_gain;
1723         }
1724         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1725                 width 16, and data pointer gain */
1726
1727         b43_nphy_tx_cal_radio_setup(dev);
1728         b43_nphy_tx_cal_phy_setup(dev);
1729
1730         phy6or5x = dev->phy.rev >= 6 ||
1731                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
1732                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
1733         if (phy6or5x) {
1734                 /* TODO */
1735         }
1736
1737         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
1738
1739         if (1 /* FIXME: the band width is 20 MHz */)
1740                 freq = 2500;
1741         else
1742                 freq = 5000;
1743
1744         if (nphy->mphase_cal_phase_id > 2)
1745                 ;/* TODO: Call N PHY Run Samples with (band width * 8),
1746                         0xFFFF, 0, 1, 0 as arguments */
1747         else
1748                 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1749                         and save result as error */
1750
1751         if (error == 0) {
1752                 if (nphy->mphase_cal_phase_id > 2) {
1753                         table = nphy->mphase_txcal_bestcoeffs;
1754                         length = 11;
1755                         if (dev->phy.rev < 3)
1756                                 length -= 2;
1757                 } else {
1758                         if (!full && nphy->txiqlocal_coeffsvalid) {
1759                                 table = nphy->txiqlocal_bestc;
1760                                 length = 11;
1761                                 if (dev->phy.rev < 3)
1762                                         length -= 2;
1763                         } else {
1764                                 full = true;
1765                                 if (dev->phy.rev >= 3) {
1766                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
1767                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
1768                                 } else {
1769                                         table = tbl_tx_iqlo_cal_startcoefs;
1770                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
1771                                 }
1772                         }
1773                 }
1774
1775                 /* TODO: Write an N PHY Table with ID 15, length from above,
1776                         offset 64, width 16, and the data pointer from above */
1777
1778                 if (full) {
1779                         if (dev->phy.rev >= 3)
1780                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
1781                         else
1782                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
1783                 } else {
1784                         if (dev->phy.rev >= 3)
1785                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
1786                         else
1787                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
1788                 }
1789
1790                 if (mphase) {
1791                         count = nphy->mphase_txcal_cmdidx;
1792                         numb = min(max,
1793                                 (u16)(count + nphy->mphase_txcal_numcmds));
1794                 } else {
1795                         count = 0;
1796                         numb = max;
1797                 }
1798
1799                 for (; count < numb; count++) {
1800                         if (full) {
1801                                 if (dev->phy.rev >= 3)
1802                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
1803                                 else
1804                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
1805                         } else {
1806                                 if (dev->phy.rev >= 3)
1807                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
1808                                 else
1809                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
1810                         }
1811
1812                         core = (cmd & 0x3000) >> 12;
1813                         type = (cmd & 0x0F00) >> 8;
1814
1815                         if (phy6or5x && updated[core] == 0) {
1816                                 b43_nphy_update_tx_cal_ladder(dev, core);
1817                                 updated[core] = 1;
1818                         }
1819
1820                         tmp = (params[core].ncorr[type] << 8) | 0x66;
1821                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
1822
1823                         if (type == 1 || type == 3 || type == 4) {
1824                                 /* TODO: Read an N PHY Table with ID 15,
1825                                         length 1, offset 69 + core,
1826                                         width 16, and data pointer buffer */
1827                                 diq_start = buffer[0];
1828                                 buffer[0] = 0;
1829                                 /* TODO: Write an N PHY Table with ID 15,
1830                                         length 1, offset 69 + core, width 16,
1831                                         and data of 0 */
1832                         }
1833
1834                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
1835                         for (i = 0; i < 2000; i++) {
1836                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
1837                                 if (tmp & 0xC000)
1838                                         break;
1839                                 udelay(10);
1840                         }
1841
1842                         /* TODO: Read an N PHY Table with ID 15,
1843                                 length table_length, offset 96, width 16,
1844                                 and data pointer buffer */
1845                         /* TODO: Write an N PHY Table with ID 15,
1846                                 length table_length, offset 64, width 16,
1847                                 and data pointer buffer */
1848
1849                         if (type == 1 || type == 3 || type == 4)
1850                                 buffer[0] = diq_start;
1851                 }
1852
1853                 if (mphase)
1854                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
1855
1856                 last = (dev->phy.rev < 3) ? 6 : 7;
1857
1858                 if (!mphase || nphy->mphase_cal_phase_id == last) {
1859                         /* TODO: Write an N PHY Table with ID 15, length 4,
1860                                 offset 96, width 16, and data pointer buffer */
1861                         /* TODO: Read an N PHY Table with ID 15, length 4,
1862                                 offset 80, width 16, and data pointer buffer */
1863                         if (dev->phy.rev < 3) {
1864                                 buffer[0] = 0;
1865                                 buffer[1] = 0;
1866                                 buffer[2] = 0;
1867                                 buffer[3] = 0;
1868                         }
1869                         /* TODO: Write an N PHY Table with ID 15, length 4,
1870                                 offset 88, width 16, and data pointer buffer */
1871                         /* TODO: Read an N PHY Table with ID 15, length 2,
1872                                 offset 101, width 16, and data pointer buffer*/
1873                         /* TODO: Write an N PHY Table with ID 15, length 2,
1874                                 offset 85, width 16, and data pointer buffer */
1875                         /* TODO: Write an N PHY Table with ID 15, length 2,
1876                                 offset 93, width 16, and data pointer buffer */
1877                         length = 11;
1878                         if (dev->phy.rev < 3)
1879                                 length -= 2;
1880                         /* TODO: Read an N PHY Table with ID 15, length length,
1881                                 offset 96, width 16, and data pointer
1882                                 nphy->txiqlocal_bestc */
1883                         nphy->txiqlocal_coeffsvalid = true;
1884                         /* TODO: Set nphy->txiqlocal_chanspec to
1885                                 the current channel */
1886                 } else {
1887                         length = 11;
1888                         if (dev->phy.rev < 3)
1889                                 length -= 2;
1890                         /* TODO: Read an N PHY Table with ID 5, length length,
1891                                 offset 96, width 16, and data pointer
1892                                 nphy->mphase_txcal_bestcoeffs */
1893                 }
1894
1895                 /* TODO: Call N PHY Stop Playback */
1896                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
1897         }
1898
1899         b43_nphy_tx_cal_phy_cleanup(dev);
1900         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1901                 width 16, and data from save */
1902
1903         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
1904                 b43_nphy_tx_iq_workaround(dev);
1905
1906         if (dev->phy.rev >= 4)
1907                 nphy->hang_avoid = avoid;
1908
1909         b43_nphy_stay_in_carrier_search(dev, false);
1910
1911         return error;
1912 }
1913
1914 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
1915 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
1916                         struct nphy_txgains target, u8 type, bool debug)
1917 {
1918         struct b43_phy_n *nphy = dev->phy.n;
1919         int i, j, index;
1920         u8 rfctl[2];
1921         u8 afectl_core;
1922         u16 tmp[6];
1923         u16 cur_hpf1, cur_hpf2, cur_lna;
1924         u32 real, imag;
1925         enum ieee80211_band band;
1926
1927         u8 use;
1928         u16 cur_hpf;
1929         u16 lna[3] = { 3, 3, 1 };
1930         u16 hpf1[3] = { 7, 2, 0 };
1931         u16 hpf2[3] = { 2, 0, 0 };
1932         u32 power[3];
1933         u16 gain_save[2];
1934         u16 cal_gain[2];
1935         struct nphy_iqcal_params cal_params[2];
1936         struct nphy_iq_est est;
1937         int ret = 0;
1938         bool playtone = true;
1939         int desired = 13;
1940
1941         b43_nphy_stay_in_carrier_search(dev, 1);
1942
1943         if (dev->phy.rev < 2)
1944                 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
1945         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1946                 width 16, and data gain_save */
1947         for (i = 0; i < 2; i++) {
1948                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
1949                 cal_gain[i] = cal_params[i].cal_gain;
1950         }
1951         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1952                 width 16, and data from cal_gain */
1953
1954         for (i = 0; i < 2; i++) {
1955                 if (i == 0) {
1956                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
1957                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
1958                         afectl_core = B43_NPHY_AFECTL_C1;
1959                 } else {
1960                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
1961                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
1962                         afectl_core = B43_NPHY_AFECTL_C2;
1963                 }
1964
1965                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
1966                 tmp[2] = b43_phy_read(dev, afectl_core);
1967                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1968                 tmp[4] = b43_phy_read(dev, rfctl[0]);
1969                 tmp[5] = b43_phy_read(dev, rfctl[1]);
1970
1971                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
1972                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
1973                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
1974                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
1975                                 (1 - i));
1976                 b43_phy_set(dev, afectl_core, 0x0006);
1977                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
1978
1979                 band = b43_current_band(dev->wl);
1980
1981                 if (nphy->rxcalparams & 0xFF000000) {
1982                         if (band == IEEE80211_BAND_5GHZ)
1983                                 b43_phy_write(dev, rfctl[0], 0x140);
1984                         else
1985                                 b43_phy_write(dev, rfctl[0], 0x110);
1986                 } else {
1987                         if (band == IEEE80211_BAND_5GHZ)
1988                                 b43_phy_write(dev, rfctl[0], 0x180);
1989                         else
1990                                 b43_phy_write(dev, rfctl[0], 0x120);
1991                 }
1992
1993                 if (band == IEEE80211_BAND_5GHZ)
1994                         b43_phy_write(dev, rfctl[1], 0x148);
1995                 else
1996                         b43_phy_write(dev, rfctl[1], 0x114);
1997
1998                 if (nphy->rxcalparams & 0x10000) {
1999                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2000                                         (i + 1));
2001                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2002                                         (2 - i));
2003                 }
2004
2005                 for (j = 0; i < 4; j++) {
2006                         if (j < 3) {
2007                                 cur_lna = lna[j];
2008                                 cur_hpf1 = hpf1[j];
2009                                 cur_hpf2 = hpf2[j];
2010                         } else {
2011                                 if (power[1] > 10000) {
2012                                         use = 1;
2013                                         cur_hpf = cur_hpf1;
2014                                         index = 2;
2015                                 } else {
2016                                         if (power[0] > 10000) {
2017                                                 use = 1;
2018                                                 cur_hpf = cur_hpf1;
2019                                                 index = 1;
2020                                         } else {
2021                                                 index = 0;
2022                                                 use = 2;
2023                                                 cur_hpf = cur_hpf2;
2024                                         }
2025                                 }
2026                                 cur_lna = lna[index];
2027                                 cur_hpf1 = hpf1[index];
2028                                 cur_hpf2 = hpf2[index];
2029                                 cur_hpf += desired - hweight32(power[index]);
2030                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2031                                 if (use == 1)
2032                                         cur_hpf1 = cur_hpf;
2033                                 else
2034                                         cur_hpf2 = cur_hpf;
2035                         }
2036
2037                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2038                                         (cur_lna << 2));
2039                         /* TODO:Call N PHY RF Ctrl Override with 0x400, tmp[0],
2040                                 3, 0 as arguments */
2041                         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2042                         /* TODO: Call N PHT Stop Playback */
2043
2044                         if (playtone) {
2045                                 /* TODO: Call N PHY TX Tone with 4000,
2046                                         (nphy_rxcalparams & 0xffff), 0, 0
2047                                         as arguments and save result as ret */
2048                                 playtone = false;
2049                         } else {
2050                                 /* TODO: Call N PHY Run Samples with 160,
2051                                         0xFFFF, 0, 0, 0 as arguments */
2052                         }
2053
2054                         if (ret == 0) {
2055                                 if (j < 3) {
2056                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2057                                                                         false);
2058                                         if (i == 0) {
2059                                                 real = est.i0_pwr;
2060                                                 imag = est.q0_pwr;
2061                                         } else {
2062                                                 real = est.i1_pwr;
2063                                                 imag = est.q1_pwr;
2064                                         }
2065                                         power[i] = ((real + imag) / 1024) + 1;
2066                                 } else {
2067                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2068                                 }
2069                                 /* TODO: Call N PHY Stop Playback */
2070                         }
2071
2072                         if (ret != 0)
2073                                 break;
2074                 }
2075
2076                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2077                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2078                 b43_phy_write(dev, rfctl[1], tmp[5]);
2079                 b43_phy_write(dev, rfctl[0], tmp[4]);
2080                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2081                 b43_phy_write(dev, afectl_core, tmp[2]);
2082                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2083
2084                 if (ret != 0)
2085                         break;
2086         }
2087
2088         /* TODO: Call N PHY RF Ctrl Override with 0x400, 0, 3, 1 as arguments*/
2089         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2090         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2091                 width 16, and data from gain_save */
2092
2093         b43_nphy_stay_in_carrier_search(dev, 0);
2094
2095         return ret;
2096 }
2097
2098 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2099                         struct nphy_txgains target, u8 type, bool debug)
2100 {
2101         return -1;
2102 }
2103
2104 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2105 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2106                         struct nphy_txgains target, u8 type, bool debug)
2107 {
2108         if (dev->phy.rev >= 3)
2109                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2110         else
2111                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2112 }
2113
2114 /*
2115  * Init N-PHY
2116  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2117  */
2118 int b43_phy_initn(struct b43_wldev *dev)
2119 {
2120         struct ssb_bus *bus = dev->dev->bus;
2121         struct b43_phy *phy = &dev->phy;
2122         struct b43_phy_n *nphy = phy->n;
2123         u8 tx_pwr_state;
2124         struct nphy_txgains target;
2125         u16 tmp;
2126         enum ieee80211_band tmp2;
2127         bool do_rssi_cal;
2128
2129         u16 clip[2];
2130         bool do_cal = false;
2131
2132         if ((dev->phy.rev >= 3) &&
2133            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2134            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2135                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2136         }
2137         nphy->deaf_count = 0;
2138         b43_nphy_tables_init(dev);
2139         nphy->crsminpwr_adjusted = false;
2140         nphy->noisevars_adjusted = false;
2141
2142         /* Clear all overrides */
2143         if (dev->phy.rev >= 3) {
2144                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2145                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2146                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2147                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2148         } else {
2149                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2150         }
2151         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2152         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2153         if (dev->phy.rev < 6) {
2154                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2155                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2156         }
2157         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2158                      ~(B43_NPHY_RFSEQMODE_CAOVER |
2159                        B43_NPHY_RFSEQMODE_TROVER));
2160         if (dev->phy.rev >= 3)
2161                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2162         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2163
2164         if (dev->phy.rev <= 2) {
2165                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2166                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2167                                 ~B43_NPHY_BPHY_CTL3_SCALE,
2168                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2169         }
2170         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2171         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2172
2173         if (bus->sprom.boardflags2_lo & 0x100 ||
2174             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2175              bus->boardinfo.type == 0x8B))
2176                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2177         else
2178                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2179         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2180         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2181         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2182
2183         /* TODO MIMO-Config */
2184         /* TODO Update TX/RX chain */
2185
2186         if (phy->rev < 2) {
2187                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2188                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2189         }
2190
2191         tmp2 = b43_current_band(dev->wl);
2192         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2193             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2194                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2195                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2196                                 nphy->papd_epsilon_offset[0] << 7);
2197                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2198                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2199                                 nphy->papd_epsilon_offset[1] << 7);
2200                 /* TODO N PHY IPA Set TX Dig Filters */
2201         } else if (phy->rev >= 5) {
2202                 /* TODO N PHY Ext PA Set TX Dig Filters */
2203         }
2204
2205         b43_nphy_workarounds(dev);
2206
2207         /* Reset CCA, in init code it differs a little from standard way */
2208         b43_nphy_bmac_clock_fgc(dev, 1);
2209         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2210         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2211         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
2212         b43_nphy_bmac_clock_fgc(dev, 0);
2213
2214         /* TODO N PHY MAC PHY Clock Set with argument 1 */
2215
2216         b43_nphy_pa_override(dev, false);
2217         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2218         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2219         b43_nphy_pa_override(dev, true);
2220
2221         b43_nphy_classifier(dev, 0, 0);
2222         b43_nphy_read_clip_detection(dev, clip);
2223         tx_pwr_state = nphy->txpwrctrl;
2224         /* TODO N PHY TX power control with argument 0
2225                 (turning off power control) */
2226         /* TODO Fix the TX Power Settings */
2227         /* TODO N PHY TX Power Control Idle TSSI */
2228         /* TODO N PHY TX Power Control Setup */
2229
2230         if (phy->rev >= 3) {
2231                 /* TODO */
2232         } else {
2233                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2234                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2235         }
2236
2237         if (nphy->phyrxchain != 3)
2238                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2239         if (nphy->mphase_cal_phase_id > 0)
2240                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2241
2242         do_rssi_cal = false;
2243         if (phy->rev >= 3) {
2244                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2245                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2246                 else
2247                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2248
2249                 if (do_rssi_cal)
2250                         b43_nphy_rssi_cal(dev);
2251                 else
2252                         b43_nphy_restore_rssi_cal(dev);
2253         } else {
2254                 b43_nphy_rssi_cal(dev);
2255         }
2256
2257         if (!((nphy->measure_hold & 0x6) != 0)) {
2258                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2259                         do_cal = (nphy->iqcal_chanspec_2G == 0);
2260                 else
2261                         do_cal = (nphy->iqcal_chanspec_5G == 0);
2262
2263                 if (nphy->mute)
2264                         do_cal = false;
2265
2266                 if (do_cal) {
2267                         target = b43_nphy_get_tx_gains(dev);
2268
2269                         if (nphy->antsel_type == 2)
2270                                 ;/*TODO NPHY Superswitch Init with argument 1*/
2271                         if (nphy->perical != 2) {
2272                                 b43_nphy_rssi_cal(dev);
2273                                 if (phy->rev >= 3) {
2274                                         nphy->cal_orig_pwr_idx[0] =
2275                                             nphy->txpwrindex[0].index_internal;
2276                                         nphy->cal_orig_pwr_idx[1] =
2277                                             nphy->txpwrindex[1].index_internal;
2278                                         /* TODO N PHY Pre Calibrate TX Gain */
2279                                         target = b43_nphy_get_tx_gains(dev);
2280                                 }
2281                         }
2282                 }
2283         }
2284
2285         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2286                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
2287                         ;/* Call N PHY Save Cal */
2288                 else if (nphy->mphase_cal_phase_id == 0)
2289                         ;/* N PHY Periodic Calibration with argument 3 */
2290         } else {
2291                 b43_nphy_restore_cal(dev);
2292         }
2293
2294         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
2295         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2296         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2297         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2298         if (phy->rev >= 3 && phy->rev <= 6)
2299                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
2300         b43_nphy_tx_lp_fbw(dev);
2301         /* TODO N PHY Spur Workaround */
2302
2303         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
2304         return 0;
2305 }
2306
2307 static int b43_nphy_op_allocate(struct b43_wldev *dev)
2308 {
2309         struct b43_phy_n *nphy;
2310
2311         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2312         if (!nphy)
2313                 return -ENOMEM;
2314         dev->phy.n = nphy;
2315
2316         return 0;
2317 }
2318
2319 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2320 {
2321         struct b43_phy *phy = &dev->phy;
2322         struct b43_phy_n *nphy = phy->n;
2323
2324         memset(nphy, 0, sizeof(*nphy));
2325
2326         //TODO init struct b43_phy_n
2327 }
2328
2329 static void b43_nphy_op_free(struct b43_wldev *dev)
2330 {
2331         struct b43_phy *phy = &dev->phy;
2332         struct b43_phy_n *nphy = phy->n;
2333
2334         kfree(nphy);
2335         phy->n = NULL;
2336 }
2337
2338 static int b43_nphy_op_init(struct b43_wldev *dev)
2339 {
2340         return b43_phy_initn(dev);
2341 }
2342
2343 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2344 {
2345 #if B43_DEBUG
2346         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2347                 /* OFDM registers are onnly available on A/G-PHYs */
2348                 b43err(dev->wl, "Invalid OFDM PHY access at "
2349                        "0x%04X on N-PHY\n", offset);
2350                 dump_stack();
2351         }
2352         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2353                 /* Ext-G registers are only available on G-PHYs */
2354                 b43err(dev->wl, "Invalid EXT-G PHY access at "
2355                        "0x%04X on N-PHY\n", offset);
2356                 dump_stack();
2357         }
2358 #endif /* B43_DEBUG */
2359 }
2360
2361 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2362 {
2363         check_phyreg(dev, reg);
2364         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2365         return b43_read16(dev, B43_MMIO_PHY_DATA);
2366 }
2367
2368 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2369 {
2370         check_phyreg(dev, reg);
2371         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2372         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2373 }
2374
2375 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2376 {
2377         /* Register 1 is a 32-bit register. */
2378         B43_WARN_ON(reg == 1);
2379         /* N-PHY needs 0x100 for read access */
2380         reg |= 0x100;
2381
2382         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2383         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2384 }
2385
2386 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2387 {
2388         /* Register 1 is a 32-bit register. */
2389         B43_WARN_ON(reg == 1);
2390
2391         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2392         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2393 }
2394
2395 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
2396                                         bool blocked)
2397 {//TODO
2398 }
2399
2400 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2401 {
2402         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2403                       on ? 0 : 0x7FFF);
2404 }
2405
2406 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2407                                       unsigned int new_channel)
2408 {
2409         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2410                 if ((new_channel < 1) || (new_channel > 14))
2411                         return -EINVAL;
2412         } else {
2413                 if (new_channel > 200)
2414                         return -EINVAL;
2415         }
2416
2417         return nphy_channel_switch(dev, new_channel);
2418 }
2419
2420 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2421 {
2422         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2423                 return 1;
2424         return 36;
2425 }
2426
2427 const struct b43_phy_operations b43_phyops_n = {
2428         .allocate               = b43_nphy_op_allocate,
2429         .free                   = b43_nphy_op_free,
2430         .prepare_structs        = b43_nphy_op_prepare_structs,
2431         .init                   = b43_nphy_op_init,
2432         .phy_read               = b43_nphy_op_read,
2433         .phy_write              = b43_nphy_op_write,
2434         .radio_read             = b43_nphy_op_radio_read,
2435         .radio_write            = b43_nphy_op_radio_write,
2436         .software_rfkill        = b43_nphy_op_software_rfkill,
2437         .switch_analog          = b43_nphy_op_switch_analog,
2438         .switch_channel         = b43_nphy_op_switch_channel,
2439         .get_default_chan       = b43_nphy_op_get_default_chan,
2440         .recalc_txpower         = b43_nphy_op_recalc_txpower,
2441         .adjust_txpower         = b43_nphy_op_adjust_txpower,
2442 };