SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31
  32 struct nphy_txgains {
  33         u16 txgm[2];
  34         u16 pga[2];
  35         u16 pad[2];
  36         u16 ipa[2];
  37 };
  38
  39 struct nphy_iqcal_params {
  40         u16 txgm;
  41         u16 pga;
  42         u16 pad;
  43         u16 ipa;
  44         u16 cal_gain;
  45         u16 ncorr[5];
  46 };
  47
  48 struct nphy_iq_est {
  49         s32 iq0_prod;
  50         u32 i0_pwr;
  51         u32 q0_pwr;
  52         s32 iq1_prod;
  53         u32 i1_pwr;
  54         u32 q1_pwr;
  55 };
  56
  57 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  58 {//TODO
  59 }
  60
  61 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  62 {//TODO
  63 }
  64
  65 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  66                                                         bool ignore_tssi)
  67 {//TODO
  68         return B43_TXPWR_RES_DONE;
  69 }
  70
  71 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  72                                      const struct b43_nphy_channeltab_entry *e)
  73 {
  74         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  75         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  77         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  78         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  79         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  80         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  81         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  82         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  83         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  84         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  86         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  88         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  89         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  90         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  91         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  93         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  94         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  95         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  96 }
  97
  98 static void b43_chantab_phy_upload(struct b43_wldev *dev,
  99                                    const struct b43_nphy_channeltab_entry *e)
 100 {
 101         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 102         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 103         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 104         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 105         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 106         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 107 }
 108
 109 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 110 {
 111         //TODO
 112 }
 113
 114 /* Tune the hardware to a new channel. */
 115 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 116 {
 117         const struct b43_nphy_channeltab_entry *tabent;
 118
 119         tabent = b43_nphy_get_chantabent(dev, channel);
 120         if (!tabent)
 121                 return -ESRCH;
 122
 123         //FIXME enable/disable band select upper20 in RXCTL
 124         if (0 /*FIXME 5Ghz*/)
 125                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 126         else
 127                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 128         b43_chantab_radio_upload(dev, tabent);
 129         udelay(50);
 130         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 133         udelay(300);
 134         if (0 /*FIXME 5Ghz*/)
 135                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 136         else
 137                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 138         b43_chantab_phy_upload(dev, tabent);
 139         b43_nphy_tx_power_fix(dev);
 140
 141         return 0;
 142 }
 143
 144 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 145 {
 146         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 147                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 148         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 149                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 150                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 151         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 152                     B43_NPHY_RFCTL_CMD_PORFORCE);
 153 }
 154
 155 static void b43_radio_init2055_post(struct b43_wldev *dev)
 156 {
 157         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 158         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 159         int i;
 160         u16 val;
 161
 162         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 163         msleep(1);
 164         if ((sprom->revision != 4) ||
 165            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 166                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 167                     (binfo->type != 0x46D) ||
 168                     (binfo->rev < 0x41)) {
 169                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         msleep(1);
 172                 }
 173         }
 174         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 175         msleep(1);
 176         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 177         msleep(1);
 178         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 179         msleep(1);
 180         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 181         msleep(1);
 182         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 183         msleep(1);
 184         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 185         msleep(1);
 186         for (i = 0; i < 100; i++) {
 187                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 188                 if (val & 0x80)
 189                         break;
 190                 udelay(10);
 191         }
 192         msleep(1);
 193         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 194         msleep(1);
 195         nphy_channel_switch(dev, dev->phy.channel);
 196         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 197         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 199         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 200 }
 201
 202 /* Initialize a Broadcom 2055 N-radio */
 203 static void b43_radio_init2055(struct b43_wldev *dev)
 204 {
 205         b43_radio_init2055_pre(dev);
 206         if (b43_status(dev) < B43_STAT_INITIALIZED)
 207                 b2055_upload_inittab(dev, 0, 1);
 208         else
 209                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 210         b43_radio_init2055_post(dev);
 211 }
 212
 213 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 214 {
 215         b43_radio_init2055(dev);
 216 }
 217
 218 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 219 {
 220         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 221                      ~B43_NPHY_RFCTL_CMD_EN);
 222 }
 223
 224 #define ntab_upload(dev, offset, data) do { \
 225                 unsigned int i;                                         \
 226                 for (i = 0; i < (offset##_SIZE); i++)                   \
 227                         b43_ntab_write(dev, (offset) + i, (data)[i]);   \
 228         } while (0)
 229
 230 /*
 231  * Upload the N-PHY tables.
 232  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 233  */
 234 static void b43_nphy_tables_init(struct b43_wldev *dev)
 235 {
 236         if (dev->phy.rev < 3)
 237                 b43_nphy_rev0_1_2_tables_init(dev);
 238         else
 239                 b43_nphy_rev3plus_tables_init(dev);
 240 }
 241
 242 static void b43_nphy_workarounds(struct b43_wldev *dev)
 243 {
 244         struct b43_phy *phy = &dev->phy;
 245         unsigned int i;
 246
 247         b43_phy_set(dev, B43_NPHY_IQFLIP,
 248                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 249         if (1 /* FIXME band is 2.4GHz */) {
 250                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 251                             B43_NPHY_CLASSCTL_CCKEN);
 252         } else {
 253                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 254                              ~B43_NPHY_CLASSCTL_CCKEN);
 255         }
 256         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 257         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 258
 259         /* Fixup some tables */
 260         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 265         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 266         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 267         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 268         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 269         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 270
 271         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 272         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 273         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 274         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 275
 276         //TODO set RF sequence
 277
 278         /* Set narrowband clip threshold */
 279         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 280         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 281
 282         /* Set wideband clip 2 threshold */
 283         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 284                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 285                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 286         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 287                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 288                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 289
 290         /* Set Clip 2 detect */
 291         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 292                     B43_NPHY_C1_CGAINI_CL2DETECT);
 293         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 294                     B43_NPHY_C2_CGAINI_CL2DETECT);
 295
 296         if (0 /*FIXME*/) {
 297                 /* Set dwell lengths */
 298                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 299                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 300                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 301                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 302
 303                 /* Set gain backoff */
 304                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 305                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 306                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 307                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 308                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 309                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 310
 311                 /* Set HPVGA2 index */
 312                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 313                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 314                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 315                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 316                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 317                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 318
 319                 //FIXME verify that the specs really mean to use autoinc here.
 320                 for (i = 0; i < 3; i++)
 321                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 322         }
 323
 324         /* Set minimum gain value */
 325         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 326                         ~B43_NPHY_C1_MINGAIN,
 327                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 328         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 329                         ~B43_NPHY_C2_MINGAIN,
 330                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 331
 332         if (phy->rev < 2) {
 333                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 334                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 335         }
 336
 337         /* Set phase track alpha and beta */
 338         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 339         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 340         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 341         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 342         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 343         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 344 }
 345
 346 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 347 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 348 {
 349         u32 tmslow;
 350
 351         if (dev->phy.type != B43_PHYTYPE_N)
 352                 return;
 353
 354         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 355         if (force)
 356                 tmslow |= SSB_TMSLOW_FGC;
 357         else
 358                 tmslow &= ~SSB_TMSLOW_FGC;
 359         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 360 }
 361
 362 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 363 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 364 {
 365         u16 bbcfg;
 366
 367         b43_nphy_bmac_clock_fgc(dev, 1);
 368         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 369         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 370         udelay(1);
 371         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 372         b43_nphy_bmac_clock_fgc(dev, 0);
 373         /* TODO: N PHY Force RF Seq with argument 2 */
 374 }
 375
 376 enum b43_nphy_rf_sequence {
 377         B43_RFSEQ_RX2TX,
 378         B43_RFSEQ_TX2RX,
 379         B43_RFSEQ_RESET2RX,
 380         B43_RFSEQ_UPDATE_GAINH,
 381         B43_RFSEQ_UPDATE_GAINL,
 382         B43_RFSEQ_UPDATE_GAINU,
 383 };
 384
 385 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 386                                        enum b43_nphy_rf_sequence seq)
 387 {
 388         static const u16 trigger[] = {
 389                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 390                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 391                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 392                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 393                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 394                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 395         };
 396         int i;
 397
 398         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 399
 400         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 401                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 402         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 403         for (i = 0; i < 200; i++) {
 404                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 405                         goto ok;
 406                 msleep(1);
 407         }
 408         b43err(dev->wl, "RF sequence status timeout\n");
 409 ok:
 410         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 411                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 412 }
 413
 414 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 415 {
 416         unsigned int i;
 417         u16 val;
 418
 419         val = 0x1E1F;
 420         for (i = 0; i < 14; i++) {
 421                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 422                 val -= 0x202;
 423         }
 424         val = 0x3E3F;
 425         for (i = 0; i < 16; i++) {
 426                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 427                 val -= 0x202;
 428         }
 429         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 430 }
 431
 432 /* RSSI Calibration */
 433 static void b43_nphy_rssi_cal(struct b43_wldev *dev, u8 type)
 434 {
 435         //TODO
 436 }
 437
 438 /*
 439  * Init N-PHY
 440  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
 441  */
 442 int b43_phy_initn(struct b43_wldev *dev)
 443 {
 444         struct ssb_bus *bus = dev->dev->bus;
 445         struct b43_phy *phy = &dev->phy;
 446         struct b43_phy_n *nphy = phy->n;
 447         u8 tx_pwr_state;
 448         struct nphy_txgains target;
 449         u16 tmp;
 450         enum ieee80211_band tmp2;
 451         bool do_rssi_cal;
 452
 453         u16 clip[2];
 454         bool do_cal = false;
 455
 456         if ((dev->phy.rev >= 3) &&
 457            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
 458            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
 459                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
 460         }
 461         nphy->deaf_count = 0;
 462         b43_nphy_tables_init(dev);
 463         nphy->crsminpwr_adjusted = false;
 464         nphy->noisevars_adjusted = false;
 465
 466         /* Clear all overrides */
 467         if (dev->phy.rev >= 3) {
 468                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
 469                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
 470                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
 471                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
 472         } else {
 473                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
 474         }
 475         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
 476         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
 477         if (dev->phy.rev < 6) {
 478                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
 479                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
 480         }
 481         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 482                      ~(B43_NPHY_RFSEQMODE_CAOVER |
 483                        B43_NPHY_RFSEQMODE_TROVER));
 484         if (dev->phy.rev >= 3)
 485                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
 486         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
 487
 488         if (dev->phy.rev <= 2) {
 489                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
 490                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 491                                 ~B43_NPHY_BPHY_CTL3_SCALE,
 492                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
 493         }
 494         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
 495         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
 496
 497         if (bus->sprom.boardflags2_lo & 0x100 ||
 498             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
 499              bus->boardinfo.type == 0x8B))
 500                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
 501         else
 502                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
 503         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
 504         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
 505         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
 506
 507         /* TODO MIMO-Config */
 508         /* TODO Update TX/RX chain */
 509
 510         if (phy->rev < 2) {
 511                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
 512                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
 513         }
 514
 515         tmp2 = b43_current_band(dev->wl);
 516         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
 517             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
 518                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
 519                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
 520                                 nphy->papd_epsilon_offset[0] << 7);
 521                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
 522                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
 523                                 nphy->papd_epsilon_offset[1] << 7);
 524                 /* TODO N PHY IPA Set TX Dig Filters */
 525         } else if (phy->rev >= 5) {
 526                 /* TODO N PHY Ext PA Set TX Dig Filters */
 527         }
 528
 529         b43_nphy_workarounds(dev);
 530
 531         /* Reset CCA, in init code it differs a little from standard way */
 532         /* b43_nphy_bmac_clock_fgc(dev, 1); */
 533         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
 534         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
 535         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
 536         /* b43_nphy_bmac_clock_fgc(dev, 0); */
 537
 538         /* TODO N PHY MAC PHY Clock Set with argument 1 */
 539
 540         /* b43_nphy_pa_override(dev, false); */
 541         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 542         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 543         /* b43_nphy_pa_override(dev, true); */
 544
 545         /* b43_nphy_classifier(dev, 0, 0); */
 546         /* b43_nphy_read_clip_detection(dev, clip); */
 547         tx_pwr_state = nphy->txpwrctrl;
 548         /* TODO N PHY TX power control with argument 0
 549                 (turning off power control) */
 550         /* TODO Fix the TX Power Settings */
 551         /* TODO N PHY TX Power Control Idle TSSI */
 552         /* TODO N PHY TX Power Control Setup */
 553
 554         if (phy->rev >= 3) {
 555                 /* TODO */
 556         } else {
 557                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
 558                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
 559         }
 560
 561         if (nphy->phyrxchain != 3)
 562                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
 563         if (nphy->mphase_cal_phase_id > 0)
 564                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
 565
 566         do_rssi_cal = false;
 567         if (phy->rev >= 3) {
 568                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 569                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
 570                 else
 571                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
 572
 573                 if (do_rssi_cal)
 574                         ;/* b43_nphy_rssi_cal(dev); */
 575                 else
 576                         ;/* b43_nphy_restore_rssi_cal(dev); */
 577         } else {
 578                 /* b43_nphy_rssi_cal(dev); */
 579         }
 580
 581         if (!((nphy->measure_hold & 0x6) != 0)) {
 582                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 583                         do_cal = (nphy->iqcal_chanspec_2G == 0);
 584                 else
 585                         do_cal = (nphy->iqcal_chanspec_5G == 0);
 586
 587                 if (nphy->mute)
 588                         do_cal = false;
 589
 590                 if (do_cal) {
 591                         /* target = b43_nphy_get_tx_gains(dev); */
 592
 593                         if (nphy->antsel_type == 2)
 594                                 ;/*TODO NPHY Superswitch Init with argument 1*/
 595                         if (nphy->perical != 2) {
 596                                 /* b43_nphy_rssi_cal(dev); */
 597                                 if (phy->rev >= 3) {
 598                                         nphy->cal_orig_pwr_idx[0] =
 599                                             nphy->txpwrindex[0].index_internal;
 600                                         nphy->cal_orig_pwr_idx[1] =
 601                                             nphy->txpwrindex[1].index_internal;
 602                                         /* TODO N PHY Pre Calibrate TX Gain */
 603                                         /*target = b43_nphy_get_tx_gains(dev)*/
 604                                 }
 605                         }
 606                 }
 607         }
 608
 609         /*
 610         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
 611                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
 612                         Call N PHY Save Cal
 613                 else if (nphy->mphase_cal_phase_id == 0)
 614                         N PHY Periodic Calibration with argument 3
 615         } else {
 616                 b43_nphy_restore_cal(dev);
 617         }
 618         */
 619
 620         /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
 621         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
 622         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
 623         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
 624         if (phy->rev >= 3 && phy->rev <= 6)
 625                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
 626         /* b43_nphy_tx_lp_fbw(dev); */
 627         /* TODO N PHY Spur Workaround */
 628
 629         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
 630         return 0;
 631 }
 632
 633 static int b43_nphy_op_allocate(struct b43_wldev *dev)
 634 {
 635         struct b43_phy_n *nphy;
 636
 637         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
 638         if (!nphy)
 639                 return -ENOMEM;
 640         dev->phy.n = nphy;
 641
 642         return 0;
 643 }
 644
 645 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
 646 {
 647         struct b43_phy *phy = &dev->phy;
 648         struct b43_phy_n *nphy = phy->n;
 649
 650         memset(nphy, 0, sizeof(*nphy));
 651
 652         //TODO init struct b43_phy_n
 653 }
 654
 655 static void b43_nphy_op_free(struct b43_wldev *dev)
 656 {
 657         struct b43_phy *phy = &dev->phy;
 658         struct b43_phy_n *nphy = phy->n;
 659
 660         kfree(nphy);
 661         phy->n = NULL;
 662 }
 663
 664 static int b43_nphy_op_init(struct b43_wldev *dev)
 665 {
 666         return b43_phy_initn(dev);
 667 }
 668
 669 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
 670 {
 671 #if B43_DEBUG
 672         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 673                 /* OFDM registers are onnly available on A/G-PHYs */
 674                 b43err(dev->wl, "Invalid OFDM PHY access at "
 675                        "0x%04X on N-PHY\n", offset);
 676                 dump_stack();
 677         }
 678         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 679                 /* Ext-G registers are only available on G-PHYs */
 680                 b43err(dev->wl, "Invalid EXT-G PHY access at "
 681                        "0x%04X on N-PHY\n", offset);
 682                 dump_stack();
 683         }
 684 #endif /* B43_DEBUG */
 685 }
 686
 687 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
 688 {
 689         check_phyreg(dev, reg);
 690         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 691         return b43_read16(dev, B43_MMIO_PHY_DATA);
 692 }
 693
 694 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 695 {
 696         check_phyreg(dev, reg);
 697         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 698         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 699 }
 700
 701 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 702 {
 703         /* Register 1 is a 32-bit register. */
 704         B43_WARN_ON(reg == 1);
 705         /* N-PHY needs 0x100 for read access */
 706         reg |= 0x100;
 707
 708         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 709         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 710 }
 711
 712 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 713 {
 714         /* Register 1 is a 32-bit register. */
 715         B43_WARN_ON(reg == 1);
 716
 717         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 718         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 719 }
 720
 721 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
 722                                         bool blocked)
 723 {//TODO
 724 }
 725
 726 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
 727 {
 728         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
 729                       on ? 0 : 0x7FFF);
 730 }
 731
 732 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
 733                                       unsigned int new_channel)
 734 {
 735         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 736                 if ((new_channel < 1) || (new_channel > 14))
 737                         return -EINVAL;
 738         } else {
 739                 if (new_channel > 200)
 740                         return -EINVAL;
 741         }
 742
 743         return nphy_channel_switch(dev, new_channel);
 744 }
 745
 746 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
 747 {
 748         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 749                 return 1;
 750         return 36;
 751 }
 752
 753 const struct b43_phy_operations b43_phyops_n = {
 754         .allocate               = b43_nphy_op_allocate,
 755         .free                   = b43_nphy_op_free,
 756         .prepare_structs        = b43_nphy_op_prepare_structs,
 757         .init                   = b43_nphy_op_init,
 758         .phy_read               = b43_nphy_op_read,
 759         .phy_write              = b43_nphy_op_write,
 760         .radio_read             = b43_nphy_op_radio_read,
 761         .radio_write            = b43_nphy_op_radio_write,
 762         .software_rfkill        = b43_nphy_op_software_rfkill,
 763         .switch_analog          = b43_nphy_op_switch_analog,
 764         .switch_channel         = b43_nphy_op_switch_channel,
 765         .get_default_chan       = b43_nphy_op_get_default_chan,
 766         .recalc_txpower         = b43_nphy_op_recalc_txpower,
 767         .adjust_txpower         = b43_nphy_op_adjust_txpower,
 768 };