SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75
  76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77 {//TODO
  78 }
  79
  80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  81 {//TODO
  82 }
  83
  84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  85                                                         bool ignore_tssi)
  86 {//TODO
  87         return B43_TXPWR_RES_DONE;
  88 }
  89
  90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  91                                      const struct b43_nphy_channeltab_entry *e)
  92 {
  93         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  94         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  95         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  96         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  97         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  98         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  99         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 100         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 101         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 102         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 103         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 104         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 105         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 106         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 107         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 108         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 109         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 110         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 111         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 112         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 113         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 114         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 115 }
 116
 117 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 118                                    const struct b43_nphy_channeltab_entry *e)
 119 {
 120         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 121         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 122         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 123         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 124         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 125         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 126 }
 127
 128 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 129 {
 130         //TODO
 131 }
 132
 133 /* Tune the hardware to a new channel. */
 134 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 135 {
 136         const struct b43_nphy_channeltab_entry *tabent;
 137
 138         tabent = b43_nphy_get_chantabent(dev, channel);
 139         if (!tabent)
 140                 return -ESRCH;
 141
 142         //FIXME enable/disable band select upper20 in RXCTL
 143         if (0 /*FIXME 5Ghz*/)
 144                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 145         else
 146                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 147         b43_chantab_radio_upload(dev, tabent);
 148         udelay(50);
 149         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 150         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 151         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 152         udelay(300);
 153         if (0 /*FIXME 5Ghz*/)
 154                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 155         else
 156                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 157         b43_chantab_phy_upload(dev, tabent);
 158         b43_nphy_tx_power_fix(dev);
 159
 160         return 0;
 161 }
 162
 163 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 164 {
 165         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 166                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 167         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 168                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 169                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 170         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 171                     B43_NPHY_RFCTL_CMD_PORFORCE);
 172 }
 173
 174 static void b43_radio_init2055_post(struct b43_wldev *dev)
 175 {
 176         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 177         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 178         int i;
 179         u16 val;
 180
 181         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 182         msleep(1);
 183         if ((sprom->revision != 4) ||
 184            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 185                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 186                     (binfo->type != 0x46D) ||
 187                     (binfo->rev < 0x41)) {
 188                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 189                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 190                         msleep(1);
 191                 }
 192         }
 193         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 194         msleep(1);
 195         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 196         msleep(1);
 197         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 198         msleep(1);
 199         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 200         msleep(1);
 201         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 202         msleep(1);
 203         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 204         msleep(1);
 205         for (i = 0; i < 100; i++) {
 206                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 207                 if (val & 0x80)
 208                         break;
 209                 udelay(10);
 210         }
 211         msleep(1);
 212         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 213         msleep(1);
 214         nphy_channel_switch(dev, dev->phy.channel);
 215         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 216         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 217         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 218         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 219 }
 220
 221 /* Initialize a Broadcom 2055 N-radio */
 222 static void b43_radio_init2055(struct b43_wldev *dev)
 223 {
 224         b43_radio_init2055_pre(dev);
 225         if (b43_status(dev) < B43_STAT_INITIALIZED)
 226                 b2055_upload_inittab(dev, 0, 1);
 227         else
 228                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 229         b43_radio_init2055_post(dev);
 230 }
 231
 232 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 233 {
 234         b43_radio_init2055(dev);
 235 }
 236
 237 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 238 {
 239         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 240                      ~B43_NPHY_RFCTL_CMD_EN);
 241 }
 242
 243 /*
 244  * Upload the N-PHY tables.
 245  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 246  */
 247 static void b43_nphy_tables_init(struct b43_wldev *dev)
 248 {
 249         if (dev->phy.rev < 3)
 250                 b43_nphy_rev0_1_2_tables_init(dev);
 251         else
 252                 b43_nphy_rev3plus_tables_init(dev);
 253 }
 254
 255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 256 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 257 {
 258         struct b43_phy_n *nphy = dev->phy.n;
 259         enum ieee80211_band band;
 260         u16 tmp;
 261
 262         if (!enable) {
 263                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 264                                                        B43_NPHY_RFCTL_INTC1);
 265                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 266                                                        B43_NPHY_RFCTL_INTC2);
 267                 band = b43_current_band(dev->wl);
 268                 if (dev->phy.rev >= 3) {
 269                         if (band == IEEE80211_BAND_5GHZ)
 270                                 tmp = 0x600;
 271                         else
 272                                 tmp = 0x480;
 273                 } else {
 274                         if (band == IEEE80211_BAND_5GHZ)
 275                                 tmp = 0x180;
 276                         else
 277                                 tmp = 0x120;
 278                 }
 279                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 280                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 281         } else {
 282                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 283                                 nphy->rfctrl_intc1_save);
 284                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 285                                 nphy->rfctrl_intc2_save);
 286         }
 287 }
 288
 289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 290 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 291 {
 292         struct b43_phy_n *nphy = dev->phy.n;
 293         u16 tmp;
 294         enum ieee80211_band band = b43_current_band(dev->wl);
 295         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 296                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 297
 298         if (dev->phy.rev >= 3) {
 299                 if (ipa) {
 300                         tmp = 4;
 301                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 302                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 303                 }
 304
 305                 tmp = 1;
 306                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 307                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 308         }
 309 }
 310
 311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 312 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 313 {
 314         u32 tmslow;
 315
 316         if (dev->phy.type != B43_PHYTYPE_N)
 317                 return;
 318
 319         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 320         if (force)
 321                 tmslow |= SSB_TMSLOW_FGC;
 322         else
 323                 tmslow &= ~SSB_TMSLOW_FGC;
 324         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 325 }
 326
 327 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 328 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 329 {
 330         u16 bbcfg;
 331
 332         b43_nphy_bmac_clock_fgc(dev, 1);
 333         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 334         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 335         udelay(1);
 336         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 337         b43_nphy_bmac_clock_fgc(dev, 0);
 338         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 342 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 343 {
 344         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 345
 346         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 347         if (preamble == 1)
 348                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 349         else
 350                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 351
 352         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 353 }
 354
 355 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 356 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 357 {
 358         struct b43_phy_n *nphy = dev->phy.n;
 359
 360         bool override = false;
 361         u16 chain = 0x33;
 362
 363         if (nphy->txrx_chain == 0) {
 364                 chain = 0x11;
 365                 override = true;
 366         } else if (nphy->txrx_chain == 1) {
 367                 chain = 0x22;
 368                 override = true;
 369         }
 370
 371         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 372                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 373                         chain);
 374
 375         if (override)
 376                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 377                                 B43_NPHY_RFSEQMODE_CAOVER);
 378         else
 379                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 380                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 381 }
 382
 383 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 384 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 385                                 u16 samps, u8 time, bool wait)
 386 {
 387         int i;
 388         u16 tmp;
 389
 390         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 391         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 392         if (wait)
 393                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 394         else
 395                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 396
 397         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 398
 399         for (i = 1000; i; i--) {
 400                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 401                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 402                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 403                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 404                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 405                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 406                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 407                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 408
 409                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 410                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 411                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 412                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 413                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 414                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 415                         return;
 416                 }
 417                 udelay(10);
 418         }
 419         memset(est, 0, sizeof(*est));
 420 }
 421
 422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 423 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 424                                         struct b43_phy_n_iq_comp *pcomp)
 425 {
 426         if (write) {
 427                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 428                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 429                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 430                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 431         } else {
 432                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 433                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 434                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 435                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 436         }
 437 }
 438
 439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 440 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 441 {
 442         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 443
 444         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 445         if (core == 0) {
 446                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 447                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 448         } else {
 449                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 450                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 451         }
 452         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 453         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 454         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 455         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 456         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 457         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 458         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 459         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 460 }
 461
 462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 463 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 464 {
 465         u8 rxval, txval;
 466         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 467
 468         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 469         if (core == 0) {
 470                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 471                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 472         } else {
 473                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 474                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 475         }
 476         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 477         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 478         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 479         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 480         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 481         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 482         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 483         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 484
 485         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 486         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 487
 488         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 489                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 490         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 491                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 492         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 493                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 494         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 495                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 496
 497         if (core == 0) {
 498                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 499                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 500         } else {
 501                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 502                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 503         }
 504
 505         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 506         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 507         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 508
 509         if (core == 0) {
 510                 rxval = 1;
 511                 txval = 8;
 512         } else {
 513                 rxval = 4;
 514                 txval = 2;
 515         }
 516         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 517         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 518 }
 519
 520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 521 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 522 {
 523         int i;
 524         s32 iq;
 525         u32 ii;
 526         u32 qq;
 527         int iq_nbits, qq_nbits;
 528         int arsh, brsh;
 529         u16 tmp, a, b;
 530
 531         struct nphy_iq_est est;
 532         struct b43_phy_n_iq_comp old;
 533         struct b43_phy_n_iq_comp new = { };
 534         bool error = false;
 535
 536         if (mask == 0)
 537                 return;
 538
 539         b43_nphy_rx_iq_coeffs(dev, false, &old);
 540         b43_nphy_rx_iq_coeffs(dev, true, &new);
 541         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 542         new = old;
 543
 544         for (i = 0; i < 2; i++) {
 545                 if (i == 0 && (mask & 1)) {
 546                         iq = est.iq0_prod;
 547                         ii = est.i0_pwr;
 548                         qq = est.q0_pwr;
 549                 } else if (i == 1 && (mask & 2)) {
 550                         iq = est.iq1_prod;
 551                         ii = est.i1_pwr;
 552                         qq = est.q1_pwr;
 553                 } else {
 554                         B43_WARN_ON(1);
 555                         continue;
 556                 }
 557
 558                 if (ii + qq < 2) {
 559                         error = true;
 560                         break;
 561                 }
 562
 563                 iq_nbits = fls(abs(iq));
 564                 qq_nbits = fls(qq);
 565
 566                 arsh = iq_nbits - 20;
 567                 if (arsh >= 0) {
 568                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 569                         tmp = ii >> arsh;
 570                 } else {
 571                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 572                         tmp = ii << -arsh;
 573                 }
 574                 if (tmp == 0) {
 575                         error = true;
 576                         break;
 577                 }
 578                 a /= tmp;
 579
 580                 brsh = qq_nbits - 11;
 581                 if (brsh >= 0) {
 582                         b = (qq << (31 - qq_nbits));
 583                         tmp = ii >> brsh;
 584                 } else {
 585                         b = (qq << (31 - qq_nbits));
 586                         tmp = ii << -brsh;
 587                 }
 588                 if (tmp == 0) {
 589                         error = true;
 590                         break;
 591                 }
 592                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 593
 594                 if (i == 0 && (mask & 0x1)) {
 595                         if (dev->phy.rev >= 3) {
 596                                 new.a0 = a & 0x3FF;
 597                                 new.b0 = b & 0x3FF;
 598                         } else {
 599                                 new.a0 = b & 0x3FF;
 600                                 new.b0 = a & 0x3FF;
 601                         }
 602                 } else if (i == 1 && (mask & 0x2)) {
 603                         if (dev->phy.rev >= 3) {
 604                                 new.a1 = a & 0x3FF;
 605                                 new.b1 = b & 0x3FF;
 606                         } else {
 607                                 new.a1 = b & 0x3FF;
 608                                 new.b1 = a & 0x3FF;
 609                         }
 610                 }
 611         }
 612
 613         if (error)
 614                 new = old;
 615
 616         b43_nphy_rx_iq_coeffs(dev, true, &new);
 617 }
 618
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 620 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 621 {
 622         u16 array[4];
 623         int i;
 624
 625         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 626         for (i = 0; i < 4; i++)
 627                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 628
 629         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 630         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 631         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 632         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 633 }
 634
 635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 636 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 637 {
 638         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 639         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 640 }
 641
 642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 643 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 644 {
 645         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 646         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 647 }
 648
 649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 650 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 651 {
 652         u16 tmp;
 653
 654         if (dev->dev->id.revision == 16)
 655                 b43_mac_suspend(dev);
 656
 657         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 658         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 659                 B43_NPHY_CLASSCTL_WAITEDEN);
 660         tmp &= ~mask;
 661         tmp |= (val & mask);
 662         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 663
 664         if (dev->dev->id.revision == 16)
 665                 b43_mac_enable(dev);
 666
 667         return tmp;
 668 }
 669
 670 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 671 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 672 {
 673         struct b43_phy *phy = &dev->phy;
 674         struct b43_phy_n *nphy = phy->n;
 675
 676         if (enable) {
 677                 u16 clip[] = { 0xFFFF, 0xFFFF };
 678                 if (nphy->deaf_count++ == 0) {
 679                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 680                         b43_nphy_classifier(dev, 0x7, 0);
 681                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 682                         b43_nphy_write_clip_detection(dev, clip);
 683                 }
 684                 b43_nphy_reset_cca(dev);
 685         } else {
 686                 if (--nphy->deaf_count == 0) {
 687                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 688                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 689                 }
 690         }
 691 }
 692
 693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 694 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 695 {
 696         struct b43_phy_n *nphy = dev->phy.n;
 697         u16 tmp;
 698
 699         if (nphy->hang_avoid)
 700                 b43_nphy_stay_in_carrier_search(dev, 1);
 701
 702         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 703         if (tmp & 0x1)
 704                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 705         else if (tmp & 0x2)
 706                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 707
 708         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 709
 710         if (nphy->bb_mult_save & 0x80000000) {
 711                 tmp = nphy->bb_mult_save & 0xFFFF;
 712                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 713                 nphy->bb_mult_save = 0;
 714         }
 715
 716         if (nphy->hang_avoid)
 717                 b43_nphy_stay_in_carrier_search(dev, 0);
 718 }
 719
 720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 721 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 722 {
 723         struct b43_phy_n *nphy = dev->phy.n;
 724
 725         unsigned int channel;
 726         int tone[2] = { 57, 58 };
 727         u32 noise[2] = { 0x3FF, 0x3FF };
 728
 729         B43_WARN_ON(dev->phy.rev < 3);
 730
 731         if (nphy->hang_avoid)
 732                 b43_nphy_stay_in_carrier_search(dev, 1);
 733
 734         /* FIXME: channel = radio_chanspec */
 735
 736         if (nphy->gband_spurwar_en) {
 737                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 738                 if (channel == 11 && dev->phy.is_40mhz)
 739                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 740                 else
 741                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 742                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 743         }
 744
 745         if (nphy->aband_spurwar_en) {
 746                 if (channel == 54) {
 747                         tone[0] = 0x20;
 748                         noise[0] = 0x25F;
 749                 } else if (channel == 38 || channel == 102 || channel == 118) {
 750                         if (0 /* FIXME */) {
 751                                 tone[0] = 0x20;
 752                                 noise[0] = 0x21F;
 753                         } else {
 754                                 tone[0] = 0;
 755                                 noise[0] = 0;
 756                         }
 757                 } else if (channel == 134) {
 758                         tone[0] = 0x20;
 759                         noise[0] = 0x21F;
 760                 } else if (channel == 151) {
 761                         tone[0] = 0x10;
 762                         noise[0] = 0x23F;
 763                 } else if (channel == 153 || channel == 161) {
 764                         tone[0] = 0x30;
 765                         noise[0] = 0x23F;
 766                 } else {
 767                         tone[0] = 0;
 768                         noise[0] = 0;
 769                 }
 770
 771                 if (!tone[0] && !noise[0])
 772                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 773                 else
 774                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 775         }
 776
 777         if (nphy->hang_avoid)
 778                 b43_nphy_stay_in_carrier_search(dev, 0);
 779 }
 780
 781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 782 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 783 {
 784         struct b43_phy_n *nphy = dev->phy.n;
 785         u8 i, j;
 786         u8 code;
 787
 788         /* TODO: for PHY >= 3
 789         s8 *lna1_gain, *lna2_gain;
 790         u8 *gain_db, *gain_bits;
 791         u16 *rfseq_init;
 792         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 793         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 794         */
 795
 796         u8 rfseq_events[3] = { 6, 8, 7 };
 797         u8 rfseq_delays[3] = { 10, 30, 1 };
 798
 799         if (dev->phy.rev >= 3) {
 800                 /* TODO */
 801         } else {
 802                 /* Set Clip 2 detect */
 803                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 804                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 805                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 806                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 807
 808                 /* Set narrowband clip threshold */
 809                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 810                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 811
 812                 if (!dev->phy.is_40mhz) {
 813                         /* Set dwell lengths */
 814                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 815                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 816                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 817                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 818                 }
 819
 820                 /* Set wideband clip 2 threshold */
 821                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 822                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 823                                 21);
 824                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 825                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 826                                 21);
 827
 828                 if (!dev->phy.is_40mhz) {
 829                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 830                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 831                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 832                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 833                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 834                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 835                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 836                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 837                 }
 838
 839                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 840
 841                 if (nphy->gain_boost) {
 842                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 843                             dev->phy.is_40mhz)
 844                                 code = 4;
 845                         else
 846                                 code = 5;
 847                 } else {
 848                         code = dev->phy.is_40mhz ? 6 : 7;
 849                 }
 850
 851                 /* Set HPVGA2 index */
 852                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 853                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 854                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 855                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 856                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 857                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 858
 859                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 860                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 861                                         (code << 8 | 0x7C));
 862                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 863                                         (code << 8 | 0x7C));
 864
 865                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 866
 867                 if (nphy->elna_gain_config) {
 868                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 869                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 870                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 871                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 872                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 873
 874                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 875                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 876                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 877                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 878                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 879
 880                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 881                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 882                                         (code << 8 | 0x74));
 883                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 884                                         (code << 8 | 0x74));
 885                 }
 886
 887                 if (dev->phy.rev == 2) {
 888                         for (i = 0; i < 4; i++) {
 889                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 890                                                 (0x0400 * i) + 0x0020);
 891                                 for (j = 0; j < 21; j++)
 892                                         b43_phy_write(dev,
 893                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 894                         }
 895
 896                         b43_nphy_set_rf_sequence(dev, 5,
 897                                         rfseq_events, rfseq_delays, 3);
 898                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 899                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 900                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 901
 902                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 903                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 904                                                 0xFF80, 4);
 905                 }
 906         }
 907 }
 908
 909 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 910 static void b43_nphy_workarounds(struct b43_wldev *dev)
 911 {
 912         struct ssb_bus *bus = dev->dev->bus;
 913         struct b43_phy *phy = &dev->phy;
 914         struct b43_phy_n *nphy = phy->n;
 915
 916         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 917         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 918
 919         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 920         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 921
 922         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 923                 b43_nphy_classifier(dev, 1, 0);
 924         else
 925                 b43_nphy_classifier(dev, 1, 1);
 926
 927         if (nphy->hang_avoid)
 928                 b43_nphy_stay_in_carrier_search(dev, 1);
 929
 930         b43_phy_set(dev, B43_NPHY_IQFLIP,
 931                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 932
 933         if (dev->phy.rev >= 3) {
 934                 /* TODO */
 935         } else {
 936                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 937                     nphy->band5g_pwrgain) {
 938                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 939                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 940                 } else {
 941                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 942                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 943                 }
 944
 945                 /* TODO: convert to b43_ntab_write? */
 946                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 947                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 948                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 949                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 950                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 951                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 952                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 953                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 954
 955                 if (dev->phy.rev < 2) {
 956                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 957                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 958                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 959                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 960                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 961                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 962                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
 963                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 964                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
 965                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 966                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
 967                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 968                 }
 969
 970                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 971                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 972                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 973                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 974
 975                 if (bus->sprom.boardflags2_lo & 0x100 &&
 976                     bus->boardinfo.type == 0x8B) {
 977                         delays1[0] = 0x1;
 978                         delays1[5] = 0x14;
 979                 }
 980                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
 981                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
 982
 983                 b43_nphy_gain_crtl_workarounds(dev);
 984
 985                 if (dev->phy.rev < 2) {
 986                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
 987                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
 988                 } else if (dev->phy.rev == 2) {
 989                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
 990                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
 991                 }
 992
 993                 if (dev->phy.rev < 2)
 994                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 995                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
 996
 997                 /* Set phase track alpha and beta */
 998                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 999                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1000                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1001                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1002                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1003                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1004
1005                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1006                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1007                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1008                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1009                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1010
1011                 if (dev->phy.rev == 2)
1012                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1013                                         B43_NPHY_FINERX2_CGC_DECGC);
1014         }
1015
1016         if (nphy->hang_avoid)
1017                 b43_nphy_stay_in_carrier_search(dev, 0);
1018 }
1019
1020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1021 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1022                                         bool test)
1023 {
1024         int i;
1025         u16 bw, len, rot, angle;
1026         struct b43_c32 *samples;
1027
1028
1029         bw = (dev->phy.is_40mhz) ? 40 : 20;
1030         len = bw << 3;
1031
1032         if (test) {
1033                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1034                         bw = 82;
1035                 else
1036                         bw = 80;
1037
1038                 if (dev->phy.is_40mhz)
1039                         bw <<= 1;
1040
1041                 len = bw << 1;
1042         }
1043
1044         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1045         rot = (((freq * 36) / bw) << 16) / 100;
1046         angle = 0;
1047
1048         for (i = 0; i < len; i++) {
1049                 samples[i] = b43_cordic(angle);
1050                 angle += rot;
1051                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1052                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1053         }
1054
1055         /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */
1056         kfree(samples);
1057         return len;
1058 }
1059
1060 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1061 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1062                                         u16 wait, bool iqmode, bool dac_test)
1063 {
1064         struct b43_phy_n *nphy = dev->phy.n;
1065         int i;
1066         u16 seq_mode;
1067         u32 tmp;
1068
1069         if (nphy->hang_avoid)
1070                 b43_nphy_stay_in_carrier_search(dev, true);
1071
1072         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1073                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1074                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1075         }
1076
1077         if (!dev->phy.is_40mhz)
1078                 tmp = 0x6464;
1079         else
1080                 tmp = 0x4747;
1081         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1082
1083         if (nphy->hang_avoid)
1084                 b43_nphy_stay_in_carrier_search(dev, false);
1085
1086         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1087
1088         if (loops != 0xFFFF)
1089                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1090         else
1091                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1092
1093         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1094
1095         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1096
1097         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1098         if (iqmode) {
1099                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1100                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1101         } else {
1102                 if (dac_test)
1103                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1104                 else
1105                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1106         }
1107         for (i = 0; i < 100; i++) {
1108                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1109                         i = 0;
1110                         break;
1111                 }
1112                 udelay(10);
1113         }
1114         if (i)
1115                 b43err(dev->wl, "run samples timeout\n");
1116
1117         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1118 }
1119
1120 /*
1121  * Transmits a known value for LO calibration
1122  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1123  */
1124 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1125                                 bool iqmode, bool dac_test)
1126 {
1127         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1128         if (samp == 0)
1129                 return -1;
1130         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1131         return 0;
1132 }
1133
1134 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1135 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1136 {
1137         struct b43_phy_n *nphy = dev->phy.n;
1138         int i, j;
1139         u32 tmp;
1140         u32 cur_real, cur_imag, real_part, imag_part;
1141
1142         u16 buffer[7];
1143
1144         if (nphy->hang_avoid)
1145                 b43_nphy_stay_in_carrier_search(dev, true);
1146
1147         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1148
1149         for (i = 0; i < 2; i++) {
1150                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1151                         (buffer[i * 2 + 1] & 0x3FF);
1152                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1153                                 (((i + 26) << 10) | 320));
1154                 for (j = 0; j < 128; j++) {
1155                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1156                                         ((tmp >> 16) & 0xFFFF));
1157                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1158                                         (tmp & 0xFFFF));
1159                 }
1160         }
1161
1162         for (i = 0; i < 2; i++) {
1163                 tmp = buffer[5 + i];
1164                 real_part = (tmp >> 8) & 0xFF;
1165                 imag_part = (tmp & 0xFF);
1166                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1167                                 (((i + 26) << 10) | 448));
1168
1169                 if (dev->phy.rev >= 3) {
1170                         cur_real = real_part;
1171                         cur_imag = imag_part;
1172                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1173                 }
1174
1175                 for (j = 0; j < 128; j++) {
1176                         if (dev->phy.rev < 3) {
1177                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1178                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1179                                 tmp = ((cur_real & 0xFF) << 8) |
1180                                         (cur_imag & 0xFF);
1181                         }
1182                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1183                                         ((tmp >> 16) & 0xFFFF));
1184                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1185                                         (tmp & 0xFFFF));
1186                 }
1187         }
1188
1189         if (dev->phy.rev >= 3) {
1190                 b43_shm_write16(dev, B43_SHM_SHARED,
1191                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1192                 b43_shm_write16(dev, B43_SHM_SHARED,
1193                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1194         }
1195
1196         if (nphy->hang_avoid)
1197                 b43_nphy_stay_in_carrier_search(dev, false);
1198 }
1199
1200 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1201 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1202                                         u8 *events, u8 *delays, u8 length)
1203 {
1204         struct b43_phy_n *nphy = dev->phy.n;
1205         u8 i;
1206         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1207         u16 offset1 = cmd << 4;
1208         u16 offset2 = offset1 + 0x80;
1209
1210         if (nphy->hang_avoid)
1211                 b43_nphy_stay_in_carrier_search(dev, true);
1212
1213         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1214         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1215
1216         for (i = length; i < 16; i++) {
1217                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1218                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1219         }
1220
1221         if (nphy->hang_avoid)
1222                 b43_nphy_stay_in_carrier_search(dev, false);
1223 }
1224
1225 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1226 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1227                                        enum b43_nphy_rf_sequence seq)
1228 {
1229         static const u16 trigger[] = {
1230                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1231                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1232                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1233                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1234                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1235                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1236         };
1237         int i;
1238         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1239
1240         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1241
1242         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1243                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1244         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1245         for (i = 0; i < 200; i++) {
1246                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1247                         goto ok;
1248                 msleep(1);
1249         }
1250         b43err(dev->wl, "RF sequence status timeout\n");
1251 ok:
1252         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1253 }
1254
1255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1256 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1257                                                 u16 value, u8 core, bool off)
1258 {
1259         int i;
1260         u8 index = fls(field);
1261         u8 addr, en_addr, val_addr;
1262         /* we expect only one bit set */
1263         B43_WARN_ON(field & (~(1 << (index - 1))));
1264
1265         if (dev->phy.rev >= 3) {
1266                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1267                 for (i = 0; i < 2; i++) {
1268                         if (index == 0 || index == 16) {
1269                                 b43err(dev->wl,
1270                                         "Unsupported RF Ctrl Override call\n");
1271                                 return;
1272                         }
1273
1274                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1275                         en_addr = B43_PHY_N((i == 0) ?
1276                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1277                         val_addr = B43_PHY_N((i == 0) ?
1278                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1279
1280                         if (off) {
1281                                 b43_phy_mask(dev, en_addr, ~(field));
1282                                 b43_phy_mask(dev, val_addr,
1283                                                 ~(rf_ctrl->val_mask));
1284                         } else {
1285                                 if (core == 0 || ((1 << core) & i) != 0) {
1286                                         b43_phy_set(dev, en_addr, field);
1287                                         b43_phy_maskset(dev, val_addr,
1288                                                 ~(rf_ctrl->val_mask),
1289                                                 (value << rf_ctrl->val_shift));
1290                                 }
1291                         }
1292                 }
1293         } else {
1294                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1295                 if (off) {
1296                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1297                         value = 0;
1298                 } else {
1299                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1300                 }
1301
1302                 for (i = 0; i < 2; i++) {
1303                         if (index <= 1 || index == 16) {
1304                                 b43err(dev->wl,
1305                                         "Unsupported RF Ctrl Override call\n");
1306                                 return;
1307                         }
1308
1309                         if (index == 2 || index == 10 ||
1310                             (index >= 13 && index <= 15)) {
1311                                 core = 1;
1312                         }
1313
1314                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1315                         addr = B43_PHY_N((i == 0) ?
1316                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1317
1318                         if ((core & (1 << i)) != 0)
1319                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1320                                                 (value << rf_ctrl->shift));
1321
1322                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1323                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1324                                         B43_NPHY_RFCTL_CMD_START);
1325                         udelay(1);
1326                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1327                 }
1328         }
1329 }
1330
1331 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1332 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1333                                                 u16 value, u8 core)
1334 {
1335         u8 i, j;
1336         u16 reg, tmp, val;
1337
1338         B43_WARN_ON(dev->phy.rev < 3);
1339         B43_WARN_ON(field > 4);
1340
1341         for (i = 0; i < 2; i++) {
1342                 if ((core == 1 && i == 1) || (core == 2 && !i))
1343                         continue;
1344
1345                 reg = (i == 0) ?
1346                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1347                 b43_phy_mask(dev, reg, 0xFBFF);
1348
1349                 switch (field) {
1350                 case 0:
1351                         b43_phy_write(dev, reg, 0);
1352                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1353                         break;
1354                 case 1:
1355                         if (!i) {
1356                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1357                                                 0xFC3F, (value << 6));
1358                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1359                                                 0xFFFE, 1);
1360                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1361                                                 B43_NPHY_RFCTL_CMD_START);
1362                                 for (j = 0; j < 100; j++) {
1363                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1364                                                 j = 0;
1365                                                 break;
1366                                         }
1367                                         udelay(10);
1368                                 }
1369                                 if (j)
1370                                         b43err(dev->wl,
1371                                                 "intc override timeout\n");
1372                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1373                                                 0xFFFE);
1374                         } else {
1375                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1376                                                 0xFC3F, (value << 6));
1377                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1378                                                 0xFFFE, 1);
1379                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1380                                                 B43_NPHY_RFCTL_CMD_RXTX);
1381                                 for (j = 0; j < 100; j++) {
1382                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1383                                                 j = 0;
1384                                                 break;
1385                                         }
1386                                         udelay(10);
1387                                 }
1388                                 if (j)
1389                                         b43err(dev->wl,
1390                                                 "intc override timeout\n");
1391                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1392                                                 0xFFFE);
1393                         }
1394                         break;
1395                 case 2:
1396                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1397                                 tmp = 0x0020;
1398                                 val = value << 5;
1399                         } else {
1400                                 tmp = 0x0010;
1401                                 val = value << 4;
1402                         }
1403                         b43_phy_maskset(dev, reg, ~tmp, val);
1404                         break;
1405                 case 3:
1406                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1407                                 tmp = 0x0001;
1408                                 val = value;
1409                         } else {
1410                                 tmp = 0x0004;
1411                                 val = value << 2;
1412                         }
1413                         b43_phy_maskset(dev, reg, ~tmp, val);
1414                         break;
1415                 case 4:
1416                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1417                                 tmp = 0x0002;
1418                                 val = value << 1;
1419                         } else {
1420                                 tmp = 0x0008;
1421                                 val = value << 3;
1422                         }
1423                         b43_phy_maskset(dev, reg, ~tmp, val);
1424                         break;
1425                 }
1426         }
1427 }
1428
1429 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1430 {
1431         unsigned int i;
1432         u16 val;
1433
1434         val = 0x1E1F;
1435         for (i = 0; i < 14; i++) {
1436                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1437                 val -= 0x202;
1438         }
1439         val = 0x3E3F;
1440         for (i = 0; i < 16; i++) {
1441                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1442                 val -= 0x202;
1443         }
1444         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1445 }
1446
1447 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1448 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1449                                        s8 offset, u8 core, u8 rail, u8 type)
1450 {
1451         u16 tmp;
1452         bool core1or5 = (core == 1) || (core == 5);
1453         bool core2or5 = (core == 2) || (core == 5);
1454
1455         offset = clamp_val(offset, -32, 31);
1456         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1457
1458         if (core1or5 && (rail == 0) && (type == 2))
1459                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1460         if (core1or5 && (rail == 1) && (type == 2))
1461                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1462         if (core2or5 && (rail == 0) && (type == 2))
1463                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1464         if (core2or5 && (rail == 1) && (type == 2))
1465                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1466         if (core1or5 && (rail == 0) && (type == 0))
1467                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1468         if (core1or5 && (rail == 1) && (type == 0))
1469                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1470         if (core2or5 && (rail == 0) && (type == 0))
1471                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1472         if (core2or5 && (rail == 1) && (type == 0))
1473                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1474         if (core1or5 && (rail == 0) && (type == 1))
1475                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1476         if (core1or5 && (rail == 1) && (type == 1))
1477                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1478         if (core2or5 && (rail == 0) && (type == 1))
1479                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1480         if (core2or5 && (rail == 1) && (type == 1))
1481                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1482         if (core1or5 && (rail == 0) && (type == 6))
1483                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1484         if (core1or5 && (rail == 1) && (type == 6))
1485                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1486         if (core2or5 && (rail == 0) && (type == 6))
1487                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1488         if (core2or5 && (rail == 1) && (type == 6))
1489                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1490         if (core1or5 && (rail == 0) && (type == 3))
1491                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1492         if (core1or5 && (rail == 1) && (type == 3))
1493                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1494         if (core2or5 && (rail == 0) && (type == 3))
1495                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1496         if (core2or5 && (rail == 1) && (type == 3))
1497                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1498         if (core1or5 && (type == 4))
1499                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1500         if (core2or5 && (type == 4))
1501                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1502         if (core1or5 && (type == 5))
1503                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1504         if (core2or5 && (type == 5))
1505                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1506 }
1507
1508 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1509 {
1510         u16 val;
1511
1512         if (type < 3)
1513                 val = 0;
1514         else if (type == 6)
1515                 val = 1;
1516         else if (type == 3)
1517                 val = 2;
1518         else
1519                 val = 3;
1520
1521         val = (val << 12) | (val << 14);
1522         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1523         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1524
1525         if (type < 3) {
1526                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1527                                 (type + 1) << 4);
1528                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1529                                 (type + 1) << 4);
1530         }
1531
1532         /* TODO use some definitions */
1533         if (code == 0) {
1534                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1535                 if (type < 3) {
1536                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1537                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1538                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1539                         udelay(20);
1540                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1541                 }
1542         } else {
1543                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1544                                 0x3000);
1545                 if (type < 3) {
1546                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1547                                         0xFEC7, 0x0180);
1548                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1549                                         0xEFDC, (code << 1 | 0x1021));
1550                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1551                         udelay(20);
1552                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1553                 }
1554         }
1555 }
1556
1557 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1558 {
1559         struct b43_phy_n *nphy = dev->phy.n;
1560         u8 i;
1561         u16 reg, val;
1562
1563         if (code == 0) {
1564                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1565                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1566                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1567                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1568                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1569                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1570                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1571                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1572         } else {
1573                 for (i = 0; i < 2; i++) {
1574                         if ((code == 1 && i == 1) || (code == 2 && !i))
1575                                 continue;
1576
1577                         reg = (i == 0) ?
1578                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1579                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1580
1581                         if (type < 3) {
1582                                 reg = (i == 0) ?
1583                                         B43_NPHY_AFECTL_C1 :
1584                                         B43_NPHY_AFECTL_C2;
1585                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1586
1587                                 reg = (i == 0) ?
1588                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1589                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1590                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1591
1592                                 if (type == 0)
1593                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1594                                 else if (type == 1)
1595                                         val = 16;
1596                                 else
1597                                         val = 32;
1598                                 b43_phy_set(dev, reg, val);
1599
1600                                 reg = (i == 0) ?
1601                                         B43_NPHY_TXF_40CO_B1S0 :
1602                                         B43_NPHY_TXF_40CO_B32S1;
1603                                 b43_phy_set(dev, reg, 0x0020);
1604                         } else {
1605                                 if (type == 6)
1606                                         val = 0x0100;
1607                                 else if (type == 3)
1608                                         val = 0x0200;
1609                                 else
1610                                         val = 0x0300;
1611
1612                                 reg = (i == 0) ?
1613                                         B43_NPHY_AFECTL_C1 :
1614                                         B43_NPHY_AFECTL_C2;
1615
1616                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1617                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1618
1619                                 if (type != 3 && type != 6) {
1620                                         enum ieee80211_band band =
1621                                                 b43_current_band(dev->wl);
1622
1623                                         if ((nphy->ipa2g_on &&
1624                                                 band == IEEE80211_BAND_2GHZ) ||
1625                                                 (nphy->ipa5g_on &&
1626                                                 band == IEEE80211_BAND_5GHZ))
1627                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1628                                         else
1629                                                 val = 0x11;
1630                                         reg = (i == 0) ? 0x2000 : 0x3000;
1631                                         reg |= B2055_PADDRV;
1632                                         b43_radio_write16(dev, reg, val);
1633
1634                                         reg = (i == 0) ?
1635                                                 B43_NPHY_AFECTL_OVER1 :
1636                                                 B43_NPHY_AFECTL_OVER;
1637                                         b43_phy_set(dev, reg, 0x0200);
1638                                 }
1639                         }
1640                 }
1641         }
1642 }
1643
1644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1645 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1646 {
1647         if (dev->phy.rev >= 3)
1648                 b43_nphy_rev3_rssi_select(dev, code, type);
1649         else
1650                 b43_nphy_rev2_rssi_select(dev, code, type);
1651 }
1652
1653 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1654 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1655 {
1656         int i;
1657         for (i = 0; i < 2; i++) {
1658                 if (type == 2) {
1659                         if (i == 0) {
1660                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1661                                                   0xFC, buf[0]);
1662                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1663                                                   0xFC, buf[1]);
1664                         } else {
1665                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1666                                                   0xFC, buf[2 * i]);
1667                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1668                                                   0xFC, buf[2 * i + 1]);
1669                         }
1670                 } else {
1671                         if (i == 0)
1672                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1673                                                   0xF3, buf[0] << 2);
1674                         else
1675                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1676                                                   0xF3, buf[2 * i + 1] << 2);
1677                 }
1678         }
1679 }
1680
1681 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1682 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1683                                 u8 nsamp)
1684 {
1685         int i;
1686         int out;
1687         u16 save_regs_phy[9];
1688         u16 s[2];
1689
1690         if (dev->phy.rev >= 3) {
1691                 save_regs_phy[0] = b43_phy_read(dev,
1692                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1693                 save_regs_phy[1] = b43_phy_read(dev,
1694                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1695                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1696                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1697                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1698                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1699                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1700                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1701         }
1702
1703         b43_nphy_rssi_select(dev, 5, type);
1704
1705         if (dev->phy.rev < 2) {
1706                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1707                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1708         }
1709
1710         for (i = 0; i < 4; i++)
1711                 buf[i] = 0;
1712
1713         for (i = 0; i < nsamp; i++) {
1714                 if (dev->phy.rev < 2) {
1715                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1716                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1717                 } else {
1718                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1719                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1720                 }
1721
1722                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1723                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1724                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1725                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1726         }
1727         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1728                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1729
1730         if (dev->phy.rev < 2)
1731                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1732
1733         if (dev->phy.rev >= 3) {
1734                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1735                                 save_regs_phy[0]);
1736                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1737                                 save_regs_phy[1]);
1738                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1739                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1740                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1741                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1742                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1743                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1744         }
1745
1746         return out;
1747 }
1748
1749 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1750 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1751 {
1752         int i, j;
1753         u8 state[4];
1754         u8 code, val;
1755         u16 class, override;
1756         u8 regs_save_radio[2];
1757         u16 regs_save_phy[2];
1758         s8 offset[4];
1759
1760         u16 clip_state[2];
1761         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1762         s32 results_min[4] = { };
1763         u8 vcm_final[4] = { };
1764         s32 results[4][4] = { };
1765         s32 miniq[4][2] = { };
1766
1767         if (type == 2) {
1768                 code = 0;
1769                 val = 6;
1770         } else if (type < 2) {
1771                 code = 25;
1772                 val = 4;
1773         } else {
1774                 B43_WARN_ON(1);
1775                 return;
1776         }
1777
1778         class = b43_nphy_classifier(dev, 0, 0);
1779         b43_nphy_classifier(dev, 7, 4);
1780         b43_nphy_read_clip_detection(dev, clip_state);
1781         b43_nphy_write_clip_detection(dev, clip_off);
1782
1783         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1784                 override = 0x140;
1785         else
1786                 override = 0x110;
1787
1788         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1789         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1790         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1791         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1792
1793         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1794         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1795         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1796         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1797
1798         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1799         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1800         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1801         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1802         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1803         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1804
1805         b43_nphy_rssi_select(dev, 5, type);
1806         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1807         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1808
1809         for (i = 0; i < 4; i++) {
1810                 u8 tmp[4];
1811                 for (j = 0; j < 4; j++)
1812                         tmp[j] = i;
1813                 if (type != 1)
1814                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1815                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1816                 if (type < 2)
1817                         for (j = 0; j < 2; j++)
1818                                 miniq[i][j] = min(results[i][2 * j],
1819                                                 results[i][2 * j + 1]);
1820         }
1821
1822         for (i = 0; i < 4; i++) {
1823                 s32 mind = 40;
1824                 u8 minvcm = 0;
1825                 s32 minpoll = 249;
1826                 s32 curr;
1827                 for (j = 0; j < 4; j++) {
1828                         if (type == 2)
1829                                 curr = abs(results[j][i]);
1830                         else
1831                                 curr = abs(miniq[j][i / 2] - code * 8);
1832
1833                         if (curr < mind) {
1834                                 mind = curr;
1835                                 minvcm = j;
1836                         }
1837
1838                         if (results[j][i] < minpoll)
1839                                 minpoll = results[j][i];
1840                 }
1841                 results_min[i] = minpoll;
1842                 vcm_final[i] = minvcm;
1843         }
1844
1845         if (type != 1)
1846                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1847
1848         for (i = 0; i < 4; i++) {
1849                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1850
1851                 if (offset[i] < 0)
1852                         offset[i] = -((abs(offset[i]) + 4) / 8);
1853                 else
1854                         offset[i] = (offset[i] + 4) / 8;
1855
1856                 if (results_min[i] == 248)
1857                         offset[i] = code - 32;
1858
1859                 if (i % 2 == 0)
1860                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1861                                                         type);
1862                 else
1863                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1864                                                         type);
1865         }
1866
1867         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1868         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1869
1870         switch (state[2]) {
1871         case 1:
1872                 b43_nphy_rssi_select(dev, 1, 2);
1873                 break;
1874         case 4:
1875                 b43_nphy_rssi_select(dev, 1, 0);
1876                 break;
1877         case 2:
1878                 b43_nphy_rssi_select(dev, 1, 1);
1879                 break;
1880         default:
1881                 b43_nphy_rssi_select(dev, 1, 1);
1882                 break;
1883         }
1884
1885         switch (state[3]) {
1886         case 1:
1887                 b43_nphy_rssi_select(dev, 2, 2);
1888                 break;
1889         case 4:
1890                 b43_nphy_rssi_select(dev, 2, 0);
1891                 break;
1892         default:
1893                 b43_nphy_rssi_select(dev, 2, 1);
1894                 break;
1895         }
1896
1897         b43_nphy_rssi_select(dev, 0, type);
1898
1899         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1900         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1901         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1902         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1903
1904         b43_nphy_classifier(dev, 7, class);
1905         b43_nphy_write_clip_detection(dev, clip_state);
1906 }
1907
1908 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1909 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1910 {
1911         /* TODO */
1912 }
1913
1914 /*
1915  * RSSI Calibration
1916  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1917  */
1918 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1919 {
1920         if (dev->phy.rev >= 3) {
1921                 b43_nphy_rev3_rssi_cal(dev);
1922         } else {
1923                 b43_nphy_rev2_rssi_cal(dev, 2);
1924                 b43_nphy_rev2_rssi_cal(dev, 0);
1925                 b43_nphy_rev2_rssi_cal(dev, 1);
1926         }
1927 }
1928
1929 /*
1930  * Restore RSSI Calibration
1931  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1932  */
1933 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1934 {
1935         struct b43_phy_n *nphy = dev->phy.n;
1936
1937         u16 *rssical_radio_regs = NULL;
1938         u16 *rssical_phy_regs = NULL;
1939
1940         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1941                 if (!nphy->rssical_chanspec_2G)
1942                         return;
1943                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1944                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1945         } else {
1946                 if (!nphy->rssical_chanspec_5G)
1947                         return;
1948                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1949                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1950         }
1951
1952         /* TODO use some definitions */
1953         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1954         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1955
1956         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1957         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1958         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1959         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1960
1961         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1962         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1963         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1964         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1965
1966         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1967         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1968         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1969         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1970 }
1971
1972 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1973 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1974 {
1975         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1976                 if (dev->phy.rev >= 6) {
1977                         /* TODO If the chip is 47162
1978                                 return txpwrctrl_tx_gain_ipa_rev5 */
1979                         return txpwrctrl_tx_gain_ipa_rev6;
1980                 } else if (dev->phy.rev >= 5) {
1981                         return txpwrctrl_tx_gain_ipa_rev5;
1982                 } else {
1983                         return txpwrctrl_tx_gain_ipa;
1984                 }
1985         } else {
1986                 return txpwrctrl_tx_gain_ipa_5g;
1987         }
1988 }
1989
1990 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1991 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1992 {
1993         struct b43_phy_n *nphy = dev->phy.n;
1994         u16 *save = nphy->tx_rx_cal_radio_saveregs;
1995         u16 tmp;
1996         u8 offset, i;
1997
1998         if (dev->phy.rev >= 3) {
1999             for (i = 0; i < 2; i++) {
2000                 tmp = (i == 0) ? 0x2000 : 0x3000;
2001                 offset = i * 11;
2002
2003                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2004                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2005                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2006                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2007                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2008                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2009                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2010                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2011                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2012                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2013                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2014
2015                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2016                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2017                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2018                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2019                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2020                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2021                         if (nphy->ipa5g_on) {
2022                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2023                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2024                         } else {
2025                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2026                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2027                         }
2028                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2029                 } else {
2030                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2031                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2032                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2033                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2034                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2035                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2036                         if (nphy->ipa2g_on) {
2037                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2038                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2039                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2040                         } else {
2041                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2042                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2043                         }
2044                 }
2045                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2046                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2047                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2048             }
2049         } else {
2050                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2051                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2052
2053                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2054                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2055
2056                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2057                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2058
2059                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2060                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2061
2062                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2063                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2064
2065                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2066                     B43_NPHY_BANDCTL_5GHZ)) {
2067                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2068                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2069                 } else {
2070                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2071                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2072                 }
2073
2074                 if (dev->phy.rev < 2) {
2075                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2076                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2077                 } else {
2078                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2079                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2080                 }
2081         }
2082 }
2083
2084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2085 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2086                                         struct nphy_txgains target,
2087                                         struct nphy_iqcal_params *params)
2088 {
2089         int i, j, indx;
2090         u16 gain;
2091
2092         if (dev->phy.rev >= 3) {
2093                 params->txgm = target.txgm[core];
2094                 params->pga = target.pga[core];
2095                 params->pad = target.pad[core];
2096                 params->ipa = target.ipa[core];
2097                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2098                                         (params->pad << 4) | (params->ipa);
2099                 for (j = 0; j < 5; j++)
2100                         params->ncorr[j] = 0x79;
2101         } else {
2102                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2103                         (target.txgm[core] << 8);
2104
2105                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2106                         1 : 0;
2107                 for (i = 0; i < 9; i++)
2108                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2109                                 break;
2110                 i = min(i, 8);
2111
2112                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2113                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2114                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2115                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2116                                         (params->pad << 2);
2117                 for (j = 0; j < 4; j++)
2118                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2119         }
2120 }
2121
2122 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2123 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2124 {
2125         struct b43_phy_n *nphy = dev->phy.n;
2126         int i;
2127         u16 scale, entry;
2128
2129         u16 tmp = nphy->txcal_bbmult;
2130         if (core == 0)
2131                 tmp >>= 8;
2132         tmp &= 0xff;
2133
2134         for (i = 0; i < 18; i++) {
2135                 scale = (ladder_lo[i].percent * tmp) / 100;
2136                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2137                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2138
2139                 scale = (ladder_iq[i].percent * tmp) / 100;
2140                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2141                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2142         }
2143 }
2144
2145 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2146 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2147 {
2148         int i;
2149         for (i = 0; i < 15; i++)
2150                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2151                                 tbl_tx_filter_coef_rev4[2][i]);
2152 }
2153
2154 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2155 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2156 {
2157         int i, j;
2158         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2159         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2160
2161         for (i = 0; i < 3; i++)
2162                 for (j = 0; j < 15; j++)
2163                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2164                                         tbl_tx_filter_coef_rev4[i][j]);
2165
2166         if (dev->phy.is_40mhz) {
2167                 for (j = 0; j < 15; j++)
2168                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2169                                         tbl_tx_filter_coef_rev4[3][j]);
2170         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2171                 for (j = 0; j < 15; j++)
2172                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2173                                         tbl_tx_filter_coef_rev4[5][j]);
2174         }
2175
2176         if (dev->phy.channel == 14)
2177                 for (j = 0; j < 15; j++)
2178                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2179                                         tbl_tx_filter_coef_rev4[6][j]);
2180 }
2181
2182 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2183 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2184 {
2185         struct b43_phy_n *nphy = dev->phy.n;
2186
2187         u16 curr_gain[2];
2188         struct nphy_txgains target;
2189         const u32 *table = NULL;
2190
2191         if (nphy->txpwrctrl == 0) {
2192                 int i;
2193
2194                 if (nphy->hang_avoid)
2195                         b43_nphy_stay_in_carrier_search(dev, true);
2196                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2197                 if (nphy->hang_avoid)
2198                         b43_nphy_stay_in_carrier_search(dev, false);
2199
2200                 for (i = 0; i < 2; ++i) {
2201                         if (dev->phy.rev >= 3) {
2202                                 target.ipa[i] = curr_gain[i] & 0x000F;
2203                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2204                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2205                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2206                         } else {
2207                                 target.ipa[i] = curr_gain[i] & 0x0003;
2208                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2209                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2210                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2211                         }
2212                 }
2213         } else {
2214                 int i;
2215                 u16 index[2];
2216                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2217                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2218                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2219                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2220                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2221                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2222
2223                 for (i = 0; i < 2; ++i) {
2224                         if (dev->phy.rev >= 3) {
2225                                 enum ieee80211_band band =
2226                                         b43_current_band(dev->wl);
2227
2228                                 if ((nphy->ipa2g_on &&
2229                                      band == IEEE80211_BAND_2GHZ) ||
2230                                     (nphy->ipa5g_on &&
2231                                      band == IEEE80211_BAND_5GHZ)) {
2232                                         table = b43_nphy_get_ipa_gain_table(dev);
2233                                 } else {
2234                                         if (band == IEEE80211_BAND_5GHZ) {
2235                                                 if (dev->phy.rev == 3)
2236                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2237                                                 else if (dev->phy.rev == 4)
2238                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2239                                                 else
2240                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2241                                         } else {
2242                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2243                                         }
2244                                 }
2245
2246                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2247                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2248                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2249                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2250                         } else {
2251                                 table = b43_ntab_tx_gain_rev0_1_2;
2252
2253                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2254                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2255                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2256                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2257                         }
2258                 }
2259         }
2260
2261         return target;
2262 }
2263
2264 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2265 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2266 {
2267         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2268
2269         if (dev->phy.rev >= 3) {
2270                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2271                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2272                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2273                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2274                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2275                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2276                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2277                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2278                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2279                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2280                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2281                 b43_nphy_reset_cca(dev);
2282         } else {
2283                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2284                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2285                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2286                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2287                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2288                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2289                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2290         }
2291 }
2292
2293 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2294 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2295 {
2296         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2297         u16 tmp;
2298
2299         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2300         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2301         if (dev->phy.rev >= 3) {
2302                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2303                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2304
2305                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2306                 regs[2] = tmp;
2307                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2308
2309                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2310                 regs[3] = tmp;
2311                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2312
2313                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2314                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2315
2316                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2317                 regs[5] = tmp;
2318                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2319
2320                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2321                 regs[6] = tmp;
2322                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2323                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2324                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2325
2326                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2327                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2328                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2329
2330                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2331                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2332                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2333                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2334         } else {
2335                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2336                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2337                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2338                 regs[2] = tmp;
2339                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2340                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2341                 regs[3] = tmp;
2342                 tmp |= 0x2000;
2343                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2344                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2345                 regs[4] = tmp;
2346                 tmp |= 0x2000;
2347                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2348                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2349                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2350                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2351                         tmp = 0x0180;
2352                 else
2353                         tmp = 0x0120;
2354                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2355                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2356         }
2357 }
2358
2359 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2360 static void b43_nphy_save_cal(struct b43_wldev *dev)
2361 {
2362         struct b43_phy_n *nphy = dev->phy.n;
2363
2364         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2365         u16 *txcal_radio_regs = NULL;
2366         u8 *iqcal_chanspec;
2367         u16 *table = NULL;
2368
2369         if (nphy->hang_avoid)
2370                 b43_nphy_stay_in_carrier_search(dev, 1);
2371
2372         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2373                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2374                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2375                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2376                 table = nphy->cal_cache.txcal_coeffs_2G;
2377         } else {
2378                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2379                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2380                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2381                 table = nphy->cal_cache.txcal_coeffs_5G;
2382         }
2383
2384         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2385         /* TODO use some definitions */
2386         if (dev->phy.rev >= 3) {
2387                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2388                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2389                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2390                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2391                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2392                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2393                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2394                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2395         } else {
2396                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2397                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2398                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2399                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2400         }
2401         *iqcal_chanspec = nphy->radio_chanspec;
2402         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2403
2404         if (nphy->hang_avoid)
2405                 b43_nphy_stay_in_carrier_search(dev, 0);
2406 }
2407
2408 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2409 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2410 {
2411         struct b43_phy_n *nphy = dev->phy.n;
2412
2413         u16 coef[4];
2414         u16 *loft = NULL;
2415         u16 *table = NULL;
2416
2417         int i;
2418         u16 *txcal_radio_regs = NULL;
2419         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2420
2421         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2422                 if (nphy->iqcal_chanspec_2G == 0)
2423                         return;
2424                 table = nphy->cal_cache.txcal_coeffs_2G;
2425                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2426         } else {
2427                 if (nphy->iqcal_chanspec_5G == 0)
2428                         return;
2429                 table = nphy->cal_cache.txcal_coeffs_5G;
2430                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2431         }
2432
2433         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2434
2435         for (i = 0; i < 4; i++) {
2436                 if (dev->phy.rev >= 3)
2437                         table[i] = coef[i];
2438                 else
2439                         coef[i] = 0;
2440         }
2441
2442         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2443         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2444         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2445
2446         if (dev->phy.rev < 2)
2447                 b43_nphy_tx_iq_workaround(dev);
2448
2449         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2450                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2451                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2452         } else {
2453                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2454                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2455         }
2456
2457         /* TODO use some definitions */
2458         if (dev->phy.rev >= 3) {
2459                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2460                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2461                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2462                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2463                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2464                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2465                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2466                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2467         } else {
2468                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2469                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2470                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2471                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2472         }
2473         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2474 }
2475
2476 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2477 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2478                                 struct nphy_txgains target,
2479                                 bool full, bool mphase)
2480 {
2481         struct b43_phy_n *nphy = dev->phy.n;
2482         int i;
2483         int error = 0;
2484         int freq;
2485         bool avoid = false;
2486         u8 length;
2487         u16 tmp, core, type, count, max, numb, last, cmd;
2488         const u16 *table;
2489         bool phy6or5x;
2490
2491         u16 buffer[11];
2492         u16 diq_start = 0;
2493         u16 save[2];
2494         u16 gain[2];
2495         struct nphy_iqcal_params params[2];
2496         bool updated[2] = { };
2497
2498         b43_nphy_stay_in_carrier_search(dev, true);
2499
2500         if (dev->phy.rev >= 4) {
2501                 avoid = nphy->hang_avoid;
2502                 nphy->hang_avoid = 0;
2503         }
2504
2505         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2506
2507         for (i = 0; i < 2; i++) {
2508                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2509                 gain[i] = params[i].cal_gain;
2510         }
2511
2512         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2513
2514         b43_nphy_tx_cal_radio_setup(dev);
2515         b43_nphy_tx_cal_phy_setup(dev);
2516
2517         phy6or5x = dev->phy.rev >= 6 ||
2518                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2519                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2520         if (phy6or5x) {
2521                 if (dev->phy.is_40mhz) {
2522                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2523                                         tbl_tx_iqlo_cal_loft_ladder_40);
2524                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2525                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2526                 } else {
2527                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2528                                         tbl_tx_iqlo_cal_loft_ladder_20);
2529                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2530                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2531                 }
2532         }
2533
2534         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2535
2536         if (!dev->phy.is_40mhz)
2537                 freq = 2500;
2538         else
2539                 freq = 5000;
2540
2541         if (nphy->mphase_cal_phase_id > 2)
2542                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2543                                         0xFFFF, 0, true, false);
2544         else
2545                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2546
2547         if (error == 0) {
2548                 if (nphy->mphase_cal_phase_id > 2) {
2549                         table = nphy->mphase_txcal_bestcoeffs;
2550                         length = 11;
2551                         if (dev->phy.rev < 3)
2552                                 length -= 2;
2553                 } else {
2554                         if (!full && nphy->txiqlocal_coeffsvalid) {
2555                                 table = nphy->txiqlocal_bestc;
2556                                 length = 11;
2557                                 if (dev->phy.rev < 3)
2558                                         length -= 2;
2559                         } else {
2560                                 full = true;
2561                                 if (dev->phy.rev >= 3) {
2562                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2563                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2564                                 } else {
2565                                         table = tbl_tx_iqlo_cal_startcoefs;
2566                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2567                                 }
2568                         }
2569                 }
2570
2571                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2572
2573                 if (full) {
2574                         if (dev->phy.rev >= 3)
2575                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2576                         else
2577                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2578                 } else {
2579                         if (dev->phy.rev >= 3)
2580                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2581                         else
2582                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2583                 }
2584
2585                 if (mphase) {
2586                         count = nphy->mphase_txcal_cmdidx;
2587                         numb = min(max,
2588                                 (u16)(count + nphy->mphase_txcal_numcmds));
2589                 } else {
2590                         count = 0;
2591                         numb = max;
2592                 }
2593
2594                 for (; count < numb; count++) {
2595                         if (full) {
2596                                 if (dev->phy.rev >= 3)
2597                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2598                                 else
2599                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2600                         } else {
2601                                 if (dev->phy.rev >= 3)
2602                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2603                                 else
2604                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2605                         }
2606
2607                         core = (cmd & 0x3000) >> 12;
2608                         type = (cmd & 0x0F00) >> 8;
2609
2610                         if (phy6or5x && updated[core] == 0) {
2611                                 b43_nphy_update_tx_cal_ladder(dev, core);
2612                                 updated[core] = 1;
2613                         }
2614
2615                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2616                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2617
2618                         if (type == 1 || type == 3 || type == 4) {
2619                                 buffer[0] = b43_ntab_read(dev,
2620                                                 B43_NTAB16(15, 69 + core));
2621                                 diq_start = buffer[0];
2622                                 buffer[0] = 0;
2623                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2624                                                 0);
2625                         }
2626
2627                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2628                         for (i = 0; i < 2000; i++) {
2629                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2630                                 if (tmp & 0xC000)
2631                                         break;
2632                                 udelay(10);
2633                         }
2634
2635                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2636                                                 buffer);
2637                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2638                                                 buffer);
2639
2640                         if (type == 1 || type == 3 || type == 4)
2641                                 buffer[0] = diq_start;
2642                 }
2643
2644                 if (mphase)
2645                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2646
2647                 last = (dev->phy.rev < 3) ? 6 : 7;
2648
2649                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2650                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2651                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2652                         if (dev->phy.rev < 3) {
2653                                 buffer[0] = 0;
2654                                 buffer[1] = 0;
2655                                 buffer[2] = 0;
2656                                 buffer[3] = 0;
2657                         }
2658                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2659                                                 buffer);
2660                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2661                                                 buffer);
2662                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2663                                                 buffer);
2664                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2665                                                 buffer);
2666                         length = 11;
2667                         if (dev->phy.rev < 3)
2668                                 length -= 2;
2669                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2670                                                 nphy->txiqlocal_bestc);
2671                         nphy->txiqlocal_coeffsvalid = true;
2672                         /* TODO: Set nphy->txiqlocal_chanspec to
2673                                 the current channel */
2674                 } else {
2675                         length = 11;
2676                         if (dev->phy.rev < 3)
2677                                 length -= 2;
2678                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2679                                                 nphy->mphase_txcal_bestcoeffs);
2680                 }
2681
2682                 b43_nphy_stop_playback(dev);
2683                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2684         }
2685
2686         b43_nphy_tx_cal_phy_cleanup(dev);
2687         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2688
2689         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2690                 b43_nphy_tx_iq_workaround(dev);
2691
2692         if (dev->phy.rev >= 4)
2693                 nphy->hang_avoid = avoid;
2694
2695         b43_nphy_stay_in_carrier_search(dev, false);
2696
2697         return error;
2698 }
2699
2700 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2701 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2702 {
2703         struct b43_phy_n *nphy = dev->phy.n;
2704         u8 i;
2705         u16 buffer[7];
2706         bool equal = true;
2707
2708         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2709                 return;
2710
2711         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2712         for (i = 0; i < 4; i++) {
2713                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2714                         equal = false;
2715                         break;
2716                 }
2717         }
2718
2719         if (!equal) {
2720                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2721                                         nphy->txiqlocal_bestc);
2722                 for (i = 0; i < 4; i++)
2723                         buffer[i] = 0;
2724                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2725                                         buffer);
2726                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2727                                         &nphy->txiqlocal_bestc[5]);
2728                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2729                                         &nphy->txiqlocal_bestc[5]);
2730         }
2731 }
2732
2733 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2734 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2735                         struct nphy_txgains target, u8 type, bool debug)
2736 {
2737         struct b43_phy_n *nphy = dev->phy.n;
2738         int i, j, index;
2739         u8 rfctl[2];
2740         u8 afectl_core;
2741         u16 tmp[6];
2742         u16 cur_hpf1, cur_hpf2, cur_lna;
2743         u32 real, imag;
2744         enum ieee80211_band band;
2745
2746         u8 use;
2747         u16 cur_hpf;
2748         u16 lna[3] = { 3, 3, 1 };
2749         u16 hpf1[3] = { 7, 2, 0 };
2750         u16 hpf2[3] = { 2, 0, 0 };
2751         u32 power[3] = { };
2752         u16 gain_save[2];
2753         u16 cal_gain[2];
2754         struct nphy_iqcal_params cal_params[2];
2755         struct nphy_iq_est est;
2756         int ret = 0;
2757         bool playtone = true;
2758         int desired = 13;
2759
2760         b43_nphy_stay_in_carrier_search(dev, 1);
2761
2762         if (dev->phy.rev < 2)
2763                 b43_nphy_reapply_tx_cal_coeffs(dev);
2764         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2765         for (i = 0; i < 2; i++) {
2766                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2767                 cal_gain[i] = cal_params[i].cal_gain;
2768         }
2769         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2770
2771         for (i = 0; i < 2; i++) {
2772                 if (i == 0) {
2773                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2774                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2775                         afectl_core = B43_NPHY_AFECTL_C1;
2776                 } else {
2777                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2778                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2779                         afectl_core = B43_NPHY_AFECTL_C2;
2780                 }
2781
2782                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2783                 tmp[2] = b43_phy_read(dev, afectl_core);
2784                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2785                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2786                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2787
2788                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2789                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2790                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2791                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2792                                 (1 - i));
2793                 b43_phy_set(dev, afectl_core, 0x0006);
2794                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2795
2796                 band = b43_current_band(dev->wl);
2797
2798                 if (nphy->rxcalparams & 0xFF000000) {
2799                         if (band == IEEE80211_BAND_5GHZ)
2800                                 b43_phy_write(dev, rfctl[0], 0x140);
2801                         else
2802                                 b43_phy_write(dev, rfctl[0], 0x110);
2803                 } else {
2804                         if (band == IEEE80211_BAND_5GHZ)
2805                                 b43_phy_write(dev, rfctl[0], 0x180);
2806                         else
2807                                 b43_phy_write(dev, rfctl[0], 0x120);
2808                 }
2809
2810                 if (band == IEEE80211_BAND_5GHZ)
2811                         b43_phy_write(dev, rfctl[1], 0x148);
2812                 else
2813                         b43_phy_write(dev, rfctl[1], 0x114);
2814
2815                 if (nphy->rxcalparams & 0x10000) {
2816                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2817                                         (i + 1));
2818                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2819                                         (2 - i));
2820                 }
2821
2822                 for (j = 0; i < 4; j++) {
2823                         if (j < 3) {
2824                                 cur_lna = lna[j];
2825                                 cur_hpf1 = hpf1[j];
2826                                 cur_hpf2 = hpf2[j];
2827                         } else {
2828                                 if (power[1] > 10000) {
2829                                         use = 1;
2830                                         cur_hpf = cur_hpf1;
2831                                         index = 2;
2832                                 } else {
2833                                         if (power[0] > 10000) {
2834                                                 use = 1;
2835                                                 cur_hpf = cur_hpf1;
2836                                                 index = 1;
2837                                         } else {
2838                                                 index = 0;
2839                                                 use = 2;
2840                                                 cur_hpf = cur_hpf2;
2841                                         }
2842                                 }
2843                                 cur_lna = lna[index];
2844                                 cur_hpf1 = hpf1[index];
2845                                 cur_hpf2 = hpf2[index];
2846                                 cur_hpf += desired - hweight32(power[index]);
2847                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2848                                 if (use == 1)
2849                                         cur_hpf1 = cur_hpf;
2850                                 else
2851                                         cur_hpf2 = cur_hpf;
2852                         }
2853
2854                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2855                                         (cur_lna << 2));
2856                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2857                                                                         false);
2858                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2859                         b43_nphy_stop_playback(dev);
2860
2861                         if (playtone) {
2862                                 ret = b43_nphy_tx_tone(dev, 4000,
2863                                                 (nphy->rxcalparams & 0xFFFF),
2864                                                 false, false);
2865                                 playtone = false;
2866                         } else {
2867                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2868                                                         false, false);
2869                         }
2870
2871                         if (ret == 0) {
2872                                 if (j < 3) {
2873                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2874                                                                         false);
2875                                         if (i == 0) {
2876                                                 real = est.i0_pwr;
2877                                                 imag = est.q0_pwr;
2878                                         } else {
2879                                                 real = est.i1_pwr;
2880                                                 imag = est.q1_pwr;
2881                                         }
2882                                         power[i] = ((real + imag) / 1024) + 1;
2883                                 } else {
2884                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2885                                 }
2886                                 b43_nphy_stop_playback(dev);
2887                         }
2888
2889                         if (ret != 0)
2890                                 break;
2891                 }
2892
2893                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2894                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2895                 b43_phy_write(dev, rfctl[1], tmp[5]);
2896                 b43_phy_write(dev, rfctl[0], tmp[4]);
2897                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2898                 b43_phy_write(dev, afectl_core, tmp[2]);
2899                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2900
2901                 if (ret != 0)
2902                         break;
2903         }
2904
2905         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2906         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2907         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2908
2909         b43_nphy_stay_in_carrier_search(dev, 0);
2910
2911         return ret;
2912 }
2913
2914 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2915                         struct nphy_txgains target, u8 type, bool debug)
2916 {
2917         return -1;
2918 }
2919
2920 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2921 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2922                         struct nphy_txgains target, u8 type, bool debug)
2923 {
2924         if (dev->phy.rev >= 3)
2925                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2926         else
2927                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2928 }
2929
2930 /*
2931  * Init N-PHY
2932  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2933  */
2934 int b43_phy_initn(struct b43_wldev *dev)
2935 {
2936         struct ssb_bus *bus = dev->dev->bus;
2937         struct b43_phy *phy = &dev->phy;
2938         struct b43_phy_n *nphy = phy->n;
2939         u8 tx_pwr_state;
2940         struct nphy_txgains target;
2941         u16 tmp;
2942         enum ieee80211_band tmp2;
2943         bool do_rssi_cal;
2944
2945         u16 clip[2];
2946         bool do_cal = false;
2947
2948         if ((dev->phy.rev >= 3) &&
2949            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2950            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2951                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2952         }
2953         nphy->deaf_count = 0;
2954         b43_nphy_tables_init(dev);
2955         nphy->crsminpwr_adjusted = false;
2956         nphy->noisevars_adjusted = false;
2957
2958         /* Clear all overrides */
2959         if (dev->phy.rev >= 3) {
2960                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2961                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2962                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2963                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2964         } else {
2965                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2966         }
2967         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2968         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2969         if (dev->phy.rev < 6) {
2970                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2971                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2972         }
2973         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2974                      ~(B43_NPHY_RFSEQMODE_CAOVER |
2975                        B43_NPHY_RFSEQMODE_TROVER));
2976         if (dev->phy.rev >= 3)
2977                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2978         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2979
2980         if (dev->phy.rev <= 2) {
2981                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2982                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2983                                 ~B43_NPHY_BPHY_CTL3_SCALE,
2984                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2985         }
2986         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2987         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2988
2989         if (bus->sprom.boardflags2_lo & 0x100 ||
2990             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2991              bus->boardinfo.type == 0x8B))
2992                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2993         else
2994                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2995         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2996         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2997         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2998
2999         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3000         b43_nphy_update_txrx_chain(dev);
3001
3002         if (phy->rev < 2) {
3003                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3004                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3005         }
3006
3007         tmp2 = b43_current_band(dev->wl);
3008         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3009             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3010                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3011                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3012                                 nphy->papd_epsilon_offset[0] << 7);
3013                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3014                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3015                                 nphy->papd_epsilon_offset[1] << 7);
3016                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3017         } else if (phy->rev >= 5) {
3018                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3019         }
3020
3021         b43_nphy_workarounds(dev);
3022
3023         /* Reset CCA, in init code it differs a little from standard way */
3024         b43_nphy_bmac_clock_fgc(dev, 1);
3025         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3026         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3027         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3028         b43_nphy_bmac_clock_fgc(dev, 0);
3029
3030         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3031
3032         b43_nphy_pa_override(dev, false);
3033         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3034         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3035         b43_nphy_pa_override(dev, true);
3036
3037         b43_nphy_classifier(dev, 0, 0);
3038         b43_nphy_read_clip_detection(dev, clip);
3039         tx_pwr_state = nphy->txpwrctrl;
3040         /* TODO N PHY TX power control with argument 0
3041                 (turning off power control) */
3042         /* TODO Fix the TX Power Settings */
3043         /* TODO N PHY TX Power Control Idle TSSI */
3044         /* TODO N PHY TX Power Control Setup */
3045
3046         if (phy->rev >= 3) {
3047                 /* TODO */
3048         } else {
3049                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3050                                         b43_ntab_tx_gain_rev0_1_2);
3051                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3052                                         b43_ntab_tx_gain_rev0_1_2);
3053         }
3054
3055         if (nphy->phyrxchain != 3)
3056                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3057         if (nphy->mphase_cal_phase_id > 0)
3058                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3059
3060         do_rssi_cal = false;
3061         if (phy->rev >= 3) {
3062                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3063                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3064                 else
3065                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3066
3067                 if (do_rssi_cal)
3068                         b43_nphy_rssi_cal(dev);
3069                 else
3070                         b43_nphy_restore_rssi_cal(dev);
3071         } else {
3072                 b43_nphy_rssi_cal(dev);
3073         }
3074
3075         if (!((nphy->measure_hold & 0x6) != 0)) {
3076                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3077                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3078                 else
3079                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3080
3081                 if (nphy->mute)
3082                         do_cal = false;
3083
3084                 if (do_cal) {
3085                         target = b43_nphy_get_tx_gains(dev);
3086
3087                         if (nphy->antsel_type == 2)
3088                                 ;/*TODO NPHY Superswitch Init with argument 1*/
3089                         if (nphy->perical != 2) {
3090                                 b43_nphy_rssi_cal(dev);
3091                                 if (phy->rev >= 3) {
3092                                         nphy->cal_orig_pwr_idx[0] =
3093                                             nphy->txpwrindex[0].index_internal;
3094                                         nphy->cal_orig_pwr_idx[1] =
3095                                             nphy->txpwrindex[1].index_internal;
3096                                         /* TODO N PHY Pre Calibrate TX Gain */
3097                                         target = b43_nphy_get_tx_gains(dev);
3098                                 }
3099                         }
3100                 }
3101         }
3102
3103         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3104                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3105                         b43_nphy_save_cal(dev);
3106                 else if (nphy->mphase_cal_phase_id == 0)
3107                         ;/* N PHY Periodic Calibration with argument 3 */
3108         } else {
3109                 b43_nphy_restore_cal(dev);
3110         }
3111
3112         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3113         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3114         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3115         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3116         if (phy->rev >= 3 && phy->rev <= 6)
3117                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3118         b43_nphy_tx_lp_fbw(dev);
3119         if (phy->rev >= 3)
3120                 b43_nphy_spur_workaround(dev);
3121
3122         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3123         return 0;
3124 }
3125
3126 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3127 {
3128         struct b43_phy_n *nphy;
3129
3130         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3131         if (!nphy)
3132                 return -ENOMEM;
3133         dev->phy.n = nphy;
3134
3135         return 0;
3136 }
3137
3138 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3139 {
3140         struct b43_phy *phy = &dev->phy;
3141         struct b43_phy_n *nphy = phy->n;
3142
3143         memset(nphy, 0, sizeof(*nphy));
3144
3145         //TODO init struct b43_phy_n
3146 }
3147
3148 static void b43_nphy_op_free(struct b43_wldev *dev)
3149 {
3150         struct b43_phy *phy = &dev->phy;
3151         struct b43_phy_n *nphy = phy->n;
3152
3153         kfree(nphy);
3154         phy->n = NULL;
3155 }
3156
3157 static int b43_nphy_op_init(struct b43_wldev *dev)
3158 {
3159         return b43_phy_initn(dev);
3160 }
3161
3162 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3163 {
3164 #if B43_DEBUG
3165         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3166                 /* OFDM registers are onnly available on A/G-PHYs */
3167                 b43err(dev->wl, "Invalid OFDM PHY access at "
3168                        "0x%04X on N-PHY\n", offset);
3169                 dump_stack();
3170         }
3171         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3172                 /* Ext-G registers are only available on G-PHYs */
3173                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3174                        "0x%04X on N-PHY\n", offset);
3175                 dump_stack();
3176         }
3177 #endif /* B43_DEBUG */
3178 }
3179
3180 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3181 {
3182         check_phyreg(dev, reg);
3183         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3184         return b43_read16(dev, B43_MMIO_PHY_DATA);
3185 }
3186
3187 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3188 {
3189         check_phyreg(dev, reg);
3190         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3191         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3192 }
3193
3194 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3195 {
3196         /* Register 1 is a 32-bit register. */
3197         B43_WARN_ON(reg == 1);
3198         /* N-PHY needs 0x100 for read access */
3199         reg |= 0x100;
3200
3201         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3202         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3203 }
3204
3205 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3206 {
3207         /* Register 1 is a 32-bit register. */
3208         B43_WARN_ON(reg == 1);
3209
3210         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3211         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3212 }
3213
3214 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3215                                         bool blocked)
3216 {//TODO
3217 }
3218
3219 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3220 {
3221         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3222                       on ? 0 : 0x7FFF);
3223 }
3224
3225 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3226                                       unsigned int new_channel)
3227 {
3228         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3229                 if ((new_channel < 1) || (new_channel > 14))
3230                         return -EINVAL;
3231         } else {
3232                 if (new_channel > 200)
3233                         return -EINVAL;
3234         }
3235
3236         return nphy_channel_switch(dev, new_channel);
3237 }
3238
3239 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3240 {
3241         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3242                 return 1;
3243         return 36;
3244 }
3245
3246 const struct b43_phy_operations b43_phyops_n = {
3247         .allocate               = b43_nphy_op_allocate,
3248         .free                   = b43_nphy_op_free,
3249         .prepare_structs        = b43_nphy_op_prepare_structs,
3250         .init                   = b43_nphy_op_init,
3251         .phy_read               = b43_nphy_op_read,
3252         .phy_write              = b43_nphy_op_write,
3253         .radio_read             = b43_nphy_op_radio_read,
3254         .radio_write            = b43_nphy_op_radio_write,
3255         .software_rfkill        = b43_nphy_op_software_rfkill,
3256         .switch_analog          = b43_nphy_op_switch_analog,
3257         .switch_channel         = b43_nphy_op_switch_channel,
3258         .get_default_chan       = b43_nphy_op_get_default_chan,
3259         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3260         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3261 };