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   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
  76
  77 static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
  78 {
  79         return !chanspec->channel && !chanspec->sideband &&
  80                 !chanspec->b_width && !chanspec->b_freq;
  81 }
  82
  83 static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1,
  84                                         struct b43_chanspec *chanspec2)
  85 {
  86         return (chanspec1->channel == chanspec2->channel &&
  87                 chanspec1->sideband == chanspec2->sideband &&
  88                 chanspec1->b_width == chanspec2->b_width &&
  89                 chanspec1->b_freq == chanspec2->b_freq);
  90 }
  91
  92 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  93 {//TODO
  94 }
  95
  96 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  97 {//TODO
  98 }
  99
 100 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
 101                                                         bool ignore_tssi)
 102 {//TODO
 103         return B43_TXPWR_RES_DONE;
 104 }
 105
 106 static void b43_chantab_radio_upload(struct b43_wldev *dev,
 107                                      const struct b43_nphy_channeltab_entry *e)
 108 {
 109         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
 110         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
 111         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
 112         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
 113         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 114
 115         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 116         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 117         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 118         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 119         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 120
 121         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 122         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 123         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 124         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 125         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 126
 127         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 128         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 129         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 130         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 131         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 132
 133         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 134         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 135         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 136         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 137         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 138
 139         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 140         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 141 }
 142
 143 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 144                                    const struct b43_nphy_channeltab_entry *e)
 145 {
 146         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 147         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 148         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 149         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 150         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 151         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 152 }
 153
 154 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 155 {
 156         //TODO
 157 }
 158
 159
 160 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
 161 static void b43_radio_2055_setup(struct b43_wldev *dev,
 162                                 const struct b43_nphy_channeltab_entry *e)
 163 {
 164         B43_WARN_ON(dev->phy.rev >= 3);
 165
 166         b43_chantab_radio_upload(dev, e);
 167         udelay(50);
 168         b43_radio_write(dev, B2055_VCO_CAL10, 5);
 169         b43_radio_write(dev, B2055_VCO_CAL10, 45);
 170         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 171         b43_radio_write(dev, B2055_VCO_CAL10, 65);
 172         udelay(300);
 173 }
 174
 175 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 176 {
 177         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 178                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 179         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 180                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 181                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 182         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 183                     B43_NPHY_RFCTL_CMD_PORFORCE);
 184 }
 185
 186 static void b43_radio_init2055_post(struct b43_wldev *dev)
 187 {
 188         struct b43_phy_n *nphy = dev->phy.n;
 189         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 190         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 191         int i;
 192         u16 val;
 193         bool workaround = false;
 194
 195         if (sprom->revision < 4)
 196                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 197                                 binfo->type != 0x46D ||
 198                                 binfo->rev < 0x41);
 199         else
 200                 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
 201
 202         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 203         if (workaround) {
 204                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 205                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 206         }
 207         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 208         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 209         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 210         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 211         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 212         msleep(1);
 213         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 214         for (i = 0; i < 200; i++) {
 215                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 216                 if (val & 0x80) {
 217                         i = 0;
 218                         break;
 219                 }
 220                 udelay(10);
 221         }
 222         if (i)
 223                 b43err(dev->wl, "radio post init timeout\n");
 224         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 225         nphy_channel_switch(dev, dev->phy.channel);
 226         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 227         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 228         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 229         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 230         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 231         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 232         if (!nphy->gain_boost) {
 233                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 234                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 235         } else {
 236                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 237                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 238         }
 239         udelay(2);
 240 }
 241
 242 /*
 243  * Initialize a Broadcom 2055 N-radio
 244  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 245  */
 246 static void b43_radio_init2055(struct b43_wldev *dev)
 247 {
 248         b43_radio_init2055_pre(dev);
 249         if (b43_status(dev) < B43_STAT_INITIALIZED)
 250                 b2055_upload_inittab(dev, 0, 1);
 251         else
 252                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 253         b43_radio_init2055_post(dev);
 254 }
 255
 256 /*
 257  * Upload the N-PHY tables.
 258  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 259  */
 260 static void b43_nphy_tables_init(struct b43_wldev *dev)
 261 {
 262         if (dev->phy.rev < 3)
 263                 b43_nphy_rev0_1_2_tables_init(dev);
 264         else
 265                 b43_nphy_rev3plus_tables_init(dev);
 266 }
 267
 268 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 269 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 270 {
 271         struct b43_phy_n *nphy = dev->phy.n;
 272         enum ieee80211_band band;
 273         u16 tmp;
 274
 275         if (!enable) {
 276                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 277                                                        B43_NPHY_RFCTL_INTC1);
 278                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 279                                                        B43_NPHY_RFCTL_INTC2);
 280                 band = b43_current_band(dev->wl);
 281                 if (dev->phy.rev >= 3) {
 282                         if (band == IEEE80211_BAND_5GHZ)
 283                                 tmp = 0x600;
 284                         else
 285                                 tmp = 0x480;
 286                 } else {
 287                         if (band == IEEE80211_BAND_5GHZ)
 288                                 tmp = 0x180;
 289                         else
 290                                 tmp = 0x120;
 291                 }
 292                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 293                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 294         } else {
 295                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 296                                 nphy->rfctrl_intc1_save);
 297                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 298                                 nphy->rfctrl_intc2_save);
 299         }
 300 }
 301
 302 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 303 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 304 {
 305         struct b43_phy_n *nphy = dev->phy.n;
 306         u16 tmp;
 307         enum ieee80211_band band = b43_current_band(dev->wl);
 308         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 309                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 310
 311         if (dev->phy.rev >= 3) {
 312                 if (ipa) {
 313                         tmp = 4;
 314                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 315                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 316                 }
 317
 318                 tmp = 1;
 319                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 320                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 321         }
 322 }
 323
 324 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 325 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 326 {
 327         u32 tmslow;
 328
 329         if (dev->phy.type != B43_PHYTYPE_N)
 330                 return;
 331
 332         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 333         if (force)
 334                 tmslow |= SSB_TMSLOW_FGC;
 335         else
 336                 tmslow &= ~SSB_TMSLOW_FGC;
 337         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 338 }
 339
 340 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 341 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 342 {
 343         u16 bbcfg;
 344
 345         b43_nphy_bmac_clock_fgc(dev, 1);
 346         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 347         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 348         udelay(1);
 349         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 350         b43_nphy_bmac_clock_fgc(dev, 0);
 351         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 352 }
 353
 354 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 355 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 356 {
 357         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 358
 359         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 360         if (preamble == 1)
 361                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 362         else
 363                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 364
 365         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 366 }
 367
 368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 369 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 370 {
 371         struct b43_phy_n *nphy = dev->phy.n;
 372
 373         bool override = false;
 374         u16 chain = 0x33;
 375
 376         if (nphy->txrx_chain == 0) {
 377                 chain = 0x11;
 378                 override = true;
 379         } else if (nphy->txrx_chain == 1) {
 380                 chain = 0x22;
 381                 override = true;
 382         }
 383
 384         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 385                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 386                         chain);
 387
 388         if (override)
 389                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 390                                 B43_NPHY_RFSEQMODE_CAOVER);
 391         else
 392                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 393                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 394 }
 395
 396 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 397 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 398                                 u16 samps, u8 time, bool wait)
 399 {
 400         int i;
 401         u16 tmp;
 402
 403         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 404         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 405         if (wait)
 406                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 407         else
 408                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 409
 410         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 411
 412         for (i = 1000; i; i--) {
 413                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 414                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 415                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 416                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 417                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 418                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 419                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 420                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 421
 422                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 423                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 424                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 425                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 426                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 427                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 428                         return;
 429                 }
 430                 udelay(10);
 431         }
 432         memset(est, 0, sizeof(*est));
 433 }
 434
 435 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 436 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 437                                         struct b43_phy_n_iq_comp *pcomp)
 438 {
 439         if (write) {
 440                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 441                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 442                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 443                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 444         } else {
 445                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 446                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 447                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 448                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 449         }
 450 }
 451
 452 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 453 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 454 {
 455         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 456
 457         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 458         if (core == 0) {
 459                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 460                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 461         } else {
 462                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 463                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 464         }
 465         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 466         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 467         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 468         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 469         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 470         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 471         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 472         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 473 }
 474
 475 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 476 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 477 {
 478         u8 rxval, txval;
 479         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 480
 481         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 482         if (core == 0) {
 483                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 484                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 485         } else {
 486                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 487                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 488         }
 489         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 490         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 491         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 492         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 493         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 494         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 495         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 496         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 497
 498         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 499         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 500
 501         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 502                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 503         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 504                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 505         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 506                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 507         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 508                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 509
 510         if (core == 0) {
 511                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 512                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 513         } else {
 514                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 515                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 516         }
 517
 518         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 519         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 520         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 521
 522         if (core == 0) {
 523                 rxval = 1;
 524                 txval = 8;
 525         } else {
 526                 rxval = 4;
 527                 txval = 2;
 528         }
 529         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 530         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 531 }
 532
 533 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 534 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 535 {
 536         int i;
 537         s32 iq;
 538         u32 ii;
 539         u32 qq;
 540         int iq_nbits, qq_nbits;
 541         int arsh, brsh;
 542         u16 tmp, a, b;
 543
 544         struct nphy_iq_est est;
 545         struct b43_phy_n_iq_comp old;
 546         struct b43_phy_n_iq_comp new = { };
 547         bool error = false;
 548
 549         if (mask == 0)
 550                 return;
 551
 552         b43_nphy_rx_iq_coeffs(dev, false, &old);
 553         b43_nphy_rx_iq_coeffs(dev, true, &new);
 554         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 555         new = old;
 556
 557         for (i = 0; i < 2; i++) {
 558                 if (i == 0 && (mask & 1)) {
 559                         iq = est.iq0_prod;
 560                         ii = est.i0_pwr;
 561                         qq = est.q0_pwr;
 562                 } else if (i == 1 && (mask & 2)) {
 563                         iq = est.iq1_prod;
 564                         ii = est.i1_pwr;
 565                         qq = est.q1_pwr;
 566                 } else {
 567                         B43_WARN_ON(1);
 568                         continue;
 569                 }
 570
 571                 if (ii + qq < 2) {
 572                         error = true;
 573                         break;
 574                 }
 575
 576                 iq_nbits = fls(abs(iq));
 577                 qq_nbits = fls(qq);
 578
 579                 arsh = iq_nbits - 20;
 580                 if (arsh >= 0) {
 581                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 582                         tmp = ii >> arsh;
 583                 } else {
 584                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 585                         tmp = ii << -arsh;
 586                 }
 587                 if (tmp == 0) {
 588                         error = true;
 589                         break;
 590                 }
 591                 a /= tmp;
 592
 593                 brsh = qq_nbits - 11;
 594                 if (brsh >= 0) {
 595                         b = (qq << (31 - qq_nbits));
 596                         tmp = ii >> brsh;
 597                 } else {
 598                         b = (qq << (31 - qq_nbits));
 599                         tmp = ii << -brsh;
 600                 }
 601                 if (tmp == 0) {
 602                         error = true;
 603                         break;
 604                 }
 605                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 606
 607                 if (i == 0 && (mask & 0x1)) {
 608                         if (dev->phy.rev >= 3) {
 609                                 new.a0 = a & 0x3FF;
 610                                 new.b0 = b & 0x3FF;
 611                         } else {
 612                                 new.a0 = b & 0x3FF;
 613                                 new.b0 = a & 0x3FF;
 614                         }
 615                 } else if (i == 1 && (mask & 0x2)) {
 616                         if (dev->phy.rev >= 3) {
 617                                 new.a1 = a & 0x3FF;
 618                                 new.b1 = b & 0x3FF;
 619                         } else {
 620                                 new.a1 = b & 0x3FF;
 621                                 new.b1 = a & 0x3FF;
 622                         }
 623                 }
 624         }
 625
 626         if (error)
 627                 new = old;
 628
 629         b43_nphy_rx_iq_coeffs(dev, true, &new);
 630 }
 631
 632 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 633 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 634 {
 635         u16 array[4];
 636         int i;
 637
 638         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 639         for (i = 0; i < 4; i++)
 640                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 641
 642         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 643         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 644         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 645         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 646 }
 647
 648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 649 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 650 {
 651         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 652         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 653 }
 654
 655 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 656 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 657 {
 658         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 659         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 660 }
 661
 662 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 663 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 664 {
 665         if (dev->phy.rev >= 3) {
 666                 if (!init)
 667                         return;
 668                 if (0 /* FIXME */) {
 669                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 670                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 671                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 672                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 673                 }
 674         } else {
 675                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 676                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 677
 678                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 679                                         0xFC00);
 680                 b43_write32(dev, B43_MMIO_MACCTL,
 681                         b43_read32(dev, B43_MMIO_MACCTL) &
 682                         ~B43_MACCTL_GPOUTSMSK);
 683                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 684                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 685                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 686                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 687
 688                 if (init) {
 689                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 690                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 691                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 692                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 693                 }
 694         }
 695 }
 696
 697 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 698 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 699 {
 700         u16 tmp;
 701
 702         if (dev->dev->id.revision == 16)
 703                 b43_mac_suspend(dev);
 704
 705         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 706         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 707                 B43_NPHY_CLASSCTL_WAITEDEN);
 708         tmp &= ~mask;
 709         tmp |= (val & mask);
 710         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 711
 712         if (dev->dev->id.revision == 16)
 713                 b43_mac_enable(dev);
 714
 715         return tmp;
 716 }
 717
 718 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 719 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 720 {
 721         struct b43_phy *phy = &dev->phy;
 722         struct b43_phy_n *nphy = phy->n;
 723
 724         if (enable) {
 725                 u16 clip[] = { 0xFFFF, 0xFFFF };
 726                 if (nphy->deaf_count++ == 0) {
 727                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 728                         b43_nphy_classifier(dev, 0x7, 0);
 729                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 730                         b43_nphy_write_clip_detection(dev, clip);
 731                 }
 732                 b43_nphy_reset_cca(dev);
 733         } else {
 734                 if (--nphy->deaf_count == 0) {
 735                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 736                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 737                 }
 738         }
 739 }
 740
 741 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 742 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 743 {
 744         struct b43_phy_n *nphy = dev->phy.n;
 745         u16 tmp;
 746
 747         if (nphy->hang_avoid)
 748                 b43_nphy_stay_in_carrier_search(dev, 1);
 749
 750         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 751         if (tmp & 0x1)
 752                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 753         else if (tmp & 0x2)
 754                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 755
 756         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 757
 758         if (nphy->bb_mult_save & 0x80000000) {
 759                 tmp = nphy->bb_mult_save & 0xFFFF;
 760                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 761                 nphy->bb_mult_save = 0;
 762         }
 763
 764         if (nphy->hang_avoid)
 765                 b43_nphy_stay_in_carrier_search(dev, 0);
 766 }
 767
 768 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 769 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 770 {
 771         struct b43_phy_n *nphy = dev->phy.n;
 772
 773         u8 channel = nphy->radio_chanspec.channel;
 774         int tone[2] = { 57, 58 };
 775         u32 noise[2] = { 0x3FF, 0x3FF };
 776
 777         B43_WARN_ON(dev->phy.rev < 3);
 778
 779         if (nphy->hang_avoid)
 780                 b43_nphy_stay_in_carrier_search(dev, 1);
 781
 782         if (nphy->gband_spurwar_en) {
 783                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 784                 if (channel == 11 && dev->phy.is_40mhz)
 785                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 786                 else
 787                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 788                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 789         }
 790
 791         if (nphy->aband_spurwar_en) {
 792                 if (channel == 54) {
 793                         tone[0] = 0x20;
 794                         noise[0] = 0x25F;
 795                 } else if (channel == 38 || channel == 102 || channel == 118) {
 796                         if (0 /* FIXME */) {
 797                                 tone[0] = 0x20;
 798                                 noise[0] = 0x21F;
 799                         } else {
 800                                 tone[0] = 0;
 801                                 noise[0] = 0;
 802                         }
 803                 } else if (channel == 134) {
 804                         tone[0] = 0x20;
 805                         noise[0] = 0x21F;
 806                 } else if (channel == 151) {
 807                         tone[0] = 0x10;
 808                         noise[0] = 0x23F;
 809                 } else if (channel == 153 || channel == 161) {
 810                         tone[0] = 0x30;
 811                         noise[0] = 0x23F;
 812                 } else {
 813                         tone[0] = 0;
 814                         noise[0] = 0;
 815                 }
 816
 817                 if (!tone[0] && !noise[0])
 818                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 819                 else
 820                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 821         }
 822
 823         if (nphy->hang_avoid)
 824                 b43_nphy_stay_in_carrier_search(dev, 0);
 825 }
 826
 827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
 828 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
 829 {
 830         struct b43_phy_n *nphy = dev->phy.n;
 831
 832         u8 i;
 833         s16 tmp;
 834         u16 data[4];
 835         s16 gain[2];
 836         u16 minmax[2];
 837         u16 lna_gain[4] = { -2, 10, 19, 25 };
 838
 839         if (nphy->hang_avoid)
 840                 b43_nphy_stay_in_carrier_search(dev, 1);
 841
 842         if (nphy->gain_boost) {
 843                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 844                         gain[0] = 6;
 845                         gain[1] = 6;
 846                 } else {
 847                         tmp = 40370 - 315 * nphy->radio_chanspec.channel;
 848                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
 849                         tmp = 23242 - 224 * nphy->radio_chanspec.channel;
 850                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
 851                 }
 852         } else {
 853                 gain[0] = 0;
 854                 gain[1] = 0;
 855         }
 856
 857         for (i = 0; i < 2; i++) {
 858                 if (nphy->elna_gain_config) {
 859                         data[0] = 19 + gain[i];
 860                         data[1] = 25 + gain[i];
 861                         data[2] = 25 + gain[i];
 862                         data[3] = 25 + gain[i];
 863                 } else {
 864                         data[0] = lna_gain[0] + gain[i];
 865                         data[1] = lna_gain[1] + gain[i];
 866                         data[2] = lna_gain[2] + gain[i];
 867                         data[3] = lna_gain[3] + gain[i];
 868                 }
 869                 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
 870
 871                 minmax[i] = 23 + gain[i];
 872         }
 873
 874         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
 875                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
 876         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
 877                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
 878
 879         if (nphy->hang_avoid)
 880                 b43_nphy_stay_in_carrier_search(dev, 0);
 881 }
 882
 883 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 884 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 885 {
 886         struct b43_phy_n *nphy = dev->phy.n;
 887         u8 i, j;
 888         u8 code;
 889
 890         /* TODO: for PHY >= 3
 891         s8 *lna1_gain, *lna2_gain;
 892         u8 *gain_db, *gain_bits;
 893         u16 *rfseq_init;
 894         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 895         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 896         */
 897
 898         u8 rfseq_events[3] = { 6, 8, 7 };
 899         u8 rfseq_delays[3] = { 10, 30, 1 };
 900
 901         if (dev->phy.rev >= 3) {
 902                 /* TODO */
 903         } else {
 904                 /* Set Clip 2 detect */
 905                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 906                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 907                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 908                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 909
 910                 /* Set narrowband clip threshold */
 911                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 912                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 913
 914                 if (!dev->phy.is_40mhz) {
 915                         /* Set dwell lengths */
 916                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 917                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 918                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 919                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 920                 }
 921
 922                 /* Set wideband clip 2 threshold */
 923                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 924                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 925                                 21);
 926                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 927                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 928                                 21);
 929
 930                 if (!dev->phy.is_40mhz) {
 931                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 932                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 933                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 934                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 935                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 936                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 937                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 938                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 939                 }
 940
 941                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 942
 943                 if (nphy->gain_boost) {
 944                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 945                             dev->phy.is_40mhz)
 946                                 code = 4;
 947                         else
 948                                 code = 5;
 949                 } else {
 950                         code = dev->phy.is_40mhz ? 6 : 7;
 951                 }
 952
 953                 /* Set HPVGA2 index */
 954                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 955                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 956                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 957                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 958                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 959                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 960
 961                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 962                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 963                                         (code << 8 | 0x7C));
 964                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 965                                         (code << 8 | 0x7C));
 966
 967                 b43_nphy_adjust_lna_gain_table(dev);
 968
 969                 if (nphy->elna_gain_config) {
 970                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 971                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 972                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 973                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 974                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 975
 976                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 977                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 978                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 979                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 980                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 981
 982                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 983                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 984                                         (code << 8 | 0x74));
 985                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 986                                         (code << 8 | 0x74));
 987                 }
 988
 989                 if (dev->phy.rev == 2) {
 990                         for (i = 0; i < 4; i++) {
 991                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 992                                                 (0x0400 * i) + 0x0020);
 993                                 for (j = 0; j < 21; j++)
 994                                         b43_phy_write(dev,
 995                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 996                         }
 997
 998                         b43_nphy_set_rf_sequence(dev, 5,
 999                                         rfseq_events, rfseq_delays, 3);
1000                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1001                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
1002                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1003
1004                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1005                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1006                                                 0xFF80, 4);
1007                 }
1008         }
1009 }
1010
1011 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1012 static void b43_nphy_workarounds(struct b43_wldev *dev)
1013 {
1014         struct ssb_bus *bus = dev->dev->bus;
1015         struct b43_phy *phy = &dev->phy;
1016         struct b43_phy_n *nphy = phy->n;
1017
1018         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1019         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1020
1021         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1022         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1023
1024         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1025                 b43_nphy_classifier(dev, 1, 0);
1026         else
1027                 b43_nphy_classifier(dev, 1, 1);
1028
1029         if (nphy->hang_avoid)
1030                 b43_nphy_stay_in_carrier_search(dev, 1);
1031
1032         b43_phy_set(dev, B43_NPHY_IQFLIP,
1033                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1034
1035         if (dev->phy.rev >= 3) {
1036                 /* TODO */
1037         } else {
1038                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1039                     nphy->band5g_pwrgain) {
1040                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1041                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1042                 } else {
1043                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1044                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1045                 }
1046
1047                 /* TODO: convert to b43_ntab_write? */
1048                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1049                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1050                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1051                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1052                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1053                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1054                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1055                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1056
1057                 if (dev->phy.rev < 2) {
1058                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1059                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1060                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1061                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1062                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1063                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1064                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1065                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1066                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1067                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1068                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1069                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1070                 }
1071
1072                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1073                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1074                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1075                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1076
1077                 if (bus->sprom.boardflags2_lo & 0x100 &&
1078                     bus->boardinfo.type == 0x8B) {
1079                         delays1[0] = 0x1;
1080                         delays1[5] = 0x14;
1081                 }
1082                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1083                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1084
1085                 b43_nphy_gain_crtl_workarounds(dev);
1086
1087                 if (dev->phy.rev < 2) {
1088                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1089                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1090                 } else if (dev->phy.rev == 2) {
1091                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1092                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1093                 }
1094
1095                 if (dev->phy.rev < 2)
1096                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1097                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1098
1099                 /* Set phase track alpha and beta */
1100                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1101                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1102                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1103                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1104                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1105                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1106
1107                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1108                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1109                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1110                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1111                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1112
1113                 if (dev->phy.rev == 2)
1114                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1115                                         B43_NPHY_FINERX2_CGC_DECGC);
1116         }
1117
1118         if (nphy->hang_avoid)
1119                 b43_nphy_stay_in_carrier_search(dev, 0);
1120 }
1121
1122 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1123 static int b43_nphy_load_samples(struct b43_wldev *dev,
1124                                         struct b43_c32 *samples, u16 len) {
1125         struct b43_phy_n *nphy = dev->phy.n;
1126         u16 i;
1127         u32 *data;
1128
1129         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1130         if (!data) {
1131                 b43err(dev->wl, "allocation for samples loading failed\n");
1132                 return -ENOMEM;
1133         }
1134         if (nphy->hang_avoid)
1135                 b43_nphy_stay_in_carrier_search(dev, 1);
1136
1137         for (i = 0; i < len; i++) {
1138                 data[i] = (samples[i].i & 0x3FF << 10);
1139                 data[i] |= samples[i].q & 0x3FF;
1140         }
1141         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1142
1143         kfree(data);
1144         if (nphy->hang_avoid)
1145                 b43_nphy_stay_in_carrier_search(dev, 0);
1146         return 0;
1147 }
1148
1149 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1150 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1151                                         bool test)
1152 {
1153         int i;
1154         u16 bw, len, rot, angle;
1155         struct b43_c32 *samples;
1156
1157
1158         bw = (dev->phy.is_40mhz) ? 40 : 20;
1159         len = bw << 3;
1160
1161         if (test) {
1162                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1163                         bw = 82;
1164                 else
1165                         bw = 80;
1166
1167                 if (dev->phy.is_40mhz)
1168                         bw <<= 1;
1169
1170                 len = bw << 1;
1171         }
1172
1173         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1174         if (!samples) {
1175                 b43err(dev->wl, "allocation for samples generation failed\n");
1176                 return 0;
1177         }
1178         rot = (((freq * 36) / bw) << 16) / 100;
1179         angle = 0;
1180
1181         for (i = 0; i < len; i++) {
1182                 samples[i] = b43_cordic(angle);
1183                 angle += rot;
1184                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1185                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1186         }
1187
1188         i = b43_nphy_load_samples(dev, samples, len);
1189         kfree(samples);
1190         return (i < 0) ? 0 : len;
1191 }
1192
1193 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1194 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1195                                         u16 wait, bool iqmode, bool dac_test)
1196 {
1197         struct b43_phy_n *nphy = dev->phy.n;
1198         int i;
1199         u16 seq_mode;
1200         u32 tmp;
1201
1202         if (nphy->hang_avoid)
1203                 b43_nphy_stay_in_carrier_search(dev, true);
1204
1205         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1206                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1207                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1208         }
1209
1210         if (!dev->phy.is_40mhz)
1211                 tmp = 0x6464;
1212         else
1213                 tmp = 0x4747;
1214         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1215
1216         if (nphy->hang_avoid)
1217                 b43_nphy_stay_in_carrier_search(dev, false);
1218
1219         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1220
1221         if (loops != 0xFFFF)
1222                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1223         else
1224                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1225
1226         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1227
1228         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1229
1230         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1231         if (iqmode) {
1232                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1233                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1234         } else {
1235                 if (dac_test)
1236                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1237                 else
1238                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1239         }
1240         for (i = 0; i < 100; i++) {
1241                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1242                         i = 0;
1243                         break;
1244                 }
1245                 udelay(10);
1246         }
1247         if (i)
1248                 b43err(dev->wl, "run samples timeout\n");
1249
1250         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1251 }
1252
1253 /*
1254  * Transmits a known value for LO calibration
1255  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1256  */
1257 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1258                                 bool iqmode, bool dac_test)
1259 {
1260         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1261         if (samp == 0)
1262                 return -1;
1263         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1264         return 0;
1265 }
1266
1267 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1268 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1269 {
1270         struct b43_phy_n *nphy = dev->phy.n;
1271         int i, j;
1272         u32 tmp;
1273         u32 cur_real, cur_imag, real_part, imag_part;
1274
1275         u16 buffer[7];
1276
1277         if (nphy->hang_avoid)
1278                 b43_nphy_stay_in_carrier_search(dev, true);
1279
1280         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1281
1282         for (i = 0; i < 2; i++) {
1283                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1284                         (buffer[i * 2 + 1] & 0x3FF);
1285                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1286                                 (((i + 26) << 10) | 320));
1287                 for (j = 0; j < 128; j++) {
1288                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1289                                         ((tmp >> 16) & 0xFFFF));
1290                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1291                                         (tmp & 0xFFFF));
1292                 }
1293         }
1294
1295         for (i = 0; i < 2; i++) {
1296                 tmp = buffer[5 + i];
1297                 real_part = (tmp >> 8) & 0xFF;
1298                 imag_part = (tmp & 0xFF);
1299                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1300                                 (((i + 26) << 10) | 448));
1301
1302                 if (dev->phy.rev >= 3) {
1303                         cur_real = real_part;
1304                         cur_imag = imag_part;
1305                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1306                 }
1307
1308                 for (j = 0; j < 128; j++) {
1309                         if (dev->phy.rev < 3) {
1310                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1311                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1312                                 tmp = ((cur_real & 0xFF) << 8) |
1313                                         (cur_imag & 0xFF);
1314                         }
1315                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1316                                         ((tmp >> 16) & 0xFFFF));
1317                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1318                                         (tmp & 0xFFFF));
1319                 }
1320         }
1321
1322         if (dev->phy.rev >= 3) {
1323                 b43_shm_write16(dev, B43_SHM_SHARED,
1324                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1325                 b43_shm_write16(dev, B43_SHM_SHARED,
1326                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1327         }
1328
1329         if (nphy->hang_avoid)
1330                 b43_nphy_stay_in_carrier_search(dev, false);
1331 }
1332
1333 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1334 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1335                                         u8 *events, u8 *delays, u8 length)
1336 {
1337         struct b43_phy_n *nphy = dev->phy.n;
1338         u8 i;
1339         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1340         u16 offset1 = cmd << 4;
1341         u16 offset2 = offset1 + 0x80;
1342
1343         if (nphy->hang_avoid)
1344                 b43_nphy_stay_in_carrier_search(dev, true);
1345
1346         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1347         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1348
1349         for (i = length; i < 16; i++) {
1350                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1351                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1352         }
1353
1354         if (nphy->hang_avoid)
1355                 b43_nphy_stay_in_carrier_search(dev, false);
1356 }
1357
1358 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1359 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1360                                        enum b43_nphy_rf_sequence seq)
1361 {
1362         static const u16 trigger[] = {
1363                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1364                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1365                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1366                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1367                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1368                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1369         };
1370         int i;
1371         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1372
1373         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1374
1375         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1376                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1377         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1378         for (i = 0; i < 200; i++) {
1379                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1380                         goto ok;
1381                 msleep(1);
1382         }
1383         b43err(dev->wl, "RF sequence status timeout\n");
1384 ok:
1385         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1386 }
1387
1388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1389 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1390                                                 u16 value, u8 core, bool off)
1391 {
1392         int i;
1393         u8 index = fls(field);
1394         u8 addr, en_addr, val_addr;
1395         /* we expect only one bit set */
1396         B43_WARN_ON(field & (~(1 << (index - 1))));
1397
1398         if (dev->phy.rev >= 3) {
1399                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1400                 for (i = 0; i < 2; i++) {
1401                         if (index == 0 || index == 16) {
1402                                 b43err(dev->wl,
1403                                         "Unsupported RF Ctrl Override call\n");
1404                                 return;
1405                         }
1406
1407                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1408                         en_addr = B43_PHY_N((i == 0) ?
1409                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1410                         val_addr = B43_PHY_N((i == 0) ?
1411                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1412
1413                         if (off) {
1414                                 b43_phy_mask(dev, en_addr, ~(field));
1415                                 b43_phy_mask(dev, val_addr,
1416                                                 ~(rf_ctrl->val_mask));
1417                         } else {
1418                                 if (core == 0 || ((1 << core) & i) != 0) {
1419                                         b43_phy_set(dev, en_addr, field);
1420                                         b43_phy_maskset(dev, val_addr,
1421                                                 ~(rf_ctrl->val_mask),
1422                                                 (value << rf_ctrl->val_shift));
1423                                 }
1424                         }
1425                 }
1426         } else {
1427                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1428                 if (off) {
1429                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1430                         value = 0;
1431                 } else {
1432                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1433                 }
1434
1435                 for (i = 0; i < 2; i++) {
1436                         if (index <= 1 || index == 16) {
1437                                 b43err(dev->wl,
1438                                         "Unsupported RF Ctrl Override call\n");
1439                                 return;
1440                         }
1441
1442                         if (index == 2 || index == 10 ||
1443                             (index >= 13 && index <= 15)) {
1444                                 core = 1;
1445                         }
1446
1447                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1448                         addr = B43_PHY_N((i == 0) ?
1449                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1450
1451                         if ((core & (1 << i)) != 0)
1452                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1453                                                 (value << rf_ctrl->shift));
1454
1455                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1456                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1457                                         B43_NPHY_RFCTL_CMD_START);
1458                         udelay(1);
1459                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1460                 }
1461         }
1462 }
1463
1464 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1465 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1466                                                 u16 value, u8 core)
1467 {
1468         u8 i, j;
1469         u16 reg, tmp, val;
1470
1471         B43_WARN_ON(dev->phy.rev < 3);
1472         B43_WARN_ON(field > 4);
1473
1474         for (i = 0; i < 2; i++) {
1475                 if ((core == 1 && i == 1) || (core == 2 && !i))
1476                         continue;
1477
1478                 reg = (i == 0) ?
1479                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1480                 b43_phy_mask(dev, reg, 0xFBFF);
1481
1482                 switch (field) {
1483                 case 0:
1484                         b43_phy_write(dev, reg, 0);
1485                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1486                         break;
1487                 case 1:
1488                         if (!i) {
1489                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1490                                                 0xFC3F, (value << 6));
1491                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1492                                                 0xFFFE, 1);
1493                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1494                                                 B43_NPHY_RFCTL_CMD_START);
1495                                 for (j = 0; j < 100; j++) {
1496                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1497                                                 j = 0;
1498                                                 break;
1499                                         }
1500                                         udelay(10);
1501                                 }
1502                                 if (j)
1503                                         b43err(dev->wl,
1504                                                 "intc override timeout\n");
1505                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1506                                                 0xFFFE);
1507                         } else {
1508                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1509                                                 0xFC3F, (value << 6));
1510                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1511                                                 0xFFFE, 1);
1512                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1513                                                 B43_NPHY_RFCTL_CMD_RXTX);
1514                                 for (j = 0; j < 100; j++) {
1515                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1516                                                 j = 0;
1517                                                 break;
1518                                         }
1519                                         udelay(10);
1520                                 }
1521                                 if (j)
1522                                         b43err(dev->wl,
1523                                                 "intc override timeout\n");
1524                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1525                                                 0xFFFE);
1526                         }
1527                         break;
1528                 case 2:
1529                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1530                                 tmp = 0x0020;
1531                                 val = value << 5;
1532                         } else {
1533                                 tmp = 0x0010;
1534                                 val = value << 4;
1535                         }
1536                         b43_phy_maskset(dev, reg, ~tmp, val);
1537                         break;
1538                 case 3:
1539                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1540                                 tmp = 0x0001;
1541                                 val = value;
1542                         } else {
1543                                 tmp = 0x0004;
1544                                 val = value << 2;
1545                         }
1546                         b43_phy_maskset(dev, reg, ~tmp, val);
1547                         break;
1548                 case 4:
1549                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1550                                 tmp = 0x0002;
1551                                 val = value << 1;
1552                         } else {
1553                                 tmp = 0x0008;
1554                                 val = value << 3;
1555                         }
1556                         b43_phy_maskset(dev, reg, ~tmp, val);
1557                         break;
1558                 }
1559         }
1560 }
1561
1562 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1563 {
1564         unsigned int i;
1565         u16 val;
1566
1567         val = 0x1E1F;
1568         for (i = 0; i < 14; i++) {
1569                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1570                 val -= 0x202;
1571         }
1572         val = 0x3E3F;
1573         for (i = 0; i < 16; i++) {
1574                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1575                 val -= 0x202;
1576         }
1577         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1578 }
1579
1580 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1581 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1582                                        s8 offset, u8 core, u8 rail, u8 type)
1583 {
1584         u16 tmp;
1585         bool core1or5 = (core == 1) || (core == 5);
1586         bool core2or5 = (core == 2) || (core == 5);
1587
1588         offset = clamp_val(offset, -32, 31);
1589         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1590
1591         if (core1or5 && (rail == 0) && (type == 2))
1592                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1593         if (core1or5 && (rail == 1) && (type == 2))
1594                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1595         if (core2or5 && (rail == 0) && (type == 2))
1596                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1597         if (core2or5 && (rail == 1) && (type == 2))
1598                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1599         if (core1or5 && (rail == 0) && (type == 0))
1600                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1601         if (core1or5 && (rail == 1) && (type == 0))
1602                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1603         if (core2or5 && (rail == 0) && (type == 0))
1604                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1605         if (core2or5 && (rail == 1) && (type == 0))
1606                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1607         if (core1or5 && (rail == 0) && (type == 1))
1608                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1609         if (core1or5 && (rail == 1) && (type == 1))
1610                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1611         if (core2or5 && (rail == 0) && (type == 1))
1612                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1613         if (core2or5 && (rail == 1) && (type == 1))
1614                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1615         if (core1or5 && (rail == 0) && (type == 6))
1616                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1617         if (core1or5 && (rail == 1) && (type == 6))
1618                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1619         if (core2or5 && (rail == 0) && (type == 6))
1620                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1621         if (core2or5 && (rail == 1) && (type == 6))
1622                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1623         if (core1or5 && (rail == 0) && (type == 3))
1624                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1625         if (core1or5 && (rail == 1) && (type == 3))
1626                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1627         if (core2or5 && (rail == 0) && (type == 3))
1628                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1629         if (core2or5 && (rail == 1) && (type == 3))
1630                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1631         if (core1or5 && (type == 4))
1632                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1633         if (core2or5 && (type == 4))
1634                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1635         if (core1or5 && (type == 5))
1636                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1637         if (core2or5 && (type == 5))
1638                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1639 }
1640
1641 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1642 {
1643         u16 val;
1644
1645         if (type < 3)
1646                 val = 0;
1647         else if (type == 6)
1648                 val = 1;
1649         else if (type == 3)
1650                 val = 2;
1651         else
1652                 val = 3;
1653
1654         val = (val << 12) | (val << 14);
1655         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1656         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1657
1658         if (type < 3) {
1659                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1660                                 (type + 1) << 4);
1661                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1662                                 (type + 1) << 4);
1663         }
1664
1665         /* TODO use some definitions */
1666         if (code == 0) {
1667                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1668                 if (type < 3) {
1669                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1670                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1671                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1672                         udelay(20);
1673                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1674                 }
1675         } else {
1676                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1677                                 0x3000);
1678                 if (type < 3) {
1679                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1680                                         0xFEC7, 0x0180);
1681                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1682                                         0xEFDC, (code << 1 | 0x1021));
1683                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1684                         udelay(20);
1685                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1686                 }
1687         }
1688 }
1689
1690 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1691 {
1692         struct b43_phy_n *nphy = dev->phy.n;
1693         u8 i;
1694         u16 reg, val;
1695
1696         if (code == 0) {
1697                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1698                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1699                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1700                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1701                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1702                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1703                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1704                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1705         } else {
1706                 for (i = 0; i < 2; i++) {
1707                         if ((code == 1 && i == 1) || (code == 2 && !i))
1708                                 continue;
1709
1710                         reg = (i == 0) ?
1711                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1712                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1713
1714                         if (type < 3) {
1715                                 reg = (i == 0) ?
1716                                         B43_NPHY_AFECTL_C1 :
1717                                         B43_NPHY_AFECTL_C2;
1718                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1719
1720                                 reg = (i == 0) ?
1721                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1722                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1723                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1724
1725                                 if (type == 0)
1726                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1727                                 else if (type == 1)
1728                                         val = 16;
1729                                 else
1730                                         val = 32;
1731                                 b43_phy_set(dev, reg, val);
1732
1733                                 reg = (i == 0) ?
1734                                         B43_NPHY_TXF_40CO_B1S0 :
1735                                         B43_NPHY_TXF_40CO_B32S1;
1736                                 b43_phy_set(dev, reg, 0x0020);
1737                         } else {
1738                                 if (type == 6)
1739                                         val = 0x0100;
1740                                 else if (type == 3)
1741                                         val = 0x0200;
1742                                 else
1743                                         val = 0x0300;
1744
1745                                 reg = (i == 0) ?
1746                                         B43_NPHY_AFECTL_C1 :
1747                                         B43_NPHY_AFECTL_C2;
1748
1749                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1750                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1751
1752                                 if (type != 3 && type != 6) {
1753                                         enum ieee80211_band band =
1754                                                 b43_current_band(dev->wl);
1755
1756                                         if ((nphy->ipa2g_on &&
1757                                                 band == IEEE80211_BAND_2GHZ) ||
1758                                                 (nphy->ipa5g_on &&
1759                                                 band == IEEE80211_BAND_5GHZ))
1760                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1761                                         else
1762                                                 val = 0x11;
1763                                         reg = (i == 0) ? 0x2000 : 0x3000;
1764                                         reg |= B2055_PADDRV;
1765                                         b43_radio_write16(dev, reg, val);
1766
1767                                         reg = (i == 0) ?
1768                                                 B43_NPHY_AFECTL_OVER1 :
1769                                                 B43_NPHY_AFECTL_OVER;
1770                                         b43_phy_set(dev, reg, 0x0200);
1771                                 }
1772                         }
1773                 }
1774         }
1775 }
1776
1777 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1778 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1779 {
1780         if (dev->phy.rev >= 3)
1781                 b43_nphy_rev3_rssi_select(dev, code, type);
1782         else
1783                 b43_nphy_rev2_rssi_select(dev, code, type);
1784 }
1785
1786 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1787 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1788 {
1789         int i;
1790         for (i = 0; i < 2; i++) {
1791                 if (type == 2) {
1792                         if (i == 0) {
1793                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1794                                                   0xFC, buf[0]);
1795                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1796                                                   0xFC, buf[1]);
1797                         } else {
1798                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1799                                                   0xFC, buf[2 * i]);
1800                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1801                                                   0xFC, buf[2 * i + 1]);
1802                         }
1803                 } else {
1804                         if (i == 0)
1805                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1806                                                   0xF3, buf[0] << 2);
1807                         else
1808                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1809                                                   0xF3, buf[2 * i + 1] << 2);
1810                 }
1811         }
1812 }
1813
1814 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1815 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1816                                 u8 nsamp)
1817 {
1818         int i;
1819         int out;
1820         u16 save_regs_phy[9];
1821         u16 s[2];
1822
1823         if (dev->phy.rev >= 3) {
1824                 save_regs_phy[0] = b43_phy_read(dev,
1825                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1826                 save_regs_phy[1] = b43_phy_read(dev,
1827                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1828                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1829                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1830                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1831                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1832                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1833                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1834         }
1835
1836         b43_nphy_rssi_select(dev, 5, type);
1837
1838         if (dev->phy.rev < 2) {
1839                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1840                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1841         }
1842
1843         for (i = 0; i < 4; i++)
1844                 buf[i] = 0;
1845
1846         for (i = 0; i < nsamp; i++) {
1847                 if (dev->phy.rev < 2) {
1848                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1849                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1850                 } else {
1851                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1852                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1853                 }
1854
1855                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1856                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1857                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1858                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1859         }
1860         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1861                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1862
1863         if (dev->phy.rev < 2)
1864                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1865
1866         if (dev->phy.rev >= 3) {
1867                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1868                                 save_regs_phy[0]);
1869                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1870                                 save_regs_phy[1]);
1871                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1872                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1873                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1874                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1875                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1876                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1877         }
1878
1879         return out;
1880 }
1881
1882 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1883 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1884 {
1885         int i, j;
1886         u8 state[4];
1887         u8 code, val;
1888         u16 class, override;
1889         u8 regs_save_radio[2];
1890         u16 regs_save_phy[2];
1891         s8 offset[4];
1892
1893         u16 clip_state[2];
1894         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1895         s32 results_min[4] = { };
1896         u8 vcm_final[4] = { };
1897         s32 results[4][4] = { };
1898         s32 miniq[4][2] = { };
1899
1900         if (type == 2) {
1901                 code = 0;
1902                 val = 6;
1903         } else if (type < 2) {
1904                 code = 25;
1905                 val = 4;
1906         } else {
1907                 B43_WARN_ON(1);
1908                 return;
1909         }
1910
1911         class = b43_nphy_classifier(dev, 0, 0);
1912         b43_nphy_classifier(dev, 7, 4);
1913         b43_nphy_read_clip_detection(dev, clip_state);
1914         b43_nphy_write_clip_detection(dev, clip_off);
1915
1916         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1917                 override = 0x140;
1918         else
1919                 override = 0x110;
1920
1921         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1922         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1923         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1924         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1925
1926         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1927         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1928         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1929         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1930
1931         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1932         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1933         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1934         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1935         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1936         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1937
1938         b43_nphy_rssi_select(dev, 5, type);
1939         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1940         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1941
1942         for (i = 0; i < 4; i++) {
1943                 u8 tmp[4];
1944                 for (j = 0; j < 4; j++)
1945                         tmp[j] = i;
1946                 if (type != 1)
1947                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1948                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1949                 if (type < 2)
1950                         for (j = 0; j < 2; j++)
1951                                 miniq[i][j] = min(results[i][2 * j],
1952                                                 results[i][2 * j + 1]);
1953         }
1954
1955         for (i = 0; i < 4; i++) {
1956                 s32 mind = 40;
1957                 u8 minvcm = 0;
1958                 s32 minpoll = 249;
1959                 s32 curr;
1960                 for (j = 0; j < 4; j++) {
1961                         if (type == 2)
1962                                 curr = abs(results[j][i]);
1963                         else
1964                                 curr = abs(miniq[j][i / 2] - code * 8);
1965
1966                         if (curr < mind) {
1967                                 mind = curr;
1968                                 minvcm = j;
1969                         }
1970
1971                         if (results[j][i] < minpoll)
1972                                 minpoll = results[j][i];
1973                 }
1974                 results_min[i] = minpoll;
1975                 vcm_final[i] = minvcm;
1976         }
1977
1978         if (type != 1)
1979                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1980
1981         for (i = 0; i < 4; i++) {
1982                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1983
1984                 if (offset[i] < 0)
1985                         offset[i] = -((abs(offset[i]) + 4) / 8);
1986                 else
1987                         offset[i] = (offset[i] + 4) / 8;
1988
1989                 if (results_min[i] == 248)
1990                         offset[i] = code - 32;
1991
1992                 if (i % 2 == 0)
1993                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1994                                                         type);
1995                 else
1996                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1997                                                         type);
1998         }
1999
2000         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2001         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2002
2003         switch (state[2]) {
2004         case 1:
2005                 b43_nphy_rssi_select(dev, 1, 2);
2006                 break;
2007         case 4:
2008                 b43_nphy_rssi_select(dev, 1, 0);
2009                 break;
2010         case 2:
2011                 b43_nphy_rssi_select(dev, 1, 1);
2012                 break;
2013         default:
2014                 b43_nphy_rssi_select(dev, 1, 1);
2015                 break;
2016         }
2017
2018         switch (state[3]) {
2019         case 1:
2020                 b43_nphy_rssi_select(dev, 2, 2);
2021                 break;
2022         case 4:
2023                 b43_nphy_rssi_select(dev, 2, 0);
2024                 break;
2025         default:
2026                 b43_nphy_rssi_select(dev, 2, 1);
2027                 break;
2028         }
2029
2030         b43_nphy_rssi_select(dev, 0, type);
2031
2032         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2033         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2034         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2035         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2036
2037         b43_nphy_classifier(dev, 7, class);
2038         b43_nphy_write_clip_detection(dev, clip_state);
2039 }
2040
2041 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2042 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2043 {
2044         /* TODO */
2045 }
2046
2047 /*
2048  * RSSI Calibration
2049  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2050  */
2051 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2052 {
2053         if (dev->phy.rev >= 3) {
2054                 b43_nphy_rev3_rssi_cal(dev);
2055         } else {
2056                 b43_nphy_rev2_rssi_cal(dev, 2);
2057                 b43_nphy_rev2_rssi_cal(dev, 0);
2058                 b43_nphy_rev2_rssi_cal(dev, 1);
2059         }
2060 }
2061
2062 /*
2063  * Restore RSSI Calibration
2064  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2065  */
2066 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2067 {
2068         struct b43_phy_n *nphy = dev->phy.n;
2069
2070         u16 *rssical_radio_regs = NULL;
2071         u16 *rssical_phy_regs = NULL;
2072
2073         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2074                 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G))
2075                         return;
2076                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2077                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2078         } else {
2079                 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G))
2080                         return;
2081                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2082                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2083         }
2084
2085         /* TODO use some definitions */
2086         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2087         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2088
2089         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2090         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2091         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2092         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2093
2094         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2095         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2096         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2097         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2098
2099         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2100         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2101         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2102         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2103 }
2104
2105 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2106 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2107 {
2108         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2109                 if (dev->phy.rev >= 6) {
2110                         /* TODO If the chip is 47162
2111                                 return txpwrctrl_tx_gain_ipa_rev5 */
2112                         return txpwrctrl_tx_gain_ipa_rev6;
2113                 } else if (dev->phy.rev >= 5) {
2114                         return txpwrctrl_tx_gain_ipa_rev5;
2115                 } else {
2116                         return txpwrctrl_tx_gain_ipa;
2117                 }
2118         } else {
2119                 return txpwrctrl_tx_gain_ipa_5g;
2120         }
2121 }
2122
2123 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2124 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2125 {
2126         struct b43_phy_n *nphy = dev->phy.n;
2127         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2128         u16 tmp;
2129         u8 offset, i;
2130
2131         if (dev->phy.rev >= 3) {
2132             for (i = 0; i < 2; i++) {
2133                 tmp = (i == 0) ? 0x2000 : 0x3000;
2134                 offset = i * 11;
2135
2136                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2137                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2138                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2139                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2140                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2141                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2142                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2143                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2144                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2145                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2146                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2147
2148                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2149                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2150                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2151                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2152                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2153                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2154                         if (nphy->ipa5g_on) {
2155                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2156                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2157                         } else {
2158                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2159                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2160                         }
2161                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2162                 } else {
2163                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2164                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2165                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2166                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2167                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2168                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2169                         if (nphy->ipa2g_on) {
2170                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2171                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2172                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2173                         } else {
2174                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2175                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2176                         }
2177                 }
2178                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2179                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2180                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2181             }
2182         } else {
2183                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2184                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2185
2186                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2187                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2188
2189                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2190                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2191
2192                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2193                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2194
2195                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2196                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2197
2198                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2199                     B43_NPHY_BANDCTL_5GHZ)) {
2200                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2201                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2202                 } else {
2203                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2204                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2205                 }
2206
2207                 if (dev->phy.rev < 2) {
2208                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2209                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2210                 } else {
2211                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2212                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2213                 }
2214         }
2215 }
2216
2217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2218 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2219                                         struct nphy_txgains target,
2220                                         struct nphy_iqcal_params *params)
2221 {
2222         int i, j, indx;
2223         u16 gain;
2224
2225         if (dev->phy.rev >= 3) {
2226                 params->txgm = target.txgm[core];
2227                 params->pga = target.pga[core];
2228                 params->pad = target.pad[core];
2229                 params->ipa = target.ipa[core];
2230                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2231                                         (params->pad << 4) | (params->ipa);
2232                 for (j = 0; j < 5; j++)
2233                         params->ncorr[j] = 0x79;
2234         } else {
2235                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2236                         (target.txgm[core] << 8);
2237
2238                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2239                         1 : 0;
2240                 for (i = 0; i < 9; i++)
2241                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2242                                 break;
2243                 i = min(i, 8);
2244
2245                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2246                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2247                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2248                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2249                                         (params->pad << 2);
2250                 for (j = 0; j < 4; j++)
2251                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2252         }
2253 }
2254
2255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2256 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2257 {
2258         struct b43_phy_n *nphy = dev->phy.n;
2259         int i;
2260         u16 scale, entry;
2261
2262         u16 tmp = nphy->txcal_bbmult;
2263         if (core == 0)
2264                 tmp >>= 8;
2265         tmp &= 0xff;
2266
2267         for (i = 0; i < 18; i++) {
2268                 scale = (ladder_lo[i].percent * tmp) / 100;
2269                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2270                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2271
2272                 scale = (ladder_iq[i].percent * tmp) / 100;
2273                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2274                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2275         }
2276 }
2277
2278 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2279 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2280 {
2281         int i;
2282         for (i = 0; i < 15; i++)
2283                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2284                                 tbl_tx_filter_coef_rev4[2][i]);
2285 }
2286
2287 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2288 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2289 {
2290         int i, j;
2291         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2292         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2293
2294         for (i = 0; i < 3; i++)
2295                 for (j = 0; j < 15; j++)
2296                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2297                                         tbl_tx_filter_coef_rev4[i][j]);
2298
2299         if (dev->phy.is_40mhz) {
2300                 for (j = 0; j < 15; j++)
2301                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2302                                         tbl_tx_filter_coef_rev4[3][j]);
2303         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2304                 for (j = 0; j < 15; j++)
2305                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2306                                         tbl_tx_filter_coef_rev4[5][j]);
2307         }
2308
2309         if (dev->phy.channel == 14)
2310                 for (j = 0; j < 15; j++)
2311                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2312                                         tbl_tx_filter_coef_rev4[6][j]);
2313 }
2314
2315 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2316 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2317 {
2318         struct b43_phy_n *nphy = dev->phy.n;
2319
2320         u16 curr_gain[2];
2321         struct nphy_txgains target;
2322         const u32 *table = NULL;
2323
2324         if (nphy->txpwrctrl == 0) {
2325                 int i;
2326
2327                 if (nphy->hang_avoid)
2328                         b43_nphy_stay_in_carrier_search(dev, true);
2329                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2330                 if (nphy->hang_avoid)
2331                         b43_nphy_stay_in_carrier_search(dev, false);
2332
2333                 for (i = 0; i < 2; ++i) {
2334                         if (dev->phy.rev >= 3) {
2335                                 target.ipa[i] = curr_gain[i] & 0x000F;
2336                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2337                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2338                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2339                         } else {
2340                                 target.ipa[i] = curr_gain[i] & 0x0003;
2341                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2342                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2343                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2344                         }
2345                 }
2346         } else {
2347                 int i;
2348                 u16 index[2];
2349                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2350                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2351                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2352                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2353                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2354                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2355
2356                 for (i = 0; i < 2; ++i) {
2357                         if (dev->phy.rev >= 3) {
2358                                 enum ieee80211_band band =
2359                                         b43_current_band(dev->wl);
2360
2361                                 if ((nphy->ipa2g_on &&
2362                                      band == IEEE80211_BAND_2GHZ) ||
2363                                     (nphy->ipa5g_on &&
2364                                      band == IEEE80211_BAND_5GHZ)) {
2365                                         table = b43_nphy_get_ipa_gain_table(dev);
2366                                 } else {
2367                                         if (band == IEEE80211_BAND_5GHZ) {
2368                                                 if (dev->phy.rev == 3)
2369                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2370                                                 else if (dev->phy.rev == 4)
2371                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2372                                                 else
2373                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2374                                         } else {
2375                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2376                                         }
2377                                 }
2378
2379                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2380                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2381                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2382                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2383                         } else {
2384                                 table = b43_ntab_tx_gain_rev0_1_2;
2385
2386                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2387                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2388                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2389                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2390                         }
2391                 }
2392         }
2393
2394         return target;
2395 }
2396
2397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2398 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2399 {
2400         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2401
2402         if (dev->phy.rev >= 3) {
2403                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2404                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2405                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2406                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2407                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2408                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2409                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2410                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2411                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2412                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2413                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2414                 b43_nphy_reset_cca(dev);
2415         } else {
2416                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2417                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2418                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2419                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2420                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2421                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2422                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2423         }
2424 }
2425
2426 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2427 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2428 {
2429         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2430         u16 tmp;
2431
2432         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2433         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2434         if (dev->phy.rev >= 3) {
2435                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2436                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2437
2438                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2439                 regs[2] = tmp;
2440                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2441
2442                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2443                 regs[3] = tmp;
2444                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2445
2446                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2447                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2448
2449                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2450                 regs[5] = tmp;
2451                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2452
2453                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2454                 regs[6] = tmp;
2455                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2456                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2457                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2458
2459                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2460                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2461                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2462
2463                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2464                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2465                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2466                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2467         } else {
2468                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2469                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2470                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2471                 regs[2] = tmp;
2472                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2473                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2474                 regs[3] = tmp;
2475                 tmp |= 0x2000;
2476                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2477                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2478                 regs[4] = tmp;
2479                 tmp |= 0x2000;
2480                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2481                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2482                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2483                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2484                         tmp = 0x0180;
2485                 else
2486                         tmp = 0x0120;
2487                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2488                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2489         }
2490 }
2491
2492 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2493 static void b43_nphy_save_cal(struct b43_wldev *dev)
2494 {
2495         struct b43_phy_n *nphy = dev->phy.n;
2496
2497         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2498         u16 *txcal_radio_regs = NULL;
2499         struct b43_chanspec *iqcal_chanspec;
2500         u16 *table = NULL;
2501
2502         if (nphy->hang_avoid)
2503                 b43_nphy_stay_in_carrier_search(dev, 1);
2504
2505         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2506                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2507                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2508                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2509                 table = nphy->cal_cache.txcal_coeffs_2G;
2510         } else {
2511                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2512                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2513                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2514                 table = nphy->cal_cache.txcal_coeffs_5G;
2515         }
2516
2517         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2518         /* TODO use some definitions */
2519         if (dev->phy.rev >= 3) {
2520                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2521                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2522                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2523                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2524                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2525                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2526                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2527                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2528         } else {
2529                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2530                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2531                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2532                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2533         }
2534         *iqcal_chanspec = nphy->radio_chanspec;
2535         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2536
2537         if (nphy->hang_avoid)
2538                 b43_nphy_stay_in_carrier_search(dev, 0);
2539 }
2540
2541 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2542 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2543 {
2544         struct b43_phy_n *nphy = dev->phy.n;
2545
2546         u16 coef[4];
2547         u16 *loft = NULL;
2548         u16 *table = NULL;
2549
2550         int i;
2551         u16 *txcal_radio_regs = NULL;
2552         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2553
2554         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2555                 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G))
2556                         return;
2557                 table = nphy->cal_cache.txcal_coeffs_2G;
2558                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2559         } else {
2560                 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G))
2561                         return;
2562                 table = nphy->cal_cache.txcal_coeffs_5G;
2563                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2564         }
2565
2566         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2567
2568         for (i = 0; i < 4; i++) {
2569                 if (dev->phy.rev >= 3)
2570                         table[i] = coef[i];
2571                 else
2572                         coef[i] = 0;
2573         }
2574
2575         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2576         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2577         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2578
2579         if (dev->phy.rev < 2)
2580                 b43_nphy_tx_iq_workaround(dev);
2581
2582         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2583                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2584                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2585         } else {
2586                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2587                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2588         }
2589
2590         /* TODO use some definitions */
2591         if (dev->phy.rev >= 3) {
2592                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2593                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2594                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2595                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2596                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2597                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2598                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2599                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2600         } else {
2601                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2602                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2603                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2604                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2605         }
2606         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2607 }
2608
2609 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2610 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2611                                 struct nphy_txgains target,
2612                                 bool full, bool mphase)
2613 {
2614         struct b43_phy_n *nphy = dev->phy.n;
2615         int i;
2616         int error = 0;
2617         int freq;
2618         bool avoid = false;
2619         u8 length;
2620         u16 tmp, core, type, count, max, numb, last, cmd;
2621         const u16 *table;
2622         bool phy6or5x;
2623
2624         u16 buffer[11];
2625         u16 diq_start = 0;
2626         u16 save[2];
2627         u16 gain[2];
2628         struct nphy_iqcal_params params[2];
2629         bool updated[2] = { };
2630
2631         b43_nphy_stay_in_carrier_search(dev, true);
2632
2633         if (dev->phy.rev >= 4) {
2634                 avoid = nphy->hang_avoid;
2635                 nphy->hang_avoid = 0;
2636         }
2637
2638         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2639
2640         for (i = 0; i < 2; i++) {
2641                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2642                 gain[i] = params[i].cal_gain;
2643         }
2644
2645         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2646
2647         b43_nphy_tx_cal_radio_setup(dev);
2648         b43_nphy_tx_cal_phy_setup(dev);
2649
2650         phy6or5x = dev->phy.rev >= 6 ||
2651                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2652                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2653         if (phy6or5x) {
2654                 if (dev->phy.is_40mhz) {
2655                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2656                                         tbl_tx_iqlo_cal_loft_ladder_40);
2657                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2658                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2659                 } else {
2660                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2661                                         tbl_tx_iqlo_cal_loft_ladder_20);
2662                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2663                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2664                 }
2665         }
2666
2667         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2668
2669         if (!dev->phy.is_40mhz)
2670                 freq = 2500;
2671         else
2672                 freq = 5000;
2673
2674         if (nphy->mphase_cal_phase_id > 2)
2675                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2676                                         0xFFFF, 0, true, false);
2677         else
2678                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2679
2680         if (error == 0) {
2681                 if (nphy->mphase_cal_phase_id > 2) {
2682                         table = nphy->mphase_txcal_bestcoeffs;
2683                         length = 11;
2684                         if (dev->phy.rev < 3)
2685                                 length -= 2;
2686                 } else {
2687                         if (!full && nphy->txiqlocal_coeffsvalid) {
2688                                 table = nphy->txiqlocal_bestc;
2689                                 length = 11;
2690                                 if (dev->phy.rev < 3)
2691                                         length -= 2;
2692                         } else {
2693                                 full = true;
2694                                 if (dev->phy.rev >= 3) {
2695                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2696                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2697                                 } else {
2698                                         table = tbl_tx_iqlo_cal_startcoefs;
2699                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2700                                 }
2701                         }
2702                 }
2703
2704                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2705
2706                 if (full) {
2707                         if (dev->phy.rev >= 3)
2708                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2709                         else
2710                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2711                 } else {
2712                         if (dev->phy.rev >= 3)
2713                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2714                         else
2715                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2716                 }
2717
2718                 if (mphase) {
2719                         count = nphy->mphase_txcal_cmdidx;
2720                         numb = min(max,
2721                                 (u16)(count + nphy->mphase_txcal_numcmds));
2722                 } else {
2723                         count = 0;
2724                         numb = max;
2725                 }
2726
2727                 for (; count < numb; count++) {
2728                         if (full) {
2729                                 if (dev->phy.rev >= 3)
2730                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2731                                 else
2732                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2733                         } else {
2734                                 if (dev->phy.rev >= 3)
2735                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2736                                 else
2737                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2738                         }
2739
2740                         core = (cmd & 0x3000) >> 12;
2741                         type = (cmd & 0x0F00) >> 8;
2742
2743                         if (phy6or5x && updated[core] == 0) {
2744                                 b43_nphy_update_tx_cal_ladder(dev, core);
2745                                 updated[core] = 1;
2746                         }
2747
2748                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2749                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2750
2751                         if (type == 1 || type == 3 || type == 4) {
2752                                 buffer[0] = b43_ntab_read(dev,
2753                                                 B43_NTAB16(15, 69 + core));
2754                                 diq_start = buffer[0];
2755                                 buffer[0] = 0;
2756                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2757                                                 0);
2758                         }
2759
2760                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2761                         for (i = 0; i < 2000; i++) {
2762                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2763                                 if (tmp & 0xC000)
2764                                         break;
2765                                 udelay(10);
2766                         }
2767
2768                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2769                                                 buffer);
2770                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2771                                                 buffer);
2772
2773                         if (type == 1 || type == 3 || type == 4)
2774                                 buffer[0] = diq_start;
2775                 }
2776
2777                 if (mphase)
2778                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2779
2780                 last = (dev->phy.rev < 3) ? 6 : 7;
2781
2782                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2783                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2784                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2785                         if (dev->phy.rev < 3) {
2786                                 buffer[0] = 0;
2787                                 buffer[1] = 0;
2788                                 buffer[2] = 0;
2789                                 buffer[3] = 0;
2790                         }
2791                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2792                                                 buffer);
2793                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2794                                                 buffer);
2795                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2796                                                 buffer);
2797                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2798                                                 buffer);
2799                         length = 11;
2800                         if (dev->phy.rev < 3)
2801                                 length -= 2;
2802                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2803                                                 nphy->txiqlocal_bestc);
2804                         nphy->txiqlocal_coeffsvalid = true;
2805                         nphy->txiqlocal_chanspec = nphy->radio_chanspec;
2806                 } else {
2807                         length = 11;
2808                         if (dev->phy.rev < 3)
2809                                 length -= 2;
2810                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2811                                                 nphy->mphase_txcal_bestcoeffs);
2812                 }
2813
2814                 b43_nphy_stop_playback(dev);
2815                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2816         }
2817
2818         b43_nphy_tx_cal_phy_cleanup(dev);
2819         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2820
2821         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2822                 b43_nphy_tx_iq_workaround(dev);
2823
2824         if (dev->phy.rev >= 4)
2825                 nphy->hang_avoid = avoid;
2826
2827         b43_nphy_stay_in_carrier_search(dev, false);
2828
2829         return error;
2830 }
2831
2832 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2833 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2834 {
2835         struct b43_phy_n *nphy = dev->phy.n;
2836         u8 i;
2837         u16 buffer[7];
2838         bool equal = true;
2839
2840         if (!nphy->txiqlocal_coeffsvalid ||
2841             b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec))
2842                 return;
2843
2844         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2845         for (i = 0; i < 4; i++) {
2846                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2847                         equal = false;
2848                         break;
2849                 }
2850         }
2851
2852         if (!equal) {
2853                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2854                                         nphy->txiqlocal_bestc);
2855                 for (i = 0; i < 4; i++)
2856                         buffer[i] = 0;
2857                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2858                                         buffer);
2859                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2860                                         &nphy->txiqlocal_bestc[5]);
2861                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2862                                         &nphy->txiqlocal_bestc[5]);
2863         }
2864 }
2865
2866 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2867 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2868                         struct nphy_txgains target, u8 type, bool debug)
2869 {
2870         struct b43_phy_n *nphy = dev->phy.n;
2871         int i, j, index;
2872         u8 rfctl[2];
2873         u8 afectl_core;
2874         u16 tmp[6];
2875         u16 cur_hpf1, cur_hpf2, cur_lna;
2876         u32 real, imag;
2877         enum ieee80211_band band;
2878
2879         u8 use;
2880         u16 cur_hpf;
2881         u16 lna[3] = { 3, 3, 1 };
2882         u16 hpf1[3] = { 7, 2, 0 };
2883         u16 hpf2[3] = { 2, 0, 0 };
2884         u32 power[3] = { };
2885         u16 gain_save[2];
2886         u16 cal_gain[2];
2887         struct nphy_iqcal_params cal_params[2];
2888         struct nphy_iq_est est;
2889         int ret = 0;
2890         bool playtone = true;
2891         int desired = 13;
2892
2893         b43_nphy_stay_in_carrier_search(dev, 1);
2894
2895         if (dev->phy.rev < 2)
2896                 b43_nphy_reapply_tx_cal_coeffs(dev);
2897         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2898         for (i = 0; i < 2; i++) {
2899                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2900                 cal_gain[i] = cal_params[i].cal_gain;
2901         }
2902         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2903
2904         for (i = 0; i < 2; i++) {
2905                 if (i == 0) {
2906                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2907                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2908                         afectl_core = B43_NPHY_AFECTL_C1;
2909                 } else {
2910                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2911                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2912                         afectl_core = B43_NPHY_AFECTL_C2;
2913                 }
2914
2915                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2916                 tmp[2] = b43_phy_read(dev, afectl_core);
2917                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2918                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2919                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2920
2921                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2922                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2923                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2924                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2925                                 (1 - i));
2926                 b43_phy_set(dev, afectl_core, 0x0006);
2927                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2928
2929                 band = b43_current_band(dev->wl);
2930
2931                 if (nphy->rxcalparams & 0xFF000000) {
2932                         if (band == IEEE80211_BAND_5GHZ)
2933                                 b43_phy_write(dev, rfctl[0], 0x140);
2934                         else
2935                                 b43_phy_write(dev, rfctl[0], 0x110);
2936                 } else {
2937                         if (band == IEEE80211_BAND_5GHZ)
2938                                 b43_phy_write(dev, rfctl[0], 0x180);
2939                         else
2940                                 b43_phy_write(dev, rfctl[0], 0x120);
2941                 }
2942
2943                 if (band == IEEE80211_BAND_5GHZ)
2944                         b43_phy_write(dev, rfctl[1], 0x148);
2945                 else
2946                         b43_phy_write(dev, rfctl[1], 0x114);
2947
2948                 if (nphy->rxcalparams & 0x10000) {
2949                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2950                                         (i + 1));
2951                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2952                                         (2 - i));
2953                 }
2954
2955                 for (j = 0; i < 4; j++) {
2956                         if (j < 3) {
2957                                 cur_lna = lna[j];
2958                                 cur_hpf1 = hpf1[j];
2959                                 cur_hpf2 = hpf2[j];
2960                         } else {
2961                                 if (power[1] > 10000) {
2962                                         use = 1;
2963                                         cur_hpf = cur_hpf1;
2964                                         index = 2;
2965                                 } else {
2966                                         if (power[0] > 10000) {
2967                                                 use = 1;
2968                                                 cur_hpf = cur_hpf1;
2969                                                 index = 1;
2970                                         } else {
2971                                                 index = 0;
2972                                                 use = 2;
2973                                                 cur_hpf = cur_hpf2;
2974                                         }
2975                                 }
2976                                 cur_lna = lna[index];
2977                                 cur_hpf1 = hpf1[index];
2978                                 cur_hpf2 = hpf2[index];
2979                                 cur_hpf += desired - hweight32(power[index]);
2980                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2981                                 if (use == 1)
2982                                         cur_hpf1 = cur_hpf;
2983                                 else
2984                                         cur_hpf2 = cur_hpf;
2985                         }
2986
2987                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2988                                         (cur_lna << 2));
2989                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2990                                                                         false);
2991                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2992                         b43_nphy_stop_playback(dev);
2993
2994                         if (playtone) {
2995                                 ret = b43_nphy_tx_tone(dev, 4000,
2996                                                 (nphy->rxcalparams & 0xFFFF),
2997                                                 false, false);
2998                                 playtone = false;
2999                         } else {
3000                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3001                                                         false, false);
3002                         }
3003
3004                         if (ret == 0) {
3005                                 if (j < 3) {
3006                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3007                                                                         false);
3008                                         if (i == 0) {
3009                                                 real = est.i0_pwr;
3010                                                 imag = est.q0_pwr;
3011                                         } else {
3012                                                 real = est.i1_pwr;
3013                                                 imag = est.q1_pwr;
3014                                         }
3015                                         power[i] = ((real + imag) / 1024) + 1;
3016                                 } else {
3017                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3018                                 }
3019                                 b43_nphy_stop_playback(dev);
3020                         }
3021
3022                         if (ret != 0)
3023                                 break;
3024                 }
3025
3026                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3027                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3028                 b43_phy_write(dev, rfctl[1], tmp[5]);
3029                 b43_phy_write(dev, rfctl[0], tmp[4]);
3030                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3031                 b43_phy_write(dev, afectl_core, tmp[2]);
3032                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3033
3034                 if (ret != 0)
3035                         break;
3036         }
3037
3038         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3039         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3040         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3041
3042         b43_nphy_stay_in_carrier_search(dev, 0);
3043
3044         return ret;
3045 }
3046
3047 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3048                         struct nphy_txgains target, u8 type, bool debug)
3049 {
3050         return -1;
3051 }
3052
3053 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3054 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3055                         struct nphy_txgains target, u8 type, bool debug)
3056 {
3057         if (dev->phy.rev >= 3)
3058                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3059         else
3060                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3061 }
3062
3063 /*
3064  * Init N-PHY
3065  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3066  */
3067 int b43_phy_initn(struct b43_wldev *dev)
3068 {
3069         struct ssb_bus *bus = dev->dev->bus;
3070         struct b43_phy *phy = &dev->phy;
3071         struct b43_phy_n *nphy = phy->n;
3072         u8 tx_pwr_state;
3073         struct nphy_txgains target;
3074         u16 tmp;
3075         enum ieee80211_band tmp2;
3076         bool do_rssi_cal;
3077
3078         u16 clip[2];
3079         bool do_cal = false;
3080
3081         if ((dev->phy.rev >= 3) &&
3082            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3083            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3084                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3085         }
3086         nphy->deaf_count = 0;
3087         b43_nphy_tables_init(dev);
3088         nphy->crsminpwr_adjusted = false;
3089         nphy->noisevars_adjusted = false;
3090
3091         /* Clear all overrides */
3092         if (dev->phy.rev >= 3) {
3093                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3094                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3095                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3096                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3097         } else {
3098                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3099         }
3100         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3101         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3102         if (dev->phy.rev < 6) {
3103                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3104                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3105         }
3106         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3107                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3108                        B43_NPHY_RFSEQMODE_TROVER));
3109         if (dev->phy.rev >= 3)
3110                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3111         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3112
3113         if (dev->phy.rev <= 2) {
3114                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3115                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3116                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3117                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3118         }
3119         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3120         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3121
3122         if (bus->sprom.boardflags2_lo & 0x100 ||
3123             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3124              bus->boardinfo.type == 0x8B))
3125                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3126         else
3127                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3128         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3129         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3130         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3131
3132         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3133         b43_nphy_update_txrx_chain(dev);
3134
3135         if (phy->rev < 2) {
3136                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3137                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3138         }
3139
3140         tmp2 = b43_current_band(dev->wl);
3141         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3142             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3143                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3144                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3145                                 nphy->papd_epsilon_offset[0] << 7);
3146                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3147                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3148                                 nphy->papd_epsilon_offset[1] << 7);
3149                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3150         } else if (phy->rev >= 5) {
3151                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3152         }
3153
3154         b43_nphy_workarounds(dev);
3155
3156         /* Reset CCA, in init code it differs a little from standard way */
3157         b43_nphy_bmac_clock_fgc(dev, 1);
3158         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3159         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3160         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3161         b43_nphy_bmac_clock_fgc(dev, 0);
3162
3163         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3164
3165         b43_nphy_pa_override(dev, false);
3166         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3167         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3168         b43_nphy_pa_override(dev, true);
3169
3170         b43_nphy_classifier(dev, 0, 0);
3171         b43_nphy_read_clip_detection(dev, clip);
3172         tx_pwr_state = nphy->txpwrctrl;
3173         /* TODO N PHY TX power control with argument 0
3174                 (turning off power control) */
3175         /* TODO Fix the TX Power Settings */
3176         /* TODO N PHY TX Power Control Idle TSSI */
3177         /* TODO N PHY TX Power Control Setup */
3178
3179         if (phy->rev >= 3) {
3180                 /* TODO */
3181         } else {
3182                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3183                                         b43_ntab_tx_gain_rev0_1_2);
3184                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3185                                         b43_ntab_tx_gain_rev0_1_2);
3186         }
3187
3188         if (nphy->phyrxchain != 3)
3189                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3190         if (nphy->mphase_cal_phase_id > 0)
3191                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3192
3193         do_rssi_cal = false;
3194         if (phy->rev >= 3) {
3195                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3196                         do_rssi_cal =
3197                                 b43_empty_chanspec(&nphy->rssical_chanspec_2G);
3198                 else
3199                         do_rssi_cal =
3200                                 b43_empty_chanspec(&nphy->rssical_chanspec_5G);
3201
3202                 if (do_rssi_cal)
3203                         b43_nphy_rssi_cal(dev);
3204                 else
3205                         b43_nphy_restore_rssi_cal(dev);
3206         } else {
3207                 b43_nphy_rssi_cal(dev);
3208         }
3209
3210         if (!((nphy->measure_hold & 0x6) != 0)) {
3211                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3212                         do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G);
3213                 else
3214                         do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G);
3215
3216                 if (nphy->mute)
3217                         do_cal = false;
3218
3219                 if (do_cal) {
3220                         target = b43_nphy_get_tx_gains(dev);
3221
3222                         if (nphy->antsel_type == 2)
3223                                 b43_nphy_superswitch_init(dev, true);
3224                         if (nphy->perical != 2) {
3225                                 b43_nphy_rssi_cal(dev);
3226                                 if (phy->rev >= 3) {
3227                                         nphy->cal_orig_pwr_idx[0] =
3228                                             nphy->txpwrindex[0].index_internal;
3229                                         nphy->cal_orig_pwr_idx[1] =
3230                                             nphy->txpwrindex[1].index_internal;
3231                                         /* TODO N PHY Pre Calibrate TX Gain */
3232                                         target = b43_nphy_get_tx_gains(dev);
3233                                 }
3234                         }
3235                 }
3236         }
3237
3238         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3239                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3240                         b43_nphy_save_cal(dev);
3241                 else if (nphy->mphase_cal_phase_id == 0)
3242                         ;/* N PHY Periodic Calibration with argument 3 */
3243         } else {
3244                 b43_nphy_restore_cal(dev);
3245         }
3246
3247         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3248         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3249         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3250         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3251         if (phy->rev >= 3 && phy->rev <= 6)
3252                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3253         b43_nphy_tx_lp_fbw(dev);
3254         if (phy->rev >= 3)
3255                 b43_nphy_spur_workaround(dev);
3256
3257         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3258         return 0;
3259 }
3260
3261 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3262 static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
3263                                 const struct b43_nphy_channeltab_entry *e,
3264                                 struct b43_chanspec chanspec)
3265 {
3266         struct b43_phy *phy = &dev->phy;
3267         struct b43_phy_n *nphy = dev->phy.n;
3268
3269         u16 tmp;
3270         u32 tmp32;
3271
3272         tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3273         if (chanspec.b_freq == 1 && tmp == 0) {
3274                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3275                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3276                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3277                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3278                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3279         } else if (chanspec.b_freq == 1) {
3280                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3281                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3282                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3283                 b43_phy_mask(dev, B43_PHY_B_BBCFG, (u16)~0xC000);
3284                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3285         }
3286
3287         b43_chantab_phy_upload(dev, e);
3288
3289         tmp = chanspec.channel;
3290         if (chanspec.b_freq == 1)
3291                 tmp |= 0x0100;
3292         if (chanspec.b_width == 3)
3293                 tmp |= 0x0200;
3294         b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
3295
3296         if (nphy->radio_chanspec.channel == 14) {
3297                 b43_nphy_classifier(dev, 2, 0);
3298                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3299         } else {
3300                 b43_nphy_classifier(dev, 2, 2);
3301                 if (chanspec.b_freq == 2)
3302                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3303         }
3304
3305         if (nphy->txpwrctrl)
3306                 b43_nphy_tx_power_fix(dev);
3307
3308         if (dev->phy.rev < 3)
3309                 b43_nphy_adjust_lna_gain_table(dev);
3310
3311         b43_nphy_tx_lp_fbw(dev);
3312
3313         if (dev->phy.rev >= 3 && 0) {
3314                 /* TODO */
3315         }
3316
3317         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3318
3319         if (phy->rev >= 3)
3320                 b43_nphy_spur_workaround(dev);
3321 }
3322
3323 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3324 static int b43_nphy_set_chanspec(struct b43_wldev *dev,
3325                                         struct b43_chanspec chanspec)
3326 {
3327         struct b43_phy_n *nphy = dev->phy.n;
3328
3329         const struct b43_nphy_channeltab_entry *tabent;
3330
3331         u8 tmp;
3332         u8 channel = chanspec.channel;
3333
3334         if (dev->phy.rev >= 3) {
3335                 /* TODO */
3336         }
3337
3338         nphy->radio_chanspec = chanspec;
3339
3340         if (chanspec.b_width != nphy->b_width)
3341                 ; /* TODO: BMAC BW Set (chanspec.b_width) */
3342
3343         /* TODO: use defines */
3344         if (chanspec.b_width == 3) {
3345                 if (chanspec.sideband == 2)
3346                         b43_phy_set(dev, B43_NPHY_RXCTL,
3347                                         B43_NPHY_RXCTL_BSELU20);
3348                 else
3349                         b43_phy_mask(dev, B43_NPHY_RXCTL,
3350                                         ~B43_NPHY_RXCTL_BSELU20);
3351         }
3352
3353         if (dev->phy.rev >= 3) {
3354                 tmp = (chanspec.b_freq == 1) ? 4 : 0;
3355                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3356                 /* TODO: PHY Radio2056 Setup (chan_info_ptr[i]) */
3357                 /* TODO: N PHY Chanspec Setup (chan_info_ptr[i]) */
3358         } else {
3359                 tabent = b43_nphy_get_chantabent(dev, channel);
3360                 if (!tabent)
3361                         return -ESRCH;
3362
3363                 tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050;
3364                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3365                 b43_radio_2055_setup(dev, tabent);
3366                 b43_nphy_chanspec_setup(dev, tabent, chanspec);
3367         }
3368
3369         return 0;
3370 }
3371
3372 /* Tune the hardware to a new channel */
3373 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
3374 {
3375         struct b43_phy_n *nphy = dev->phy.n;
3376
3377         struct b43_chanspec chanspec;
3378         chanspec = nphy->radio_chanspec;
3379         chanspec.channel = channel;
3380
3381         return b43_nphy_set_chanspec(dev, chanspec);
3382 }
3383
3384 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3385 {
3386         struct b43_phy_n *nphy;
3387
3388         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3389         if (!nphy)
3390                 return -ENOMEM;
3391         dev->phy.n = nphy;
3392
3393         return 0;
3394 }
3395
3396 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3397 {
3398         struct b43_phy *phy = &dev->phy;
3399         struct b43_phy_n *nphy = phy->n;
3400
3401         memset(nphy, 0, sizeof(*nphy));
3402
3403         //TODO init struct b43_phy_n
3404 }
3405
3406 static void b43_nphy_op_free(struct b43_wldev *dev)
3407 {
3408         struct b43_phy *phy = &dev->phy;
3409         struct b43_phy_n *nphy = phy->n;
3410
3411         kfree(nphy);
3412         phy->n = NULL;
3413 }
3414
3415 static int b43_nphy_op_init(struct b43_wldev *dev)
3416 {
3417         return b43_phy_initn(dev);
3418 }
3419
3420 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3421 {
3422 #if B43_DEBUG
3423         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3424                 /* OFDM registers are onnly available on A/G-PHYs */
3425                 b43err(dev->wl, "Invalid OFDM PHY access at "
3426                        "0x%04X on N-PHY\n", offset);
3427                 dump_stack();
3428         }
3429         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3430                 /* Ext-G registers are only available on G-PHYs */
3431                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3432                        "0x%04X on N-PHY\n", offset);
3433                 dump_stack();
3434         }
3435 #endif /* B43_DEBUG */
3436 }
3437
3438 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3439 {
3440         check_phyreg(dev, reg);
3441         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3442         return b43_read16(dev, B43_MMIO_PHY_DATA);
3443 }
3444
3445 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3446 {
3447         check_phyreg(dev, reg);
3448         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3449         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3450 }
3451
3452 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3453 {
3454         /* Register 1 is a 32-bit register. */
3455         B43_WARN_ON(reg == 1);
3456         /* N-PHY needs 0x100 for read access */
3457         reg |= 0x100;
3458
3459         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3460         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3461 }
3462
3463 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3464 {
3465         /* Register 1 is a 32-bit register. */
3466         B43_WARN_ON(reg == 1);
3467
3468         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3469         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3470 }
3471
3472 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3473 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3474                                         bool blocked)
3475 {
3476         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3477                 b43err(dev->wl, "MAC not suspended\n");
3478
3479         if (blocked) {
3480                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3481                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3482                 if (dev->phy.rev >= 3) {
3483                         b43_radio_mask(dev, 0x09, ~0x2);
3484
3485                         b43_radio_write(dev, 0x204D, 0);
3486                         b43_radio_write(dev, 0x2053, 0);
3487                         b43_radio_write(dev, 0x2058, 0);
3488                         b43_radio_write(dev, 0x205E, 0);
3489                         b43_radio_mask(dev, 0x2062, ~0xF0);
3490                         b43_radio_write(dev, 0x2064, 0);
3491
3492                         b43_radio_write(dev, 0x304D, 0);
3493                         b43_radio_write(dev, 0x3053, 0);
3494                         b43_radio_write(dev, 0x3058, 0);
3495                         b43_radio_write(dev, 0x305E, 0);
3496                         b43_radio_mask(dev, 0x3062, ~0xF0);
3497                         b43_radio_write(dev, 0x3064, 0);
3498                 }
3499         } else {
3500                 if (dev->phy.rev >= 3) {
3501                         /* TODO: b43_radio_init2056(dev); */
3502                         /* TODO: PHY Set Channel Spec (dev, radio_chanspec) */
3503                 } else {
3504                         b43_radio_init2055(dev);
3505                 }
3506         }
3507 }
3508
3509 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3510 {
3511         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3512                       on ? 0 : 0x7FFF);
3513 }
3514
3515 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3516                                       unsigned int new_channel)
3517 {
3518         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3519                 if ((new_channel < 1) || (new_channel > 14))
3520                         return -EINVAL;
3521         } else {
3522                 if (new_channel > 200)
3523                         return -EINVAL;
3524         }
3525
3526         return nphy_channel_switch(dev, new_channel);
3527 }
3528
3529 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3530 {
3531         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3532                 return 1;
3533         return 36;
3534 }
3535
3536 const struct b43_phy_operations b43_phyops_n = {
3537         .allocate               = b43_nphy_op_allocate,
3538         .free                   = b43_nphy_op_free,
3539         .prepare_structs        = b43_nphy_op_prepare_structs,
3540         .init                   = b43_nphy_op_init,
3541         .phy_read               = b43_nphy_op_read,
3542         .phy_write              = b43_nphy_op_write,
3543         .radio_read             = b43_nphy_op_radio_read,
3544         .radio_write            = b43_nphy_op_radio_write,
3545         .software_rfkill        = b43_nphy_op_software_rfkill,
3546         .switch_analog          = b43_nphy_op_switch_analog,
3547         .switch_channel         = b43_nphy_op_switch_channel,
3548         .get_default_chan       = b43_nphy_op_get_default_chan,
3549         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3550         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3551 };