SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 #define ntab_upload(dev, offset, data) do { \
 226                 unsigned int i;                                         \
 227                 for (i = 0; i < (offset##_SIZE); i++)                   \
 228                         b43_ntab_write(dev, (offset) + i, (data)[i]);   \
 229         } while (0)
 230
 231 /*
 232  * Upload the N-PHY tables.
 233  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 234  */
 235 static void b43_nphy_tables_init(struct b43_wldev *dev)
 236 {
 237         if (dev->phy.rev < 3)
 238                 b43_nphy_rev0_1_2_tables_init(dev);
 239         else
 240                 b43_nphy_rev3plus_tables_init(dev);
 241 }
 242
 243 static void b43_nphy_workarounds(struct b43_wldev *dev)
 244 {
 245         struct b43_phy *phy = &dev->phy;
 246         unsigned int i;
 247
 248         b43_phy_set(dev, B43_NPHY_IQFLIP,
 249                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 250         if (1 /* FIXME band is 2.4GHz */) {
 251                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 252                             B43_NPHY_CLASSCTL_CCKEN);
 253         } else {
 254                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 255                              ~B43_NPHY_CLASSCTL_CCKEN);
 256         }
 257         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 258         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 259
 260         /* Fixup some tables */
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 265         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 266         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 267         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 268         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 269         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 270         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 271
 272         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 273         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 274         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 275         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 276
 277         //TODO set RF sequence
 278
 279         /* Set narrowband clip threshold */
 280         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 281         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 282
 283         /* Set wideband clip 2 threshold */
 284         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 285                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 286                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 287         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 288                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 289                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 290
 291         /* Set Clip 2 detect */
 292         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 293                     B43_NPHY_C1_CGAINI_CL2DETECT);
 294         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 295                     B43_NPHY_C2_CGAINI_CL2DETECT);
 296
 297         if (0 /*FIXME*/) {
 298                 /* Set dwell lengths */
 299                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 300                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 301                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 302                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 303
 304                 /* Set gain backoff */
 305                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 306                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 307                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 308                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 309                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 310                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 311
 312                 /* Set HPVGA2 index */
 313                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 314                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 315                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 316                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 317                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 318                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 319
 320                 //FIXME verify that the specs really mean to use autoinc here.
 321                 for (i = 0; i < 3; i++)
 322                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 323         }
 324
 325         /* Set minimum gain value */
 326         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 327                         ~B43_NPHY_C1_MINGAIN,
 328                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 329         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 330                         ~B43_NPHY_C2_MINGAIN,
 331                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 332
 333         if (phy->rev < 2) {
 334                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 335                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 336         }
 337
 338         /* Set phase track alpha and beta */
 339         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 340         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 341         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 342         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 343         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 344         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 345 }
 346
 347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 348 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 349 {
 350         struct b43_phy_n *nphy = dev->phy.n;
 351         enum ieee80211_band band;
 352         u16 tmp;
 353
 354         if (!enable) {
 355                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 356                                                        B43_NPHY_RFCTL_INTC1);
 357                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 358                                                        B43_NPHY_RFCTL_INTC2);
 359                 band = b43_current_band(dev->wl);
 360                 if (dev->phy.rev >= 3) {
 361                         if (band == IEEE80211_BAND_5GHZ)
 362                                 tmp = 0x600;
 363                         else
 364                                 tmp = 0x480;
 365                 } else {
 366                         if (band == IEEE80211_BAND_5GHZ)
 367                                 tmp = 0x180;
 368                         else
 369                                 tmp = 0x120;
 370                 }
 371                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 372                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 373         } else {
 374                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 375                                 nphy->rfctrl_intc1_save);
 376                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 377                                 nphy->rfctrl_intc2_save);
 378         }
 379 }
 380
 381 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 382 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 383 {
 384         u32 tmslow;
 385
 386         if (dev->phy.type != B43_PHYTYPE_N)
 387                 return;
 388
 389         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 390         if (force)
 391                 tmslow |= SSB_TMSLOW_FGC;
 392         else
 393                 tmslow &= ~SSB_TMSLOW_FGC;
 394         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 395 }
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 398 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 399 {
 400         u16 bbcfg;
 401
 402         b43_nphy_bmac_clock_fgc(dev, 1);
 403         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 404         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 405         udelay(1);
 406         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 407         b43_nphy_bmac_clock_fgc(dev, 0);
 408         /* TODO: N PHY Force RF Seq with argument 2 */
 409 }
 410
 411 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 412 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 413                                         struct b43_phy_n_iq_comp *pcomp)
 414 {
 415         if (write) {
 416                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 417                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 418                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 419                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 420         } else {
 421                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 422                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 423                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 424                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 425         }
 426 }
 427
 428 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 429 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 430 {
 431         u16 array[4];
 432         int i;
 433
 434         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 435         for (i = 0; i < 4; i++)
 436                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 437
 438         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 439         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 440         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 441         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 442 }
 443
 444 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 445 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 446 {
 447         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 448         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 449 }
 450
 451 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 452 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 453 {
 454         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 455         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 456 }
 457
 458 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 459 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 460 {
 461         u16 tmp;
 462
 463         if (dev->dev->id.revision == 16)
 464                 b43_mac_suspend(dev);
 465
 466         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 467         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 468                 B43_NPHY_CLASSCTL_WAITEDEN);
 469         tmp &= ~mask;
 470         tmp |= (val & mask);
 471         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 472
 473         if (dev->dev->id.revision == 16)
 474                 b43_mac_enable(dev);
 475
 476         return tmp;
 477 }
 478
 479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 480 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 481 {
 482         struct b43_phy *phy = &dev->phy;
 483         struct b43_phy_n *nphy = phy->n;
 484
 485         if (enable) {
 486                 u16 clip[] = { 0xFFFF, 0xFFFF };
 487                 if (nphy->deaf_count++ == 0) {
 488                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 489                         b43_nphy_classifier(dev, 0x7, 0);
 490                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 491                         b43_nphy_write_clip_detection(dev, clip);
 492                 }
 493                 b43_nphy_reset_cca(dev);
 494         } else {
 495                 if (--nphy->deaf_count == 0) {
 496                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 497                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 498                 }
 499         }
 500 }
 501
 502 enum b43_nphy_rf_sequence {
 503         B43_RFSEQ_RX2TX,
 504         B43_RFSEQ_TX2RX,
 505         B43_RFSEQ_RESET2RX,
 506         B43_RFSEQ_UPDATE_GAINH,
 507         B43_RFSEQ_UPDATE_GAINL,
 508         B43_RFSEQ_UPDATE_GAINU,
 509 };
 510
 511 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 512                                        enum b43_nphy_rf_sequence seq)
 513 {
 514         static const u16 trigger[] = {
 515                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 516                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 517                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 518                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 519                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 520                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 521         };
 522         int i;
 523
 524         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 525
 526         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 527                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 528         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 529         for (i = 0; i < 200; i++) {
 530                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 531                         goto ok;
 532                 msleep(1);
 533         }
 534         b43err(dev->wl, "RF sequence status timeout\n");
 535 ok:
 536         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 537                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 538 }
 539
 540 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 541 {
 542         unsigned int i;
 543         u16 val;
 544
 545         val = 0x1E1F;
 546         for (i = 0; i < 14; i++) {
 547                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 548                 val -= 0x202;
 549         }
 550         val = 0x3E3F;
 551         for (i = 0; i < 16; i++) {
 552                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 553                 val -= 0x202;
 554         }
 555         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 556 }
 557
 558 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 559 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 560                                        s8 offset, u8 core, u8 rail, u8 type)
 561 {
 562         u16 tmp;
 563         bool core1or5 = (core == 1) || (core == 5);
 564         bool core2or5 = (core == 2) || (core == 5);
 565
 566         offset = clamp_val(offset, -32, 31);
 567         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 568
 569         if (core1or5 && (rail == 0) && (type == 2))
 570                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 571         if (core1or5 && (rail == 1) && (type == 2))
 572                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 573         if (core2or5 && (rail == 0) && (type == 2))
 574                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 575         if (core2or5 && (rail == 1) && (type == 2))
 576                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 577         if (core1or5 && (rail == 0) && (type == 0))
 578                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 579         if (core1or5 && (rail == 1) && (type == 0))
 580                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 581         if (core2or5 && (rail == 0) && (type == 0))
 582                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 583         if (core2or5 && (rail == 1) && (type == 0))
 584                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 585         if (core1or5 && (rail == 0) && (type == 1))
 586                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 587         if (core1or5 && (rail == 1) && (type == 1))
 588                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 589         if (core2or5 && (rail == 0) && (type == 1))
 590                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 591         if (core2or5 && (rail == 1) && (type == 1))
 592                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 593         if (core1or5 && (rail == 0) && (type == 6))
 594                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 595         if (core1or5 && (rail == 1) && (type == 6))
 596                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 597         if (core2or5 && (rail == 0) && (type == 6))
 598                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 599         if (core2or5 && (rail == 1) && (type == 6))
 600                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 601         if (core1or5 && (rail == 0) && (type == 3))
 602                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 603         if (core1or5 && (rail == 1) && (type == 3))
 604                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 605         if (core2or5 && (rail == 0) && (type == 3))
 606                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 607         if (core2or5 && (rail == 1) && (type == 3))
 608                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 609         if (core1or5 && (type == 4))
 610                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 611         if (core2or5 && (type == 4))
 612                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 613         if (core1or5 && (type == 5))
 614                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 615         if (core2or5 && (type == 5))
 616                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 617 }
 618
 619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
 620 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 621 {
 622         u16 val;
 623
 624         if (dev->phy.rev >= 3) {
 625                 /* TODO */
 626         } else {
 627                 if (type < 3)
 628                         val = 0;
 629                 else if (type == 6)
 630                         val = 1;
 631                 else if (type == 3)
 632                         val = 2;
 633                 else
 634                         val = 3;
 635
 636                 val = (val << 12) | (val << 14);
 637                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
 638                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
 639
 640                 if (type < 3) {
 641                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
 642                                         (type + 1) << 4);
 643                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
 644                                         (type + 1) << 4);
 645                 }
 646
 647                 /* TODO use some definitions */
 648                 if (code == 0) {
 649                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
 650                         if (type < 3) {
 651                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 652                                                 0xFEC7, 0);
 653                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 654                                                 0xEFDC, 0);
 655                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 656                                                 0xFFFE, 0);
 657                                 udelay(20);
 658                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 659                                                 0xFFFE, 0);
 660                         }
 661                 } else {
 662                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
 663                                         0x3000);
 664                         if (type < 3) {
 665                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 666                                                 0xFEC7, 0x0180);
 667                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 668                                                 0xEFDC, (code << 1 | 0x1021));
 669                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
 670                                                 0xFFFE, 0x0001);
 671                                 udelay(20);
 672                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
 673                                                 0xFFFE, 0);
 674                         }
 675                 }
 676         }
 677 }
 678
 679 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
 680 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
 681 {
 682         int i;
 683         for (i = 0; i < 2; i++) {
 684                 if (type == 2) {
 685                         if (i == 0) {
 686                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
 687                                                   0xFC, buf[0]);
 688                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
 689                                                   0xFC, buf[1]);
 690                         } else {
 691                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
 692                                                   0xFC, buf[2 * i]);
 693                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
 694                                                   0xFC, buf[2 * i + 1]);
 695                         }
 696                 } else {
 697                         if (i == 0)
 698                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
 699                                                   0xF3, buf[0] << 2);
 700                         else
 701                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
 702                                                   0xF3, buf[2 * i + 1] << 2);
 703                 }
 704         }
 705 }
 706
 707 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
 708 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
 709                                 u8 nsamp)
 710 {
 711         int i;
 712         int out;
 713         u16 save_regs_phy[9];
 714         u16 s[2];
 715
 716         if (dev->phy.rev >= 3) {
 717                 save_regs_phy[0] = b43_phy_read(dev,
 718                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
 719                 save_regs_phy[1] = b43_phy_read(dev,
 720                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
 721                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 722                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 723                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 724                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 725                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
 726                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
 727         }
 728
 729         b43_nphy_rssi_select(dev, 5, type);
 730
 731         if (dev->phy.rev < 2) {
 732                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
 733                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
 734         }
 735
 736         for (i = 0; i < 4; i++)
 737                 buf[i] = 0;
 738
 739         for (i = 0; i < nsamp; i++) {
 740                 if (dev->phy.rev < 2) {
 741                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
 742                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
 743                 } else {
 744                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
 745                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
 746                 }
 747
 748                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
 749                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
 750                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
 751                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
 752         }
 753         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
 754                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
 755
 756         if (dev->phy.rev < 2)
 757                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
 758
 759         if (dev->phy.rev >= 3) {
 760                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
 761                                 save_regs_phy[0]);
 762                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
 763                                 save_regs_phy[1]);
 764                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
 765                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
 766                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
 767                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
 768                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
 769                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
 770         }
 771
 772         return out;
 773 }
 774
 775 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
 776 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
 777 {
 778         int i, j;
 779         u8 state[4];
 780         u8 code, val;
 781         u16 class, override;
 782         u8 regs_save_radio[2];
 783         u16 regs_save_phy[2];
 784         s8 offset[4];
 785
 786         u16 clip_state[2];
 787         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
 788         s32 results_min[4] = { };
 789         u8 vcm_final[4] = { };
 790         s32 results[4][4] = { };
 791         s32 miniq[4][2] = { };
 792
 793         if (type == 2) {
 794                 code = 0;
 795                 val = 6;
 796         } else if (type < 2) {
 797                 code = 25;
 798                 val = 4;
 799         } else {
 800                 B43_WARN_ON(1);
 801                 return;
 802         }
 803
 804         class = b43_nphy_classifier(dev, 0, 0);
 805         b43_nphy_classifier(dev, 7, 4);
 806         b43_nphy_read_clip_detection(dev, clip_state);
 807         b43_nphy_write_clip_detection(dev, clip_off);
 808
 809         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
 810                 override = 0x140;
 811         else
 812                 override = 0x110;
 813
 814         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 815         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
 816         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
 817         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
 818
 819         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 820         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
 821         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
 822         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
 823
 824         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
 825         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
 826         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
 827         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
 828         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
 829         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
 830
 831         b43_nphy_rssi_select(dev, 5, type);
 832         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
 833         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
 834
 835         for (i = 0; i < 4; i++) {
 836                 u8 tmp[4];
 837                 for (j = 0; j < 4; j++)
 838                         tmp[j] = i;
 839                 if (type != 1)
 840                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
 841                 b43_nphy_poll_rssi(dev, type, results[i], 8);
 842                 if (type < 2)
 843                         for (j = 0; j < 2; j++)
 844                                 miniq[i][j] = min(results[i][2 * j],
 845                                                 results[i][2 * j + 1]);
 846         }
 847
 848         for (i = 0; i < 4; i++) {
 849                 s32 mind = 40;
 850                 u8 minvcm = 0;
 851                 s32 minpoll = 249;
 852                 s32 curr;
 853                 for (j = 0; j < 4; j++) {
 854                         if (type == 2)
 855                                 curr = abs(results[j][i]);
 856                         else
 857                                 curr = abs(miniq[j][i / 2] - code * 8);
 858
 859                         if (curr < mind) {
 860                                 mind = curr;
 861                                 minvcm = j;
 862                         }
 863
 864                         if (results[j][i] < minpoll)
 865                                 minpoll = results[j][i];
 866                 }
 867                 results_min[i] = minpoll;
 868                 vcm_final[i] = minvcm;
 869         }
 870
 871         if (type != 1)
 872                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
 873
 874         for (i = 0; i < 4; i++) {
 875                 offset[i] = (code * 8) - results[vcm_final[i]][i];
 876
 877                 if (offset[i] < 0)
 878                         offset[i] = -((abs(offset[i]) + 4) / 8);
 879                 else
 880                         offset[i] = (offset[i] + 4) / 8;
 881
 882                 if (results_min[i] == 248)
 883                         offset[i] = code - 32;
 884
 885                 if (i % 2 == 0)
 886                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
 887                                                         type);
 888                 else
 889                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
 890                                                         type);
 891         }
 892
 893         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
 894         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
 895
 896         switch (state[2]) {
 897         case 1:
 898                 b43_nphy_rssi_select(dev, 1, 2);
 899                 break;
 900         case 4:
 901                 b43_nphy_rssi_select(dev, 1, 0);
 902                 break;
 903         case 2:
 904                 b43_nphy_rssi_select(dev, 1, 1);
 905                 break;
 906         default:
 907                 b43_nphy_rssi_select(dev, 1, 1);
 908                 break;
 909         }
 910
 911         switch (state[3]) {
 912         case 1:
 913                 b43_nphy_rssi_select(dev, 2, 2);
 914                 break;
 915         case 4:
 916                 b43_nphy_rssi_select(dev, 2, 0);
 917                 break;
 918         default:
 919                 b43_nphy_rssi_select(dev, 2, 1);
 920                 break;
 921         }
 922
 923         b43_nphy_rssi_select(dev, 0, type);
 924
 925         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
 926         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
 927         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
 928         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
 929
 930         b43_nphy_classifier(dev, 7, class);
 931         b43_nphy_write_clip_detection(dev, clip_state);
 932 }
 933
 934 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
 935 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
 936 {
 937         /* TODO */
 938 }
 939
 940 /*
 941  * RSSI Calibration
 942  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
 943  */
 944 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
 945 {
 946         if (dev->phy.rev >= 3) {
 947                 b43_nphy_rev3_rssi_cal(dev);
 948         } else {
 949                 b43_nphy_rev2_rssi_cal(dev, 2);
 950                 b43_nphy_rev2_rssi_cal(dev, 0);
 951                 b43_nphy_rev2_rssi_cal(dev, 1);
 952         }
 953 }
 954
 955 /*
 956  * Restore RSSI Calibration
 957  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
 958  */
 959 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
 960 {
 961         struct b43_phy_n *nphy = dev->phy.n;
 962
 963         u16 *rssical_radio_regs = NULL;
 964         u16 *rssical_phy_regs = NULL;
 965
 966         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 967                 if (!nphy->rssical_chanspec_2G)
 968                         return;
 969                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
 970                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
 971         } else {
 972                 if (!nphy->rssical_chanspec_5G)
 973                         return;
 974                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
 975                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
 976         }
 977
 978         /* TODO use some definitions */
 979         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
 980         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
 981
 982         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
 983         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
 984         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
 985         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
 986
 987         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
 988         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
 989         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
 990         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
 991
 992         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
 993         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
 994         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
 995         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
 996 }
 997
 998 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
 999 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1000 {
1001         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1002                 if (dev->phy.rev >= 6) {
1003                         /* TODO If the chip is 47162
1004                                 return txpwrctrl_tx_gain_ipa_rev5 */
1005                         return txpwrctrl_tx_gain_ipa_rev6;
1006                 } else if (dev->phy.rev >= 5) {
1007                         return txpwrctrl_tx_gain_ipa_rev5;
1008                 } else {
1009                         return txpwrctrl_tx_gain_ipa;
1010                 }
1011         } else {
1012                 return txpwrctrl_tx_gain_ipa_5g;
1013         }
1014 }
1015
1016 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1017 static void b43_nphy_restore_cal(struct b43_wldev *dev)
1018 {
1019         struct b43_phy_n *nphy = dev->phy.n;
1020
1021         u16 coef[4];
1022         u16 *loft = NULL;
1023         u16 *table = NULL;
1024
1025         int i;
1026         u16 *txcal_radio_regs = NULL;
1027         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1028
1029         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1030                 if (nphy->iqcal_chanspec_2G == 0)
1031                         return;
1032                 table = nphy->cal_cache.txcal_coeffs_2G;
1033                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1034         } else {
1035                 if (nphy->iqcal_chanspec_5G == 0)
1036                         return;
1037                 table = nphy->cal_cache.txcal_coeffs_5G;
1038                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1039         }
1040
1041         /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1042                 width 16, and data from table */
1043
1044         for (i = 0; i < 4; i++) {
1045                 if (dev->phy.rev >= 3)
1046                         table[i] = coef[i];
1047                 else
1048                         coef[i] = 0;
1049         }
1050
1051         /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1052                 width 16, and data from coef */
1053         /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1054                 width 16 and data from loft */
1055         /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1056                 width 16 and data from loft */
1057
1058         if (dev->phy.rev < 2)
1059                 b43_nphy_tx_iq_workaround(dev);
1060
1061         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1062                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1063                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1064         } else {
1065                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1066                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1067         }
1068
1069         /* TODO use some definitions */
1070         if (dev->phy.rev >= 3) {
1071                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1072                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1073                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1074                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1075                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1076                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1077                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1078                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1079         } else {
1080                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1081                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1082                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1083                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1084         }
1085         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1086 }
1087
1088 /*
1089  * Init N-PHY
1090  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
1091  */
1092 int b43_phy_initn(struct b43_wldev *dev)
1093 {
1094         struct ssb_bus *bus = dev->dev->bus;
1095         struct b43_phy *phy = &dev->phy;
1096         struct b43_phy_n *nphy = phy->n;
1097         u8 tx_pwr_state;
1098         struct nphy_txgains target;
1099         u16 tmp;
1100         enum ieee80211_band tmp2;
1101         bool do_rssi_cal;
1102
1103         u16 clip[2];
1104         bool do_cal = false;
1105
1106         if ((dev->phy.rev >= 3) &&
1107            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
1108            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
1109                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
1110         }
1111         nphy->deaf_count = 0;
1112         b43_nphy_tables_init(dev);
1113         nphy->crsminpwr_adjusted = false;
1114         nphy->noisevars_adjusted = false;
1115
1116         /* Clear all overrides */
1117         if (dev->phy.rev >= 3) {
1118                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
1119                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1120                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
1121                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
1122         } else {
1123                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
1124         }
1125         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
1126         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
1127         if (dev->phy.rev < 6) {
1128                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
1129                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
1130         }
1131         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
1132                      ~(B43_NPHY_RFSEQMODE_CAOVER |
1133                        B43_NPHY_RFSEQMODE_TROVER));
1134         if (dev->phy.rev >= 3)
1135                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
1136         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
1137
1138         if (dev->phy.rev <= 2) {
1139                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
1140                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1141                                 ~B43_NPHY_BPHY_CTL3_SCALE,
1142                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
1143         }
1144         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
1145         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
1146
1147         if (bus->sprom.boardflags2_lo & 0x100 ||
1148             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
1149              bus->boardinfo.type == 0x8B))
1150                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
1151         else
1152                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
1153         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
1154         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
1155         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
1156
1157         /* TODO MIMO-Config */
1158         /* TODO Update TX/RX chain */
1159
1160         if (phy->rev < 2) {
1161                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
1162                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
1163         }
1164
1165         tmp2 = b43_current_band(dev->wl);
1166         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
1167             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
1168                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
1169                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
1170                                 nphy->papd_epsilon_offset[0] << 7);
1171                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
1172                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
1173                                 nphy->papd_epsilon_offset[1] << 7);
1174                 /* TODO N PHY IPA Set TX Dig Filters */
1175         } else if (phy->rev >= 5) {
1176                 /* TODO N PHY Ext PA Set TX Dig Filters */
1177         }
1178
1179         b43_nphy_workarounds(dev);
1180
1181         /* Reset CCA, in init code it differs a little from standard way */
1182         /* b43_nphy_bmac_clock_fgc(dev, 1); */
1183         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
1184         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
1185         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
1186         /* b43_nphy_bmac_clock_fgc(dev, 0); */
1187
1188         /* TODO N PHY MAC PHY Clock Set with argument 1 */
1189
1190         b43_nphy_pa_override(dev, false);
1191         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1192         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1193         b43_nphy_pa_override(dev, true);
1194
1195         b43_nphy_classifier(dev, 0, 0);
1196         b43_nphy_read_clip_detection(dev, clip);
1197         tx_pwr_state = nphy->txpwrctrl;
1198         /* TODO N PHY TX power control with argument 0
1199                 (turning off power control) */
1200         /* TODO Fix the TX Power Settings */
1201         /* TODO N PHY TX Power Control Idle TSSI */
1202         /* TODO N PHY TX Power Control Setup */
1203
1204         if (phy->rev >= 3) {
1205                 /* TODO */
1206         } else {
1207                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1208                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1209         }
1210
1211         if (nphy->phyrxchain != 3)
1212                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1213         if (nphy->mphase_cal_phase_id > 0)
1214                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1215
1216         do_rssi_cal = false;
1217         if (phy->rev >= 3) {
1218                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1219                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1220                 else
1221                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1222
1223                 if (do_rssi_cal)
1224                         b43_nphy_rssi_cal(dev);
1225                 else
1226                         b43_nphy_restore_rssi_cal(dev);
1227         } else {
1228                 b43_nphy_rssi_cal(dev);
1229         }
1230
1231         if (!((nphy->measure_hold & 0x6) != 0)) {
1232                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1233                         do_cal = (nphy->iqcal_chanspec_2G == 0);
1234                 else
1235                         do_cal = (nphy->iqcal_chanspec_5G == 0);
1236
1237                 if (nphy->mute)
1238                         do_cal = false;
1239
1240                 if (do_cal) {
1241                         /* target = b43_nphy_get_tx_gains(dev); */
1242
1243                         if (nphy->antsel_type == 2)
1244                                 ;/*TODO NPHY Superswitch Init with argument 1*/
1245                         if (nphy->perical != 2) {
1246                                 b43_nphy_rssi_cal(dev);
1247                                 if (phy->rev >= 3) {
1248                                         nphy->cal_orig_pwr_idx[0] =
1249                                             nphy->txpwrindex[0].index_internal;
1250                                         nphy->cal_orig_pwr_idx[1] =
1251                                             nphy->txpwrindex[1].index_internal;
1252                                         /* TODO N PHY Pre Calibrate TX Gain */
1253                                         /*target = b43_nphy_get_tx_gains(dev)*/
1254                                 }
1255                         }
1256                 }
1257         }
1258
1259         /*
1260         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1261                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1262                         Call N PHY Save Cal
1263                 else if (nphy->mphase_cal_phase_id == 0)
1264                         N PHY Periodic Calibration with argument 3
1265         } else {
1266                 b43_nphy_restore_cal(dev);
1267         }
1268         */
1269
1270         /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1271         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1272         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1273         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1274         if (phy->rev >= 3 && phy->rev <= 6)
1275                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1276         /* b43_nphy_tx_lp_fbw(dev); */
1277         /* TODO N PHY Spur Workaround */
1278
1279         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
1280         return 0;
1281 }
1282
1283 static int b43_nphy_op_allocate(struct b43_wldev *dev)
1284 {
1285         struct b43_phy_n *nphy;
1286
1287         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1288         if (!nphy)
1289                 return -ENOMEM;
1290         dev->phy.n = nphy;
1291
1292         return 0;
1293 }
1294
1295 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
1296 {
1297         struct b43_phy *phy = &dev->phy;
1298         struct b43_phy_n *nphy = phy->n;
1299
1300         memset(nphy, 0, sizeof(*nphy));
1301
1302         //TODO init struct b43_phy_n
1303 }
1304
1305 static void b43_nphy_op_free(struct b43_wldev *dev)
1306 {
1307         struct b43_phy *phy = &dev->phy;
1308         struct b43_phy_n *nphy = phy->n;
1309
1310         kfree(nphy);
1311         phy->n = NULL;
1312 }
1313
1314 static int b43_nphy_op_init(struct b43_wldev *dev)
1315 {
1316         return b43_phy_initn(dev);
1317 }
1318
1319 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1320 {
1321 #if B43_DEBUG
1322         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1323                 /* OFDM registers are onnly available on A/G-PHYs */
1324                 b43err(dev->wl, "Invalid OFDM PHY access at "
1325                        "0x%04X on N-PHY\n", offset);
1326                 dump_stack();
1327         }
1328         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1329                 /* Ext-G registers are only available on G-PHYs */
1330                 b43err(dev->wl, "Invalid EXT-G PHY access at "
1331                        "0x%04X on N-PHY\n", offset);
1332                 dump_stack();
1333         }
1334 #endif /* B43_DEBUG */
1335 }
1336
1337 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1338 {
1339         check_phyreg(dev, reg);
1340         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1341         return b43_read16(dev, B43_MMIO_PHY_DATA);
1342 }
1343
1344 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1345 {
1346         check_phyreg(dev, reg);
1347         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1348         b43_write16(dev, B43_MMIO_PHY_DATA, value);
1349 }
1350
1351 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1352 {
1353         /* Register 1 is a 32-bit register. */
1354         B43_WARN_ON(reg == 1);
1355         /* N-PHY needs 0x100 for read access */
1356         reg |= 0x100;
1357
1358         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1359         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1360 }
1361
1362 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1363 {
1364         /* Register 1 is a 32-bit register. */
1365         B43_WARN_ON(reg == 1);
1366
1367         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1368         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1369 }
1370
1371 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
1372                                         bool blocked)
1373 {//TODO
1374 }
1375
1376 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1377 {
1378         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1379                       on ? 0 : 0x7FFF);
1380 }
1381
1382 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1383                                       unsigned int new_channel)
1384 {
1385         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1386                 if ((new_channel < 1) || (new_channel > 14))
1387                         return -EINVAL;
1388         } else {
1389                 if (new_channel > 200)
1390                         return -EINVAL;
1391         }
1392
1393         return nphy_channel_switch(dev, new_channel);
1394 }
1395
1396 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1397 {
1398         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1399                 return 1;
1400         return 36;
1401 }
1402
1403 const struct b43_phy_operations b43_phyops_n = {
1404         .allocate               = b43_nphy_op_allocate,
1405         .free                   = b43_nphy_op_free,
1406         .prepare_structs        = b43_nphy_op_prepare_structs,
1407         .init                   = b43_nphy_op_init,
1408         .phy_read               = b43_nphy_op_read,
1409         .phy_write              = b43_nphy_op_write,
1410         .radio_read             = b43_nphy_op_radio_read,
1411         .radio_write            = b43_nphy_op_radio_write,
1412         .software_rfkill        = b43_nphy_op_software_rfkill,
1413         .switch_analog          = b43_nphy_op_switch_analog,
1414         .switch_channel         = b43_nphy_op_switch_channel,
1415         .get_default_chan       = b43_nphy_op_get_default_chan,
1416         .recalc_txpower         = b43_nphy_op_recalc_txpower,
1417         .adjust_txpower         = b43_nphy_op_adjust_txpower,
1418 };