SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75
  76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77 {//TODO
  78 }
  79
  80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  81 {//TODO
  82 }
  83
  84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  85                                                         bool ignore_tssi)
  86 {//TODO
  87         return B43_TXPWR_RES_DONE;
  88 }
  89
  90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  91                                      const struct b43_nphy_channeltab_entry *e)
  92 {
  93         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
  94         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  95         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  96         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  97         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  98
  99         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 100         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 101         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 102         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 103         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 104
 105         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 106         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 107         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 108         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 109         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 110
 111         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 112         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 113         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 114         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 115         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 116
 117         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 118         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 119         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 120         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 121         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 122
 123         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 124         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 125 }
 126
 127 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 128                                    const struct b43_nphy_channeltab_entry *e)
 129 {
 130         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 131         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 132         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 133         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 134         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 135         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 136 }
 137
 138 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 139 {
 140         //TODO
 141 }
 142
 143 /* Tune the hardware to a new channel. */
 144 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 145 {
 146         const struct b43_nphy_channeltab_entry *tabent;
 147
 148         tabent = b43_nphy_get_chantabent(dev, channel);
 149         if (!tabent)
 150                 return -ESRCH;
 151
 152         //FIXME enable/disable band select upper20 in RXCTL
 153         if (0 /*FIXME 5Ghz*/)
 154                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 155         else
 156                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 157         b43_chantab_radio_upload(dev, tabent);
 158         udelay(50);
 159         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 160         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 161         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 162         udelay(300);
 163         if (0 /*FIXME 5Ghz*/)
 164                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 165         else
 166                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 167         b43_chantab_phy_upload(dev, tabent);
 168         b43_nphy_tx_power_fix(dev);
 169
 170         return 0;
 171 }
 172
 173 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 174 {
 175         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 176                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 177         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 178                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 179                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 180         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 181                     B43_NPHY_RFCTL_CMD_PORFORCE);
 182 }
 183
 184 static void b43_radio_init2055_post(struct b43_wldev *dev)
 185 {
 186         struct b43_phy_n *nphy = dev->phy.n;
 187         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 188         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 189         int i;
 190         u16 val;
 191         bool workaround = false;
 192
 193         if (sprom->revision < 4)
 194                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
 195                                 binfo->type != 0x46D ||
 196                                 binfo->rev < 0x41);
 197         else
 198                 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
 199
 200         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 201         if (workaround) {
 202                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 203                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
 204         }
 205         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
 206         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
 207         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 208         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 209         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 210         msleep(1);
 211         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 212         for (i = 0; i < 200; i++) {
 213                 val = b43_radio_read(dev, B2055_CAL_COUT2);
 214                 if (val & 0x80) {
 215                         i = 0;
 216                         break;
 217                 }
 218                 udelay(10);
 219         }
 220         if (i)
 221                 b43err(dev->wl, "radio post init timeout\n");
 222         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 223         nphy_channel_switch(dev, dev->phy.channel);
 224         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
 225         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
 226         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 227         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 228         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
 229         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
 230         if (!nphy->gain_boost) {
 231                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
 232                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
 233         } else {
 234                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
 235                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
 236         }
 237         udelay(2);
 238 }
 239
 240 /*
 241  * Initialize a Broadcom 2055 N-radio
 242  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 243  */
 244 static void b43_radio_init2055(struct b43_wldev *dev)
 245 {
 246         b43_radio_init2055_pre(dev);
 247         if (b43_status(dev) < B43_STAT_INITIALIZED)
 248                 b2055_upload_inittab(dev, 0, 1);
 249         else
 250                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 251         b43_radio_init2055_post(dev);
 252 }
 253
 254 /*
 255  * Upload the N-PHY tables.
 256  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 257  */
 258 static void b43_nphy_tables_init(struct b43_wldev *dev)
 259 {
 260         if (dev->phy.rev < 3)
 261                 b43_nphy_rev0_1_2_tables_init(dev);
 262         else
 263                 b43_nphy_rev3plus_tables_init(dev);
 264 }
 265
 266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 267 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 268 {
 269         struct b43_phy_n *nphy = dev->phy.n;
 270         enum ieee80211_band band;
 271         u16 tmp;
 272
 273         if (!enable) {
 274                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 275                                                        B43_NPHY_RFCTL_INTC1);
 276                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 277                                                        B43_NPHY_RFCTL_INTC2);
 278                 band = b43_current_band(dev->wl);
 279                 if (dev->phy.rev >= 3) {
 280                         if (band == IEEE80211_BAND_5GHZ)
 281                                 tmp = 0x600;
 282                         else
 283                                 tmp = 0x480;
 284                 } else {
 285                         if (band == IEEE80211_BAND_5GHZ)
 286                                 tmp = 0x180;
 287                         else
 288                                 tmp = 0x120;
 289                 }
 290                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 291                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 292         } else {
 293                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 294                                 nphy->rfctrl_intc1_save);
 295                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 296                                 nphy->rfctrl_intc2_save);
 297         }
 298 }
 299
 300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 301 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 302 {
 303         struct b43_phy_n *nphy = dev->phy.n;
 304         u16 tmp;
 305         enum ieee80211_band band = b43_current_band(dev->wl);
 306         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 307                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 308
 309         if (dev->phy.rev >= 3) {
 310                 if (ipa) {
 311                         tmp = 4;
 312                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 313                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 314                 }
 315
 316                 tmp = 1;
 317                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 318                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 319         }
 320 }
 321
 322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 323 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 324 {
 325         u32 tmslow;
 326
 327         if (dev->phy.type != B43_PHYTYPE_N)
 328                 return;
 329
 330         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 331         if (force)
 332                 tmslow |= SSB_TMSLOW_FGC;
 333         else
 334                 tmslow &= ~SSB_TMSLOW_FGC;
 335         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 336 }
 337
 338 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 339 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 340 {
 341         u16 bbcfg;
 342
 343         b43_nphy_bmac_clock_fgc(dev, 1);
 344         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 345         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 346         udelay(1);
 347         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 348         b43_nphy_bmac_clock_fgc(dev, 0);
 349         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 350 }
 351
 352 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 353 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 354 {
 355         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 356
 357         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 358         if (preamble == 1)
 359                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 360         else
 361                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 362
 363         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 364 }
 365
 366 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 367 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 368 {
 369         struct b43_phy_n *nphy = dev->phy.n;
 370
 371         bool override = false;
 372         u16 chain = 0x33;
 373
 374         if (nphy->txrx_chain == 0) {
 375                 chain = 0x11;
 376                 override = true;
 377         } else if (nphy->txrx_chain == 1) {
 378                 chain = 0x22;
 379                 override = true;
 380         }
 381
 382         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 383                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 384                         chain);
 385
 386         if (override)
 387                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 388                                 B43_NPHY_RFSEQMODE_CAOVER);
 389         else
 390                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 391                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 392 }
 393
 394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 395 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 396                                 u16 samps, u8 time, bool wait)
 397 {
 398         int i;
 399         u16 tmp;
 400
 401         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 402         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 403         if (wait)
 404                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 405         else
 406                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 407
 408         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 409
 410         for (i = 1000; i; i--) {
 411                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 412                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 413                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 414                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 415                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 416                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 417                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 418                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 419
 420                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 421                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 422                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 423                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 424                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 425                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 426                         return;
 427                 }
 428                 udelay(10);
 429         }
 430         memset(est, 0, sizeof(*est));
 431 }
 432
 433 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 434 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 435                                         struct b43_phy_n_iq_comp *pcomp)
 436 {
 437         if (write) {
 438                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 439                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 440                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 441                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 442         } else {
 443                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 444                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 445                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 446                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 447         }
 448 }
 449
 450 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 451 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 452 {
 453         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 454
 455         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 456         if (core == 0) {
 457                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 458                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 459         } else {
 460                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 461                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 462         }
 463         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 464         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 465         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 466         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 467         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 468         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 469         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 470         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 471 }
 472
 473 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 474 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 475 {
 476         u8 rxval, txval;
 477         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 478
 479         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 480         if (core == 0) {
 481                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 482                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 483         } else {
 484                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 485                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 486         }
 487         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 488         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 489         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 490         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 491         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 492         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 493         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 494         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 495
 496         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 497         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 498
 499         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 500                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 501         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 502                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 503         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 504                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 505         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 506                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 507
 508         if (core == 0) {
 509                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 510                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 511         } else {
 512                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 513                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 514         }
 515
 516         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 517         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 518         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 519
 520         if (core == 0) {
 521                 rxval = 1;
 522                 txval = 8;
 523         } else {
 524                 rxval = 4;
 525                 txval = 2;
 526         }
 527         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 528         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 529 }
 530
 531 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 532 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 533 {
 534         int i;
 535         s32 iq;
 536         u32 ii;
 537         u32 qq;
 538         int iq_nbits, qq_nbits;
 539         int arsh, brsh;
 540         u16 tmp, a, b;
 541
 542         struct nphy_iq_est est;
 543         struct b43_phy_n_iq_comp old;
 544         struct b43_phy_n_iq_comp new = { };
 545         bool error = false;
 546
 547         if (mask == 0)
 548                 return;
 549
 550         b43_nphy_rx_iq_coeffs(dev, false, &old);
 551         b43_nphy_rx_iq_coeffs(dev, true, &new);
 552         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 553         new = old;
 554
 555         for (i = 0; i < 2; i++) {
 556                 if (i == 0 && (mask & 1)) {
 557                         iq = est.iq0_prod;
 558                         ii = est.i0_pwr;
 559                         qq = est.q0_pwr;
 560                 } else if (i == 1 && (mask & 2)) {
 561                         iq = est.iq1_prod;
 562                         ii = est.i1_pwr;
 563                         qq = est.q1_pwr;
 564                 } else {
 565                         B43_WARN_ON(1);
 566                         continue;
 567                 }
 568
 569                 if (ii + qq < 2) {
 570                         error = true;
 571                         break;
 572                 }
 573
 574                 iq_nbits = fls(abs(iq));
 575                 qq_nbits = fls(qq);
 576
 577                 arsh = iq_nbits - 20;
 578                 if (arsh >= 0) {
 579                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 580                         tmp = ii >> arsh;
 581                 } else {
 582                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 583                         tmp = ii << -arsh;
 584                 }
 585                 if (tmp == 0) {
 586                         error = true;
 587                         break;
 588                 }
 589                 a /= tmp;
 590
 591                 brsh = qq_nbits - 11;
 592                 if (brsh >= 0) {
 593                         b = (qq << (31 - qq_nbits));
 594                         tmp = ii >> brsh;
 595                 } else {
 596                         b = (qq << (31 - qq_nbits));
 597                         tmp = ii << -brsh;
 598                 }
 599                 if (tmp == 0) {
 600                         error = true;
 601                         break;
 602                 }
 603                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 604
 605                 if (i == 0 && (mask & 0x1)) {
 606                         if (dev->phy.rev >= 3) {
 607                                 new.a0 = a & 0x3FF;
 608                                 new.b0 = b & 0x3FF;
 609                         } else {
 610                                 new.a0 = b & 0x3FF;
 611                                 new.b0 = a & 0x3FF;
 612                         }
 613                 } else if (i == 1 && (mask & 0x2)) {
 614                         if (dev->phy.rev >= 3) {
 615                                 new.a1 = a & 0x3FF;
 616                                 new.b1 = b & 0x3FF;
 617                         } else {
 618                                 new.a1 = b & 0x3FF;
 619                                 new.b1 = a & 0x3FF;
 620                         }
 621                 }
 622         }
 623
 624         if (error)
 625                 new = old;
 626
 627         b43_nphy_rx_iq_coeffs(dev, true, &new);
 628 }
 629
 630 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 631 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 632 {
 633         u16 array[4];
 634         int i;
 635
 636         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 637         for (i = 0; i < 4; i++)
 638                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 639
 640         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 641         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 642         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 643         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 644 }
 645
 646 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 647 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 648 {
 649         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 650         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 651 }
 652
 653 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 654 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 655 {
 656         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 657         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 658 }
 659
 660 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 661 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 662 {
 663         if (dev->phy.rev >= 3) {
 664                 if (!init)
 665                         return;
 666                 if (0 /* FIXME */) {
 667                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 668                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 669                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 670                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 671                 }
 672         } else {
 673                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 674                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 675
 676                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 677                                         0xFC00);
 678                 b43_write32(dev, B43_MMIO_MACCTL,
 679                         b43_read32(dev, B43_MMIO_MACCTL) &
 680                         ~B43_MACCTL_GPOUTSMSK);
 681                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 682                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 683                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 684                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 685
 686                 if (init) {
 687                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 688                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 689                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 690                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 691                 }
 692         }
 693 }
 694
 695 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 696 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 697 {
 698         u16 tmp;
 699
 700         if (dev->dev->id.revision == 16)
 701                 b43_mac_suspend(dev);
 702
 703         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 704         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 705                 B43_NPHY_CLASSCTL_WAITEDEN);
 706         tmp &= ~mask;
 707         tmp |= (val & mask);
 708         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 709
 710         if (dev->dev->id.revision == 16)
 711                 b43_mac_enable(dev);
 712
 713         return tmp;
 714 }
 715
 716 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 717 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 718 {
 719         struct b43_phy *phy = &dev->phy;
 720         struct b43_phy_n *nphy = phy->n;
 721
 722         if (enable) {
 723                 u16 clip[] = { 0xFFFF, 0xFFFF };
 724                 if (nphy->deaf_count++ == 0) {
 725                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 726                         b43_nphy_classifier(dev, 0x7, 0);
 727                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 728                         b43_nphy_write_clip_detection(dev, clip);
 729                 }
 730                 b43_nphy_reset_cca(dev);
 731         } else {
 732                 if (--nphy->deaf_count == 0) {
 733                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 734                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 735                 }
 736         }
 737 }
 738
 739 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 740 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 741 {
 742         struct b43_phy_n *nphy = dev->phy.n;
 743         u16 tmp;
 744
 745         if (nphy->hang_avoid)
 746                 b43_nphy_stay_in_carrier_search(dev, 1);
 747
 748         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 749         if (tmp & 0x1)
 750                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 751         else if (tmp & 0x2)
 752                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 753
 754         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 755
 756         if (nphy->bb_mult_save & 0x80000000) {
 757                 tmp = nphy->bb_mult_save & 0xFFFF;
 758                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 759                 nphy->bb_mult_save = 0;
 760         }
 761
 762         if (nphy->hang_avoid)
 763                 b43_nphy_stay_in_carrier_search(dev, 0);
 764 }
 765
 766 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 767 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 768 {
 769         struct b43_phy_n *nphy = dev->phy.n;
 770
 771         unsigned int channel;
 772         int tone[2] = { 57, 58 };
 773         u32 noise[2] = { 0x3FF, 0x3FF };
 774
 775         B43_WARN_ON(dev->phy.rev < 3);
 776
 777         if (nphy->hang_avoid)
 778                 b43_nphy_stay_in_carrier_search(dev, 1);
 779
 780         /* FIXME: channel = radio_chanspec */
 781
 782         if (nphy->gband_spurwar_en) {
 783                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 784                 if (channel == 11 && dev->phy.is_40mhz)
 785                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 786                 else
 787                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 788                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 789         }
 790
 791         if (nphy->aband_spurwar_en) {
 792                 if (channel == 54) {
 793                         tone[0] = 0x20;
 794                         noise[0] = 0x25F;
 795                 } else if (channel == 38 || channel == 102 || channel == 118) {
 796                         if (0 /* FIXME */) {
 797                                 tone[0] = 0x20;
 798                                 noise[0] = 0x21F;
 799                         } else {
 800                                 tone[0] = 0;
 801                                 noise[0] = 0;
 802                         }
 803                 } else if (channel == 134) {
 804                         tone[0] = 0x20;
 805                         noise[0] = 0x21F;
 806                 } else if (channel == 151) {
 807                         tone[0] = 0x10;
 808                         noise[0] = 0x23F;
 809                 } else if (channel == 153 || channel == 161) {
 810                         tone[0] = 0x30;
 811                         noise[0] = 0x23F;
 812                 } else {
 813                         tone[0] = 0;
 814                         noise[0] = 0;
 815                 }
 816
 817                 if (!tone[0] && !noise[0])
 818                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 819                 else
 820                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 821         }
 822
 823         if (nphy->hang_avoid)
 824                 b43_nphy_stay_in_carrier_search(dev, 0);
 825 }
 826
 827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 828 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 829 {
 830         struct b43_phy_n *nphy = dev->phy.n;
 831         u8 i, j;
 832         u8 code;
 833
 834         /* TODO: for PHY >= 3
 835         s8 *lna1_gain, *lna2_gain;
 836         u8 *gain_db, *gain_bits;
 837         u16 *rfseq_init;
 838         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 839         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 840         */
 841
 842         u8 rfseq_events[3] = { 6, 8, 7 };
 843         u8 rfseq_delays[3] = { 10, 30, 1 };
 844
 845         if (dev->phy.rev >= 3) {
 846                 /* TODO */
 847         } else {
 848                 /* Set Clip 2 detect */
 849                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 850                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 851                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 852                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 853
 854                 /* Set narrowband clip threshold */
 855                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 856                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 857
 858                 if (!dev->phy.is_40mhz) {
 859                         /* Set dwell lengths */
 860                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 861                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 862                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 863                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 864                 }
 865
 866                 /* Set wideband clip 2 threshold */
 867                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 868                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 869                                 21);
 870                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 871                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 872                                 21);
 873
 874                 if (!dev->phy.is_40mhz) {
 875                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 876                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 877                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 878                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 879                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 880                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 881                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 882                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 883                 }
 884
 885                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 886
 887                 if (nphy->gain_boost) {
 888                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 889                             dev->phy.is_40mhz)
 890                                 code = 4;
 891                         else
 892                                 code = 5;
 893                 } else {
 894                         code = dev->phy.is_40mhz ? 6 : 7;
 895                 }
 896
 897                 /* Set HPVGA2 index */
 898                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 899                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 900                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 901                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 902                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 903                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 904
 905                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 906                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 907                                         (code << 8 | 0x7C));
 908                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 909                                         (code << 8 | 0x7C));
 910
 911                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 912
 913                 if (nphy->elna_gain_config) {
 914                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 915                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 916                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 917                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 918                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 919
 920                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 921                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 922                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 923                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 924                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 925
 926                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 927                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 928                                         (code << 8 | 0x74));
 929                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 930                                         (code << 8 | 0x74));
 931                 }
 932
 933                 if (dev->phy.rev == 2) {
 934                         for (i = 0; i < 4; i++) {
 935                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 936                                                 (0x0400 * i) + 0x0020);
 937                                 for (j = 0; j < 21; j++)
 938                                         b43_phy_write(dev,
 939                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 940                         }
 941
 942                         b43_nphy_set_rf_sequence(dev, 5,
 943                                         rfseq_events, rfseq_delays, 3);
 944                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 945                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 946                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 947
 948                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 949                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 950                                                 0xFF80, 4);
 951                 }
 952         }
 953 }
 954
 955 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 956 static void b43_nphy_workarounds(struct b43_wldev *dev)
 957 {
 958         struct ssb_bus *bus = dev->dev->bus;
 959         struct b43_phy *phy = &dev->phy;
 960         struct b43_phy_n *nphy = phy->n;
 961
 962         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 963         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 964
 965         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 966         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 967
 968         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 969                 b43_nphy_classifier(dev, 1, 0);
 970         else
 971                 b43_nphy_classifier(dev, 1, 1);
 972
 973         if (nphy->hang_avoid)
 974                 b43_nphy_stay_in_carrier_search(dev, 1);
 975
 976         b43_phy_set(dev, B43_NPHY_IQFLIP,
 977                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 978
 979         if (dev->phy.rev >= 3) {
 980                 /* TODO */
 981         } else {
 982                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 983                     nphy->band5g_pwrgain) {
 984                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 985                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 986                 } else {
 987                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 988                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 989                 }
 990
 991                 /* TODO: convert to b43_ntab_write? */
 992                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 993                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 994                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 995                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 996                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 997                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 998                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 999                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1000
1001                 if (dev->phy.rev < 2) {
1002                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1003                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1004                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1005                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1006                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1007                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1008                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1009                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1010                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1011                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1012                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1013                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1014                 }
1015
1016                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1017                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1018                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1019                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1020
1021                 if (bus->sprom.boardflags2_lo & 0x100 &&
1022                     bus->boardinfo.type == 0x8B) {
1023                         delays1[0] = 0x1;
1024                         delays1[5] = 0x14;
1025                 }
1026                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1027                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1028
1029                 b43_nphy_gain_crtl_workarounds(dev);
1030
1031                 if (dev->phy.rev < 2) {
1032                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1033                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1034                 } else if (dev->phy.rev == 2) {
1035                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1036                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1037                 }
1038
1039                 if (dev->phy.rev < 2)
1040                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1041                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1042
1043                 /* Set phase track alpha and beta */
1044                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1045                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1046                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1047                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1048                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1049                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1050
1051                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1052                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1053                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1054                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1055                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1056
1057                 if (dev->phy.rev == 2)
1058                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1059                                         B43_NPHY_FINERX2_CGC_DECGC);
1060         }
1061
1062         if (nphy->hang_avoid)
1063                 b43_nphy_stay_in_carrier_search(dev, 0);
1064 }
1065
1066 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1067 static int b43_nphy_load_samples(struct b43_wldev *dev,
1068                                         struct b43_c32 *samples, u16 len) {
1069         struct b43_phy_n *nphy = dev->phy.n;
1070         u16 i;
1071         u32 *data;
1072
1073         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1074         if (!data) {
1075                 b43err(dev->wl, "allocation for samples loading failed\n");
1076                 return -ENOMEM;
1077         }
1078         if (nphy->hang_avoid)
1079                 b43_nphy_stay_in_carrier_search(dev, 1);
1080
1081         for (i = 0; i < len; i++) {
1082                 data[i] = (samples[i].i & 0x3FF << 10);
1083                 data[i] |= samples[i].q & 0x3FF;
1084         }
1085         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1086
1087         kfree(data);
1088         if (nphy->hang_avoid)
1089                 b43_nphy_stay_in_carrier_search(dev, 0);
1090         return 0;
1091 }
1092
1093 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1094 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1095                                         bool test)
1096 {
1097         int i;
1098         u16 bw, len, rot, angle;
1099         struct b43_c32 *samples;
1100
1101
1102         bw = (dev->phy.is_40mhz) ? 40 : 20;
1103         len = bw << 3;
1104
1105         if (test) {
1106                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1107                         bw = 82;
1108                 else
1109                         bw = 80;
1110
1111                 if (dev->phy.is_40mhz)
1112                         bw <<= 1;
1113
1114                 len = bw << 1;
1115         }
1116
1117         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1118         if (!samples) {
1119                 b43err(dev->wl, "allocation for samples generation failed\n");
1120                 return 0;
1121         }
1122         rot = (((freq * 36) / bw) << 16) / 100;
1123         angle = 0;
1124
1125         for (i = 0; i < len; i++) {
1126                 samples[i] = b43_cordic(angle);
1127                 angle += rot;
1128                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1129                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1130         }
1131
1132         i = b43_nphy_load_samples(dev, samples, len);
1133         kfree(samples);
1134         return (i < 0) ? 0 : len;
1135 }
1136
1137 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1138 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1139                                         u16 wait, bool iqmode, bool dac_test)
1140 {
1141         struct b43_phy_n *nphy = dev->phy.n;
1142         int i;
1143         u16 seq_mode;
1144         u32 tmp;
1145
1146         if (nphy->hang_avoid)
1147                 b43_nphy_stay_in_carrier_search(dev, true);
1148
1149         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1150                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1151                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1152         }
1153
1154         if (!dev->phy.is_40mhz)
1155                 tmp = 0x6464;
1156         else
1157                 tmp = 0x4747;
1158         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1159
1160         if (nphy->hang_avoid)
1161                 b43_nphy_stay_in_carrier_search(dev, false);
1162
1163         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1164
1165         if (loops != 0xFFFF)
1166                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1167         else
1168                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1169
1170         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1171
1172         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1173
1174         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1175         if (iqmode) {
1176                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1177                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1178         } else {
1179                 if (dac_test)
1180                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1181                 else
1182                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1183         }
1184         for (i = 0; i < 100; i++) {
1185                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1186                         i = 0;
1187                         break;
1188                 }
1189                 udelay(10);
1190         }
1191         if (i)
1192                 b43err(dev->wl, "run samples timeout\n");
1193
1194         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1195 }
1196
1197 /*
1198  * Transmits a known value for LO calibration
1199  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1200  */
1201 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1202                                 bool iqmode, bool dac_test)
1203 {
1204         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1205         if (samp == 0)
1206                 return -1;
1207         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1208         return 0;
1209 }
1210
1211 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1212 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1213 {
1214         struct b43_phy_n *nphy = dev->phy.n;
1215         int i, j;
1216         u32 tmp;
1217         u32 cur_real, cur_imag, real_part, imag_part;
1218
1219         u16 buffer[7];
1220
1221         if (nphy->hang_avoid)
1222                 b43_nphy_stay_in_carrier_search(dev, true);
1223
1224         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1225
1226         for (i = 0; i < 2; i++) {
1227                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1228                         (buffer[i * 2 + 1] & 0x3FF);
1229                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1230                                 (((i + 26) << 10) | 320));
1231                 for (j = 0; j < 128; j++) {
1232                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1233                                         ((tmp >> 16) & 0xFFFF));
1234                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1235                                         (tmp & 0xFFFF));
1236                 }
1237         }
1238
1239         for (i = 0; i < 2; i++) {
1240                 tmp = buffer[5 + i];
1241                 real_part = (tmp >> 8) & 0xFF;
1242                 imag_part = (tmp & 0xFF);
1243                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1244                                 (((i + 26) << 10) | 448));
1245
1246                 if (dev->phy.rev >= 3) {
1247                         cur_real = real_part;
1248                         cur_imag = imag_part;
1249                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1250                 }
1251
1252                 for (j = 0; j < 128; j++) {
1253                         if (dev->phy.rev < 3) {
1254                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1255                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1256                                 tmp = ((cur_real & 0xFF) << 8) |
1257                                         (cur_imag & 0xFF);
1258                         }
1259                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1260                                         ((tmp >> 16) & 0xFFFF));
1261                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1262                                         (tmp & 0xFFFF));
1263                 }
1264         }
1265
1266         if (dev->phy.rev >= 3) {
1267                 b43_shm_write16(dev, B43_SHM_SHARED,
1268                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1269                 b43_shm_write16(dev, B43_SHM_SHARED,
1270                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1271         }
1272
1273         if (nphy->hang_avoid)
1274                 b43_nphy_stay_in_carrier_search(dev, false);
1275 }
1276
1277 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1278 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1279                                         u8 *events, u8 *delays, u8 length)
1280 {
1281         struct b43_phy_n *nphy = dev->phy.n;
1282         u8 i;
1283         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1284         u16 offset1 = cmd << 4;
1285         u16 offset2 = offset1 + 0x80;
1286
1287         if (nphy->hang_avoid)
1288                 b43_nphy_stay_in_carrier_search(dev, true);
1289
1290         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1291         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1292
1293         for (i = length; i < 16; i++) {
1294                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1295                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1296         }
1297
1298         if (nphy->hang_avoid)
1299                 b43_nphy_stay_in_carrier_search(dev, false);
1300 }
1301
1302 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1303 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1304                                        enum b43_nphy_rf_sequence seq)
1305 {
1306         static const u16 trigger[] = {
1307                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1308                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1309                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1310                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1311                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1312                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1313         };
1314         int i;
1315         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1316
1317         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1318
1319         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1320                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1321         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1322         for (i = 0; i < 200; i++) {
1323                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1324                         goto ok;
1325                 msleep(1);
1326         }
1327         b43err(dev->wl, "RF sequence status timeout\n");
1328 ok:
1329         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1330 }
1331
1332 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1333 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1334                                                 u16 value, u8 core, bool off)
1335 {
1336         int i;
1337         u8 index = fls(field);
1338         u8 addr, en_addr, val_addr;
1339         /* we expect only one bit set */
1340         B43_WARN_ON(field & (~(1 << (index - 1))));
1341
1342         if (dev->phy.rev >= 3) {
1343                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1344                 for (i = 0; i < 2; i++) {
1345                         if (index == 0 || index == 16) {
1346                                 b43err(dev->wl,
1347                                         "Unsupported RF Ctrl Override call\n");
1348                                 return;
1349                         }
1350
1351                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1352                         en_addr = B43_PHY_N((i == 0) ?
1353                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1354                         val_addr = B43_PHY_N((i == 0) ?
1355                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1356
1357                         if (off) {
1358                                 b43_phy_mask(dev, en_addr, ~(field));
1359                                 b43_phy_mask(dev, val_addr,
1360                                                 ~(rf_ctrl->val_mask));
1361                         } else {
1362                                 if (core == 0 || ((1 << core) & i) != 0) {
1363                                         b43_phy_set(dev, en_addr, field);
1364                                         b43_phy_maskset(dev, val_addr,
1365                                                 ~(rf_ctrl->val_mask),
1366                                                 (value << rf_ctrl->val_shift));
1367                                 }
1368                         }
1369                 }
1370         } else {
1371                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1372                 if (off) {
1373                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1374                         value = 0;
1375                 } else {
1376                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1377                 }
1378
1379                 for (i = 0; i < 2; i++) {
1380                         if (index <= 1 || index == 16) {
1381                                 b43err(dev->wl,
1382                                         "Unsupported RF Ctrl Override call\n");
1383                                 return;
1384                         }
1385
1386                         if (index == 2 || index == 10 ||
1387                             (index >= 13 && index <= 15)) {
1388                                 core = 1;
1389                         }
1390
1391                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1392                         addr = B43_PHY_N((i == 0) ?
1393                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1394
1395                         if ((core & (1 << i)) != 0)
1396                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1397                                                 (value << rf_ctrl->shift));
1398
1399                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1400                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1401                                         B43_NPHY_RFCTL_CMD_START);
1402                         udelay(1);
1403                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1404                 }
1405         }
1406 }
1407
1408 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1409 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1410                                                 u16 value, u8 core)
1411 {
1412         u8 i, j;
1413         u16 reg, tmp, val;
1414
1415         B43_WARN_ON(dev->phy.rev < 3);
1416         B43_WARN_ON(field > 4);
1417
1418         for (i = 0; i < 2; i++) {
1419                 if ((core == 1 && i == 1) || (core == 2 && !i))
1420                         continue;
1421
1422                 reg = (i == 0) ?
1423                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1424                 b43_phy_mask(dev, reg, 0xFBFF);
1425
1426                 switch (field) {
1427                 case 0:
1428                         b43_phy_write(dev, reg, 0);
1429                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1430                         break;
1431                 case 1:
1432                         if (!i) {
1433                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1434                                                 0xFC3F, (value << 6));
1435                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1436                                                 0xFFFE, 1);
1437                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1438                                                 B43_NPHY_RFCTL_CMD_START);
1439                                 for (j = 0; j < 100; j++) {
1440                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1441                                                 j = 0;
1442                                                 break;
1443                                         }
1444                                         udelay(10);
1445                                 }
1446                                 if (j)
1447                                         b43err(dev->wl,
1448                                                 "intc override timeout\n");
1449                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1450                                                 0xFFFE);
1451                         } else {
1452                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1453                                                 0xFC3F, (value << 6));
1454                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1455                                                 0xFFFE, 1);
1456                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1457                                                 B43_NPHY_RFCTL_CMD_RXTX);
1458                                 for (j = 0; j < 100; j++) {
1459                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1460                                                 j = 0;
1461                                                 break;
1462                                         }
1463                                         udelay(10);
1464                                 }
1465                                 if (j)
1466                                         b43err(dev->wl,
1467                                                 "intc override timeout\n");
1468                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1469                                                 0xFFFE);
1470                         }
1471                         break;
1472                 case 2:
1473                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1474                                 tmp = 0x0020;
1475                                 val = value << 5;
1476                         } else {
1477                                 tmp = 0x0010;
1478                                 val = value << 4;
1479                         }
1480                         b43_phy_maskset(dev, reg, ~tmp, val);
1481                         break;
1482                 case 3:
1483                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1484                                 tmp = 0x0001;
1485                                 val = value;
1486                         } else {
1487                                 tmp = 0x0004;
1488                                 val = value << 2;
1489                         }
1490                         b43_phy_maskset(dev, reg, ~tmp, val);
1491                         break;
1492                 case 4:
1493                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1494                                 tmp = 0x0002;
1495                                 val = value << 1;
1496                         } else {
1497                                 tmp = 0x0008;
1498                                 val = value << 3;
1499                         }
1500                         b43_phy_maskset(dev, reg, ~tmp, val);
1501                         break;
1502                 }
1503         }
1504 }
1505
1506 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1507 {
1508         unsigned int i;
1509         u16 val;
1510
1511         val = 0x1E1F;
1512         for (i = 0; i < 14; i++) {
1513                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1514                 val -= 0x202;
1515         }
1516         val = 0x3E3F;
1517         for (i = 0; i < 16; i++) {
1518                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1519                 val -= 0x202;
1520         }
1521         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1522 }
1523
1524 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1525 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1526                                        s8 offset, u8 core, u8 rail, u8 type)
1527 {
1528         u16 tmp;
1529         bool core1or5 = (core == 1) || (core == 5);
1530         bool core2or5 = (core == 2) || (core == 5);
1531
1532         offset = clamp_val(offset, -32, 31);
1533         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1534
1535         if (core1or5 && (rail == 0) && (type == 2))
1536                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1537         if (core1or5 && (rail == 1) && (type == 2))
1538                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1539         if (core2or5 && (rail == 0) && (type == 2))
1540                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1541         if (core2or5 && (rail == 1) && (type == 2))
1542                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1543         if (core1or5 && (rail == 0) && (type == 0))
1544                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1545         if (core1or5 && (rail == 1) && (type == 0))
1546                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1547         if (core2or5 && (rail == 0) && (type == 0))
1548                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1549         if (core2or5 && (rail == 1) && (type == 0))
1550                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1551         if (core1or5 && (rail == 0) && (type == 1))
1552                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1553         if (core1or5 && (rail == 1) && (type == 1))
1554                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1555         if (core2or5 && (rail == 0) && (type == 1))
1556                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1557         if (core2or5 && (rail == 1) && (type == 1))
1558                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1559         if (core1or5 && (rail == 0) && (type == 6))
1560                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1561         if (core1or5 && (rail == 1) && (type == 6))
1562                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1563         if (core2or5 && (rail == 0) && (type == 6))
1564                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1565         if (core2or5 && (rail == 1) && (type == 6))
1566                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1567         if (core1or5 && (rail == 0) && (type == 3))
1568                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1569         if (core1or5 && (rail == 1) && (type == 3))
1570                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1571         if (core2or5 && (rail == 0) && (type == 3))
1572                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1573         if (core2or5 && (rail == 1) && (type == 3))
1574                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1575         if (core1or5 && (type == 4))
1576                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1577         if (core2or5 && (type == 4))
1578                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1579         if (core1or5 && (type == 5))
1580                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1581         if (core2or5 && (type == 5))
1582                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1583 }
1584
1585 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1586 {
1587         u16 val;
1588
1589         if (type < 3)
1590                 val = 0;
1591         else if (type == 6)
1592                 val = 1;
1593         else if (type == 3)
1594                 val = 2;
1595         else
1596                 val = 3;
1597
1598         val = (val << 12) | (val << 14);
1599         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1600         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1601
1602         if (type < 3) {
1603                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1604                                 (type + 1) << 4);
1605                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1606                                 (type + 1) << 4);
1607         }
1608
1609         /* TODO use some definitions */
1610         if (code == 0) {
1611                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1612                 if (type < 3) {
1613                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1614                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1615                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1616                         udelay(20);
1617                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1618                 }
1619         } else {
1620                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1621                                 0x3000);
1622                 if (type < 3) {
1623                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1624                                         0xFEC7, 0x0180);
1625                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1626                                         0xEFDC, (code << 1 | 0x1021));
1627                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1628                         udelay(20);
1629                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1630                 }
1631         }
1632 }
1633
1634 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1635 {
1636         struct b43_phy_n *nphy = dev->phy.n;
1637         u8 i;
1638         u16 reg, val;
1639
1640         if (code == 0) {
1641                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1642                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1643                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1644                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1645                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1646                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1647                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1648                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1649         } else {
1650                 for (i = 0; i < 2; i++) {
1651                         if ((code == 1 && i == 1) || (code == 2 && !i))
1652                                 continue;
1653
1654                         reg = (i == 0) ?
1655                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1656                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1657
1658                         if (type < 3) {
1659                                 reg = (i == 0) ?
1660                                         B43_NPHY_AFECTL_C1 :
1661                                         B43_NPHY_AFECTL_C2;
1662                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1663
1664                                 reg = (i == 0) ?
1665                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1666                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1667                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1668
1669                                 if (type == 0)
1670                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1671                                 else if (type == 1)
1672                                         val = 16;
1673                                 else
1674                                         val = 32;
1675                                 b43_phy_set(dev, reg, val);
1676
1677                                 reg = (i == 0) ?
1678                                         B43_NPHY_TXF_40CO_B1S0 :
1679                                         B43_NPHY_TXF_40CO_B32S1;
1680                                 b43_phy_set(dev, reg, 0x0020);
1681                         } else {
1682                                 if (type == 6)
1683                                         val = 0x0100;
1684                                 else if (type == 3)
1685                                         val = 0x0200;
1686                                 else
1687                                         val = 0x0300;
1688
1689                                 reg = (i == 0) ?
1690                                         B43_NPHY_AFECTL_C1 :
1691                                         B43_NPHY_AFECTL_C2;
1692
1693                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1694                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1695
1696                                 if (type != 3 && type != 6) {
1697                                         enum ieee80211_band band =
1698                                                 b43_current_band(dev->wl);
1699
1700                                         if ((nphy->ipa2g_on &&
1701                                                 band == IEEE80211_BAND_2GHZ) ||
1702                                                 (nphy->ipa5g_on &&
1703                                                 band == IEEE80211_BAND_5GHZ))
1704                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1705                                         else
1706                                                 val = 0x11;
1707                                         reg = (i == 0) ? 0x2000 : 0x3000;
1708                                         reg |= B2055_PADDRV;
1709                                         b43_radio_write16(dev, reg, val);
1710
1711                                         reg = (i == 0) ?
1712                                                 B43_NPHY_AFECTL_OVER1 :
1713                                                 B43_NPHY_AFECTL_OVER;
1714                                         b43_phy_set(dev, reg, 0x0200);
1715                                 }
1716                         }
1717                 }
1718         }
1719 }
1720
1721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1722 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1723 {
1724         if (dev->phy.rev >= 3)
1725                 b43_nphy_rev3_rssi_select(dev, code, type);
1726         else
1727                 b43_nphy_rev2_rssi_select(dev, code, type);
1728 }
1729
1730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1731 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1732 {
1733         int i;
1734         for (i = 0; i < 2; i++) {
1735                 if (type == 2) {
1736                         if (i == 0) {
1737                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1738                                                   0xFC, buf[0]);
1739                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1740                                                   0xFC, buf[1]);
1741                         } else {
1742                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1743                                                   0xFC, buf[2 * i]);
1744                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1745                                                   0xFC, buf[2 * i + 1]);
1746                         }
1747                 } else {
1748                         if (i == 0)
1749                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1750                                                   0xF3, buf[0] << 2);
1751                         else
1752                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1753                                                   0xF3, buf[2 * i + 1] << 2);
1754                 }
1755         }
1756 }
1757
1758 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1759 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1760                                 u8 nsamp)
1761 {
1762         int i;
1763         int out;
1764         u16 save_regs_phy[9];
1765         u16 s[2];
1766
1767         if (dev->phy.rev >= 3) {
1768                 save_regs_phy[0] = b43_phy_read(dev,
1769                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1770                 save_regs_phy[1] = b43_phy_read(dev,
1771                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1772                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1773                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1774                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1775                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1776                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1777                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1778         }
1779
1780         b43_nphy_rssi_select(dev, 5, type);
1781
1782         if (dev->phy.rev < 2) {
1783                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1784                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1785         }
1786
1787         for (i = 0; i < 4; i++)
1788                 buf[i] = 0;
1789
1790         for (i = 0; i < nsamp; i++) {
1791                 if (dev->phy.rev < 2) {
1792                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1793                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1794                 } else {
1795                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1796                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1797                 }
1798
1799                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1800                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1801                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1802                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1803         }
1804         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1805                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1806
1807         if (dev->phy.rev < 2)
1808                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1809
1810         if (dev->phy.rev >= 3) {
1811                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1812                                 save_regs_phy[0]);
1813                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1814                                 save_regs_phy[1]);
1815                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1816                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1817                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1818                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1819                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1820                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1821         }
1822
1823         return out;
1824 }
1825
1826 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1827 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1828 {
1829         int i, j;
1830         u8 state[4];
1831         u8 code, val;
1832         u16 class, override;
1833         u8 regs_save_radio[2];
1834         u16 regs_save_phy[2];
1835         s8 offset[4];
1836
1837         u16 clip_state[2];
1838         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1839         s32 results_min[4] = { };
1840         u8 vcm_final[4] = { };
1841         s32 results[4][4] = { };
1842         s32 miniq[4][2] = { };
1843
1844         if (type == 2) {
1845                 code = 0;
1846                 val = 6;
1847         } else if (type < 2) {
1848                 code = 25;
1849                 val = 4;
1850         } else {
1851                 B43_WARN_ON(1);
1852                 return;
1853         }
1854
1855         class = b43_nphy_classifier(dev, 0, 0);
1856         b43_nphy_classifier(dev, 7, 4);
1857         b43_nphy_read_clip_detection(dev, clip_state);
1858         b43_nphy_write_clip_detection(dev, clip_off);
1859
1860         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1861                 override = 0x140;
1862         else
1863                 override = 0x110;
1864
1865         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1866         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1867         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1868         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1869
1870         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1871         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1872         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1873         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1874
1875         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1876         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1877         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1878         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1879         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1880         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1881
1882         b43_nphy_rssi_select(dev, 5, type);
1883         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1884         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1885
1886         for (i = 0; i < 4; i++) {
1887                 u8 tmp[4];
1888                 for (j = 0; j < 4; j++)
1889                         tmp[j] = i;
1890                 if (type != 1)
1891                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1892                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1893                 if (type < 2)
1894                         for (j = 0; j < 2; j++)
1895                                 miniq[i][j] = min(results[i][2 * j],
1896                                                 results[i][2 * j + 1]);
1897         }
1898
1899         for (i = 0; i < 4; i++) {
1900                 s32 mind = 40;
1901                 u8 minvcm = 0;
1902                 s32 minpoll = 249;
1903                 s32 curr;
1904                 for (j = 0; j < 4; j++) {
1905                         if (type == 2)
1906                                 curr = abs(results[j][i]);
1907                         else
1908                                 curr = abs(miniq[j][i / 2] - code * 8);
1909
1910                         if (curr < mind) {
1911                                 mind = curr;
1912                                 minvcm = j;
1913                         }
1914
1915                         if (results[j][i] < minpoll)
1916                                 minpoll = results[j][i];
1917                 }
1918                 results_min[i] = minpoll;
1919                 vcm_final[i] = minvcm;
1920         }
1921
1922         if (type != 1)
1923                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1924
1925         for (i = 0; i < 4; i++) {
1926                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1927
1928                 if (offset[i] < 0)
1929                         offset[i] = -((abs(offset[i]) + 4) / 8);
1930                 else
1931                         offset[i] = (offset[i] + 4) / 8;
1932
1933                 if (results_min[i] == 248)
1934                         offset[i] = code - 32;
1935
1936                 if (i % 2 == 0)
1937                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1938                                                         type);
1939                 else
1940                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1941                                                         type);
1942         }
1943
1944         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1945         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1946
1947         switch (state[2]) {
1948         case 1:
1949                 b43_nphy_rssi_select(dev, 1, 2);
1950                 break;
1951         case 4:
1952                 b43_nphy_rssi_select(dev, 1, 0);
1953                 break;
1954         case 2:
1955                 b43_nphy_rssi_select(dev, 1, 1);
1956                 break;
1957         default:
1958                 b43_nphy_rssi_select(dev, 1, 1);
1959                 break;
1960         }
1961
1962         switch (state[3]) {
1963         case 1:
1964                 b43_nphy_rssi_select(dev, 2, 2);
1965                 break;
1966         case 4:
1967                 b43_nphy_rssi_select(dev, 2, 0);
1968                 break;
1969         default:
1970                 b43_nphy_rssi_select(dev, 2, 1);
1971                 break;
1972         }
1973
1974         b43_nphy_rssi_select(dev, 0, type);
1975
1976         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1977         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1978         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1979         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1980
1981         b43_nphy_classifier(dev, 7, class);
1982         b43_nphy_write_clip_detection(dev, clip_state);
1983 }
1984
1985 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1986 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1987 {
1988         /* TODO */
1989 }
1990
1991 /*
1992  * RSSI Calibration
1993  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1994  */
1995 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1996 {
1997         if (dev->phy.rev >= 3) {
1998                 b43_nphy_rev3_rssi_cal(dev);
1999         } else {
2000                 b43_nphy_rev2_rssi_cal(dev, 2);
2001                 b43_nphy_rev2_rssi_cal(dev, 0);
2002                 b43_nphy_rev2_rssi_cal(dev, 1);
2003         }
2004 }
2005
2006 /*
2007  * Restore RSSI Calibration
2008  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2009  */
2010 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2011 {
2012         struct b43_phy_n *nphy = dev->phy.n;
2013
2014         u16 *rssical_radio_regs = NULL;
2015         u16 *rssical_phy_regs = NULL;
2016
2017         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2018                 if (!nphy->rssical_chanspec_2G)
2019                         return;
2020                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2021                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2022         } else {
2023                 if (!nphy->rssical_chanspec_5G)
2024                         return;
2025                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2026                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2027         }
2028
2029         /* TODO use some definitions */
2030         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2031         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2032
2033         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2034         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2035         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2036         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2037
2038         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2039         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2040         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2041         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2042
2043         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2044         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2045         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2046         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2047 }
2048
2049 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2050 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2051 {
2052         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2053                 if (dev->phy.rev >= 6) {
2054                         /* TODO If the chip is 47162
2055                                 return txpwrctrl_tx_gain_ipa_rev5 */
2056                         return txpwrctrl_tx_gain_ipa_rev6;
2057                 } else if (dev->phy.rev >= 5) {
2058                         return txpwrctrl_tx_gain_ipa_rev5;
2059                 } else {
2060                         return txpwrctrl_tx_gain_ipa;
2061                 }
2062         } else {
2063                 return txpwrctrl_tx_gain_ipa_5g;
2064         }
2065 }
2066
2067 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2068 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2069 {
2070         struct b43_phy_n *nphy = dev->phy.n;
2071         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2072         u16 tmp;
2073         u8 offset, i;
2074
2075         if (dev->phy.rev >= 3) {
2076             for (i = 0; i < 2; i++) {
2077                 tmp = (i == 0) ? 0x2000 : 0x3000;
2078                 offset = i * 11;
2079
2080                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2081                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2082                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2083                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2084                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2085                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2086                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2087                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2088                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2089                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2090                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2091
2092                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2093                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2094                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2095                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2096                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2097                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2098                         if (nphy->ipa5g_on) {
2099                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2100                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2101                         } else {
2102                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2103                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2104                         }
2105                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2106                 } else {
2107                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2108                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2109                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2110                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2111                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2112                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2113                         if (nphy->ipa2g_on) {
2114                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2115                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2116                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2117                         } else {
2118                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2119                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2120                         }
2121                 }
2122                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2123                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2124                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2125             }
2126         } else {
2127                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2128                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2129
2130                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2131                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2132
2133                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2134                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2135
2136                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2137                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2138
2139                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2140                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2141
2142                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2143                     B43_NPHY_BANDCTL_5GHZ)) {
2144                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2145                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2146                 } else {
2147                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2148                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2149                 }
2150
2151                 if (dev->phy.rev < 2) {
2152                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2153                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2154                 } else {
2155                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2156                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2157                 }
2158         }
2159 }
2160
2161 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2162 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2163                                         struct nphy_txgains target,
2164                                         struct nphy_iqcal_params *params)
2165 {
2166         int i, j, indx;
2167         u16 gain;
2168
2169         if (dev->phy.rev >= 3) {
2170                 params->txgm = target.txgm[core];
2171                 params->pga = target.pga[core];
2172                 params->pad = target.pad[core];
2173                 params->ipa = target.ipa[core];
2174                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2175                                         (params->pad << 4) | (params->ipa);
2176                 for (j = 0; j < 5; j++)
2177                         params->ncorr[j] = 0x79;
2178         } else {
2179                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2180                         (target.txgm[core] << 8);
2181
2182                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2183                         1 : 0;
2184                 for (i = 0; i < 9; i++)
2185                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2186                                 break;
2187                 i = min(i, 8);
2188
2189                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2190                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2191                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2192                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2193                                         (params->pad << 2);
2194                 for (j = 0; j < 4; j++)
2195                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2196         }
2197 }
2198
2199 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2200 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2201 {
2202         struct b43_phy_n *nphy = dev->phy.n;
2203         int i;
2204         u16 scale, entry;
2205
2206         u16 tmp = nphy->txcal_bbmult;
2207         if (core == 0)
2208                 tmp >>= 8;
2209         tmp &= 0xff;
2210
2211         for (i = 0; i < 18; i++) {
2212                 scale = (ladder_lo[i].percent * tmp) / 100;
2213                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2214                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2215
2216                 scale = (ladder_iq[i].percent * tmp) / 100;
2217                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2218                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2219         }
2220 }
2221
2222 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2223 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2224 {
2225         int i;
2226         for (i = 0; i < 15; i++)
2227                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2228                                 tbl_tx_filter_coef_rev4[2][i]);
2229 }
2230
2231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2232 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2233 {
2234         int i, j;
2235         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2236         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2237
2238         for (i = 0; i < 3; i++)
2239                 for (j = 0; j < 15; j++)
2240                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2241                                         tbl_tx_filter_coef_rev4[i][j]);
2242
2243         if (dev->phy.is_40mhz) {
2244                 for (j = 0; j < 15; j++)
2245                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2246                                         tbl_tx_filter_coef_rev4[3][j]);
2247         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2248                 for (j = 0; j < 15; j++)
2249                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2250                                         tbl_tx_filter_coef_rev4[5][j]);
2251         }
2252
2253         if (dev->phy.channel == 14)
2254                 for (j = 0; j < 15; j++)
2255                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2256                                         tbl_tx_filter_coef_rev4[6][j]);
2257 }
2258
2259 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2260 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2261 {
2262         struct b43_phy_n *nphy = dev->phy.n;
2263
2264         u16 curr_gain[2];
2265         struct nphy_txgains target;
2266         const u32 *table = NULL;
2267
2268         if (nphy->txpwrctrl == 0) {
2269                 int i;
2270
2271                 if (nphy->hang_avoid)
2272                         b43_nphy_stay_in_carrier_search(dev, true);
2273                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2274                 if (nphy->hang_avoid)
2275                         b43_nphy_stay_in_carrier_search(dev, false);
2276
2277                 for (i = 0; i < 2; ++i) {
2278                         if (dev->phy.rev >= 3) {
2279                                 target.ipa[i] = curr_gain[i] & 0x000F;
2280                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2281                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2282                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2283                         } else {
2284                                 target.ipa[i] = curr_gain[i] & 0x0003;
2285                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2286                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2287                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2288                         }
2289                 }
2290         } else {
2291                 int i;
2292                 u16 index[2];
2293                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2294                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2295                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2296                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2297                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2298                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2299
2300                 for (i = 0; i < 2; ++i) {
2301                         if (dev->phy.rev >= 3) {
2302                                 enum ieee80211_band band =
2303                                         b43_current_band(dev->wl);
2304
2305                                 if ((nphy->ipa2g_on &&
2306                                      band == IEEE80211_BAND_2GHZ) ||
2307                                     (nphy->ipa5g_on &&
2308                                      band == IEEE80211_BAND_5GHZ)) {
2309                                         table = b43_nphy_get_ipa_gain_table(dev);
2310                                 } else {
2311                                         if (band == IEEE80211_BAND_5GHZ) {
2312                                                 if (dev->phy.rev == 3)
2313                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2314                                                 else if (dev->phy.rev == 4)
2315                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2316                                                 else
2317                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2318                                         } else {
2319                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2320                                         }
2321                                 }
2322
2323                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2324                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2325                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2326                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2327                         } else {
2328                                 table = b43_ntab_tx_gain_rev0_1_2;
2329
2330                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2331                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2332                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2333                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2334                         }
2335                 }
2336         }
2337
2338         return target;
2339 }
2340
2341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2342 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2343 {
2344         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2345
2346         if (dev->phy.rev >= 3) {
2347                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2348                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2349                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2350                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2351                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2352                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2353                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2354                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2355                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2356                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2357                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2358                 b43_nphy_reset_cca(dev);
2359         } else {
2360                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2361                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2362                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2363                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2364                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2365                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2366                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2367         }
2368 }
2369
2370 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2371 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2372 {
2373         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2374         u16 tmp;
2375
2376         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2377         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2378         if (dev->phy.rev >= 3) {
2379                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2380                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2381
2382                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2383                 regs[2] = tmp;
2384                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2385
2386                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2387                 regs[3] = tmp;
2388                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2389
2390                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2391                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2392
2393                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2394                 regs[5] = tmp;
2395                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2396
2397                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2398                 regs[6] = tmp;
2399                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2400                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2401                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2402
2403                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2404                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2405                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2406
2407                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2408                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2409                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2410                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2411         } else {
2412                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2413                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2414                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2415                 regs[2] = tmp;
2416                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2417                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2418                 regs[3] = tmp;
2419                 tmp |= 0x2000;
2420                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2421                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2422                 regs[4] = tmp;
2423                 tmp |= 0x2000;
2424                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2425                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2426                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2427                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2428                         tmp = 0x0180;
2429                 else
2430                         tmp = 0x0120;
2431                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2432                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2433         }
2434 }
2435
2436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2437 static void b43_nphy_save_cal(struct b43_wldev *dev)
2438 {
2439         struct b43_phy_n *nphy = dev->phy.n;
2440
2441         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2442         u16 *txcal_radio_regs = NULL;
2443         u8 *iqcal_chanspec;
2444         u16 *table = NULL;
2445
2446         if (nphy->hang_avoid)
2447                 b43_nphy_stay_in_carrier_search(dev, 1);
2448
2449         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2450                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2451                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2452                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2453                 table = nphy->cal_cache.txcal_coeffs_2G;
2454         } else {
2455                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2456                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2457                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2458                 table = nphy->cal_cache.txcal_coeffs_5G;
2459         }
2460
2461         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2462         /* TODO use some definitions */
2463         if (dev->phy.rev >= 3) {
2464                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2465                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2466                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2467                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2468                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2469                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2470                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2471                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2472         } else {
2473                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2474                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2475                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2476                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2477         }
2478         *iqcal_chanspec = nphy->radio_chanspec;
2479         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2480
2481         if (nphy->hang_avoid)
2482                 b43_nphy_stay_in_carrier_search(dev, 0);
2483 }
2484
2485 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2486 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2487 {
2488         struct b43_phy_n *nphy = dev->phy.n;
2489
2490         u16 coef[4];
2491         u16 *loft = NULL;
2492         u16 *table = NULL;
2493
2494         int i;
2495         u16 *txcal_radio_regs = NULL;
2496         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2497
2498         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2499                 if (nphy->iqcal_chanspec_2G == 0)
2500                         return;
2501                 table = nphy->cal_cache.txcal_coeffs_2G;
2502                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2503         } else {
2504                 if (nphy->iqcal_chanspec_5G == 0)
2505                         return;
2506                 table = nphy->cal_cache.txcal_coeffs_5G;
2507                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2508         }
2509
2510         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2511
2512         for (i = 0; i < 4; i++) {
2513                 if (dev->phy.rev >= 3)
2514                         table[i] = coef[i];
2515                 else
2516                         coef[i] = 0;
2517         }
2518
2519         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2520         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2521         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2522
2523         if (dev->phy.rev < 2)
2524                 b43_nphy_tx_iq_workaround(dev);
2525
2526         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2527                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2528                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2529         } else {
2530                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2531                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2532         }
2533
2534         /* TODO use some definitions */
2535         if (dev->phy.rev >= 3) {
2536                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2537                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2538                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2539                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2540                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2541                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2542                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2543                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2544         } else {
2545                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2546                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2547                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2548                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2549         }
2550         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2551 }
2552
2553 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2554 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2555                                 struct nphy_txgains target,
2556                                 bool full, bool mphase)
2557 {
2558         struct b43_phy_n *nphy = dev->phy.n;
2559         int i;
2560         int error = 0;
2561         int freq;
2562         bool avoid = false;
2563         u8 length;
2564         u16 tmp, core, type, count, max, numb, last, cmd;
2565         const u16 *table;
2566         bool phy6or5x;
2567
2568         u16 buffer[11];
2569         u16 diq_start = 0;
2570         u16 save[2];
2571         u16 gain[2];
2572         struct nphy_iqcal_params params[2];
2573         bool updated[2] = { };
2574
2575         b43_nphy_stay_in_carrier_search(dev, true);
2576
2577         if (dev->phy.rev >= 4) {
2578                 avoid = nphy->hang_avoid;
2579                 nphy->hang_avoid = 0;
2580         }
2581
2582         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2583
2584         for (i = 0; i < 2; i++) {
2585                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2586                 gain[i] = params[i].cal_gain;
2587         }
2588
2589         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2590
2591         b43_nphy_tx_cal_radio_setup(dev);
2592         b43_nphy_tx_cal_phy_setup(dev);
2593
2594         phy6or5x = dev->phy.rev >= 6 ||
2595                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2596                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2597         if (phy6or5x) {
2598                 if (dev->phy.is_40mhz) {
2599                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2600                                         tbl_tx_iqlo_cal_loft_ladder_40);
2601                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2602                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2603                 } else {
2604                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2605                                         tbl_tx_iqlo_cal_loft_ladder_20);
2606                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2607                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2608                 }
2609         }
2610
2611         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2612
2613         if (!dev->phy.is_40mhz)
2614                 freq = 2500;
2615         else
2616                 freq = 5000;
2617
2618         if (nphy->mphase_cal_phase_id > 2)
2619                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2620                                         0xFFFF, 0, true, false);
2621         else
2622                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2623
2624         if (error == 0) {
2625                 if (nphy->mphase_cal_phase_id > 2) {
2626                         table = nphy->mphase_txcal_bestcoeffs;
2627                         length = 11;
2628                         if (dev->phy.rev < 3)
2629                                 length -= 2;
2630                 } else {
2631                         if (!full && nphy->txiqlocal_coeffsvalid) {
2632                                 table = nphy->txiqlocal_bestc;
2633                                 length = 11;
2634                                 if (dev->phy.rev < 3)
2635                                         length -= 2;
2636                         } else {
2637                                 full = true;
2638                                 if (dev->phy.rev >= 3) {
2639                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2640                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2641                                 } else {
2642                                         table = tbl_tx_iqlo_cal_startcoefs;
2643                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2644                                 }
2645                         }
2646                 }
2647
2648                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2649
2650                 if (full) {
2651                         if (dev->phy.rev >= 3)
2652                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2653                         else
2654                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2655                 } else {
2656                         if (dev->phy.rev >= 3)
2657                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2658                         else
2659                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2660                 }
2661
2662                 if (mphase) {
2663                         count = nphy->mphase_txcal_cmdidx;
2664                         numb = min(max,
2665                                 (u16)(count + nphy->mphase_txcal_numcmds));
2666                 } else {
2667                         count = 0;
2668                         numb = max;
2669                 }
2670
2671                 for (; count < numb; count++) {
2672                         if (full) {
2673                                 if (dev->phy.rev >= 3)
2674                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2675                                 else
2676                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2677                         } else {
2678                                 if (dev->phy.rev >= 3)
2679                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2680                                 else
2681                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2682                         }
2683
2684                         core = (cmd & 0x3000) >> 12;
2685                         type = (cmd & 0x0F00) >> 8;
2686
2687                         if (phy6or5x && updated[core] == 0) {
2688                                 b43_nphy_update_tx_cal_ladder(dev, core);
2689                                 updated[core] = 1;
2690                         }
2691
2692                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2693                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2694
2695                         if (type == 1 || type == 3 || type == 4) {
2696                                 buffer[0] = b43_ntab_read(dev,
2697                                                 B43_NTAB16(15, 69 + core));
2698                                 diq_start = buffer[0];
2699                                 buffer[0] = 0;
2700                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2701                                                 0);
2702                         }
2703
2704                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2705                         for (i = 0; i < 2000; i++) {
2706                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2707                                 if (tmp & 0xC000)
2708                                         break;
2709                                 udelay(10);
2710                         }
2711
2712                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2713                                                 buffer);
2714                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2715                                                 buffer);
2716
2717                         if (type == 1 || type == 3 || type == 4)
2718                                 buffer[0] = diq_start;
2719                 }
2720
2721                 if (mphase)
2722                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2723
2724                 last = (dev->phy.rev < 3) ? 6 : 7;
2725
2726                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2727                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2728                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2729                         if (dev->phy.rev < 3) {
2730                                 buffer[0] = 0;
2731                                 buffer[1] = 0;
2732                                 buffer[2] = 0;
2733                                 buffer[3] = 0;
2734                         }
2735                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2736                                                 buffer);
2737                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2738                                                 buffer);
2739                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2740                                                 buffer);
2741                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2742                                                 buffer);
2743                         length = 11;
2744                         if (dev->phy.rev < 3)
2745                                 length -= 2;
2746                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2747                                                 nphy->txiqlocal_bestc);
2748                         nphy->txiqlocal_coeffsvalid = true;
2749                         /* TODO: Set nphy->txiqlocal_chanspec to
2750                                 the current channel */
2751                 } else {
2752                         length = 11;
2753                         if (dev->phy.rev < 3)
2754                                 length -= 2;
2755                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2756                                                 nphy->mphase_txcal_bestcoeffs);
2757                 }
2758
2759                 b43_nphy_stop_playback(dev);
2760                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2761         }
2762
2763         b43_nphy_tx_cal_phy_cleanup(dev);
2764         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2765
2766         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2767                 b43_nphy_tx_iq_workaround(dev);
2768
2769         if (dev->phy.rev >= 4)
2770                 nphy->hang_avoid = avoid;
2771
2772         b43_nphy_stay_in_carrier_search(dev, false);
2773
2774         return error;
2775 }
2776
2777 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2778 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2779 {
2780         struct b43_phy_n *nphy = dev->phy.n;
2781         u8 i;
2782         u16 buffer[7];
2783         bool equal = true;
2784
2785         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2786                 return;
2787
2788         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2789         for (i = 0; i < 4; i++) {
2790                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2791                         equal = false;
2792                         break;
2793                 }
2794         }
2795
2796         if (!equal) {
2797                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2798                                         nphy->txiqlocal_bestc);
2799                 for (i = 0; i < 4; i++)
2800                         buffer[i] = 0;
2801                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2802                                         buffer);
2803                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2804                                         &nphy->txiqlocal_bestc[5]);
2805                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2806                                         &nphy->txiqlocal_bestc[5]);
2807         }
2808 }
2809
2810 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2811 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2812                         struct nphy_txgains target, u8 type, bool debug)
2813 {
2814         struct b43_phy_n *nphy = dev->phy.n;
2815         int i, j, index;
2816         u8 rfctl[2];
2817         u8 afectl_core;
2818         u16 tmp[6];
2819         u16 cur_hpf1, cur_hpf2, cur_lna;
2820         u32 real, imag;
2821         enum ieee80211_band band;
2822
2823         u8 use;
2824         u16 cur_hpf;
2825         u16 lna[3] = { 3, 3, 1 };
2826         u16 hpf1[3] = { 7, 2, 0 };
2827         u16 hpf2[3] = { 2, 0, 0 };
2828         u32 power[3] = { };
2829         u16 gain_save[2];
2830         u16 cal_gain[2];
2831         struct nphy_iqcal_params cal_params[2];
2832         struct nphy_iq_est est;
2833         int ret = 0;
2834         bool playtone = true;
2835         int desired = 13;
2836
2837         b43_nphy_stay_in_carrier_search(dev, 1);
2838
2839         if (dev->phy.rev < 2)
2840                 b43_nphy_reapply_tx_cal_coeffs(dev);
2841         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2842         for (i = 0; i < 2; i++) {
2843                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2844                 cal_gain[i] = cal_params[i].cal_gain;
2845         }
2846         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2847
2848         for (i = 0; i < 2; i++) {
2849                 if (i == 0) {
2850                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2851                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2852                         afectl_core = B43_NPHY_AFECTL_C1;
2853                 } else {
2854                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2855                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2856                         afectl_core = B43_NPHY_AFECTL_C2;
2857                 }
2858
2859                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2860                 tmp[2] = b43_phy_read(dev, afectl_core);
2861                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2862                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2863                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2864
2865                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2866                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2867                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2868                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2869                                 (1 - i));
2870                 b43_phy_set(dev, afectl_core, 0x0006);
2871                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2872
2873                 band = b43_current_band(dev->wl);
2874
2875                 if (nphy->rxcalparams & 0xFF000000) {
2876                         if (band == IEEE80211_BAND_5GHZ)
2877                                 b43_phy_write(dev, rfctl[0], 0x140);
2878                         else
2879                                 b43_phy_write(dev, rfctl[0], 0x110);
2880                 } else {
2881                         if (band == IEEE80211_BAND_5GHZ)
2882                                 b43_phy_write(dev, rfctl[0], 0x180);
2883                         else
2884                                 b43_phy_write(dev, rfctl[0], 0x120);
2885                 }
2886
2887                 if (band == IEEE80211_BAND_5GHZ)
2888                         b43_phy_write(dev, rfctl[1], 0x148);
2889                 else
2890                         b43_phy_write(dev, rfctl[1], 0x114);
2891
2892                 if (nphy->rxcalparams & 0x10000) {
2893                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2894                                         (i + 1));
2895                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2896                                         (2 - i));
2897                 }
2898
2899                 for (j = 0; i < 4; j++) {
2900                         if (j < 3) {
2901                                 cur_lna = lna[j];
2902                                 cur_hpf1 = hpf1[j];
2903                                 cur_hpf2 = hpf2[j];
2904                         } else {
2905                                 if (power[1] > 10000) {
2906                                         use = 1;
2907                                         cur_hpf = cur_hpf1;
2908                                         index = 2;
2909                                 } else {
2910                                         if (power[0] > 10000) {
2911                                                 use = 1;
2912                                                 cur_hpf = cur_hpf1;
2913                                                 index = 1;
2914                                         } else {
2915                                                 index = 0;
2916                                                 use = 2;
2917                                                 cur_hpf = cur_hpf2;
2918                                         }
2919                                 }
2920                                 cur_lna = lna[index];
2921                                 cur_hpf1 = hpf1[index];
2922                                 cur_hpf2 = hpf2[index];
2923                                 cur_hpf += desired - hweight32(power[index]);
2924                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2925                                 if (use == 1)
2926                                         cur_hpf1 = cur_hpf;
2927                                 else
2928                                         cur_hpf2 = cur_hpf;
2929                         }
2930
2931                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2932                                         (cur_lna << 2));
2933                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2934                                                                         false);
2935                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2936                         b43_nphy_stop_playback(dev);
2937
2938                         if (playtone) {
2939                                 ret = b43_nphy_tx_tone(dev, 4000,
2940                                                 (nphy->rxcalparams & 0xFFFF),
2941                                                 false, false);
2942                                 playtone = false;
2943                         } else {
2944                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2945                                                         false, false);
2946                         }
2947
2948                         if (ret == 0) {
2949                                 if (j < 3) {
2950                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2951                                                                         false);
2952                                         if (i == 0) {
2953                                                 real = est.i0_pwr;
2954                                                 imag = est.q0_pwr;
2955                                         } else {
2956                                                 real = est.i1_pwr;
2957                                                 imag = est.q1_pwr;
2958                                         }
2959                                         power[i] = ((real + imag) / 1024) + 1;
2960                                 } else {
2961                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2962                                 }
2963                                 b43_nphy_stop_playback(dev);
2964                         }
2965
2966                         if (ret != 0)
2967                                 break;
2968                 }
2969
2970                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2971                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2972                 b43_phy_write(dev, rfctl[1], tmp[5]);
2973                 b43_phy_write(dev, rfctl[0], tmp[4]);
2974                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2975                 b43_phy_write(dev, afectl_core, tmp[2]);
2976                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2977
2978                 if (ret != 0)
2979                         break;
2980         }
2981
2982         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2983         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2984         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2985
2986         b43_nphy_stay_in_carrier_search(dev, 0);
2987
2988         return ret;
2989 }
2990
2991 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2992                         struct nphy_txgains target, u8 type, bool debug)
2993 {
2994         return -1;
2995 }
2996
2997 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2998 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2999                         struct nphy_txgains target, u8 type, bool debug)
3000 {
3001         if (dev->phy.rev >= 3)
3002                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3003         else
3004                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3005 }
3006
3007 /*
3008  * Init N-PHY
3009  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3010  */
3011 int b43_phy_initn(struct b43_wldev *dev)
3012 {
3013         struct ssb_bus *bus = dev->dev->bus;
3014         struct b43_phy *phy = &dev->phy;
3015         struct b43_phy_n *nphy = phy->n;
3016         u8 tx_pwr_state;
3017         struct nphy_txgains target;
3018         u16 tmp;
3019         enum ieee80211_band tmp2;
3020         bool do_rssi_cal;
3021
3022         u16 clip[2];
3023         bool do_cal = false;
3024
3025         if ((dev->phy.rev >= 3) &&
3026            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3027            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3028                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3029         }
3030         nphy->deaf_count = 0;
3031         b43_nphy_tables_init(dev);
3032         nphy->crsminpwr_adjusted = false;
3033         nphy->noisevars_adjusted = false;
3034
3035         /* Clear all overrides */
3036         if (dev->phy.rev >= 3) {
3037                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3038                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3039                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3040                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3041         } else {
3042                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3043         }
3044         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3045         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3046         if (dev->phy.rev < 6) {
3047                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3048                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3049         }
3050         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3051                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3052                        B43_NPHY_RFSEQMODE_TROVER));
3053         if (dev->phy.rev >= 3)
3054                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3055         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3056
3057         if (dev->phy.rev <= 2) {
3058                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3059                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3060                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3061                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3062         }
3063         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3064         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3065
3066         if (bus->sprom.boardflags2_lo & 0x100 ||
3067             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3068              bus->boardinfo.type == 0x8B))
3069                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3070         else
3071                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3072         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3073         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3074         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3075
3076         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3077         b43_nphy_update_txrx_chain(dev);
3078
3079         if (phy->rev < 2) {
3080                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3081                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3082         }
3083
3084         tmp2 = b43_current_band(dev->wl);
3085         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3086             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3087                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3088                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3089                                 nphy->papd_epsilon_offset[0] << 7);
3090                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3091                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3092                                 nphy->papd_epsilon_offset[1] << 7);
3093                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3094         } else if (phy->rev >= 5) {
3095                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3096         }
3097
3098         b43_nphy_workarounds(dev);
3099
3100         /* Reset CCA, in init code it differs a little from standard way */
3101         b43_nphy_bmac_clock_fgc(dev, 1);
3102         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3103         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3104         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3105         b43_nphy_bmac_clock_fgc(dev, 0);
3106
3107         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3108
3109         b43_nphy_pa_override(dev, false);
3110         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3111         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3112         b43_nphy_pa_override(dev, true);
3113
3114         b43_nphy_classifier(dev, 0, 0);
3115         b43_nphy_read_clip_detection(dev, clip);
3116         tx_pwr_state = nphy->txpwrctrl;
3117         /* TODO N PHY TX power control with argument 0
3118                 (turning off power control) */
3119         /* TODO Fix the TX Power Settings */
3120         /* TODO N PHY TX Power Control Idle TSSI */
3121         /* TODO N PHY TX Power Control Setup */
3122
3123         if (phy->rev >= 3) {
3124                 /* TODO */
3125         } else {
3126                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3127                                         b43_ntab_tx_gain_rev0_1_2);
3128                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3129                                         b43_ntab_tx_gain_rev0_1_2);
3130         }
3131
3132         if (nphy->phyrxchain != 3)
3133                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3134         if (nphy->mphase_cal_phase_id > 0)
3135                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3136
3137         do_rssi_cal = false;
3138         if (phy->rev >= 3) {
3139                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3140                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3141                 else
3142                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3143
3144                 if (do_rssi_cal)
3145                         b43_nphy_rssi_cal(dev);
3146                 else
3147                         b43_nphy_restore_rssi_cal(dev);
3148         } else {
3149                 b43_nphy_rssi_cal(dev);
3150         }
3151
3152         if (!((nphy->measure_hold & 0x6) != 0)) {
3153                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3154                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3155                 else
3156                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3157
3158                 if (nphy->mute)
3159                         do_cal = false;
3160
3161                 if (do_cal) {
3162                         target = b43_nphy_get_tx_gains(dev);
3163
3164                         if (nphy->antsel_type == 2)
3165                                 b43_nphy_superswitch_init(dev, true);
3166                         if (nphy->perical != 2) {
3167                                 b43_nphy_rssi_cal(dev);
3168                                 if (phy->rev >= 3) {
3169                                         nphy->cal_orig_pwr_idx[0] =
3170                                             nphy->txpwrindex[0].index_internal;
3171                                         nphy->cal_orig_pwr_idx[1] =
3172                                             nphy->txpwrindex[1].index_internal;
3173                                         /* TODO N PHY Pre Calibrate TX Gain */
3174                                         target = b43_nphy_get_tx_gains(dev);
3175                                 }
3176                         }
3177                 }
3178         }
3179
3180         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3181                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3182                         b43_nphy_save_cal(dev);
3183                 else if (nphy->mphase_cal_phase_id == 0)
3184                         ;/* N PHY Periodic Calibration with argument 3 */
3185         } else {
3186                 b43_nphy_restore_cal(dev);
3187         }
3188
3189         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3190         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3191         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3192         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3193         if (phy->rev >= 3 && phy->rev <= 6)
3194                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3195         b43_nphy_tx_lp_fbw(dev);
3196         if (phy->rev >= 3)
3197                 b43_nphy_spur_workaround(dev);
3198
3199         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3200         return 0;
3201 }
3202
3203 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3204 {
3205         struct b43_phy_n *nphy;
3206
3207         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3208         if (!nphy)
3209                 return -ENOMEM;
3210         dev->phy.n = nphy;
3211
3212         return 0;
3213 }
3214
3215 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3216 {
3217         struct b43_phy *phy = &dev->phy;
3218         struct b43_phy_n *nphy = phy->n;
3219
3220         memset(nphy, 0, sizeof(*nphy));
3221
3222         //TODO init struct b43_phy_n
3223 }
3224
3225 static void b43_nphy_op_free(struct b43_wldev *dev)
3226 {
3227         struct b43_phy *phy = &dev->phy;
3228         struct b43_phy_n *nphy = phy->n;
3229
3230         kfree(nphy);
3231         phy->n = NULL;
3232 }
3233
3234 static int b43_nphy_op_init(struct b43_wldev *dev)
3235 {
3236         return b43_phy_initn(dev);
3237 }
3238
3239 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3240 {
3241 #if B43_DEBUG
3242         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3243                 /* OFDM registers are onnly available on A/G-PHYs */
3244                 b43err(dev->wl, "Invalid OFDM PHY access at "
3245                        "0x%04X on N-PHY\n", offset);
3246                 dump_stack();
3247         }
3248         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3249                 /* Ext-G registers are only available on G-PHYs */
3250                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3251                        "0x%04X on N-PHY\n", offset);
3252                 dump_stack();
3253         }
3254 #endif /* B43_DEBUG */
3255 }
3256
3257 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3258 {
3259         check_phyreg(dev, reg);
3260         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3261         return b43_read16(dev, B43_MMIO_PHY_DATA);
3262 }
3263
3264 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3265 {
3266         check_phyreg(dev, reg);
3267         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3268         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3269 }
3270
3271 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3272 {
3273         /* Register 1 is a 32-bit register. */
3274         B43_WARN_ON(reg == 1);
3275         /* N-PHY needs 0x100 for read access */
3276         reg |= 0x100;
3277
3278         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3279         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3280 }
3281
3282 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3283 {
3284         /* Register 1 is a 32-bit register. */
3285         B43_WARN_ON(reg == 1);
3286
3287         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3288         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3289 }
3290
3291 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3292 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3293                                         bool blocked)
3294 {
3295         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3296                 b43err(dev->wl, "MAC not suspended\n");
3297
3298         if (blocked) {
3299                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3300                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3301                 if (dev->phy.rev >= 3) {
3302                         b43_radio_mask(dev, 0x09, ~0x2);
3303
3304                         b43_radio_write(dev, 0x204D, 0);
3305                         b43_radio_write(dev, 0x2053, 0);
3306                         b43_radio_write(dev, 0x2058, 0);
3307                         b43_radio_write(dev, 0x205E, 0);
3308                         b43_radio_mask(dev, 0x2062, ~0xF0);
3309                         b43_radio_write(dev, 0x2064, 0);
3310
3311                         b43_radio_write(dev, 0x304D, 0);
3312                         b43_radio_write(dev, 0x3053, 0);
3313                         b43_radio_write(dev, 0x3058, 0);
3314                         b43_radio_write(dev, 0x305E, 0);
3315                         b43_radio_mask(dev, 0x3062, ~0xF0);
3316                         b43_radio_write(dev, 0x3064, 0);
3317                 }
3318         } else {
3319                 if (dev->phy.rev >= 3) {
3320                         /* TODO: b43_radio_init2056(dev); */
3321                         /* TODO: PHY Set Channel Spec (dev, radio_chanspec) */
3322                 } else {
3323                         b43_radio_init2055(dev);
3324                 }
3325         }
3326 }
3327
3328 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3329 {
3330         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3331                       on ? 0 : 0x7FFF);
3332 }
3333
3334 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3335                                       unsigned int new_channel)
3336 {
3337         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3338                 if ((new_channel < 1) || (new_channel > 14))
3339                         return -EINVAL;
3340         } else {
3341                 if (new_channel > 200)
3342                         return -EINVAL;
3343         }
3344
3345         return nphy_channel_switch(dev, new_channel);
3346 }
3347
3348 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3349 {
3350         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3351                 return 1;
3352         return 36;
3353 }
3354
3355 const struct b43_phy_operations b43_phyops_n = {
3356         .allocate               = b43_nphy_op_allocate,
3357         .free                   = b43_nphy_op_free,
3358         .prepare_structs        = b43_nphy_op_prepare_structs,
3359         .init                   = b43_nphy_op_init,
3360         .phy_read               = b43_nphy_op_read,
3361         .phy_write              = b43_nphy_op_write,
3362         .radio_read             = b43_nphy_op_radio_read,
3363         .radio_write            = b43_nphy_op_radio_write,
3364         .software_rfkill        = b43_nphy_op_software_rfkill,
3365         .switch_analog          = b43_nphy_op_switch_analog,
3366         .switch_channel         = b43_nphy_op_switch_channel,
3367         .get_default_chan       = b43_nphy_op_get_default_chan,
3368         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3369         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3370 };