SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71
  72 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  73 {//TODO
  74 }
  75
  76 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  77 {//TODO
  78 }
  79
  80 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  81                                                         bool ignore_tssi)
  82 {//TODO
  83         return B43_TXPWR_RES_DONE;
  84 }
  85
  86 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  87                                      const struct b43_nphy_channeltab_entry *e)
  88 {
  89         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  90         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  91         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  92         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  93         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  94         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  95         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  96         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  97         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  98         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  99         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 100         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 101         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 102         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 103         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 104         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 105         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 106         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 107         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 108         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 109         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 110         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 111 }
 112
 113 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 114                                    const struct b43_nphy_channeltab_entry *e)
 115 {
 116         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 117         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 118         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 119         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 120         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 121         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 122 }
 123
 124 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 125 {
 126         //TODO
 127 }
 128
 129 /* Tune the hardware to a new channel. */
 130 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 131 {
 132         const struct b43_nphy_channeltab_entry *tabent;
 133
 134         tabent = b43_nphy_get_chantabent(dev, channel);
 135         if (!tabent)
 136                 return -ESRCH;
 137
 138         //FIXME enable/disable band select upper20 in RXCTL
 139         if (0 /*FIXME 5Ghz*/)
 140                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 141         else
 142                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 143         b43_chantab_radio_upload(dev, tabent);
 144         udelay(50);
 145         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 146         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 147         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 148         udelay(300);
 149         if (0 /*FIXME 5Ghz*/)
 150                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 151         else
 152                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 153         b43_chantab_phy_upload(dev, tabent);
 154         b43_nphy_tx_power_fix(dev);
 155
 156         return 0;
 157 }
 158
 159 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 160 {
 161         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 162                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 163         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 164                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 165                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 166         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 167                     B43_NPHY_RFCTL_CMD_PORFORCE);
 168 }
 169
 170 static void b43_radio_init2055_post(struct b43_wldev *dev)
 171 {
 172         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 173         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 174         int i;
 175         u16 val;
 176
 177         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 178         msleep(1);
 179         if ((sprom->revision != 4) ||
 180            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 181                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 182                     (binfo->type != 0x46D) ||
 183                     (binfo->rev < 0x41)) {
 184                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 185                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 186                         msleep(1);
 187                 }
 188         }
 189         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 190         msleep(1);
 191         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 192         msleep(1);
 193         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 194         msleep(1);
 195         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 196         msleep(1);
 197         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 198         msleep(1);
 199         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 200         msleep(1);
 201         for (i = 0; i < 100; i++) {
 202                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 203                 if (val & 0x80)
 204                         break;
 205                 udelay(10);
 206         }
 207         msleep(1);
 208         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 209         msleep(1);
 210         nphy_channel_switch(dev, dev->phy.channel);
 211         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 212         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 213         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 214         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 215 }
 216
 217 /* Initialize a Broadcom 2055 N-radio */
 218 static void b43_radio_init2055(struct b43_wldev *dev)
 219 {
 220         b43_radio_init2055_pre(dev);
 221         if (b43_status(dev) < B43_STAT_INITIALIZED)
 222                 b2055_upload_inittab(dev, 0, 1);
 223         else
 224                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 225         b43_radio_init2055_post(dev);
 226 }
 227
 228 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 229 {
 230         b43_radio_init2055(dev);
 231 }
 232
 233 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 234 {
 235         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 236                      ~B43_NPHY_RFCTL_CMD_EN);
 237 }
 238
 239 /*
 240  * Upload the N-PHY tables.
 241  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 242  */
 243 static void b43_nphy_tables_init(struct b43_wldev *dev)
 244 {
 245         if (dev->phy.rev < 3)
 246                 b43_nphy_rev0_1_2_tables_init(dev);
 247         else
 248                 b43_nphy_rev3plus_tables_init(dev);
 249 }
 250
 251 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 252 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 253 {
 254         struct b43_phy_n *nphy = dev->phy.n;
 255         enum ieee80211_band band;
 256         u16 tmp;
 257
 258         if (!enable) {
 259                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 260                                                        B43_NPHY_RFCTL_INTC1);
 261                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 262                                                        B43_NPHY_RFCTL_INTC2);
 263                 band = b43_current_band(dev->wl);
 264                 if (dev->phy.rev >= 3) {
 265                         if (band == IEEE80211_BAND_5GHZ)
 266                                 tmp = 0x600;
 267                         else
 268                                 tmp = 0x480;
 269                 } else {
 270                         if (band == IEEE80211_BAND_5GHZ)
 271                                 tmp = 0x180;
 272                         else
 273                                 tmp = 0x120;
 274                 }
 275                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 276                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 277         } else {
 278                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 279                                 nphy->rfctrl_intc1_save);
 280                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 281                                 nphy->rfctrl_intc2_save);
 282         }
 283 }
 284
 285 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 286 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 287 {
 288         struct b43_phy_n *nphy = dev->phy.n;
 289         u16 tmp;
 290         enum ieee80211_band band = b43_current_band(dev->wl);
 291         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 292                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 293
 294         if (dev->phy.rev >= 3) {
 295                 if (ipa) {
 296                         tmp = 4;
 297                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 298                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 299                 }
 300
 301                 tmp = 1;
 302                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 303                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 304         }
 305 }
 306
 307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 308 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 309 {
 310         u32 tmslow;
 311
 312         if (dev->phy.type != B43_PHYTYPE_N)
 313                 return;
 314
 315         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 316         if (force)
 317                 tmslow |= SSB_TMSLOW_FGC;
 318         else
 319                 tmslow &= ~SSB_TMSLOW_FGC;
 320         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 321 }
 322
 323 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 324 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 325 {
 326         u16 bbcfg;
 327
 328         b43_nphy_bmac_clock_fgc(dev, 1);
 329         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 330         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 331         udelay(1);
 332         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 333         b43_nphy_bmac_clock_fgc(dev, 0);
 334         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 335 }
 336
 337 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 338 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 339 {
 340         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 341
 342         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 343         if (preamble == 1)
 344                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 345         else
 346                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 347
 348         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 349 }
 350
 351 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 352 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 353 {
 354         struct b43_phy_n *nphy = dev->phy.n;
 355
 356         bool override = false;
 357         u16 chain = 0x33;
 358
 359         if (nphy->txrx_chain == 0) {
 360                 chain = 0x11;
 361                 override = true;
 362         } else if (nphy->txrx_chain == 1) {
 363                 chain = 0x22;
 364                 override = true;
 365         }
 366
 367         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 368                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 369                         chain);
 370
 371         if (override)
 372                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 373                                 B43_NPHY_RFSEQMODE_CAOVER);
 374         else
 375                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 376                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 377 }
 378
 379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 380 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 381                                 u16 samps, u8 time, bool wait)
 382 {
 383         int i;
 384         u16 tmp;
 385
 386         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 387         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 388         if (wait)
 389                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 390         else
 391                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 392
 393         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 394
 395         for (i = 1000; i; i--) {
 396                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 397                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 398                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 399                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 400                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 401                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 402                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 403                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 404
 405                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 406                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 407                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 408                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 409                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 410                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 411                         return;
 412                 }
 413                 udelay(10);
 414         }
 415         memset(est, 0, sizeof(*est));
 416 }
 417
 418 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 419 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 420                                         struct b43_phy_n_iq_comp *pcomp)
 421 {
 422         if (write) {
 423                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 424                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 425                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 426                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 427         } else {
 428                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 429                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 430                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 431                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 432         }
 433 }
 434
 435 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 436 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 437 {
 438         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 439
 440         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 441         if (core == 0) {
 442                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 443                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 444         } else {
 445                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 446                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 447         }
 448         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 449         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 450         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 451         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 452         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 453         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 454         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 455         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 456 }
 457
 458 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 459 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 460 {
 461         u8 rxval, txval;
 462         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 463
 464         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 465         if (core == 0) {
 466                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 467                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 468         } else {
 469                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 470                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 471         }
 472         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 473         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 474         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 475         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 476         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 477         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 478         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 479         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 480
 481         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 482         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 483
 484         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 485                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 486         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 487                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 488         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 489                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 490         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 491                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 492
 493         if (core == 0) {
 494                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 495                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 496         } else {
 497                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 498                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 499         }
 500
 501         /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
 502         /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
 503         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 504
 505         if (core == 0) {
 506                 rxval = 1;
 507                 txval = 8;
 508         } else {
 509                 rxval = 4;
 510                 txval = 2;
 511         }
 512
 513         /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
 514         /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
 515 }
 516
 517 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 518 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 519 {
 520         int i;
 521         s32 iq;
 522         u32 ii;
 523         u32 qq;
 524         int iq_nbits, qq_nbits;
 525         int arsh, brsh;
 526         u16 tmp, a, b;
 527
 528         struct nphy_iq_est est;
 529         struct b43_phy_n_iq_comp old;
 530         struct b43_phy_n_iq_comp new = { };
 531         bool error = false;
 532
 533         if (mask == 0)
 534                 return;
 535
 536         b43_nphy_rx_iq_coeffs(dev, false, &old);
 537         b43_nphy_rx_iq_coeffs(dev, true, &new);
 538         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 539         new = old;
 540
 541         for (i = 0; i < 2; i++) {
 542                 if (i == 0 && (mask & 1)) {
 543                         iq = est.iq0_prod;
 544                         ii = est.i0_pwr;
 545                         qq = est.q0_pwr;
 546                 } else if (i == 1 && (mask & 2)) {
 547                         iq = est.iq1_prod;
 548                         ii = est.i1_pwr;
 549                         qq = est.q1_pwr;
 550                 } else {
 551                         B43_WARN_ON(1);
 552                         continue;
 553                 }
 554
 555                 if (ii + qq < 2) {
 556                         error = true;
 557                         break;
 558                 }
 559
 560                 iq_nbits = fls(abs(iq));
 561                 qq_nbits = fls(qq);
 562
 563                 arsh = iq_nbits - 20;
 564                 if (arsh >= 0) {
 565                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 566                         tmp = ii >> arsh;
 567                 } else {
 568                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 569                         tmp = ii << -arsh;
 570                 }
 571                 if (tmp == 0) {
 572                         error = true;
 573                         break;
 574                 }
 575                 a /= tmp;
 576
 577                 brsh = qq_nbits - 11;
 578                 if (brsh >= 0) {
 579                         b = (qq << (31 - qq_nbits));
 580                         tmp = ii >> brsh;
 581                 } else {
 582                         b = (qq << (31 - qq_nbits));
 583                         tmp = ii << -brsh;
 584                 }
 585                 if (tmp == 0) {
 586                         error = true;
 587                         break;
 588                 }
 589                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 590
 591                 if (i == 0 && (mask & 0x1)) {
 592                         if (dev->phy.rev >= 3) {
 593                                 new.a0 = a & 0x3FF;
 594                                 new.b0 = b & 0x3FF;
 595                         } else {
 596                                 new.a0 = b & 0x3FF;
 597                                 new.b0 = a & 0x3FF;
 598                         }
 599                 } else if (i == 1 && (mask & 0x2)) {
 600                         if (dev->phy.rev >= 3) {
 601                                 new.a1 = a & 0x3FF;
 602                                 new.b1 = b & 0x3FF;
 603                         } else {
 604                                 new.a1 = b & 0x3FF;
 605                                 new.b1 = a & 0x3FF;
 606                         }
 607                 }
 608         }
 609
 610         if (error)
 611                 new = old;
 612
 613         b43_nphy_rx_iq_coeffs(dev, true, &new);
 614 }
 615
 616 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 617 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 618 {
 619         u16 array[4];
 620         int i;
 621
 622         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 623         for (i = 0; i < 4; i++)
 624                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 625
 626         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 627         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 628         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 629         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 630 }
 631
 632 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 633 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 634 {
 635         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 636         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 637 }
 638
 639 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 640 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 641 {
 642         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 643         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 644 }
 645
 646 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 647 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 648 {
 649         u16 tmp;
 650
 651         if (dev->dev->id.revision == 16)
 652                 b43_mac_suspend(dev);
 653
 654         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 655         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 656                 B43_NPHY_CLASSCTL_WAITEDEN);
 657         tmp &= ~mask;
 658         tmp |= (val & mask);
 659         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 660
 661         if (dev->dev->id.revision == 16)
 662                 b43_mac_enable(dev);
 663
 664         return tmp;
 665 }
 666
 667 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 668 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 669 {
 670         struct b43_phy *phy = &dev->phy;
 671         struct b43_phy_n *nphy = phy->n;
 672
 673         if (enable) {
 674                 u16 clip[] = { 0xFFFF, 0xFFFF };
 675                 if (nphy->deaf_count++ == 0) {
 676                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 677                         b43_nphy_classifier(dev, 0x7, 0);
 678                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 679                         b43_nphy_write_clip_detection(dev, clip);
 680                 }
 681                 b43_nphy_reset_cca(dev);
 682         } else {
 683                 if (--nphy->deaf_count == 0) {
 684                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 685                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 686                 }
 687         }
 688 }
 689
 690 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 691 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 692 {
 693         struct b43_phy_n *nphy = dev->phy.n;
 694         u16 tmp;
 695
 696         if (nphy->hang_avoid)
 697                 b43_nphy_stay_in_carrier_search(dev, 1);
 698
 699         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 700         if (tmp & 0x1)
 701                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 702         else if (tmp & 0x2)
 703                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 704
 705         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 706
 707         if (nphy->bb_mult_save & 0x80000000) {
 708                 tmp = nphy->bb_mult_save & 0xFFFF;
 709                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 710                 nphy->bb_mult_save = 0;
 711         }
 712
 713         if (nphy->hang_avoid)
 714                 b43_nphy_stay_in_carrier_search(dev, 0);
 715 }
 716
 717 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 718 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 719 {
 720         struct b43_phy_n *nphy = dev->phy.n;
 721         u8 i, j;
 722         u8 code;
 723
 724         /* TODO: for PHY >= 3
 725         s8 *lna1_gain, *lna2_gain;
 726         u8 *gain_db, *gain_bits;
 727         u16 *rfseq_init;
 728         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 729         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 730         */
 731
 732         u8 rfseq_events[3] = { 6, 8, 7 };
 733         u8 rfseq_delays[3] = { 10, 30, 1 };
 734
 735         if (dev->phy.rev >= 3) {
 736                 /* TODO */
 737         } else {
 738                 /* Set Clip 2 detect */
 739                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 740                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 741                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 742                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 743
 744                 /* Set narrowband clip threshold */
 745                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 746                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 747
 748                 if (!dev->phy.is_40mhz) {
 749                         /* Set dwell lengths */
 750                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 751                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 752                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 753                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 754                 }
 755
 756                 /* Set wideband clip 2 threshold */
 757                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 758                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 759                                 21);
 760                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 761                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 762                                 21);
 763
 764                 if (!dev->phy.is_40mhz) {
 765                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 766                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 767                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 768                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 769                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 770                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 771                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 772                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 773                 }
 774
 775                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 776
 777                 if (nphy->gain_boost) {
 778                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 779                             dev->phy.is_40mhz)
 780                                 code = 4;
 781                         else
 782                                 code = 5;
 783                 } else {
 784                         code = dev->phy.is_40mhz ? 6 : 7;
 785                 }
 786
 787                 /* Set HPVGA2 index */
 788                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 789                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 790                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 791                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 792                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 793                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 794
 795                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 796                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 797                                         (code << 8 | 0x7C));
 798                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 799                                         (code << 8 | 0x7C));
 800
 801                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 802
 803                 if (nphy->elna_gain_config) {
 804                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 805                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 806                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 807                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 808                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 809
 810                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 811                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 812                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 813                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 814                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 815
 816                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 817                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 818                                         (code << 8 | 0x74));
 819                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 820                                         (code << 8 | 0x74));
 821                 }
 822
 823                 if (dev->phy.rev == 2) {
 824                         for (i = 0; i < 4; i++) {
 825                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 826                                                 (0x0400 * i) + 0x0020);
 827                                 for (j = 0; j < 21; j++)
 828                                         b43_phy_write(dev,
 829                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 830                         }
 831
 832                         b43_nphy_set_rf_sequence(dev, 5,
 833                                         rfseq_events, rfseq_delays, 3);
 834                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 835                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 836                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 837
 838                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 839                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 840                                                 0xFF80, 4);
 841                 }
 842         }
 843 }
 844
 845 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 846 static void b43_nphy_workarounds(struct b43_wldev *dev)
 847 {
 848         struct ssb_bus *bus = dev->dev->bus;
 849         struct b43_phy *phy = &dev->phy;
 850         struct b43_phy_n *nphy = phy->n;
 851
 852         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 853         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 854
 855         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 856         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 857
 858         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 859                 b43_nphy_classifier(dev, 1, 0);
 860         else
 861                 b43_nphy_classifier(dev, 1, 1);
 862
 863         if (nphy->hang_avoid)
 864                 b43_nphy_stay_in_carrier_search(dev, 1);
 865
 866         b43_phy_set(dev, B43_NPHY_IQFLIP,
 867                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 868
 869         if (dev->phy.rev >= 3) {
 870                 /* TODO */
 871         } else {
 872                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 873                     nphy->band5g_pwrgain) {
 874                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 875                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 876                 } else {
 877                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 878                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 879                 }
 880
 881                 /* TODO: convert to b43_ntab_write? */
 882                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 883                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 884                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 885                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 886                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 887                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 888                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 889                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 890
 891                 if (dev->phy.rev < 2) {
 892                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 893                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 894                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 895                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 896                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 897                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 898                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
 899                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 900                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
 901                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 902                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
 903                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
 904                 }
 905
 906                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 907                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 908                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 909                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 910
 911                 if (bus->sprom.boardflags2_lo & 0x100 &&
 912                     bus->boardinfo.type == 0x8B) {
 913                         delays1[0] = 0x1;
 914                         delays1[5] = 0x14;
 915                 }
 916                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
 917                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
 918
 919                 b43_nphy_gain_crtl_workarounds(dev);
 920
 921                 if (dev->phy.rev < 2) {
 922                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
 923                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
 924                 } else if (dev->phy.rev == 2) {
 925                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
 926                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
 927                 }
 928
 929                 if (dev->phy.rev < 2)
 930                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 931                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
 932
 933                 /* Set phase track alpha and beta */
 934                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 935                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 936                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 937                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 938                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 939                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 940
 941                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
 942                                 (u16)~B43_NPHY_PIL_DW_64QAM);
 943                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
 944                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
 945                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
 946
 947                 if (dev->phy.rev == 2)
 948                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
 949                                         B43_NPHY_FINERX2_CGC_DECGC);
 950         }
 951
 952         if (nphy->hang_avoid)
 953                 b43_nphy_stay_in_carrier_search(dev, 0);
 954 }
 955
 956 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
 957 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
 958                                         bool test)
 959 {
 960         int i;
 961         u16 bw, len, rot, angle;
 962         struct b43_c32 *samples;
 963
 964
 965         bw = (dev->phy.is_40mhz) ? 40 : 20;
 966         len = bw << 3;
 967
 968         if (test) {
 969                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
 970                         bw = 82;
 971                 else
 972                         bw = 80;
 973
 974                 if (dev->phy.is_40mhz)
 975                         bw <<= 1;
 976
 977                 len = bw << 1;
 978         }
 979
 980         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
 981         rot = (((freq * 36) / bw) << 16) / 100;
 982         angle = 0;
 983
 984         for (i = 0; i < len; i++) {
 985                 samples[i] = b43_cordic(angle);
 986                 angle += rot;
 987                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
 988                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
 989         }
 990
 991         /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */
 992         kfree(samples);
 993         return len;
 994 }
 995
 996 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
 997 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
 998                                         u16 wait, bool iqmode, bool dac_test)
 999 {
1000         struct b43_phy_n *nphy = dev->phy.n;
1001         int i;
1002         u16 seq_mode;
1003         u32 tmp;
1004
1005         if (nphy->hang_avoid)
1006                 b43_nphy_stay_in_carrier_search(dev, true);
1007
1008         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1009                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1010                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1011         }
1012
1013         if (!dev->phy.is_40mhz)
1014                 tmp = 0x6464;
1015         else
1016                 tmp = 0x4747;
1017         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1018
1019         if (nphy->hang_avoid)
1020                 b43_nphy_stay_in_carrier_search(dev, false);
1021
1022         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1023
1024         if (loops != 0xFFFF)
1025                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1026         else
1027                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1028
1029         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1030
1031         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1032
1033         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1034         if (iqmode) {
1035                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1036                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1037         } else {
1038                 if (dac_test)
1039                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1040                 else
1041                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1042         }
1043         for (i = 0; i < 100; i++) {
1044                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1045                         i = 0;
1046                         break;
1047                 }
1048                 udelay(10);
1049         }
1050         if (i)
1051                 b43err(dev->wl, "run samples timeout\n");
1052
1053         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1054 }
1055
1056 /*
1057  * Transmits a known value for LO calibration
1058  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1059  */
1060 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1061                                 bool iqmode, bool dac_test)
1062 {
1063         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1064         if (samp == 0)
1065                 return -1;
1066         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1067         return 0;
1068 }
1069
1070 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1071 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1072 {
1073         struct b43_phy_n *nphy = dev->phy.n;
1074         int i, j;
1075         u32 tmp;
1076         u32 cur_real, cur_imag, real_part, imag_part;
1077
1078         u16 buffer[7];
1079
1080         if (nphy->hang_avoid)
1081                 b43_nphy_stay_in_carrier_search(dev, true);
1082
1083         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1084
1085         for (i = 0; i < 2; i++) {
1086                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1087                         (buffer[i * 2 + 1] & 0x3FF);
1088                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1089                                 (((i + 26) << 10) | 320));
1090                 for (j = 0; j < 128; j++) {
1091                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1092                                         ((tmp >> 16) & 0xFFFF));
1093                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1094                                         (tmp & 0xFFFF));
1095                 }
1096         }
1097
1098         for (i = 0; i < 2; i++) {
1099                 tmp = buffer[5 + i];
1100                 real_part = (tmp >> 8) & 0xFF;
1101                 imag_part = (tmp & 0xFF);
1102                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1103                                 (((i + 26) << 10) | 448));
1104
1105                 if (dev->phy.rev >= 3) {
1106                         cur_real = real_part;
1107                         cur_imag = imag_part;
1108                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1109                 }
1110
1111                 for (j = 0; j < 128; j++) {
1112                         if (dev->phy.rev < 3) {
1113                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1114                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1115                                 tmp = ((cur_real & 0xFF) << 8) |
1116                                         (cur_imag & 0xFF);
1117                         }
1118                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1119                                         ((tmp >> 16) & 0xFFFF));
1120                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1121                                         (tmp & 0xFFFF));
1122                 }
1123         }
1124
1125         if (dev->phy.rev >= 3) {
1126                 b43_shm_write16(dev, B43_SHM_SHARED,
1127                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1128                 b43_shm_write16(dev, B43_SHM_SHARED,
1129                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1130         }
1131
1132         if (nphy->hang_avoid)
1133                 b43_nphy_stay_in_carrier_search(dev, false);
1134 }
1135
1136 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1137 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1138                                         u8 *events, u8 *delays, u8 length)
1139 {
1140         struct b43_phy_n *nphy = dev->phy.n;
1141         u8 i;
1142         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1143         u16 offset1 = cmd << 4;
1144         u16 offset2 = offset1 + 0x80;
1145
1146         if (nphy->hang_avoid)
1147                 b43_nphy_stay_in_carrier_search(dev, true);
1148
1149         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1150         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1151
1152         for (i = length; i < 16; i++) {
1153                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1154                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1155         }
1156
1157         if (nphy->hang_avoid)
1158                 b43_nphy_stay_in_carrier_search(dev, false);
1159 }
1160
1161 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1162 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1163                                        enum b43_nphy_rf_sequence seq)
1164 {
1165         static const u16 trigger[] = {
1166                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1167                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1168                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1169                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1170                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1171                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1172         };
1173         int i;
1174         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1175
1176         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1177
1178         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1179                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1180         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1181         for (i = 0; i < 200; i++) {
1182                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1183                         goto ok;
1184                 msleep(1);
1185         }
1186         b43err(dev->wl, "RF sequence status timeout\n");
1187 ok:
1188         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1189 }
1190
1191 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1192 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1193                                                 u16 value, u8 core, bool off)
1194 {
1195         int i;
1196         u8 index = fls(field);
1197         u8 addr, en_addr, val_addr;
1198         /* we expect only one bit set */
1199         B43_WARN_ON(field & (~(1 << (index - 1))));
1200
1201         if (dev->phy.rev >= 3) {
1202                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1203                 for (i = 0; i < 2; i++) {
1204                         if (index == 0 || index == 16) {
1205                                 b43err(dev->wl,
1206                                         "Unsupported RF Ctrl Override call\n");
1207                                 return;
1208                         }
1209
1210                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1211                         en_addr = B43_PHY_N((i == 0) ?
1212                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1213                         val_addr = B43_PHY_N((i == 0) ?
1214                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1215
1216                         if (off) {
1217                                 b43_phy_mask(dev, en_addr, ~(field));
1218                                 b43_phy_mask(dev, val_addr,
1219                                                 ~(rf_ctrl->val_mask));
1220                         } else {
1221                                 if (core == 0 || ((1 << core) & i) != 0) {
1222                                         b43_phy_set(dev, en_addr, field);
1223                                         b43_phy_maskset(dev, val_addr,
1224                                                 ~(rf_ctrl->val_mask),
1225                                                 (value << rf_ctrl->val_shift));
1226                                 }
1227                         }
1228                 }
1229         } else {
1230                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1231                 if (off) {
1232                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1233                         value = 0;
1234                 } else {
1235                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1236                 }
1237
1238                 for (i = 0; i < 2; i++) {
1239                         if (index <= 1 || index == 16) {
1240                                 b43err(dev->wl,
1241                                         "Unsupported RF Ctrl Override call\n");
1242                                 return;
1243                         }
1244
1245                         if (index == 2 || index == 10 ||
1246                             (index >= 13 && index <= 15)) {
1247                                 core = 1;
1248                         }
1249
1250                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1251                         addr = B43_PHY_N((i == 0) ?
1252                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1253
1254                         if ((core & (1 << i)) != 0)
1255                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1256                                                 (value << rf_ctrl->shift));
1257
1258                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1259                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1260                                         B43_NPHY_RFCTL_CMD_START);
1261                         udelay(1);
1262                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1263                 }
1264         }
1265 }
1266
1267 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1268 {
1269         unsigned int i;
1270         u16 val;
1271
1272         val = 0x1E1F;
1273         for (i = 0; i < 14; i++) {
1274                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1275                 val -= 0x202;
1276         }
1277         val = 0x3E3F;
1278         for (i = 0; i < 16; i++) {
1279                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1280                 val -= 0x202;
1281         }
1282         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1283 }
1284
1285 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1286 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1287                                        s8 offset, u8 core, u8 rail, u8 type)
1288 {
1289         u16 tmp;
1290         bool core1or5 = (core == 1) || (core == 5);
1291         bool core2or5 = (core == 2) || (core == 5);
1292
1293         offset = clamp_val(offset, -32, 31);
1294         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1295
1296         if (core1or5 && (rail == 0) && (type == 2))
1297                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1298         if (core1or5 && (rail == 1) && (type == 2))
1299                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1300         if (core2or5 && (rail == 0) && (type == 2))
1301                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1302         if (core2or5 && (rail == 1) && (type == 2))
1303                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1304         if (core1or5 && (rail == 0) && (type == 0))
1305                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1306         if (core1or5 && (rail == 1) && (type == 0))
1307                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1308         if (core2or5 && (rail == 0) && (type == 0))
1309                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1310         if (core2or5 && (rail == 1) && (type == 0))
1311                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1312         if (core1or5 && (rail == 0) && (type == 1))
1313                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1314         if (core1or5 && (rail == 1) && (type == 1))
1315                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1316         if (core2or5 && (rail == 0) && (type == 1))
1317                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1318         if (core2or5 && (rail == 1) && (type == 1))
1319                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1320         if (core1or5 && (rail == 0) && (type == 6))
1321                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1322         if (core1or5 && (rail == 1) && (type == 6))
1323                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1324         if (core2or5 && (rail == 0) && (type == 6))
1325                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1326         if (core2or5 && (rail == 1) && (type == 6))
1327                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1328         if (core1or5 && (rail == 0) && (type == 3))
1329                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1330         if (core1or5 && (rail == 1) && (type == 3))
1331                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1332         if (core2or5 && (rail == 0) && (type == 3))
1333                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1334         if (core2or5 && (rail == 1) && (type == 3))
1335                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1336         if (core1or5 && (type == 4))
1337                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1338         if (core2or5 && (type == 4))
1339                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1340         if (core1or5 && (type == 5))
1341                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1342         if (core2or5 && (type == 5))
1343                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1344 }
1345
1346 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1347 {
1348         u16 val;
1349
1350         if (type < 3)
1351                 val = 0;
1352         else if (type == 6)
1353                 val = 1;
1354         else if (type == 3)
1355                 val = 2;
1356         else
1357                 val = 3;
1358
1359         val = (val << 12) | (val << 14);
1360         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1361         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1362
1363         if (type < 3) {
1364                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1365                                 (type + 1) << 4);
1366                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1367                                 (type + 1) << 4);
1368         }
1369
1370         /* TODO use some definitions */
1371         if (code == 0) {
1372                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1373                 if (type < 3) {
1374                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1375                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1376                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1377                         udelay(20);
1378                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1379                 }
1380         } else {
1381                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1382                                 0x3000);
1383                 if (type < 3) {
1384                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1385                                         0xFEC7, 0x0180);
1386                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1387                                         0xEFDC, (code << 1 | 0x1021));
1388                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1389                         udelay(20);
1390                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1391                 }
1392         }
1393 }
1394
1395 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1396 {
1397         struct b43_phy_n *nphy = dev->phy.n;
1398         u8 i;
1399         u16 reg, val;
1400
1401         if (code == 0) {
1402                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1403                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1404                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1405                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1406                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1407                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1408                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1409                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1410         } else {
1411                 for (i = 0; i < 2; i++) {
1412                         if ((code == 1 && i == 1) || (code == 2 && !i))
1413                                 continue;
1414
1415                         reg = (i == 0) ?
1416                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1417                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1418
1419                         if (type < 3) {
1420                                 reg = (i == 0) ?
1421                                         B43_NPHY_AFECTL_C1 :
1422                                         B43_NPHY_AFECTL_C2;
1423                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1424
1425                                 reg = (i == 0) ?
1426                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1427                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1428                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1429
1430                                 if (type == 0)
1431                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1432                                 else if (type == 1)
1433                                         val = 16;
1434                                 else
1435                                         val = 32;
1436                                 b43_phy_set(dev, reg, val);
1437
1438                                 reg = (i == 0) ?
1439                                         B43_NPHY_TXF_40CO_B1S0 :
1440                                         B43_NPHY_TXF_40CO_B32S1;
1441                                 b43_phy_set(dev, reg, 0x0020);
1442                         } else {
1443                                 if (type == 6)
1444                                         val = 0x0100;
1445                                 else if (type == 3)
1446                                         val = 0x0200;
1447                                 else
1448                                         val = 0x0300;
1449
1450                                 reg = (i == 0) ?
1451                                         B43_NPHY_AFECTL_C1 :
1452                                         B43_NPHY_AFECTL_C2;
1453
1454                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1455                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1456
1457                                 if (type != 3 && type != 6) {
1458                                         enum ieee80211_band band =
1459                                                 b43_current_band(dev->wl);
1460
1461                                         if ((nphy->ipa2g_on &&
1462                                                 band == IEEE80211_BAND_2GHZ) ||
1463                                                 (nphy->ipa5g_on &&
1464                                                 band == IEEE80211_BAND_5GHZ))
1465                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1466                                         else
1467                                                 val = 0x11;
1468                                         reg = (i == 0) ? 0x2000 : 0x3000;
1469                                         reg |= B2055_PADDRV;
1470                                         b43_radio_write16(dev, reg, val);
1471
1472                                         reg = (i == 0) ?
1473                                                 B43_NPHY_AFECTL_OVER1 :
1474                                                 B43_NPHY_AFECTL_OVER;
1475                                         b43_phy_set(dev, reg, 0x0200);
1476                                 }
1477                         }
1478                 }
1479         }
1480 }
1481
1482 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1483 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1484 {
1485         if (dev->phy.rev >= 3)
1486                 b43_nphy_rev3_rssi_select(dev, code, type);
1487         else
1488                 b43_nphy_rev2_rssi_select(dev, code, type);
1489 }
1490
1491 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1492 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1493 {
1494         int i;
1495         for (i = 0; i < 2; i++) {
1496                 if (type == 2) {
1497                         if (i == 0) {
1498                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1499                                                   0xFC, buf[0]);
1500                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1501                                                   0xFC, buf[1]);
1502                         } else {
1503                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1504                                                   0xFC, buf[2 * i]);
1505                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1506                                                   0xFC, buf[2 * i + 1]);
1507                         }
1508                 } else {
1509                         if (i == 0)
1510                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1511                                                   0xF3, buf[0] << 2);
1512                         else
1513                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1514                                                   0xF3, buf[2 * i + 1] << 2);
1515                 }
1516         }
1517 }
1518
1519 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1520 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1521                                 u8 nsamp)
1522 {
1523         int i;
1524         int out;
1525         u16 save_regs_phy[9];
1526         u16 s[2];
1527
1528         if (dev->phy.rev >= 3) {
1529                 save_regs_phy[0] = b43_phy_read(dev,
1530                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1531                 save_regs_phy[1] = b43_phy_read(dev,
1532                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1533                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1534                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1535                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1536                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1537                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1538                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1539         }
1540
1541         b43_nphy_rssi_select(dev, 5, type);
1542
1543         if (dev->phy.rev < 2) {
1544                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1545                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1546         }
1547
1548         for (i = 0; i < 4; i++)
1549                 buf[i] = 0;
1550
1551         for (i = 0; i < nsamp; i++) {
1552                 if (dev->phy.rev < 2) {
1553                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1554                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1555                 } else {
1556                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1557                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1558                 }
1559
1560                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1561                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1562                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1563                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1564         }
1565         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1566                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1567
1568         if (dev->phy.rev < 2)
1569                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1570
1571         if (dev->phy.rev >= 3) {
1572                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1573                                 save_regs_phy[0]);
1574                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1575                                 save_regs_phy[1]);
1576                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1577                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1578                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1579                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1580                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1581                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1582         }
1583
1584         return out;
1585 }
1586
1587 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1588 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1589 {
1590         int i, j;
1591         u8 state[4];
1592         u8 code, val;
1593         u16 class, override;
1594         u8 regs_save_radio[2];
1595         u16 regs_save_phy[2];
1596         s8 offset[4];
1597
1598         u16 clip_state[2];
1599         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1600         s32 results_min[4] = { };
1601         u8 vcm_final[4] = { };
1602         s32 results[4][4] = { };
1603         s32 miniq[4][2] = { };
1604
1605         if (type == 2) {
1606                 code = 0;
1607                 val = 6;
1608         } else if (type < 2) {
1609                 code = 25;
1610                 val = 4;
1611         } else {
1612                 B43_WARN_ON(1);
1613                 return;
1614         }
1615
1616         class = b43_nphy_classifier(dev, 0, 0);
1617         b43_nphy_classifier(dev, 7, 4);
1618         b43_nphy_read_clip_detection(dev, clip_state);
1619         b43_nphy_write_clip_detection(dev, clip_off);
1620
1621         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1622                 override = 0x140;
1623         else
1624                 override = 0x110;
1625
1626         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1627         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1628         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1629         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1630
1631         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1632         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1633         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1634         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1635
1636         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1637         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1638         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1639         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1640         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1641         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1642
1643         b43_nphy_rssi_select(dev, 5, type);
1644         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1645         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1646
1647         for (i = 0; i < 4; i++) {
1648                 u8 tmp[4];
1649                 for (j = 0; j < 4; j++)
1650                         tmp[j] = i;
1651                 if (type != 1)
1652                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1653                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1654                 if (type < 2)
1655                         for (j = 0; j < 2; j++)
1656                                 miniq[i][j] = min(results[i][2 * j],
1657                                                 results[i][2 * j + 1]);
1658         }
1659
1660         for (i = 0; i < 4; i++) {
1661                 s32 mind = 40;
1662                 u8 minvcm = 0;
1663                 s32 minpoll = 249;
1664                 s32 curr;
1665                 for (j = 0; j < 4; j++) {
1666                         if (type == 2)
1667                                 curr = abs(results[j][i]);
1668                         else
1669                                 curr = abs(miniq[j][i / 2] - code * 8);
1670
1671                         if (curr < mind) {
1672                                 mind = curr;
1673                                 minvcm = j;
1674                         }
1675
1676                         if (results[j][i] < minpoll)
1677                                 minpoll = results[j][i];
1678                 }
1679                 results_min[i] = minpoll;
1680                 vcm_final[i] = minvcm;
1681         }
1682
1683         if (type != 1)
1684                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1685
1686         for (i = 0; i < 4; i++) {
1687                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1688
1689                 if (offset[i] < 0)
1690                         offset[i] = -((abs(offset[i]) + 4) / 8);
1691                 else
1692                         offset[i] = (offset[i] + 4) / 8;
1693
1694                 if (results_min[i] == 248)
1695                         offset[i] = code - 32;
1696
1697                 if (i % 2 == 0)
1698                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1699                                                         type);
1700                 else
1701                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1702                                                         type);
1703         }
1704
1705         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1706         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1707
1708         switch (state[2]) {
1709         case 1:
1710                 b43_nphy_rssi_select(dev, 1, 2);
1711                 break;
1712         case 4:
1713                 b43_nphy_rssi_select(dev, 1, 0);
1714                 break;
1715         case 2:
1716                 b43_nphy_rssi_select(dev, 1, 1);
1717                 break;
1718         default:
1719                 b43_nphy_rssi_select(dev, 1, 1);
1720                 break;
1721         }
1722
1723         switch (state[3]) {
1724         case 1:
1725                 b43_nphy_rssi_select(dev, 2, 2);
1726                 break;
1727         case 4:
1728                 b43_nphy_rssi_select(dev, 2, 0);
1729                 break;
1730         default:
1731                 b43_nphy_rssi_select(dev, 2, 1);
1732                 break;
1733         }
1734
1735         b43_nphy_rssi_select(dev, 0, type);
1736
1737         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1738         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1739         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1740         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1741
1742         b43_nphy_classifier(dev, 7, class);
1743         b43_nphy_write_clip_detection(dev, clip_state);
1744 }
1745
1746 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1747 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1748 {
1749         /* TODO */
1750 }
1751
1752 /*
1753  * RSSI Calibration
1754  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1755  */
1756 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1757 {
1758         if (dev->phy.rev >= 3) {
1759                 b43_nphy_rev3_rssi_cal(dev);
1760         } else {
1761                 b43_nphy_rev2_rssi_cal(dev, 2);
1762                 b43_nphy_rev2_rssi_cal(dev, 0);
1763                 b43_nphy_rev2_rssi_cal(dev, 1);
1764         }
1765 }
1766
1767 /*
1768  * Restore RSSI Calibration
1769  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1770  */
1771 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1772 {
1773         struct b43_phy_n *nphy = dev->phy.n;
1774
1775         u16 *rssical_radio_regs = NULL;
1776         u16 *rssical_phy_regs = NULL;
1777
1778         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1779                 if (!nphy->rssical_chanspec_2G)
1780                         return;
1781                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1782                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1783         } else {
1784                 if (!nphy->rssical_chanspec_5G)
1785                         return;
1786                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1787                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1788         }
1789
1790         /* TODO use some definitions */
1791         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1792         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1793
1794         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1795         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1796         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1797         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1798
1799         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1800         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1801         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1802         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1803
1804         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1805         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1806         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1807         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1808 }
1809
1810 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1811 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1812 {
1813         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1814                 if (dev->phy.rev >= 6) {
1815                         /* TODO If the chip is 47162
1816                                 return txpwrctrl_tx_gain_ipa_rev5 */
1817                         return txpwrctrl_tx_gain_ipa_rev6;
1818                 } else if (dev->phy.rev >= 5) {
1819                         return txpwrctrl_tx_gain_ipa_rev5;
1820                 } else {
1821                         return txpwrctrl_tx_gain_ipa;
1822                 }
1823         } else {
1824                 return txpwrctrl_tx_gain_ipa_5g;
1825         }
1826 }
1827
1828 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1829 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1830 {
1831         struct b43_phy_n *nphy = dev->phy.n;
1832         u16 *save = nphy->tx_rx_cal_radio_saveregs;
1833         u16 tmp;
1834         u8 offset, i;
1835
1836         if (dev->phy.rev >= 3) {
1837             for (i = 0; i < 2; i++) {
1838                 tmp = (i == 0) ? 0x2000 : 0x3000;
1839                 offset = i * 11;
1840
1841                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
1842                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
1843                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
1844                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
1845                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
1846                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
1847                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
1848                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
1849                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
1850                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
1851                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
1852
1853                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1854                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
1855                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
1856                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
1857                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
1858                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
1859                         if (nphy->ipa5g_on) {
1860                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
1861                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
1862                         } else {
1863                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
1864                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
1865                         }
1866                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
1867                 } else {
1868                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
1869                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
1870                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
1871                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
1872                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
1873                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
1874                         if (nphy->ipa2g_on) {
1875                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
1876                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
1877                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
1878                         } else {
1879                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
1880                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
1881                         }
1882                 }
1883                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
1884                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
1885                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
1886             }
1887         } else {
1888                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1889                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1890
1891                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1892                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1893
1894                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1895                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1896
1897                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1898                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1899
1900                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1901                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1902
1903                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1904                     B43_NPHY_BANDCTL_5GHZ)) {
1905                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1906                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1907                 } else {
1908                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1909                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1910                 }
1911
1912                 if (dev->phy.rev < 2) {
1913                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1914                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1915                 } else {
1916                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1917                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1918                 }
1919         }
1920 }
1921
1922 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1923 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1924                                         struct nphy_txgains target,
1925                                         struct nphy_iqcal_params *params)
1926 {
1927         int i, j, indx;
1928         u16 gain;
1929
1930         if (dev->phy.rev >= 3) {
1931                 params->txgm = target.txgm[core];
1932                 params->pga = target.pga[core];
1933                 params->pad = target.pad[core];
1934                 params->ipa = target.ipa[core];
1935                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1936                                         (params->pad << 4) | (params->ipa);
1937                 for (j = 0; j < 5; j++)
1938                         params->ncorr[j] = 0x79;
1939         } else {
1940                 gain = (target.pad[core]) | (target.pga[core] << 4) |
1941                         (target.txgm[core] << 8);
1942
1943                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1944                         1 : 0;
1945                 for (i = 0; i < 9; i++)
1946                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
1947                                 break;
1948                 i = min(i, 8);
1949
1950                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1951                 params->pga = tbl_iqcal_gainparams[indx][i][2];
1952                 params->pad = tbl_iqcal_gainparams[indx][i][3];
1953                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1954                                         (params->pad << 2);
1955                 for (j = 0; j < 4; j++)
1956                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1957         }
1958 }
1959
1960 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1961 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1962 {
1963         struct b43_phy_n *nphy = dev->phy.n;
1964         int i;
1965         u16 scale, entry;
1966
1967         u16 tmp = nphy->txcal_bbmult;
1968         if (core == 0)
1969                 tmp >>= 8;
1970         tmp &= 0xff;
1971
1972         for (i = 0; i < 18; i++) {
1973                 scale = (ladder_lo[i].percent * tmp) / 100;
1974                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
1975                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
1976
1977                 scale = (ladder_iq[i].percent * tmp) / 100;
1978                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
1979                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
1980         }
1981 }
1982
1983 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
1984 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
1985 {
1986         int i;
1987         for (i = 0; i < 15; i++)
1988                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
1989                                 tbl_tx_filter_coef_rev4[2][i]);
1990 }
1991
1992 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
1993 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
1994 {
1995         int i, j;
1996         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
1997         u16 offset[] = { 0x186, 0x195, 0x2C5 };
1998
1999         for (i = 0; i < 3; i++)
2000                 for (j = 0; j < 15; j++)
2001                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2002                                         tbl_tx_filter_coef_rev4[i][j]);
2003
2004         if (dev->phy.is_40mhz) {
2005                 for (j = 0; j < 15; j++)
2006                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2007                                         tbl_tx_filter_coef_rev4[3][j]);
2008         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2009                 for (j = 0; j < 15; j++)
2010                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2011                                         tbl_tx_filter_coef_rev4[5][j]);
2012         }
2013
2014         if (dev->phy.channel == 14)
2015                 for (j = 0; j < 15; j++)
2016                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2017                                         tbl_tx_filter_coef_rev4[6][j]);
2018 }
2019
2020 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2021 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2022 {
2023         struct b43_phy_n *nphy = dev->phy.n;
2024
2025         u16 curr_gain[2];
2026         struct nphy_txgains target;
2027         const u32 *table = NULL;
2028
2029         if (nphy->txpwrctrl == 0) {
2030                 int i;
2031
2032                 if (nphy->hang_avoid)
2033                         b43_nphy_stay_in_carrier_search(dev, true);
2034                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2035                 if (nphy->hang_avoid)
2036                         b43_nphy_stay_in_carrier_search(dev, false);
2037
2038                 for (i = 0; i < 2; ++i) {
2039                         if (dev->phy.rev >= 3) {
2040                                 target.ipa[i] = curr_gain[i] & 0x000F;
2041                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2042                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2043                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2044                         } else {
2045                                 target.ipa[i] = curr_gain[i] & 0x0003;
2046                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2047                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2048                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2049                         }
2050                 }
2051         } else {
2052                 int i;
2053                 u16 index[2];
2054                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2055                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2056                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2057                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2058                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2059                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2060
2061                 for (i = 0; i < 2; ++i) {
2062                         if (dev->phy.rev >= 3) {
2063                                 enum ieee80211_band band =
2064                                         b43_current_band(dev->wl);
2065
2066                                 if ((nphy->ipa2g_on &&
2067                                      band == IEEE80211_BAND_2GHZ) ||
2068                                     (nphy->ipa5g_on &&
2069                                      band == IEEE80211_BAND_5GHZ)) {
2070                                         table = b43_nphy_get_ipa_gain_table(dev);
2071                                 } else {
2072                                         if (band == IEEE80211_BAND_5GHZ) {
2073                                                 if (dev->phy.rev == 3)
2074                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2075                                                 else if (dev->phy.rev == 4)
2076                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2077                                                 else
2078                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2079                                         } else {
2080                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2081                                         }
2082                                 }
2083
2084                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2085                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2086                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2087                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2088                         } else {
2089                                 table = b43_ntab_tx_gain_rev0_1_2;
2090
2091                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2092                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2093                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2094                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2095                         }
2096                 }
2097         }
2098
2099         return target;
2100 }
2101
2102 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2103 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2104 {
2105         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2106
2107         if (dev->phy.rev >= 3) {
2108                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2109                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2110                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2111                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2112                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2113                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2114                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2115                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2116                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2117                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2118                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2119                 b43_nphy_reset_cca(dev);
2120         } else {
2121                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2122                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2123                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2124                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2125                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2126                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2127                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2128         }
2129 }
2130
2131 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2132 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2133 {
2134         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2135         u16 tmp;
2136
2137         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2138         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2139         if (dev->phy.rev >= 3) {
2140                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2141                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2142
2143                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2144                 regs[2] = tmp;
2145                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2146
2147                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2148                 regs[3] = tmp;
2149                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2150
2151                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2152                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2153
2154                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2155                 regs[5] = tmp;
2156                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2157
2158                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2159                 regs[6] = tmp;
2160                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2161                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2162                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2163
2164                 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
2165                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
2166                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
2167
2168                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2169                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2170                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2171                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2172         } else {
2173                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2174                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2175                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2176                 regs[2] = tmp;
2177                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2178                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2179                 regs[3] = tmp;
2180                 tmp |= 0x2000;
2181                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2182                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2183                 regs[4] = tmp;
2184                 tmp |= 0x2000;
2185                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2186                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2187                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2188                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2189                         tmp = 0x0180;
2190                 else
2191                         tmp = 0x0120;
2192                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2193                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2194         }
2195 }
2196
2197 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2198 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2199 {
2200         struct b43_phy_n *nphy = dev->phy.n;
2201
2202         u16 coef[4];
2203         u16 *loft = NULL;
2204         u16 *table = NULL;
2205
2206         int i;
2207         u16 *txcal_radio_regs = NULL;
2208         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2209
2210         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2211                 if (nphy->iqcal_chanspec_2G == 0)
2212                         return;
2213                 table = nphy->cal_cache.txcal_coeffs_2G;
2214                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2215         } else {
2216                 if (nphy->iqcal_chanspec_5G == 0)
2217                         return;
2218                 table = nphy->cal_cache.txcal_coeffs_5G;
2219                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2220         }
2221
2222         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2223
2224         for (i = 0; i < 4; i++) {
2225                 if (dev->phy.rev >= 3)
2226                         table[i] = coef[i];
2227                 else
2228                         coef[i] = 0;
2229         }
2230
2231         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2232         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2233         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2234
2235         if (dev->phy.rev < 2)
2236                 b43_nphy_tx_iq_workaround(dev);
2237
2238         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2239                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2240                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2241         } else {
2242                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2243                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2244         }
2245
2246         /* TODO use some definitions */
2247         if (dev->phy.rev >= 3) {
2248                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2249                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2250                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2251                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2252                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2253                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2254                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2255                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2256         } else {
2257                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2258                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2259                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2260                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2261         }
2262         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2263 }
2264
2265 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2266 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2267                                 struct nphy_txgains target,
2268                                 bool full, bool mphase)
2269 {
2270         struct b43_phy_n *nphy = dev->phy.n;
2271         int i;
2272         int error = 0;
2273         int freq;
2274         bool avoid = false;
2275         u8 length;
2276         u16 tmp, core, type, count, max, numb, last, cmd;
2277         const u16 *table;
2278         bool phy6or5x;
2279
2280         u16 buffer[11];
2281         u16 diq_start = 0;
2282         u16 save[2];
2283         u16 gain[2];
2284         struct nphy_iqcal_params params[2];
2285         bool updated[2] = { };
2286
2287         b43_nphy_stay_in_carrier_search(dev, true);
2288
2289         if (dev->phy.rev >= 4) {
2290                 avoid = nphy->hang_avoid;
2291                 nphy->hang_avoid = 0;
2292         }
2293
2294         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2295
2296         for (i = 0; i < 2; i++) {
2297                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2298                 gain[i] = params[i].cal_gain;
2299         }
2300
2301         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2302
2303         b43_nphy_tx_cal_radio_setup(dev);
2304         b43_nphy_tx_cal_phy_setup(dev);
2305
2306         phy6or5x = dev->phy.rev >= 6 ||
2307                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2308                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2309         if (phy6or5x) {
2310                 if (dev->phy.is_40mhz) {
2311                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2312                                         tbl_tx_iqlo_cal_loft_ladder_40);
2313                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2314                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2315                 } else {
2316                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2317                                         tbl_tx_iqlo_cal_loft_ladder_20);
2318                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2319                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2320                 }
2321         }
2322
2323         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2324
2325         if (!dev->phy.is_40mhz)
2326                 freq = 2500;
2327         else
2328                 freq = 5000;
2329
2330         if (nphy->mphase_cal_phase_id > 2)
2331                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2332                                         0xFFFF, 0, true, false);
2333         else
2334                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2335
2336         if (error == 0) {
2337                 if (nphy->mphase_cal_phase_id > 2) {
2338                         table = nphy->mphase_txcal_bestcoeffs;
2339                         length = 11;
2340                         if (dev->phy.rev < 3)
2341                                 length -= 2;
2342                 } else {
2343                         if (!full && nphy->txiqlocal_coeffsvalid) {
2344                                 table = nphy->txiqlocal_bestc;
2345                                 length = 11;
2346                                 if (dev->phy.rev < 3)
2347                                         length -= 2;
2348                         } else {
2349                                 full = true;
2350                                 if (dev->phy.rev >= 3) {
2351                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2352                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2353                                 } else {
2354                                         table = tbl_tx_iqlo_cal_startcoefs;
2355                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2356                                 }
2357                         }
2358                 }
2359
2360                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2361
2362                 if (full) {
2363                         if (dev->phy.rev >= 3)
2364                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2365                         else
2366                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2367                 } else {
2368                         if (dev->phy.rev >= 3)
2369                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2370                         else
2371                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2372                 }
2373
2374                 if (mphase) {
2375                         count = nphy->mphase_txcal_cmdidx;
2376                         numb = min(max,
2377                                 (u16)(count + nphy->mphase_txcal_numcmds));
2378                 } else {
2379                         count = 0;
2380                         numb = max;
2381                 }
2382
2383                 for (; count < numb; count++) {
2384                         if (full) {
2385                                 if (dev->phy.rev >= 3)
2386                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2387                                 else
2388                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2389                         } else {
2390                                 if (dev->phy.rev >= 3)
2391                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2392                                 else
2393                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2394                         }
2395
2396                         core = (cmd & 0x3000) >> 12;
2397                         type = (cmd & 0x0F00) >> 8;
2398
2399                         if (phy6or5x && updated[core] == 0) {
2400                                 b43_nphy_update_tx_cal_ladder(dev, core);
2401                                 updated[core] = 1;
2402                         }
2403
2404                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2405                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2406
2407                         if (type == 1 || type == 3 || type == 4) {
2408                                 buffer[0] = b43_ntab_read(dev,
2409                                                 B43_NTAB16(15, 69 + core));
2410                                 diq_start = buffer[0];
2411                                 buffer[0] = 0;
2412                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2413                                                 0);
2414                         }
2415
2416                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2417                         for (i = 0; i < 2000; i++) {
2418                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2419                                 if (tmp & 0xC000)
2420                                         break;
2421                                 udelay(10);
2422                         }
2423
2424                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2425                                                 buffer);
2426                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2427                                                 buffer);
2428
2429                         if (type == 1 || type == 3 || type == 4)
2430                                 buffer[0] = diq_start;
2431                 }
2432
2433                 if (mphase)
2434                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2435
2436                 last = (dev->phy.rev < 3) ? 6 : 7;
2437
2438                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2439                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2440                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2441                         if (dev->phy.rev < 3) {
2442                                 buffer[0] = 0;
2443                                 buffer[1] = 0;
2444                                 buffer[2] = 0;
2445                                 buffer[3] = 0;
2446                         }
2447                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2448                                                 buffer);
2449                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2450                                                 buffer);
2451                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2452                                                 buffer);
2453                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2454                                                 buffer);
2455                         length = 11;
2456                         if (dev->phy.rev < 3)
2457                                 length -= 2;
2458                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2459                                                 nphy->txiqlocal_bestc);
2460                         nphy->txiqlocal_coeffsvalid = true;
2461                         /* TODO: Set nphy->txiqlocal_chanspec to
2462                                 the current channel */
2463                 } else {
2464                         length = 11;
2465                         if (dev->phy.rev < 3)
2466                                 length -= 2;
2467                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2468                                                 nphy->mphase_txcal_bestcoeffs);
2469                 }
2470
2471                 b43_nphy_stop_playback(dev);
2472                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2473         }
2474
2475         b43_nphy_tx_cal_phy_cleanup(dev);
2476         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2477
2478         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2479                 b43_nphy_tx_iq_workaround(dev);
2480
2481         if (dev->phy.rev >= 4)
2482                 nphy->hang_avoid = avoid;
2483
2484         b43_nphy_stay_in_carrier_search(dev, false);
2485
2486         return error;
2487 }
2488
2489 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2490 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2491                         struct nphy_txgains target, u8 type, bool debug)
2492 {
2493         struct b43_phy_n *nphy = dev->phy.n;
2494         int i, j, index;
2495         u8 rfctl[2];
2496         u8 afectl_core;
2497         u16 tmp[6];
2498         u16 cur_hpf1, cur_hpf2, cur_lna;
2499         u32 real, imag;
2500         enum ieee80211_band band;
2501
2502         u8 use;
2503         u16 cur_hpf;
2504         u16 lna[3] = { 3, 3, 1 };
2505         u16 hpf1[3] = { 7, 2, 0 };
2506         u16 hpf2[3] = { 2, 0, 0 };
2507         u32 power[3] = { };
2508         u16 gain_save[2];
2509         u16 cal_gain[2];
2510         struct nphy_iqcal_params cal_params[2];
2511         struct nphy_iq_est est;
2512         int ret = 0;
2513         bool playtone = true;
2514         int desired = 13;
2515
2516         b43_nphy_stay_in_carrier_search(dev, 1);
2517
2518         if (dev->phy.rev < 2)
2519                 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
2520         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2521         for (i = 0; i < 2; i++) {
2522                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2523                 cal_gain[i] = cal_params[i].cal_gain;
2524         }
2525         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2526
2527         for (i = 0; i < 2; i++) {
2528                 if (i == 0) {
2529                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2530                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2531                         afectl_core = B43_NPHY_AFECTL_C1;
2532                 } else {
2533                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2534                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2535                         afectl_core = B43_NPHY_AFECTL_C2;
2536                 }
2537
2538                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2539                 tmp[2] = b43_phy_read(dev, afectl_core);
2540                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2541                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2542                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2543
2544                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2545                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2546                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2547                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2548                                 (1 - i));
2549                 b43_phy_set(dev, afectl_core, 0x0006);
2550                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2551
2552                 band = b43_current_band(dev->wl);
2553
2554                 if (nphy->rxcalparams & 0xFF000000) {
2555                         if (band == IEEE80211_BAND_5GHZ)
2556                                 b43_phy_write(dev, rfctl[0], 0x140);
2557                         else
2558                                 b43_phy_write(dev, rfctl[0], 0x110);
2559                 } else {
2560                         if (band == IEEE80211_BAND_5GHZ)
2561                                 b43_phy_write(dev, rfctl[0], 0x180);
2562                         else
2563                                 b43_phy_write(dev, rfctl[0], 0x120);
2564                 }
2565
2566                 if (band == IEEE80211_BAND_5GHZ)
2567                         b43_phy_write(dev, rfctl[1], 0x148);
2568                 else
2569                         b43_phy_write(dev, rfctl[1], 0x114);
2570
2571                 if (nphy->rxcalparams & 0x10000) {
2572                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2573                                         (i + 1));
2574                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2575                                         (2 - i));
2576                 }
2577
2578                 for (j = 0; i < 4; j++) {
2579                         if (j < 3) {
2580                                 cur_lna = lna[j];
2581                                 cur_hpf1 = hpf1[j];
2582                                 cur_hpf2 = hpf2[j];
2583                         } else {
2584                                 if (power[1] > 10000) {
2585                                         use = 1;
2586                                         cur_hpf = cur_hpf1;
2587                                         index = 2;
2588                                 } else {
2589                                         if (power[0] > 10000) {
2590                                                 use = 1;
2591                                                 cur_hpf = cur_hpf1;
2592                                                 index = 1;
2593                                         } else {
2594                                                 index = 0;
2595                                                 use = 2;
2596                                                 cur_hpf = cur_hpf2;
2597                                         }
2598                                 }
2599                                 cur_lna = lna[index];
2600                                 cur_hpf1 = hpf1[index];
2601                                 cur_hpf2 = hpf2[index];
2602                                 cur_hpf += desired - hweight32(power[index]);
2603                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2604                                 if (use == 1)
2605                                         cur_hpf1 = cur_hpf;
2606                                 else
2607                                         cur_hpf2 = cur_hpf;
2608                         }
2609
2610                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2611                                         (cur_lna << 2));
2612                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2613                                                                         false);
2614                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2615                         b43_nphy_stop_playback(dev);
2616
2617                         if (playtone) {
2618                                 ret = b43_nphy_tx_tone(dev, 4000,
2619                                                 (nphy->rxcalparams & 0xFFFF),
2620                                                 false, false);
2621                                 playtone = false;
2622                         } else {
2623                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2624                                                         false, false);
2625                         }
2626
2627                         if (ret == 0) {
2628                                 if (j < 3) {
2629                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2630                                                                         false);
2631                                         if (i == 0) {
2632                                                 real = est.i0_pwr;
2633                                                 imag = est.q0_pwr;
2634                                         } else {
2635                                                 real = est.i1_pwr;
2636                                                 imag = est.q1_pwr;
2637                                         }
2638                                         power[i] = ((real + imag) / 1024) + 1;
2639                                 } else {
2640                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2641                                 }
2642                                 b43_nphy_stop_playback(dev);
2643                         }
2644
2645                         if (ret != 0)
2646                                 break;
2647                 }
2648
2649                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2650                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2651                 b43_phy_write(dev, rfctl[1], tmp[5]);
2652                 b43_phy_write(dev, rfctl[0], tmp[4]);
2653                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2654                 b43_phy_write(dev, afectl_core, tmp[2]);
2655                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2656
2657                 if (ret != 0)
2658                         break;
2659         }
2660
2661         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2662         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2663         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2664
2665         b43_nphy_stay_in_carrier_search(dev, 0);
2666
2667         return ret;
2668 }
2669
2670 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2671                         struct nphy_txgains target, u8 type, bool debug)
2672 {
2673         return -1;
2674 }
2675
2676 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2677 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2678                         struct nphy_txgains target, u8 type, bool debug)
2679 {
2680         if (dev->phy.rev >= 3)
2681                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2682         else
2683                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2684 }
2685
2686 /*
2687  * Init N-PHY
2688  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2689  */
2690 int b43_phy_initn(struct b43_wldev *dev)
2691 {
2692         struct ssb_bus *bus = dev->dev->bus;
2693         struct b43_phy *phy = &dev->phy;
2694         struct b43_phy_n *nphy = phy->n;
2695         u8 tx_pwr_state;
2696         struct nphy_txgains target;
2697         u16 tmp;
2698         enum ieee80211_band tmp2;
2699         bool do_rssi_cal;
2700
2701         u16 clip[2];
2702         bool do_cal = false;
2703
2704         if ((dev->phy.rev >= 3) &&
2705            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2706            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2707                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2708         }
2709         nphy->deaf_count = 0;
2710         b43_nphy_tables_init(dev);
2711         nphy->crsminpwr_adjusted = false;
2712         nphy->noisevars_adjusted = false;
2713
2714         /* Clear all overrides */
2715         if (dev->phy.rev >= 3) {
2716                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2717                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2718                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2719                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2720         } else {
2721                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2722         }
2723         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2724         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2725         if (dev->phy.rev < 6) {
2726                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2727                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2728         }
2729         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2730                      ~(B43_NPHY_RFSEQMODE_CAOVER |
2731                        B43_NPHY_RFSEQMODE_TROVER));
2732         if (dev->phy.rev >= 3)
2733                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2734         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2735
2736         if (dev->phy.rev <= 2) {
2737                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2738                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2739                                 ~B43_NPHY_BPHY_CTL3_SCALE,
2740                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2741         }
2742         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2743         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2744
2745         if (bus->sprom.boardflags2_lo & 0x100 ||
2746             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2747              bus->boardinfo.type == 0x8B))
2748                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2749         else
2750                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2751         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2752         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2753         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2754
2755         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
2756         b43_nphy_update_txrx_chain(dev);
2757
2758         if (phy->rev < 2) {
2759                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2760                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2761         }
2762
2763         tmp2 = b43_current_band(dev->wl);
2764         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2765             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2766                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2767                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2768                                 nphy->papd_epsilon_offset[0] << 7);
2769                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2770                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2771                                 nphy->papd_epsilon_offset[1] << 7);
2772                 b43_nphy_int_pa_set_tx_dig_filters(dev);
2773         } else if (phy->rev >= 5) {
2774                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
2775         }
2776
2777         b43_nphy_workarounds(dev);
2778
2779         /* Reset CCA, in init code it differs a little from standard way */
2780         b43_nphy_bmac_clock_fgc(dev, 1);
2781         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2782         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2783         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
2784         b43_nphy_bmac_clock_fgc(dev, 0);
2785
2786         /* TODO N PHY MAC PHY Clock Set with argument 1 */
2787
2788         b43_nphy_pa_override(dev, false);
2789         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2790         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2791         b43_nphy_pa_override(dev, true);
2792
2793         b43_nphy_classifier(dev, 0, 0);
2794         b43_nphy_read_clip_detection(dev, clip);
2795         tx_pwr_state = nphy->txpwrctrl;
2796         /* TODO N PHY TX power control with argument 0
2797                 (turning off power control) */
2798         /* TODO Fix the TX Power Settings */
2799         /* TODO N PHY TX Power Control Idle TSSI */
2800         /* TODO N PHY TX Power Control Setup */
2801
2802         if (phy->rev >= 3) {
2803                 /* TODO */
2804         } else {
2805                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
2806                                         b43_ntab_tx_gain_rev0_1_2);
2807                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
2808                                         b43_ntab_tx_gain_rev0_1_2);
2809         }
2810
2811         if (nphy->phyrxchain != 3)
2812                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2813         if (nphy->mphase_cal_phase_id > 0)
2814                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2815
2816         do_rssi_cal = false;
2817         if (phy->rev >= 3) {
2818                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2819                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2820                 else
2821                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2822
2823                 if (do_rssi_cal)
2824                         b43_nphy_rssi_cal(dev);
2825                 else
2826                         b43_nphy_restore_rssi_cal(dev);
2827         } else {
2828                 b43_nphy_rssi_cal(dev);
2829         }
2830
2831         if (!((nphy->measure_hold & 0x6) != 0)) {
2832                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2833                         do_cal = (nphy->iqcal_chanspec_2G == 0);
2834                 else
2835                         do_cal = (nphy->iqcal_chanspec_5G == 0);
2836
2837                 if (nphy->mute)
2838                         do_cal = false;
2839
2840                 if (do_cal) {
2841                         target = b43_nphy_get_tx_gains(dev);
2842
2843                         if (nphy->antsel_type == 2)
2844                                 ;/*TODO NPHY Superswitch Init with argument 1*/
2845                         if (nphy->perical != 2) {
2846                                 b43_nphy_rssi_cal(dev);
2847                                 if (phy->rev >= 3) {
2848                                         nphy->cal_orig_pwr_idx[0] =
2849                                             nphy->txpwrindex[0].index_internal;
2850                                         nphy->cal_orig_pwr_idx[1] =
2851                                             nphy->txpwrindex[1].index_internal;
2852                                         /* TODO N PHY Pre Calibrate TX Gain */
2853                                         target = b43_nphy_get_tx_gains(dev);
2854                                 }
2855                         }
2856                 }
2857         }
2858
2859         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2860                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
2861                         ;/* Call N PHY Save Cal */
2862                 else if (nphy->mphase_cal_phase_id == 0)
2863                         ;/* N PHY Periodic Calibration with argument 3 */
2864         } else {
2865                 b43_nphy_restore_cal(dev);
2866         }
2867
2868         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
2869         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2870         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2871         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2872         if (phy->rev >= 3 && phy->rev <= 6)
2873                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
2874         b43_nphy_tx_lp_fbw(dev);
2875         /* TODO N PHY Spur Workaround */
2876
2877         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
2878         return 0;
2879 }
2880
2881 static int b43_nphy_op_allocate(struct b43_wldev *dev)
2882 {
2883         struct b43_phy_n *nphy;
2884
2885         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2886         if (!nphy)
2887                 return -ENOMEM;
2888         dev->phy.n = nphy;
2889
2890         return 0;
2891 }
2892
2893 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2894 {
2895         struct b43_phy *phy = &dev->phy;
2896         struct b43_phy_n *nphy = phy->n;
2897
2898         memset(nphy, 0, sizeof(*nphy));
2899
2900         //TODO init struct b43_phy_n
2901 }
2902
2903 static void b43_nphy_op_free(struct b43_wldev *dev)
2904 {
2905         struct b43_phy *phy = &dev->phy;
2906         struct b43_phy_n *nphy = phy->n;
2907
2908         kfree(nphy);
2909         phy->n = NULL;
2910 }
2911
2912 static int b43_nphy_op_init(struct b43_wldev *dev)
2913 {
2914         return b43_phy_initn(dev);
2915 }
2916
2917 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2918 {
2919 #if B43_DEBUG
2920         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2921                 /* OFDM registers are onnly available on A/G-PHYs */
2922                 b43err(dev->wl, "Invalid OFDM PHY access at "
2923                        "0x%04X on N-PHY\n", offset);
2924                 dump_stack();
2925         }
2926         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2927                 /* Ext-G registers are only available on G-PHYs */
2928                 b43err(dev->wl, "Invalid EXT-G PHY access at "
2929                        "0x%04X on N-PHY\n", offset);
2930                 dump_stack();
2931         }
2932 #endif /* B43_DEBUG */
2933 }
2934
2935 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2936 {
2937         check_phyreg(dev, reg);
2938         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2939         return b43_read16(dev, B43_MMIO_PHY_DATA);
2940 }
2941
2942 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2943 {
2944         check_phyreg(dev, reg);
2945         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2946         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2947 }
2948
2949 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2950 {
2951         /* Register 1 is a 32-bit register. */
2952         B43_WARN_ON(reg == 1);
2953         /* N-PHY needs 0x100 for read access */
2954         reg |= 0x100;
2955
2956         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2957         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2958 }
2959
2960 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2961 {
2962         /* Register 1 is a 32-bit register. */
2963         B43_WARN_ON(reg == 1);
2964
2965         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2966         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2967 }
2968
2969 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
2970                                         bool blocked)
2971 {//TODO
2972 }
2973
2974 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2975 {
2976         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2977                       on ? 0 : 0x7FFF);
2978 }
2979
2980 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2981                                       unsigned int new_channel)
2982 {
2983         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2984                 if ((new_channel < 1) || (new_channel > 14))
2985                         return -EINVAL;
2986         } else {
2987                 if (new_channel > 200)
2988                         return -EINVAL;
2989         }
2990
2991         return nphy_channel_switch(dev, new_channel);
2992 }
2993
2994 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2995 {
2996         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2997                 return 1;
2998         return 36;
2999 }
3000
3001 const struct b43_phy_operations b43_phyops_n = {
3002         .allocate               = b43_nphy_op_allocate,
3003         .free                   = b43_nphy_op_free,
3004         .prepare_structs        = b43_nphy_op_prepare_structs,
3005         .init                   = b43_nphy_op_init,
3006         .phy_read               = b43_nphy_op_read,
3007         .phy_write              = b43_nphy_op_write,
3008         .radio_read             = b43_nphy_op_radio_read,
3009         .radio_write            = b43_nphy_op_radio_write,
3010         .software_rfkill        = b43_nphy_op_software_rfkill,
3011         .switch_analog          = b43_nphy_op_switch_analog,
3012         .switch_channel         = b43_nphy_op_switch_channel,
3013         .get_default_chan       = b43_nphy_op_get_default_chan,
3014         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3015         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3016 };