SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 enum b43_nphy_rf_sequence {
  59         B43_RFSEQ_RX2TX,
  60         B43_RFSEQ_TX2RX,
  61         B43_RFSEQ_RESET2RX,
  62         B43_RFSEQ_UPDATE_GAINH,
  63         B43_RFSEQ_UPDATE_GAINL,
  64         B43_RFSEQ_UPDATE_GAINU,
  65 };
  66
  67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
  68                                         u8 *events, u8 *delays, u8 length);
  69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
  70                                        enum b43_nphy_rf_sequence seq);
  71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
  72                                                 u16 value, u8 core, bool off);
  73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
  74                                                 u16 value, u8 core);
  75
  76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  77 {//TODO
  78 }
  79
  80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  81 {//TODO
  82 }
  83
  84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  85                                                         bool ignore_tssi)
  86 {//TODO
  87         return B43_TXPWR_RES_DONE;
  88 }
  89
  90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  91                                      const struct b43_nphy_channeltab_entry *e)
  92 {
  93         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
  94         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  95         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  96         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  97         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
  98
  99         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
 100         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
 101         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
 102         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
 103         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 104
 105         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
 106         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
 107         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
 108         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
 109         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 110
 111         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
 112         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
 113         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
 114         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
 115         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 116
 117         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
 118         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
 119         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
 120         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
 121         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
 122
 123         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
 124         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 125 }
 126
 127 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 128                                    const struct b43_nphy_channeltab_entry *e)
 129 {
 130         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 131         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 132         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 133         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 134         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 135         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 136 }
 137
 138 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 139 {
 140         //TODO
 141 }
 142
 143 /* Tune the hardware to a new channel. */
 144 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 145 {
 146         const struct b43_nphy_channeltab_entry *tabent;
 147
 148         tabent = b43_nphy_get_chantabent(dev, channel);
 149         if (!tabent)
 150                 return -ESRCH;
 151
 152         //FIXME enable/disable band select upper20 in RXCTL
 153         if (0 /*FIXME 5Ghz*/)
 154                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 155         else
 156                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 157         b43_chantab_radio_upload(dev, tabent);
 158         udelay(50);
 159         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 160         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 161         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 162         udelay(300);
 163         if (0 /*FIXME 5Ghz*/)
 164                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 165         else
 166                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 167         b43_chantab_phy_upload(dev, tabent);
 168         b43_nphy_tx_power_fix(dev);
 169
 170         return 0;
 171 }
 172
 173 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 174 {
 175         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 176                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 177         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 178                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 179                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 180         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 181                     B43_NPHY_RFCTL_CMD_PORFORCE);
 182 }
 183
 184 static void b43_radio_init2055_post(struct b43_wldev *dev)
 185 {
 186         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 187         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 188         int i;
 189         u16 val;
 190
 191         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 192         msleep(1);
 193         if ((sprom->revision != 4) ||
 194            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 195                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 196                     (binfo->type != 0x46D) ||
 197                     (binfo->rev < 0x41)) {
 198                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 199                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 200                         msleep(1);
 201                 }
 202         }
 203         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 204         msleep(1);
 205         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 206         msleep(1);
 207         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 208         msleep(1);
 209         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 210         msleep(1);
 211         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 212         msleep(1);
 213         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 214         msleep(1);
 215         for (i = 0; i < 100; i++) {
 216                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 217                 if (val & 0x80)
 218                         break;
 219                 udelay(10);
 220         }
 221         msleep(1);
 222         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 223         msleep(1);
 224         nphy_channel_switch(dev, dev->phy.channel);
 225         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 226         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 227         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 228         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 229 }
 230
 231 /*
 232  * Initialize a Broadcom 2055 N-radio
 233  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
 234  */
 235 static void b43_radio_init2055(struct b43_wldev *dev)
 236 {
 237         b43_radio_init2055_pre(dev);
 238         if (b43_status(dev) < B43_STAT_INITIALIZED)
 239                 b2055_upload_inittab(dev, 0, 1);
 240         else
 241                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 242         b43_radio_init2055_post(dev);
 243 }
 244
 245 /*
 246  * Upload the N-PHY tables.
 247  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 248  */
 249 static void b43_nphy_tables_init(struct b43_wldev *dev)
 250 {
 251         if (dev->phy.rev < 3)
 252                 b43_nphy_rev0_1_2_tables_init(dev);
 253         else
 254                 b43_nphy_rev3plus_tables_init(dev);
 255 }
 256
 257 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 258 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 259 {
 260         struct b43_phy_n *nphy = dev->phy.n;
 261         enum ieee80211_band band;
 262         u16 tmp;
 263
 264         if (!enable) {
 265                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 266                                                        B43_NPHY_RFCTL_INTC1);
 267                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 268                                                        B43_NPHY_RFCTL_INTC2);
 269                 band = b43_current_band(dev->wl);
 270                 if (dev->phy.rev >= 3) {
 271                         if (band == IEEE80211_BAND_5GHZ)
 272                                 tmp = 0x600;
 273                         else
 274                                 tmp = 0x480;
 275                 } else {
 276                         if (band == IEEE80211_BAND_5GHZ)
 277                                 tmp = 0x180;
 278                         else
 279                                 tmp = 0x120;
 280                 }
 281                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 282                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 283         } else {
 284                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 285                                 nphy->rfctrl_intc1_save);
 286                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 287                                 nphy->rfctrl_intc2_save);
 288         }
 289 }
 290
 291 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 292 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 293 {
 294         struct b43_phy_n *nphy = dev->phy.n;
 295         u16 tmp;
 296         enum ieee80211_band band = b43_current_band(dev->wl);
 297         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 298                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 299
 300         if (dev->phy.rev >= 3) {
 301                 if (ipa) {
 302                         tmp = 4;
 303                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 304                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 305                 }
 306
 307                 tmp = 1;
 308                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 309                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 310         }
 311 }
 312
 313 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 314 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 315 {
 316         u32 tmslow;
 317
 318         if (dev->phy.type != B43_PHYTYPE_N)
 319                 return;
 320
 321         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 322         if (force)
 323                 tmslow |= SSB_TMSLOW_FGC;
 324         else
 325                 tmslow &= ~SSB_TMSLOW_FGC;
 326         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 327 }
 328
 329 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 330 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 331 {
 332         u16 bbcfg;
 333
 334         b43_nphy_bmac_clock_fgc(dev, 1);
 335         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 336         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 337         udelay(1);
 338         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 339         b43_nphy_bmac_clock_fgc(dev, 0);
 340         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 341 }
 342
 343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 344 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 345 {
 346         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 347
 348         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 349         if (preamble == 1)
 350                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 351         else
 352                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 353
 354         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 355 }
 356
 357 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 358 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 359 {
 360         struct b43_phy_n *nphy = dev->phy.n;
 361
 362         bool override = false;
 363         u16 chain = 0x33;
 364
 365         if (nphy->txrx_chain == 0) {
 366                 chain = 0x11;
 367                 override = true;
 368         } else if (nphy->txrx_chain == 1) {
 369                 chain = 0x22;
 370                 override = true;
 371         }
 372
 373         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 374                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 375                         chain);
 376
 377         if (override)
 378                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 379                                 B43_NPHY_RFSEQMODE_CAOVER);
 380         else
 381                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 382                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 383 }
 384
 385 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 386 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 387                                 u16 samps, u8 time, bool wait)
 388 {
 389         int i;
 390         u16 tmp;
 391
 392         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 393         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 394         if (wait)
 395                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 396         else
 397                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 398
 399         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 400
 401         for (i = 1000; i; i--) {
 402                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 403                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 404                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 405                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 406                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 407                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 408                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 409                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 410
 411                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 412                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 413                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 414                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 415                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 416                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 417                         return;
 418                 }
 419                 udelay(10);
 420         }
 421         memset(est, 0, sizeof(*est));
 422 }
 423
 424 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 425 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 426                                         struct b43_phy_n_iq_comp *pcomp)
 427 {
 428         if (write) {
 429                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 430                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 431                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 432                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 433         } else {
 434                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 435                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 436                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 437                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 438         }
 439 }
 440
 441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 442 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 443 {
 444         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 445
 446         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 447         if (core == 0) {
 448                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 449                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 450         } else {
 451                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 452                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 453         }
 454         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 455         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 456         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 457         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 458         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 459         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 460         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 461         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 462 }
 463
 464 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 465 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 466 {
 467         u8 rxval, txval;
 468         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 469
 470         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 471         if (core == 0) {
 472                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 473                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 474         } else {
 475                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 476                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 477         }
 478         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 479         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 480         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 481         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 482         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 483         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 484         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 485         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 486
 487         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 488         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 489
 490         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 491                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 492         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 493                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 494         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 495                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 496         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 497                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 498
 499         if (core == 0) {
 500                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 501                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 502         } else {
 503                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 504                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 505         }
 506
 507         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
 508         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
 509         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 510
 511         if (core == 0) {
 512                 rxval = 1;
 513                 txval = 8;
 514         } else {
 515                 rxval = 4;
 516                 txval = 2;
 517         }
 518         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
 519         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 520 }
 521
 522 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 523 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 524 {
 525         int i;
 526         s32 iq;
 527         u32 ii;
 528         u32 qq;
 529         int iq_nbits, qq_nbits;
 530         int arsh, brsh;
 531         u16 tmp, a, b;
 532
 533         struct nphy_iq_est est;
 534         struct b43_phy_n_iq_comp old;
 535         struct b43_phy_n_iq_comp new = { };
 536         bool error = false;
 537
 538         if (mask == 0)
 539                 return;
 540
 541         b43_nphy_rx_iq_coeffs(dev, false, &old);
 542         b43_nphy_rx_iq_coeffs(dev, true, &new);
 543         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 544         new = old;
 545
 546         for (i = 0; i < 2; i++) {
 547                 if (i == 0 && (mask & 1)) {
 548                         iq = est.iq0_prod;
 549                         ii = est.i0_pwr;
 550                         qq = est.q0_pwr;
 551                 } else if (i == 1 && (mask & 2)) {
 552                         iq = est.iq1_prod;
 553                         ii = est.i1_pwr;
 554                         qq = est.q1_pwr;
 555                 } else {
 556                         B43_WARN_ON(1);
 557                         continue;
 558                 }
 559
 560                 if (ii + qq < 2) {
 561                         error = true;
 562                         break;
 563                 }
 564
 565                 iq_nbits = fls(abs(iq));
 566                 qq_nbits = fls(qq);
 567
 568                 arsh = iq_nbits - 20;
 569                 if (arsh >= 0) {
 570                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 571                         tmp = ii >> arsh;
 572                 } else {
 573                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 574                         tmp = ii << -arsh;
 575                 }
 576                 if (tmp == 0) {
 577                         error = true;
 578                         break;
 579                 }
 580                 a /= tmp;
 581
 582                 brsh = qq_nbits - 11;
 583                 if (brsh >= 0) {
 584                         b = (qq << (31 - qq_nbits));
 585                         tmp = ii >> brsh;
 586                 } else {
 587                         b = (qq << (31 - qq_nbits));
 588                         tmp = ii << -brsh;
 589                 }
 590                 if (tmp == 0) {
 591                         error = true;
 592                         break;
 593                 }
 594                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 595
 596                 if (i == 0 && (mask & 0x1)) {
 597                         if (dev->phy.rev >= 3) {
 598                                 new.a0 = a & 0x3FF;
 599                                 new.b0 = b & 0x3FF;
 600                         } else {
 601                                 new.a0 = b & 0x3FF;
 602                                 new.b0 = a & 0x3FF;
 603                         }
 604                 } else if (i == 1 && (mask & 0x2)) {
 605                         if (dev->phy.rev >= 3) {
 606                                 new.a1 = a & 0x3FF;
 607                                 new.b1 = b & 0x3FF;
 608                         } else {
 609                                 new.a1 = b & 0x3FF;
 610                                 new.b1 = a & 0x3FF;
 611                         }
 612                 }
 613         }
 614
 615         if (error)
 616                 new = old;
 617
 618         b43_nphy_rx_iq_coeffs(dev, true, &new);
 619 }
 620
 621 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 622 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 623 {
 624         u16 array[4];
 625         int i;
 626
 627         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 628         for (i = 0; i < 4; i++)
 629                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 630
 631         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 632         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 633         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 634         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 635 }
 636
 637 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 638 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 639 {
 640         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 641         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 642 }
 643
 644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 645 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 646 {
 647         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 648         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 649 }
 650
 651 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
 652 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
 653 {
 654         if (dev->phy.rev >= 3) {
 655                 if (!init)
 656                         return;
 657                 if (0 /* FIXME */) {
 658                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
 659                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
 660                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
 661                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
 662                 }
 663         } else {
 664                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
 665                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
 666
 667                 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
 668                                         0xFC00);
 669                 b43_write32(dev, B43_MMIO_MACCTL,
 670                         b43_read32(dev, B43_MMIO_MACCTL) &
 671                         ~B43_MACCTL_GPOUTSMSK);
 672                 b43_write16(dev, B43_MMIO_GPIO_MASK,
 673                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
 674                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
 675                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
 676
 677                 if (init) {
 678                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 679                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 680                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 681                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 682                 }
 683         }
 684 }
 685
 686 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 687 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 688 {
 689         u16 tmp;
 690
 691         if (dev->dev->id.revision == 16)
 692                 b43_mac_suspend(dev);
 693
 694         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 695         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 696                 B43_NPHY_CLASSCTL_WAITEDEN);
 697         tmp &= ~mask;
 698         tmp |= (val & mask);
 699         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 700
 701         if (dev->dev->id.revision == 16)
 702                 b43_mac_enable(dev);
 703
 704         return tmp;
 705 }
 706
 707 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 708 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 709 {
 710         struct b43_phy *phy = &dev->phy;
 711         struct b43_phy_n *nphy = phy->n;
 712
 713         if (enable) {
 714                 u16 clip[] = { 0xFFFF, 0xFFFF };
 715                 if (nphy->deaf_count++ == 0) {
 716                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 717                         b43_nphy_classifier(dev, 0x7, 0);
 718                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 719                         b43_nphy_write_clip_detection(dev, clip);
 720                 }
 721                 b43_nphy_reset_cca(dev);
 722         } else {
 723                 if (--nphy->deaf_count == 0) {
 724                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 725                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 726                 }
 727         }
 728 }
 729
 730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 731 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 732 {
 733         struct b43_phy_n *nphy = dev->phy.n;
 734         u16 tmp;
 735
 736         if (nphy->hang_avoid)
 737                 b43_nphy_stay_in_carrier_search(dev, 1);
 738
 739         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 740         if (tmp & 0x1)
 741                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 742         else if (tmp & 0x2)
 743                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 744
 745         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 746
 747         if (nphy->bb_mult_save & 0x80000000) {
 748                 tmp = nphy->bb_mult_save & 0xFFFF;
 749                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
 750                 nphy->bb_mult_save = 0;
 751         }
 752
 753         if (nphy->hang_avoid)
 754                 b43_nphy_stay_in_carrier_search(dev, 0);
 755 }
 756
 757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
 758 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
 759 {
 760         struct b43_phy_n *nphy = dev->phy.n;
 761
 762         unsigned int channel;
 763         int tone[2] = { 57, 58 };
 764         u32 noise[2] = { 0x3FF, 0x3FF };
 765
 766         B43_WARN_ON(dev->phy.rev < 3);
 767
 768         if (nphy->hang_avoid)
 769                 b43_nphy_stay_in_carrier_search(dev, 1);
 770
 771         /* FIXME: channel = radio_chanspec */
 772
 773         if (nphy->gband_spurwar_en) {
 774                 /* TODO: N PHY Adjust Analog Pfbw (7) */
 775                 if (channel == 11 && dev->phy.is_40mhz)
 776                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
 777                 else
 778                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 779                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
 780         }
 781
 782         if (nphy->aband_spurwar_en) {
 783                 if (channel == 54) {
 784                         tone[0] = 0x20;
 785                         noise[0] = 0x25F;
 786                 } else if (channel == 38 || channel == 102 || channel == 118) {
 787                         if (0 /* FIXME */) {
 788                                 tone[0] = 0x20;
 789                                 noise[0] = 0x21F;
 790                         } else {
 791                                 tone[0] = 0;
 792                                 noise[0] = 0;
 793                         }
 794                 } else if (channel == 134) {
 795                         tone[0] = 0x20;
 796                         noise[0] = 0x21F;
 797                 } else if (channel == 151) {
 798                         tone[0] = 0x10;
 799                         noise[0] = 0x23F;
 800                 } else if (channel == 153 || channel == 161) {
 801                         tone[0] = 0x30;
 802                         noise[0] = 0x23F;
 803                 } else {
 804                         tone[0] = 0;
 805                         noise[0] = 0;
 806                 }
 807
 808                 if (!tone[0] && !noise[0])
 809                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
 810                 else
 811                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
 812         }
 813
 814         if (nphy->hang_avoid)
 815                 b43_nphy_stay_in_carrier_search(dev, 0);
 816 }
 817
 818 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
 819 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
 820 {
 821         struct b43_phy_n *nphy = dev->phy.n;
 822         u8 i, j;
 823         u8 code;
 824
 825         /* TODO: for PHY >= 3
 826         s8 *lna1_gain, *lna2_gain;
 827         u8 *gain_db, *gain_bits;
 828         u16 *rfseq_init;
 829         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
 830         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
 831         */
 832
 833         u8 rfseq_events[3] = { 6, 8, 7 };
 834         u8 rfseq_delays[3] = { 10, 30, 1 };
 835
 836         if (dev->phy.rev >= 3) {
 837                 /* TODO */
 838         } else {
 839                 /* Set Clip 2 detect */
 840                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 841                                 B43_NPHY_C1_CGAINI_CL2DETECT);
 842                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 843                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 844
 845                 /* Set narrowband clip threshold */
 846                 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
 847                 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 848
 849                 if (!dev->phy.is_40mhz) {
 850                         /* Set dwell lengths */
 851                         b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
 852                         b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
 853                         b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
 854                         b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
 855                 }
 856
 857                 /* Set wideband clip 2 threshold */
 858                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 859                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 860                                 21);
 861                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 862                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 863                                 21);
 864
 865                 if (!dev->phy.is_40mhz) {
 866                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 867                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
 868                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 869                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
 870                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
 871                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
 872                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
 873                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
 874                 }
 875
 876                 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 877
 878                 if (nphy->gain_boost) {
 879                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
 880                             dev->phy.is_40mhz)
 881                                 code = 4;
 882                         else
 883                                 code = 5;
 884                 } else {
 885                         code = dev->phy.is_40mhz ? 6 : 7;
 886                 }
 887
 888                 /* Set HPVGA2 index */
 889                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 890                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 891                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 892                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 893                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 894                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 895
 896                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 897                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 898                                         (code << 8 | 0x7C));
 899                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 900                                         (code << 8 | 0x7C));
 901
 902                 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
 903
 904                 if (nphy->elna_gain_config) {
 905                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
 906                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 907                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 908                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 909                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 910
 911                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
 912                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
 913                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 914                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 915                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 916
 917                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
 918                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 919                                         (code << 8 | 0x74));
 920                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 921                                         (code << 8 | 0x74));
 922                 }
 923
 924                 if (dev->phy.rev == 2) {
 925                         for (i = 0; i < 4; i++) {
 926                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 927                                                 (0x0400 * i) + 0x0020);
 928                                 for (j = 0; j < 21; j++)
 929                                         b43_phy_write(dev,
 930                                                 B43_NPHY_TABLE_DATALO, 3 * j);
 931                         }
 932
 933                         b43_nphy_set_rf_sequence(dev, 5,
 934                                         rfseq_events, rfseq_delays, 3);
 935                         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
 936                                 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
 937                                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
 938
 939                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 940                                 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
 941                                                 0xFF80, 4);
 942                 }
 943         }
 944 }
 945
 946 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
 947 static void b43_nphy_workarounds(struct b43_wldev *dev)
 948 {
 949         struct ssb_bus *bus = dev->dev->bus;
 950         struct b43_phy *phy = &dev->phy;
 951         struct b43_phy_n *nphy = phy->n;
 952
 953         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
 954         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
 955
 956         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
 957         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 958
 959         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 960                 b43_nphy_classifier(dev, 1, 0);
 961         else
 962                 b43_nphy_classifier(dev, 1, 1);
 963
 964         if (nphy->hang_avoid)
 965                 b43_nphy_stay_in_carrier_search(dev, 1);
 966
 967         b43_phy_set(dev, B43_NPHY_IQFLIP,
 968                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 969
 970         if (dev->phy.rev >= 3) {
 971                 /* TODO */
 972         } else {
 973                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
 974                     nphy->band5g_pwrgain) {
 975                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
 976                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
 977                 } else {
 978                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 979                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
 980                 }
 981
 982                 /* TODO: convert to b43_ntab_write? */
 983                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
 984                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 985                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
 986                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
 987                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
 988                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 989                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
 990                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
 991
 992                 if (dev->phy.rev < 2) {
 993                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
 994                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 995                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
 996                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
 997                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
 998                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
 999                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1000                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1001                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1002                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1003                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1004                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1005                 }
1006
1007                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1008                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1009                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1010                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1011
1012                 if (bus->sprom.boardflags2_lo & 0x100 &&
1013                     bus->boardinfo.type == 0x8B) {
1014                         delays1[0] = 0x1;
1015                         delays1[5] = 0x14;
1016                 }
1017                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1018                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1019
1020                 b43_nphy_gain_crtl_workarounds(dev);
1021
1022                 if (dev->phy.rev < 2) {
1023                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1024                                 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
1025                 } else if (dev->phy.rev == 2) {
1026                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1027                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1028                 }
1029
1030                 if (dev->phy.rev < 2)
1031                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1032                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1033
1034                 /* Set phase track alpha and beta */
1035                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1036                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1037                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1038                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1039                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1040                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1041
1042                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1043                                 (u16)~B43_NPHY_PIL_DW_64QAM);
1044                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1045                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1046                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1047
1048                 if (dev->phy.rev == 2)
1049                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1050                                         B43_NPHY_FINERX2_CGC_DECGC);
1051         }
1052
1053         if (nphy->hang_avoid)
1054                 b43_nphy_stay_in_carrier_search(dev, 0);
1055 }
1056
1057 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1058 static int b43_nphy_load_samples(struct b43_wldev *dev,
1059                                         struct b43_c32 *samples, u16 len) {
1060         struct b43_phy_n *nphy = dev->phy.n;
1061         u16 i;
1062         u32 *data;
1063
1064         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1065         if (!data) {
1066                 b43err(dev->wl, "allocation for samples loading failed\n");
1067                 return -ENOMEM;
1068         }
1069         if (nphy->hang_avoid)
1070                 b43_nphy_stay_in_carrier_search(dev, 1);
1071
1072         for (i = 0; i < len; i++) {
1073                 data[i] = (samples[i].i & 0x3FF << 10);
1074                 data[i] |= samples[i].q & 0x3FF;
1075         }
1076         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1077
1078         kfree(data);
1079         if (nphy->hang_avoid)
1080                 b43_nphy_stay_in_carrier_search(dev, 0);
1081         return 0;
1082 }
1083
1084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1085 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1086                                         bool test)
1087 {
1088         int i;
1089         u16 bw, len, rot, angle;
1090         struct b43_c32 *samples;
1091
1092
1093         bw = (dev->phy.is_40mhz) ? 40 : 20;
1094         len = bw << 3;
1095
1096         if (test) {
1097                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1098                         bw = 82;
1099                 else
1100                         bw = 80;
1101
1102                 if (dev->phy.is_40mhz)
1103                         bw <<= 1;
1104
1105                 len = bw << 1;
1106         }
1107
1108         samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
1109         if (!samples) {
1110                 b43err(dev->wl, "allocation for samples generation failed\n");
1111                 return 0;
1112         }
1113         rot = (((freq * 36) / bw) << 16) / 100;
1114         angle = 0;
1115
1116         for (i = 0; i < len; i++) {
1117                 samples[i] = b43_cordic(angle);
1118                 angle += rot;
1119                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1120                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1121         }
1122
1123         i = b43_nphy_load_samples(dev, samples, len);
1124         kfree(samples);
1125         return (i < 0) ? 0 : len;
1126 }
1127
1128 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1129 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1130                                         u16 wait, bool iqmode, bool dac_test)
1131 {
1132         struct b43_phy_n *nphy = dev->phy.n;
1133         int i;
1134         u16 seq_mode;
1135         u32 tmp;
1136
1137         if (nphy->hang_avoid)
1138                 b43_nphy_stay_in_carrier_search(dev, true);
1139
1140         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1141                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1142                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1143         }
1144
1145         if (!dev->phy.is_40mhz)
1146                 tmp = 0x6464;
1147         else
1148                 tmp = 0x4747;
1149         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1150
1151         if (nphy->hang_avoid)
1152                 b43_nphy_stay_in_carrier_search(dev, false);
1153
1154         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1155
1156         if (loops != 0xFFFF)
1157                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1158         else
1159                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1160
1161         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1162
1163         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1164
1165         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1166         if (iqmode) {
1167                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1168                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1169         } else {
1170                 if (dac_test)
1171                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1172                 else
1173                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1174         }
1175         for (i = 0; i < 100; i++) {
1176                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1177                         i = 0;
1178                         break;
1179                 }
1180                 udelay(10);
1181         }
1182         if (i)
1183                 b43err(dev->wl, "run samples timeout\n");
1184
1185         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1186 }
1187
1188 /*
1189  * Transmits a known value for LO calibration
1190  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1191  */
1192 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1193                                 bool iqmode, bool dac_test)
1194 {
1195         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1196         if (samp == 0)
1197                 return -1;
1198         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1199         return 0;
1200 }
1201
1202 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1203 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1204 {
1205         struct b43_phy_n *nphy = dev->phy.n;
1206         int i, j;
1207         u32 tmp;
1208         u32 cur_real, cur_imag, real_part, imag_part;
1209
1210         u16 buffer[7];
1211
1212         if (nphy->hang_avoid)
1213                 b43_nphy_stay_in_carrier_search(dev, true);
1214
1215         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1216
1217         for (i = 0; i < 2; i++) {
1218                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1219                         (buffer[i * 2 + 1] & 0x3FF);
1220                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1221                                 (((i + 26) << 10) | 320));
1222                 for (j = 0; j < 128; j++) {
1223                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1224                                         ((tmp >> 16) & 0xFFFF));
1225                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1226                                         (tmp & 0xFFFF));
1227                 }
1228         }
1229
1230         for (i = 0; i < 2; i++) {
1231                 tmp = buffer[5 + i];
1232                 real_part = (tmp >> 8) & 0xFF;
1233                 imag_part = (tmp & 0xFF);
1234                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1235                                 (((i + 26) << 10) | 448));
1236
1237                 if (dev->phy.rev >= 3) {
1238                         cur_real = real_part;
1239                         cur_imag = imag_part;
1240                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1241                 }
1242
1243                 for (j = 0; j < 128; j++) {
1244                         if (dev->phy.rev < 3) {
1245                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1246                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1247                                 tmp = ((cur_real & 0xFF) << 8) |
1248                                         (cur_imag & 0xFF);
1249                         }
1250                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1251                                         ((tmp >> 16) & 0xFFFF));
1252                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1253                                         (tmp & 0xFFFF));
1254                 }
1255         }
1256
1257         if (dev->phy.rev >= 3) {
1258                 b43_shm_write16(dev, B43_SHM_SHARED,
1259                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1260                 b43_shm_write16(dev, B43_SHM_SHARED,
1261                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1262         }
1263
1264         if (nphy->hang_avoid)
1265                 b43_nphy_stay_in_carrier_search(dev, false);
1266 }
1267
1268 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1269 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1270                                         u8 *events, u8 *delays, u8 length)
1271 {
1272         struct b43_phy_n *nphy = dev->phy.n;
1273         u8 i;
1274         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1275         u16 offset1 = cmd << 4;
1276         u16 offset2 = offset1 + 0x80;
1277
1278         if (nphy->hang_avoid)
1279                 b43_nphy_stay_in_carrier_search(dev, true);
1280
1281         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1282         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1283
1284         for (i = length; i < 16; i++) {
1285                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1286                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1287         }
1288
1289         if (nphy->hang_avoid)
1290                 b43_nphy_stay_in_carrier_search(dev, false);
1291 }
1292
1293 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1294 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1295                                        enum b43_nphy_rf_sequence seq)
1296 {
1297         static const u16 trigger[] = {
1298                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1299                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1300                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1301                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1302                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1303                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1304         };
1305         int i;
1306         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1307
1308         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1309
1310         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1311                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1312         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1313         for (i = 0; i < 200; i++) {
1314                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1315                         goto ok;
1316                 msleep(1);
1317         }
1318         b43err(dev->wl, "RF sequence status timeout\n");
1319 ok:
1320         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1321 }
1322
1323 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1324 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1325                                                 u16 value, u8 core, bool off)
1326 {
1327         int i;
1328         u8 index = fls(field);
1329         u8 addr, en_addr, val_addr;
1330         /* we expect only one bit set */
1331         B43_WARN_ON(field & (~(1 << (index - 1))));
1332
1333         if (dev->phy.rev >= 3) {
1334                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1335                 for (i = 0; i < 2; i++) {
1336                         if (index == 0 || index == 16) {
1337                                 b43err(dev->wl,
1338                                         "Unsupported RF Ctrl Override call\n");
1339                                 return;
1340                         }
1341
1342                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1343                         en_addr = B43_PHY_N((i == 0) ?
1344                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1345                         val_addr = B43_PHY_N((i == 0) ?
1346                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1347
1348                         if (off) {
1349                                 b43_phy_mask(dev, en_addr, ~(field));
1350                                 b43_phy_mask(dev, val_addr,
1351                                                 ~(rf_ctrl->val_mask));
1352                         } else {
1353                                 if (core == 0 || ((1 << core) & i) != 0) {
1354                                         b43_phy_set(dev, en_addr, field);
1355                                         b43_phy_maskset(dev, val_addr,
1356                                                 ~(rf_ctrl->val_mask),
1357                                                 (value << rf_ctrl->val_shift));
1358                                 }
1359                         }
1360                 }
1361         } else {
1362                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1363                 if (off) {
1364                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1365                         value = 0;
1366                 } else {
1367                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1368                 }
1369
1370                 for (i = 0; i < 2; i++) {
1371                         if (index <= 1 || index == 16) {
1372                                 b43err(dev->wl,
1373                                         "Unsupported RF Ctrl Override call\n");
1374                                 return;
1375                         }
1376
1377                         if (index == 2 || index == 10 ||
1378                             (index >= 13 && index <= 15)) {
1379                                 core = 1;
1380                         }
1381
1382                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1383                         addr = B43_PHY_N((i == 0) ?
1384                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1385
1386                         if ((core & (1 << i)) != 0)
1387                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1388                                                 (value << rf_ctrl->shift));
1389
1390                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1391                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1392                                         B43_NPHY_RFCTL_CMD_START);
1393                         udelay(1);
1394                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1395                 }
1396         }
1397 }
1398
1399 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1400 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1401                                                 u16 value, u8 core)
1402 {
1403         u8 i, j;
1404         u16 reg, tmp, val;
1405
1406         B43_WARN_ON(dev->phy.rev < 3);
1407         B43_WARN_ON(field > 4);
1408
1409         for (i = 0; i < 2; i++) {
1410                 if ((core == 1 && i == 1) || (core == 2 && !i))
1411                         continue;
1412
1413                 reg = (i == 0) ?
1414                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1415                 b43_phy_mask(dev, reg, 0xFBFF);
1416
1417                 switch (field) {
1418                 case 0:
1419                         b43_phy_write(dev, reg, 0);
1420                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1421                         break;
1422                 case 1:
1423                         if (!i) {
1424                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1425                                                 0xFC3F, (value << 6));
1426                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1427                                                 0xFFFE, 1);
1428                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1429                                                 B43_NPHY_RFCTL_CMD_START);
1430                                 for (j = 0; j < 100; j++) {
1431                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1432                                                 j = 0;
1433                                                 break;
1434                                         }
1435                                         udelay(10);
1436                                 }
1437                                 if (j)
1438                                         b43err(dev->wl,
1439                                                 "intc override timeout\n");
1440                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1441                                                 0xFFFE);
1442                         } else {
1443                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1444                                                 0xFC3F, (value << 6));
1445                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1446                                                 0xFFFE, 1);
1447                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1448                                                 B43_NPHY_RFCTL_CMD_RXTX);
1449                                 for (j = 0; j < 100; j++) {
1450                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1451                                                 j = 0;
1452                                                 break;
1453                                         }
1454                                         udelay(10);
1455                                 }
1456                                 if (j)
1457                                         b43err(dev->wl,
1458                                                 "intc override timeout\n");
1459                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1460                                                 0xFFFE);
1461                         }
1462                         break;
1463                 case 2:
1464                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1465                                 tmp = 0x0020;
1466                                 val = value << 5;
1467                         } else {
1468                                 tmp = 0x0010;
1469                                 val = value << 4;
1470                         }
1471                         b43_phy_maskset(dev, reg, ~tmp, val);
1472                         break;
1473                 case 3:
1474                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1475                                 tmp = 0x0001;
1476                                 val = value;
1477                         } else {
1478                                 tmp = 0x0004;
1479                                 val = value << 2;
1480                         }
1481                         b43_phy_maskset(dev, reg, ~tmp, val);
1482                         break;
1483                 case 4:
1484                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1485                                 tmp = 0x0002;
1486                                 val = value << 1;
1487                         } else {
1488                                 tmp = 0x0008;
1489                                 val = value << 3;
1490                         }
1491                         b43_phy_maskset(dev, reg, ~tmp, val);
1492                         break;
1493                 }
1494         }
1495 }
1496
1497 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1498 {
1499         unsigned int i;
1500         u16 val;
1501
1502         val = 0x1E1F;
1503         for (i = 0; i < 14; i++) {
1504                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1505                 val -= 0x202;
1506         }
1507         val = 0x3E3F;
1508         for (i = 0; i < 16; i++) {
1509                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1510                 val -= 0x202;
1511         }
1512         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1513 }
1514
1515 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1516 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1517                                        s8 offset, u8 core, u8 rail, u8 type)
1518 {
1519         u16 tmp;
1520         bool core1or5 = (core == 1) || (core == 5);
1521         bool core2or5 = (core == 2) || (core == 5);
1522
1523         offset = clamp_val(offset, -32, 31);
1524         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1525
1526         if (core1or5 && (rail == 0) && (type == 2))
1527                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1528         if (core1or5 && (rail == 1) && (type == 2))
1529                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1530         if (core2or5 && (rail == 0) && (type == 2))
1531                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1532         if (core2or5 && (rail == 1) && (type == 2))
1533                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1534         if (core1or5 && (rail == 0) && (type == 0))
1535                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1536         if (core1or5 && (rail == 1) && (type == 0))
1537                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1538         if (core2or5 && (rail == 0) && (type == 0))
1539                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1540         if (core2or5 && (rail == 1) && (type == 0))
1541                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1542         if (core1or5 && (rail == 0) && (type == 1))
1543                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1544         if (core1or5 && (rail == 1) && (type == 1))
1545                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1546         if (core2or5 && (rail == 0) && (type == 1))
1547                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1548         if (core2or5 && (rail == 1) && (type == 1))
1549                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1550         if (core1or5 && (rail == 0) && (type == 6))
1551                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1552         if (core1or5 && (rail == 1) && (type == 6))
1553                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1554         if (core2or5 && (rail == 0) && (type == 6))
1555                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1556         if (core2or5 && (rail == 1) && (type == 6))
1557                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1558         if (core1or5 && (rail == 0) && (type == 3))
1559                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1560         if (core1or5 && (rail == 1) && (type == 3))
1561                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1562         if (core2or5 && (rail == 0) && (type == 3))
1563                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1564         if (core2or5 && (rail == 1) && (type == 3))
1565                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1566         if (core1or5 && (type == 4))
1567                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1568         if (core2or5 && (type == 4))
1569                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1570         if (core1or5 && (type == 5))
1571                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1572         if (core2or5 && (type == 5))
1573                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1574 }
1575
1576 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1577 {
1578         u16 val;
1579
1580         if (type < 3)
1581                 val = 0;
1582         else if (type == 6)
1583                 val = 1;
1584         else if (type == 3)
1585                 val = 2;
1586         else
1587                 val = 3;
1588
1589         val = (val << 12) | (val << 14);
1590         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1591         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1592
1593         if (type < 3) {
1594                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1595                                 (type + 1) << 4);
1596                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1597                                 (type + 1) << 4);
1598         }
1599
1600         /* TODO use some definitions */
1601         if (code == 0) {
1602                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1603                 if (type < 3) {
1604                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1605                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1606                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1607                         udelay(20);
1608                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1609                 }
1610         } else {
1611                 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1612                                 0x3000);
1613                 if (type < 3) {
1614                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1615                                         0xFEC7, 0x0180);
1616                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1617                                         0xEFDC, (code << 1 | 0x1021));
1618                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1619                         udelay(20);
1620                         b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1621                 }
1622         }
1623 }
1624
1625 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1626 {
1627         struct b43_phy_n *nphy = dev->phy.n;
1628         u8 i;
1629         u16 reg, val;
1630
1631         if (code == 0) {
1632                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1633                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1634                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1635                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1636                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1637                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1638                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1639                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1640         } else {
1641                 for (i = 0; i < 2; i++) {
1642                         if ((code == 1 && i == 1) || (code == 2 && !i))
1643                                 continue;
1644
1645                         reg = (i == 0) ?
1646                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1647                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1648
1649                         if (type < 3) {
1650                                 reg = (i == 0) ?
1651                                         B43_NPHY_AFECTL_C1 :
1652                                         B43_NPHY_AFECTL_C2;
1653                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1654
1655                                 reg = (i == 0) ?
1656                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1657                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1658                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1659
1660                                 if (type == 0)
1661                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1662                                 else if (type == 1)
1663                                         val = 16;
1664                                 else
1665                                         val = 32;
1666                                 b43_phy_set(dev, reg, val);
1667
1668                                 reg = (i == 0) ?
1669                                         B43_NPHY_TXF_40CO_B1S0 :
1670                                         B43_NPHY_TXF_40CO_B32S1;
1671                                 b43_phy_set(dev, reg, 0x0020);
1672                         } else {
1673                                 if (type == 6)
1674                                         val = 0x0100;
1675                                 else if (type == 3)
1676                                         val = 0x0200;
1677                                 else
1678                                         val = 0x0300;
1679
1680                                 reg = (i == 0) ?
1681                                         B43_NPHY_AFECTL_C1 :
1682                                         B43_NPHY_AFECTL_C2;
1683
1684                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1685                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1686
1687                                 if (type != 3 && type != 6) {
1688                                         enum ieee80211_band band =
1689                                                 b43_current_band(dev->wl);
1690
1691                                         if ((nphy->ipa2g_on &&
1692                                                 band == IEEE80211_BAND_2GHZ) ||
1693                                                 (nphy->ipa5g_on &&
1694                                                 band == IEEE80211_BAND_5GHZ))
1695                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1696                                         else
1697                                                 val = 0x11;
1698                                         reg = (i == 0) ? 0x2000 : 0x3000;
1699                                         reg |= B2055_PADDRV;
1700                                         b43_radio_write16(dev, reg, val);
1701
1702                                         reg = (i == 0) ?
1703                                                 B43_NPHY_AFECTL_OVER1 :
1704                                                 B43_NPHY_AFECTL_OVER;
1705                                         b43_phy_set(dev, reg, 0x0200);
1706                                 }
1707                         }
1708                 }
1709         }
1710 }
1711
1712 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1713 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1714 {
1715         if (dev->phy.rev >= 3)
1716                 b43_nphy_rev3_rssi_select(dev, code, type);
1717         else
1718                 b43_nphy_rev2_rssi_select(dev, code, type);
1719 }
1720
1721 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1722 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1723 {
1724         int i;
1725         for (i = 0; i < 2; i++) {
1726                 if (type == 2) {
1727                         if (i == 0) {
1728                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1729                                                   0xFC, buf[0]);
1730                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1731                                                   0xFC, buf[1]);
1732                         } else {
1733                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1734                                                   0xFC, buf[2 * i]);
1735                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1736                                                   0xFC, buf[2 * i + 1]);
1737                         }
1738                 } else {
1739                         if (i == 0)
1740                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1741                                                   0xF3, buf[0] << 2);
1742                         else
1743                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1744                                                   0xF3, buf[2 * i + 1] << 2);
1745                 }
1746         }
1747 }
1748
1749 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1750 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1751                                 u8 nsamp)
1752 {
1753         int i;
1754         int out;
1755         u16 save_regs_phy[9];
1756         u16 s[2];
1757
1758         if (dev->phy.rev >= 3) {
1759                 save_regs_phy[0] = b43_phy_read(dev,
1760                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1761                 save_regs_phy[1] = b43_phy_read(dev,
1762                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1763                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1764                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1765                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1766                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1767                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1768                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1769         }
1770
1771         b43_nphy_rssi_select(dev, 5, type);
1772
1773         if (dev->phy.rev < 2) {
1774                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1775                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1776         }
1777
1778         for (i = 0; i < 4; i++)
1779                 buf[i] = 0;
1780
1781         for (i = 0; i < nsamp; i++) {
1782                 if (dev->phy.rev < 2) {
1783                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1784                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1785                 } else {
1786                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1787                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1788                 }
1789
1790                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1791                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1792                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1793                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1794         }
1795         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1796                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1797
1798         if (dev->phy.rev < 2)
1799                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1800
1801         if (dev->phy.rev >= 3) {
1802                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1803                                 save_regs_phy[0]);
1804                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1805                                 save_regs_phy[1]);
1806                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1807                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1808                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1809                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1810                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1811                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1812         }
1813
1814         return out;
1815 }
1816
1817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1818 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1819 {
1820         int i, j;
1821         u8 state[4];
1822         u8 code, val;
1823         u16 class, override;
1824         u8 regs_save_radio[2];
1825         u16 regs_save_phy[2];
1826         s8 offset[4];
1827
1828         u16 clip_state[2];
1829         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1830         s32 results_min[4] = { };
1831         u8 vcm_final[4] = { };
1832         s32 results[4][4] = { };
1833         s32 miniq[4][2] = { };
1834
1835         if (type == 2) {
1836                 code = 0;
1837                 val = 6;
1838         } else if (type < 2) {
1839                 code = 25;
1840                 val = 4;
1841         } else {
1842                 B43_WARN_ON(1);
1843                 return;
1844         }
1845
1846         class = b43_nphy_classifier(dev, 0, 0);
1847         b43_nphy_classifier(dev, 7, 4);
1848         b43_nphy_read_clip_detection(dev, clip_state);
1849         b43_nphy_write_clip_detection(dev, clip_off);
1850
1851         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1852                 override = 0x140;
1853         else
1854                 override = 0x110;
1855
1856         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1857         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1858         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1859         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1860
1861         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1862         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1863         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1864         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1865
1866         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1867         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1868         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1869         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1870         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1871         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1872
1873         b43_nphy_rssi_select(dev, 5, type);
1874         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1875         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1876
1877         for (i = 0; i < 4; i++) {
1878                 u8 tmp[4];
1879                 for (j = 0; j < 4; j++)
1880                         tmp[j] = i;
1881                 if (type != 1)
1882                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1883                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1884                 if (type < 2)
1885                         for (j = 0; j < 2; j++)
1886                                 miniq[i][j] = min(results[i][2 * j],
1887                                                 results[i][2 * j + 1]);
1888         }
1889
1890         for (i = 0; i < 4; i++) {
1891                 s32 mind = 40;
1892                 u8 minvcm = 0;
1893                 s32 minpoll = 249;
1894                 s32 curr;
1895                 for (j = 0; j < 4; j++) {
1896                         if (type == 2)
1897                                 curr = abs(results[j][i]);
1898                         else
1899                                 curr = abs(miniq[j][i / 2] - code * 8);
1900
1901                         if (curr < mind) {
1902                                 mind = curr;
1903                                 minvcm = j;
1904                         }
1905
1906                         if (results[j][i] < minpoll)
1907                                 minpoll = results[j][i];
1908                 }
1909                 results_min[i] = minpoll;
1910                 vcm_final[i] = minvcm;
1911         }
1912
1913         if (type != 1)
1914                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1915
1916         for (i = 0; i < 4; i++) {
1917                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1918
1919                 if (offset[i] < 0)
1920                         offset[i] = -((abs(offset[i]) + 4) / 8);
1921                 else
1922                         offset[i] = (offset[i] + 4) / 8;
1923
1924                 if (results_min[i] == 248)
1925                         offset[i] = code - 32;
1926
1927                 if (i % 2 == 0)
1928                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1929                                                         type);
1930                 else
1931                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1932                                                         type);
1933         }
1934
1935         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1936         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1937
1938         switch (state[2]) {
1939         case 1:
1940                 b43_nphy_rssi_select(dev, 1, 2);
1941                 break;
1942         case 4:
1943                 b43_nphy_rssi_select(dev, 1, 0);
1944                 break;
1945         case 2:
1946                 b43_nphy_rssi_select(dev, 1, 1);
1947                 break;
1948         default:
1949                 b43_nphy_rssi_select(dev, 1, 1);
1950                 break;
1951         }
1952
1953         switch (state[3]) {
1954         case 1:
1955                 b43_nphy_rssi_select(dev, 2, 2);
1956                 break;
1957         case 4:
1958                 b43_nphy_rssi_select(dev, 2, 0);
1959                 break;
1960         default:
1961                 b43_nphy_rssi_select(dev, 2, 1);
1962                 break;
1963         }
1964
1965         b43_nphy_rssi_select(dev, 0, type);
1966
1967         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1968         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1969         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1970         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1971
1972         b43_nphy_classifier(dev, 7, class);
1973         b43_nphy_write_clip_detection(dev, clip_state);
1974 }
1975
1976 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1977 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1978 {
1979         /* TODO */
1980 }
1981
1982 /*
1983  * RSSI Calibration
1984  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1985  */
1986 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1987 {
1988         if (dev->phy.rev >= 3) {
1989                 b43_nphy_rev3_rssi_cal(dev);
1990         } else {
1991                 b43_nphy_rev2_rssi_cal(dev, 2);
1992                 b43_nphy_rev2_rssi_cal(dev, 0);
1993                 b43_nphy_rev2_rssi_cal(dev, 1);
1994         }
1995 }
1996
1997 /*
1998  * Restore RSSI Calibration
1999  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2000  */
2001 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2002 {
2003         struct b43_phy_n *nphy = dev->phy.n;
2004
2005         u16 *rssical_radio_regs = NULL;
2006         u16 *rssical_phy_regs = NULL;
2007
2008         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2009                 if (!nphy->rssical_chanspec_2G)
2010                         return;
2011                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2012                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2013         } else {
2014                 if (!nphy->rssical_chanspec_5G)
2015                         return;
2016                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2017                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2018         }
2019
2020         /* TODO use some definitions */
2021         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2022         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2023
2024         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2025         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2026         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2027         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2028
2029         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2030         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2031         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2032         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2033
2034         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2035         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2036         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2037         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2038 }
2039
2040 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2041 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2042 {
2043         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2044                 if (dev->phy.rev >= 6) {
2045                         /* TODO If the chip is 47162
2046                                 return txpwrctrl_tx_gain_ipa_rev5 */
2047                         return txpwrctrl_tx_gain_ipa_rev6;
2048                 } else if (dev->phy.rev >= 5) {
2049                         return txpwrctrl_tx_gain_ipa_rev5;
2050                 } else {
2051                         return txpwrctrl_tx_gain_ipa;
2052                 }
2053         } else {
2054                 return txpwrctrl_tx_gain_ipa_5g;
2055         }
2056 }
2057
2058 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2059 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2060 {
2061         struct b43_phy_n *nphy = dev->phy.n;
2062         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2063         u16 tmp;
2064         u8 offset, i;
2065
2066         if (dev->phy.rev >= 3) {
2067             for (i = 0; i < 2; i++) {
2068                 tmp = (i == 0) ? 0x2000 : 0x3000;
2069                 offset = i * 11;
2070
2071                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2072                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2073                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2074                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2075                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2076                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2077                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2078                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2079                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2080                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2081                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2082
2083                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2084                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2085                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2086                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2087                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2088                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2089                         if (nphy->ipa5g_on) {
2090                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2091                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2092                         } else {
2093                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2094                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2095                         }
2096                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2097                 } else {
2098                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2099                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2100                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2101                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2102                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2103                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2104                         if (nphy->ipa2g_on) {
2105                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2106                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2107                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2108                         } else {
2109                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2110                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2111                         }
2112                 }
2113                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2114                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2115                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2116             }
2117         } else {
2118                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2119                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2120
2121                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2122                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2123
2124                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2125                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2126
2127                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2128                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2129
2130                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2131                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2132
2133                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2134                     B43_NPHY_BANDCTL_5GHZ)) {
2135                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2136                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2137                 } else {
2138                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2139                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2140                 }
2141
2142                 if (dev->phy.rev < 2) {
2143                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2144                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2145                 } else {
2146                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2147                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2148                 }
2149         }
2150 }
2151
2152 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2153 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2154                                         struct nphy_txgains target,
2155                                         struct nphy_iqcal_params *params)
2156 {
2157         int i, j, indx;
2158         u16 gain;
2159
2160         if (dev->phy.rev >= 3) {
2161                 params->txgm = target.txgm[core];
2162                 params->pga = target.pga[core];
2163                 params->pad = target.pad[core];
2164                 params->ipa = target.ipa[core];
2165                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2166                                         (params->pad << 4) | (params->ipa);
2167                 for (j = 0; j < 5; j++)
2168                         params->ncorr[j] = 0x79;
2169         } else {
2170                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2171                         (target.txgm[core] << 8);
2172
2173                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2174                         1 : 0;
2175                 for (i = 0; i < 9; i++)
2176                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2177                                 break;
2178                 i = min(i, 8);
2179
2180                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2181                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2182                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2183                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2184                                         (params->pad << 2);
2185                 for (j = 0; j < 4; j++)
2186                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2187         }
2188 }
2189
2190 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2191 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2192 {
2193         struct b43_phy_n *nphy = dev->phy.n;
2194         int i;
2195         u16 scale, entry;
2196
2197         u16 tmp = nphy->txcal_bbmult;
2198         if (core == 0)
2199                 tmp >>= 8;
2200         tmp &= 0xff;
2201
2202         for (i = 0; i < 18; i++) {
2203                 scale = (ladder_lo[i].percent * tmp) / 100;
2204                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2205                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2206
2207                 scale = (ladder_iq[i].percent * tmp) / 100;
2208                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2209                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2210         }
2211 }
2212
2213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2214 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2215 {
2216         int i;
2217         for (i = 0; i < 15; i++)
2218                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2219                                 tbl_tx_filter_coef_rev4[2][i]);
2220 }
2221
2222 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2223 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2224 {
2225         int i, j;
2226         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2227         u16 offset[] = { 0x186, 0x195, 0x2C5 };
2228
2229         for (i = 0; i < 3; i++)
2230                 for (j = 0; j < 15; j++)
2231                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2232                                         tbl_tx_filter_coef_rev4[i][j]);
2233
2234         if (dev->phy.is_40mhz) {
2235                 for (j = 0; j < 15; j++)
2236                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2237                                         tbl_tx_filter_coef_rev4[3][j]);
2238         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2239                 for (j = 0; j < 15; j++)
2240                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2241                                         tbl_tx_filter_coef_rev4[5][j]);
2242         }
2243
2244         if (dev->phy.channel == 14)
2245                 for (j = 0; j < 15; j++)
2246                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2247                                         tbl_tx_filter_coef_rev4[6][j]);
2248 }
2249
2250 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2251 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2252 {
2253         struct b43_phy_n *nphy = dev->phy.n;
2254
2255         u16 curr_gain[2];
2256         struct nphy_txgains target;
2257         const u32 *table = NULL;
2258
2259         if (nphy->txpwrctrl == 0) {
2260                 int i;
2261
2262                 if (nphy->hang_avoid)
2263                         b43_nphy_stay_in_carrier_search(dev, true);
2264                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2265                 if (nphy->hang_avoid)
2266                         b43_nphy_stay_in_carrier_search(dev, false);
2267
2268                 for (i = 0; i < 2; ++i) {
2269                         if (dev->phy.rev >= 3) {
2270                                 target.ipa[i] = curr_gain[i] & 0x000F;
2271                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2272                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2273                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2274                         } else {
2275                                 target.ipa[i] = curr_gain[i] & 0x0003;
2276                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2277                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2278                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2279                         }
2280                 }
2281         } else {
2282                 int i;
2283                 u16 index[2];
2284                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2285                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2286                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2287                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2288                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2289                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2290
2291                 for (i = 0; i < 2; ++i) {
2292                         if (dev->phy.rev >= 3) {
2293                                 enum ieee80211_band band =
2294                                         b43_current_band(dev->wl);
2295
2296                                 if ((nphy->ipa2g_on &&
2297                                      band == IEEE80211_BAND_2GHZ) ||
2298                                     (nphy->ipa5g_on &&
2299                                      band == IEEE80211_BAND_5GHZ)) {
2300                                         table = b43_nphy_get_ipa_gain_table(dev);
2301                                 } else {
2302                                         if (band == IEEE80211_BAND_5GHZ) {
2303                                                 if (dev->phy.rev == 3)
2304                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2305                                                 else if (dev->phy.rev == 4)
2306                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2307                                                 else
2308                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2309                                         } else {
2310                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2311                                         }
2312                                 }
2313
2314                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2315                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2316                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2317                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2318                         } else {
2319                                 table = b43_ntab_tx_gain_rev0_1_2;
2320
2321                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2322                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2323                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2324                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2325                         }
2326                 }
2327         }
2328
2329         return target;
2330 }
2331
2332 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2333 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2334 {
2335         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2336
2337         if (dev->phy.rev >= 3) {
2338                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2339                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2340                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2341                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2342                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2343                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2344                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2345                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2346                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2347                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2348                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2349                 b43_nphy_reset_cca(dev);
2350         } else {
2351                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2352                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2353                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2354                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2355                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2356                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2357                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2358         }
2359 }
2360
2361 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2362 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2363 {
2364         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2365         u16 tmp;
2366
2367         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2368         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2369         if (dev->phy.rev >= 3) {
2370                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2371                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2372
2373                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2374                 regs[2] = tmp;
2375                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2376
2377                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2378                 regs[3] = tmp;
2379                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2380
2381                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2382                 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2383
2384                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2385                 regs[5] = tmp;
2386                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2387
2388                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2389                 regs[6] = tmp;
2390                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2391                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2392                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2393
2394                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2395                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2396                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2397
2398                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2399                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2400                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2401                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2402         } else {
2403                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2404                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2405                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2406                 regs[2] = tmp;
2407                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2408                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2409                 regs[3] = tmp;
2410                 tmp |= 0x2000;
2411                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2412                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2413                 regs[4] = tmp;
2414                 tmp |= 0x2000;
2415                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2416                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2417                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2418                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2419                         tmp = 0x0180;
2420                 else
2421                         tmp = 0x0120;
2422                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2423                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2424         }
2425 }
2426
2427 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2428 static void b43_nphy_save_cal(struct b43_wldev *dev)
2429 {
2430         struct b43_phy_n *nphy = dev->phy.n;
2431
2432         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2433         u16 *txcal_radio_regs = NULL;
2434         u8 *iqcal_chanspec;
2435         u16 *table = NULL;
2436
2437         if (nphy->hang_avoid)
2438                 b43_nphy_stay_in_carrier_search(dev, 1);
2439
2440         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2441                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2442                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2443                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2444                 table = nphy->cal_cache.txcal_coeffs_2G;
2445         } else {
2446                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2447                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2448                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2449                 table = nphy->cal_cache.txcal_coeffs_5G;
2450         }
2451
2452         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2453         /* TODO use some definitions */
2454         if (dev->phy.rev >= 3) {
2455                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2456                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2457                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2458                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2459                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2460                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2461                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2462                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2463         } else {
2464                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2465                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2466                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2467                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2468         }
2469         *iqcal_chanspec = nphy->radio_chanspec;
2470         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2471
2472         if (nphy->hang_avoid)
2473                 b43_nphy_stay_in_carrier_search(dev, 0);
2474 }
2475
2476 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2477 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2478 {
2479         struct b43_phy_n *nphy = dev->phy.n;
2480
2481         u16 coef[4];
2482         u16 *loft = NULL;
2483         u16 *table = NULL;
2484
2485         int i;
2486         u16 *txcal_radio_regs = NULL;
2487         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2488
2489         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2490                 if (nphy->iqcal_chanspec_2G == 0)
2491                         return;
2492                 table = nphy->cal_cache.txcal_coeffs_2G;
2493                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2494         } else {
2495                 if (nphy->iqcal_chanspec_5G == 0)
2496                         return;
2497                 table = nphy->cal_cache.txcal_coeffs_5G;
2498                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2499         }
2500
2501         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2502
2503         for (i = 0; i < 4; i++) {
2504                 if (dev->phy.rev >= 3)
2505                         table[i] = coef[i];
2506                 else
2507                         coef[i] = 0;
2508         }
2509
2510         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2511         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2512         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2513
2514         if (dev->phy.rev < 2)
2515                 b43_nphy_tx_iq_workaround(dev);
2516
2517         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2518                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2519                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2520         } else {
2521                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2522                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2523         }
2524
2525         /* TODO use some definitions */
2526         if (dev->phy.rev >= 3) {
2527                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2528                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2529                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2530                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2531                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2532                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2533                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2534                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2535         } else {
2536                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2537                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2538                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2539                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2540         }
2541         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2542 }
2543
2544 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2545 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2546                                 struct nphy_txgains target,
2547                                 bool full, bool mphase)
2548 {
2549         struct b43_phy_n *nphy = dev->phy.n;
2550         int i;
2551         int error = 0;
2552         int freq;
2553         bool avoid = false;
2554         u8 length;
2555         u16 tmp, core, type, count, max, numb, last, cmd;
2556         const u16 *table;
2557         bool phy6or5x;
2558
2559         u16 buffer[11];
2560         u16 diq_start = 0;
2561         u16 save[2];
2562         u16 gain[2];
2563         struct nphy_iqcal_params params[2];
2564         bool updated[2] = { };
2565
2566         b43_nphy_stay_in_carrier_search(dev, true);
2567
2568         if (dev->phy.rev >= 4) {
2569                 avoid = nphy->hang_avoid;
2570                 nphy->hang_avoid = 0;
2571         }
2572
2573         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2574
2575         for (i = 0; i < 2; i++) {
2576                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2577                 gain[i] = params[i].cal_gain;
2578         }
2579
2580         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2581
2582         b43_nphy_tx_cal_radio_setup(dev);
2583         b43_nphy_tx_cal_phy_setup(dev);
2584
2585         phy6or5x = dev->phy.rev >= 6 ||
2586                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2587                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2588         if (phy6or5x) {
2589                 if (dev->phy.is_40mhz) {
2590                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2591                                         tbl_tx_iqlo_cal_loft_ladder_40);
2592                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2593                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
2594                 } else {
2595                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2596                                         tbl_tx_iqlo_cal_loft_ladder_20);
2597                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2598                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
2599                 }
2600         }
2601
2602         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2603
2604         if (!dev->phy.is_40mhz)
2605                 freq = 2500;
2606         else
2607                 freq = 5000;
2608
2609         if (nphy->mphase_cal_phase_id > 2)
2610                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2611                                         0xFFFF, 0, true, false);
2612         else
2613                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2614
2615         if (error == 0) {
2616                 if (nphy->mphase_cal_phase_id > 2) {
2617                         table = nphy->mphase_txcal_bestcoeffs;
2618                         length = 11;
2619                         if (dev->phy.rev < 3)
2620                                 length -= 2;
2621                 } else {
2622                         if (!full && nphy->txiqlocal_coeffsvalid) {
2623                                 table = nphy->txiqlocal_bestc;
2624                                 length = 11;
2625                                 if (dev->phy.rev < 3)
2626                                         length -= 2;
2627                         } else {
2628                                 full = true;
2629                                 if (dev->phy.rev >= 3) {
2630                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2631                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2632                                 } else {
2633                                         table = tbl_tx_iqlo_cal_startcoefs;
2634                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2635                                 }
2636                         }
2637                 }
2638
2639                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2640
2641                 if (full) {
2642                         if (dev->phy.rev >= 3)
2643                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2644                         else
2645                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2646                 } else {
2647                         if (dev->phy.rev >= 3)
2648                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2649                         else
2650                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2651                 }
2652
2653                 if (mphase) {
2654                         count = nphy->mphase_txcal_cmdidx;
2655                         numb = min(max,
2656                                 (u16)(count + nphy->mphase_txcal_numcmds));
2657                 } else {
2658                         count = 0;
2659                         numb = max;
2660                 }
2661
2662                 for (; count < numb; count++) {
2663                         if (full) {
2664                                 if (dev->phy.rev >= 3)
2665                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2666                                 else
2667                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2668                         } else {
2669                                 if (dev->phy.rev >= 3)
2670                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2671                                 else
2672                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2673                         }
2674
2675                         core = (cmd & 0x3000) >> 12;
2676                         type = (cmd & 0x0F00) >> 8;
2677
2678                         if (phy6or5x && updated[core] == 0) {
2679                                 b43_nphy_update_tx_cal_ladder(dev, core);
2680                                 updated[core] = 1;
2681                         }
2682
2683                         tmp = (params[core].ncorr[type] << 8) | 0x66;
2684                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2685
2686                         if (type == 1 || type == 3 || type == 4) {
2687                                 buffer[0] = b43_ntab_read(dev,
2688                                                 B43_NTAB16(15, 69 + core));
2689                                 diq_start = buffer[0];
2690                                 buffer[0] = 0;
2691                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2692                                                 0);
2693                         }
2694
2695                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2696                         for (i = 0; i < 2000; i++) {
2697                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2698                                 if (tmp & 0xC000)
2699                                         break;
2700                                 udelay(10);
2701                         }
2702
2703                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2704                                                 buffer);
2705                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2706                                                 buffer);
2707
2708                         if (type == 1 || type == 3 || type == 4)
2709                                 buffer[0] = diq_start;
2710                 }
2711
2712                 if (mphase)
2713                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2714
2715                 last = (dev->phy.rev < 3) ? 6 : 7;
2716
2717                 if (!mphase || nphy->mphase_cal_phase_id == last) {
2718                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2719                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2720                         if (dev->phy.rev < 3) {
2721                                 buffer[0] = 0;
2722                                 buffer[1] = 0;
2723                                 buffer[2] = 0;
2724                                 buffer[3] = 0;
2725                         }
2726                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2727                                                 buffer);
2728                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2729                                                 buffer);
2730                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2731                                                 buffer);
2732                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2733                                                 buffer);
2734                         length = 11;
2735                         if (dev->phy.rev < 3)
2736                                 length -= 2;
2737                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2738                                                 nphy->txiqlocal_bestc);
2739                         nphy->txiqlocal_coeffsvalid = true;
2740                         /* TODO: Set nphy->txiqlocal_chanspec to
2741                                 the current channel */
2742                 } else {
2743                         length = 11;
2744                         if (dev->phy.rev < 3)
2745                                 length -= 2;
2746                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2747                                                 nphy->mphase_txcal_bestcoeffs);
2748                 }
2749
2750                 b43_nphy_stop_playback(dev);
2751                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2752         }
2753
2754         b43_nphy_tx_cal_phy_cleanup(dev);
2755         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2756
2757         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2758                 b43_nphy_tx_iq_workaround(dev);
2759
2760         if (dev->phy.rev >= 4)
2761                 nphy->hang_avoid = avoid;
2762
2763         b43_nphy_stay_in_carrier_search(dev, false);
2764
2765         return error;
2766 }
2767
2768 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2769 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2770 {
2771         struct b43_phy_n *nphy = dev->phy.n;
2772         u8 i;
2773         u16 buffer[7];
2774         bool equal = true;
2775
2776         if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2777                 return;
2778
2779         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2780         for (i = 0; i < 4; i++) {
2781                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2782                         equal = false;
2783                         break;
2784                 }
2785         }
2786
2787         if (!equal) {
2788                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2789                                         nphy->txiqlocal_bestc);
2790                 for (i = 0; i < 4; i++)
2791                         buffer[i] = 0;
2792                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2793                                         buffer);
2794                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2795                                         &nphy->txiqlocal_bestc[5]);
2796                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2797                                         &nphy->txiqlocal_bestc[5]);
2798         }
2799 }
2800
2801 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2802 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2803                         struct nphy_txgains target, u8 type, bool debug)
2804 {
2805         struct b43_phy_n *nphy = dev->phy.n;
2806         int i, j, index;
2807         u8 rfctl[2];
2808         u8 afectl_core;
2809         u16 tmp[6];
2810         u16 cur_hpf1, cur_hpf2, cur_lna;
2811         u32 real, imag;
2812         enum ieee80211_band band;
2813
2814         u8 use;
2815         u16 cur_hpf;
2816         u16 lna[3] = { 3, 3, 1 };
2817         u16 hpf1[3] = { 7, 2, 0 };
2818         u16 hpf2[3] = { 2, 0, 0 };
2819         u32 power[3] = { };
2820         u16 gain_save[2];
2821         u16 cal_gain[2];
2822         struct nphy_iqcal_params cal_params[2];
2823         struct nphy_iq_est est;
2824         int ret = 0;
2825         bool playtone = true;
2826         int desired = 13;
2827
2828         b43_nphy_stay_in_carrier_search(dev, 1);
2829
2830         if (dev->phy.rev < 2)
2831                 b43_nphy_reapply_tx_cal_coeffs(dev);
2832         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2833         for (i = 0; i < 2; i++) {
2834                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2835                 cal_gain[i] = cal_params[i].cal_gain;
2836         }
2837         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2838
2839         for (i = 0; i < 2; i++) {
2840                 if (i == 0) {
2841                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2842                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2843                         afectl_core = B43_NPHY_AFECTL_C1;
2844                 } else {
2845                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2846                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2847                         afectl_core = B43_NPHY_AFECTL_C2;
2848                 }
2849
2850                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2851                 tmp[2] = b43_phy_read(dev, afectl_core);
2852                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2853                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2854                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2855
2856                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2857                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2858                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2859                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2860                                 (1 - i));
2861                 b43_phy_set(dev, afectl_core, 0x0006);
2862                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2863
2864                 band = b43_current_band(dev->wl);
2865
2866                 if (nphy->rxcalparams & 0xFF000000) {
2867                         if (band == IEEE80211_BAND_5GHZ)
2868                                 b43_phy_write(dev, rfctl[0], 0x140);
2869                         else
2870                                 b43_phy_write(dev, rfctl[0], 0x110);
2871                 } else {
2872                         if (band == IEEE80211_BAND_5GHZ)
2873                                 b43_phy_write(dev, rfctl[0], 0x180);
2874                         else
2875                                 b43_phy_write(dev, rfctl[0], 0x120);
2876                 }
2877
2878                 if (band == IEEE80211_BAND_5GHZ)
2879                         b43_phy_write(dev, rfctl[1], 0x148);
2880                 else
2881                         b43_phy_write(dev, rfctl[1], 0x114);
2882
2883                 if (nphy->rxcalparams & 0x10000) {
2884                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2885                                         (i + 1));
2886                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2887                                         (2 - i));
2888                 }
2889
2890                 for (j = 0; i < 4; j++) {
2891                         if (j < 3) {
2892                                 cur_lna = lna[j];
2893                                 cur_hpf1 = hpf1[j];
2894                                 cur_hpf2 = hpf2[j];
2895                         } else {
2896                                 if (power[1] > 10000) {
2897                                         use = 1;
2898                                         cur_hpf = cur_hpf1;
2899                                         index = 2;
2900                                 } else {
2901                                         if (power[0] > 10000) {
2902                                                 use = 1;
2903                                                 cur_hpf = cur_hpf1;
2904                                                 index = 1;
2905                                         } else {
2906                                                 index = 0;
2907                                                 use = 2;
2908                                                 cur_hpf = cur_hpf2;
2909                                         }
2910                                 }
2911                                 cur_lna = lna[index];
2912                                 cur_hpf1 = hpf1[index];
2913                                 cur_hpf2 = hpf2[index];
2914                                 cur_hpf += desired - hweight32(power[index]);
2915                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2916                                 if (use == 1)
2917                                         cur_hpf1 = cur_hpf;
2918                                 else
2919                                         cur_hpf2 = cur_hpf;
2920                         }
2921
2922                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2923                                         (cur_lna << 2));
2924                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2925                                                                         false);
2926                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2927                         b43_nphy_stop_playback(dev);
2928
2929                         if (playtone) {
2930                                 ret = b43_nphy_tx_tone(dev, 4000,
2931                                                 (nphy->rxcalparams & 0xFFFF),
2932                                                 false, false);
2933                                 playtone = false;
2934                         } else {
2935                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2936                                                         false, false);
2937                         }
2938
2939                         if (ret == 0) {
2940                                 if (j < 3) {
2941                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2942                                                                         false);
2943                                         if (i == 0) {
2944                                                 real = est.i0_pwr;
2945                                                 imag = est.q0_pwr;
2946                                         } else {
2947                                                 real = est.i1_pwr;
2948                                                 imag = est.q1_pwr;
2949                                         }
2950                                         power[i] = ((real + imag) / 1024) + 1;
2951                                 } else {
2952                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2953                                 }
2954                                 b43_nphy_stop_playback(dev);
2955                         }
2956
2957                         if (ret != 0)
2958                                 break;
2959                 }
2960
2961                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2962                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2963                 b43_phy_write(dev, rfctl[1], tmp[5]);
2964                 b43_phy_write(dev, rfctl[0], tmp[4]);
2965                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2966                 b43_phy_write(dev, afectl_core, tmp[2]);
2967                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2968
2969                 if (ret != 0)
2970                         break;
2971         }
2972
2973         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2974         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2975         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2976
2977         b43_nphy_stay_in_carrier_search(dev, 0);
2978
2979         return ret;
2980 }
2981
2982 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2983                         struct nphy_txgains target, u8 type, bool debug)
2984 {
2985         return -1;
2986 }
2987
2988 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2989 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2990                         struct nphy_txgains target, u8 type, bool debug)
2991 {
2992         if (dev->phy.rev >= 3)
2993                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2994         else
2995                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2996 }
2997
2998 /*
2999  * Init N-PHY
3000  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3001  */
3002 int b43_phy_initn(struct b43_wldev *dev)
3003 {
3004         struct ssb_bus *bus = dev->dev->bus;
3005         struct b43_phy *phy = &dev->phy;
3006         struct b43_phy_n *nphy = phy->n;
3007         u8 tx_pwr_state;
3008         struct nphy_txgains target;
3009         u16 tmp;
3010         enum ieee80211_band tmp2;
3011         bool do_rssi_cal;
3012
3013         u16 clip[2];
3014         bool do_cal = false;
3015
3016         if ((dev->phy.rev >= 3) &&
3017            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3018            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3019                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3020         }
3021         nphy->deaf_count = 0;
3022         b43_nphy_tables_init(dev);
3023         nphy->crsminpwr_adjusted = false;
3024         nphy->noisevars_adjusted = false;
3025
3026         /* Clear all overrides */
3027         if (dev->phy.rev >= 3) {
3028                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3029                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3030                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3031                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3032         } else {
3033                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3034         }
3035         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3036         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3037         if (dev->phy.rev < 6) {
3038                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3039                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3040         }
3041         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3042                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3043                        B43_NPHY_RFSEQMODE_TROVER));
3044         if (dev->phy.rev >= 3)
3045                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3046         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3047
3048         if (dev->phy.rev <= 2) {
3049                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3050                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3051                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3052                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3053         }
3054         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3055         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3056
3057         if (bus->sprom.boardflags2_lo & 0x100 ||
3058             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3059              bus->boardinfo.type == 0x8B))
3060                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3061         else
3062                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3063         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3064         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3065         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3066
3067         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3068         b43_nphy_update_txrx_chain(dev);
3069
3070         if (phy->rev < 2) {
3071                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3072                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3073         }
3074
3075         tmp2 = b43_current_band(dev->wl);
3076         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3077             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3078                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3079                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3080                                 nphy->papd_epsilon_offset[0] << 7);
3081                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3082                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3083                                 nphy->papd_epsilon_offset[1] << 7);
3084                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3085         } else if (phy->rev >= 5) {
3086                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3087         }
3088
3089         b43_nphy_workarounds(dev);
3090
3091         /* Reset CCA, in init code it differs a little from standard way */
3092         b43_nphy_bmac_clock_fgc(dev, 1);
3093         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3094         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3095         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3096         b43_nphy_bmac_clock_fgc(dev, 0);
3097
3098         /* TODO N PHY MAC PHY Clock Set with argument 1 */
3099
3100         b43_nphy_pa_override(dev, false);
3101         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3102         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3103         b43_nphy_pa_override(dev, true);
3104
3105         b43_nphy_classifier(dev, 0, 0);
3106         b43_nphy_read_clip_detection(dev, clip);
3107         tx_pwr_state = nphy->txpwrctrl;
3108         /* TODO N PHY TX power control with argument 0
3109                 (turning off power control) */
3110         /* TODO Fix the TX Power Settings */
3111         /* TODO N PHY TX Power Control Idle TSSI */
3112         /* TODO N PHY TX Power Control Setup */
3113
3114         if (phy->rev >= 3) {
3115                 /* TODO */
3116         } else {
3117                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3118                                         b43_ntab_tx_gain_rev0_1_2);
3119                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3120                                         b43_ntab_tx_gain_rev0_1_2);
3121         }
3122
3123         if (nphy->phyrxchain != 3)
3124                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
3125         if (nphy->mphase_cal_phase_id > 0)
3126                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3127
3128         do_rssi_cal = false;
3129         if (phy->rev >= 3) {
3130                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3131                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3132                 else
3133                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3134
3135                 if (do_rssi_cal)
3136                         b43_nphy_rssi_cal(dev);
3137                 else
3138                         b43_nphy_restore_rssi_cal(dev);
3139         } else {
3140                 b43_nphy_rssi_cal(dev);
3141         }
3142
3143         if (!((nphy->measure_hold & 0x6) != 0)) {
3144                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3145                         do_cal = (nphy->iqcal_chanspec_2G == 0);
3146                 else
3147                         do_cal = (nphy->iqcal_chanspec_5G == 0);
3148
3149                 if (nphy->mute)
3150                         do_cal = false;
3151
3152                 if (do_cal) {
3153                         target = b43_nphy_get_tx_gains(dev);
3154
3155                         if (nphy->antsel_type == 2)
3156                                 b43_nphy_superswitch_init(dev, true);
3157                         if (nphy->perical != 2) {
3158                                 b43_nphy_rssi_cal(dev);
3159                                 if (phy->rev >= 3) {
3160                                         nphy->cal_orig_pwr_idx[0] =
3161                                             nphy->txpwrindex[0].index_internal;
3162                                         nphy->cal_orig_pwr_idx[1] =
3163                                             nphy->txpwrindex[1].index_internal;
3164                                         /* TODO N PHY Pre Calibrate TX Gain */
3165                                         target = b43_nphy_get_tx_gains(dev);
3166                                 }
3167                         }
3168                 }
3169         }
3170
3171         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3172                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3173                         b43_nphy_save_cal(dev);
3174                 else if (nphy->mphase_cal_phase_id == 0)
3175                         ;/* N PHY Periodic Calibration with argument 3 */
3176         } else {
3177                 b43_nphy_restore_cal(dev);
3178         }
3179
3180         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3181         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3182         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3183         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3184         if (phy->rev >= 3 && phy->rev <= 6)
3185                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3186         b43_nphy_tx_lp_fbw(dev);
3187         if (phy->rev >= 3)
3188                 b43_nphy_spur_workaround(dev);
3189
3190         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3191         return 0;
3192 }
3193
3194 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3195 {
3196         struct b43_phy_n *nphy;
3197
3198         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3199         if (!nphy)
3200                 return -ENOMEM;
3201         dev->phy.n = nphy;
3202
3203         return 0;
3204 }
3205
3206 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3207 {
3208         struct b43_phy *phy = &dev->phy;
3209         struct b43_phy_n *nphy = phy->n;
3210
3211         memset(nphy, 0, sizeof(*nphy));
3212
3213         //TODO init struct b43_phy_n
3214 }
3215
3216 static void b43_nphy_op_free(struct b43_wldev *dev)
3217 {
3218         struct b43_phy *phy = &dev->phy;
3219         struct b43_phy_n *nphy = phy->n;
3220
3221         kfree(nphy);
3222         phy->n = NULL;
3223 }
3224
3225 static int b43_nphy_op_init(struct b43_wldev *dev)
3226 {
3227         return b43_phy_initn(dev);
3228 }
3229
3230 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3231 {
3232 #if B43_DEBUG
3233         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3234                 /* OFDM registers are onnly available on A/G-PHYs */
3235                 b43err(dev->wl, "Invalid OFDM PHY access at "
3236                        "0x%04X on N-PHY\n", offset);
3237                 dump_stack();
3238         }
3239         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3240                 /* Ext-G registers are only available on G-PHYs */
3241                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3242                        "0x%04X on N-PHY\n", offset);
3243                 dump_stack();
3244         }
3245 #endif /* B43_DEBUG */
3246 }
3247
3248 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3249 {
3250         check_phyreg(dev, reg);
3251         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3252         return b43_read16(dev, B43_MMIO_PHY_DATA);
3253 }
3254
3255 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3256 {
3257         check_phyreg(dev, reg);
3258         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3259         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3260 }
3261
3262 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3263 {
3264         /* Register 1 is a 32-bit register. */
3265         B43_WARN_ON(reg == 1);
3266         /* N-PHY needs 0x100 for read access */
3267         reg |= 0x100;
3268
3269         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3270         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3271 }
3272
3273 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3274 {
3275         /* Register 1 is a 32-bit register. */
3276         B43_WARN_ON(reg == 1);
3277
3278         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3279         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3280 }
3281
3282 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3283 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3284                                         bool blocked)
3285 {
3286         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3287                 b43err(dev->wl, "MAC not suspended\n");
3288
3289         if (blocked) {
3290                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3291                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3292                 if (dev->phy.rev >= 3) {
3293                         b43_radio_mask(dev, 0x09, ~0x2);
3294
3295                         b43_radio_write(dev, 0x204D, 0);
3296                         b43_radio_write(dev, 0x2053, 0);
3297                         b43_radio_write(dev, 0x2058, 0);
3298                         b43_radio_write(dev, 0x205E, 0);
3299                         b43_radio_mask(dev, 0x2062, ~0xF0);
3300                         b43_radio_write(dev, 0x2064, 0);
3301
3302                         b43_radio_write(dev, 0x304D, 0);
3303                         b43_radio_write(dev, 0x3053, 0);
3304                         b43_radio_write(dev, 0x3058, 0);
3305                         b43_radio_write(dev, 0x305E, 0);
3306                         b43_radio_mask(dev, 0x3062, ~0xF0);
3307                         b43_radio_write(dev, 0x3064, 0);
3308                 }
3309         } else {
3310                 if (dev->phy.rev >= 3) {
3311                         /* TODO: b43_radio_init2056(dev); */
3312                         /* TODO: PHY Set Channel Spec (dev, radio_chanspec) */
3313                 } else {
3314                         b43_radio_init2055(dev);
3315                 }
3316         }
3317 }
3318
3319 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3320 {
3321         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3322                       on ? 0 : 0x7FFF);
3323 }
3324
3325 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3326                                       unsigned int new_channel)
3327 {
3328         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3329                 if ((new_channel < 1) || (new_channel > 14))
3330                         return -EINVAL;
3331         } else {
3332                 if (new_channel > 200)
3333                         return -EINVAL;
3334         }
3335
3336         return nphy_channel_switch(dev, new_channel);
3337 }
3338
3339 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3340 {
3341         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3342                 return 1;
3343         return 36;
3344 }
3345
3346 const struct b43_phy_operations b43_phyops_n = {
3347         .allocate               = b43_nphy_op_allocate,
3348         .free                   = b43_nphy_op_free,
3349         .prepare_structs        = b43_nphy_op_prepare_structs,
3350         .init                   = b43_nphy_op_init,
3351         .phy_read               = b43_nphy_op_read,
3352         .phy_write              = b43_nphy_op_write,
3353         .radio_read             = b43_nphy_op_radio_read,
3354         .radio_write            = b43_nphy_op_radio_write,
3355         .software_rfkill        = b43_nphy_op_software_rfkill,
3356         .switch_analog          = b43_nphy_op_switch_analog,
3357         .switch_channel         = b43_nphy_op_switch_channel,
3358         .get_default_chan       = b43_nphy_op_get_default_chan,
3359         .recalc_txpower         = b43_nphy_op_recalc_txpower,
3360         .adjust_txpower         = b43_nphy_op_adjust_txpower,
3361 };