3 Broadcom B43 wireless driver
4 IEEE 802.11a PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
37 /* Get the freq, as it has to be written to the device. */
38 static inline u16 channel2freq_a(u8 channel)
40 B43_WARN_ON(channel > 200);
42 return (5000 + 5 * channel);
45 static inline u16 freq_r3A_value(u16 frequency)
51 else if (frequency < 5321)
53 else if (frequency < 5806)
62 /* This function converts a TSSI value to dBm in Q5.2 */
63 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_a *aphy = phy->a;
70 tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi);
72 tmp = clamp_val(tmp, 0x00, 0xFF);
73 dbm = aphy->tssi2dbm[tmp];
74 //TODO: There's a FIXME on the specs
80 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
82 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
83 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
84 u16 tmp = b43_radio_read16(dev, 0x001E);
87 for (i = 0; i < 5; i++) {
88 for (j = 0; j < 5; j++) {
89 if (tmp == (data_high[i] << 4 | data_low[j])) {
90 b43_phy_write(dev, 0x0069,
91 (i - j) << 8 | 0x00C0);
98 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
102 freq = channel2freq_a(channel);
104 r8 = b43_radio_read16(dev, 0x0008);
105 b43_write16(dev, 0x03F0, freq);
106 b43_radio_write16(dev, 0x0008, r8);
108 //TODO: write max channel TX power? to Radio 0x2D
109 tmp = b43_radio_read16(dev, 0x002E);
111 //TODO: OR tmp with the Power out estimation for this channel?
112 b43_radio_write16(dev, 0x002E, tmp);
114 if (freq >= 4920 && freq <= 5500) {
116 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
117 * = (freq * 0.025862069
119 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
121 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
122 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
123 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
124 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
125 & 0x000F) | (r8 << 4));
126 b43_radio_write16(dev, 0x002A, (r8 << 4));
127 b43_radio_write16(dev, 0x002B, (r8 << 4));
128 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
129 & 0x00F0) | (r8 << 4));
130 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
132 b43_radio_write16(dev, 0x0035, 0x00AA);
133 b43_radio_write16(dev, 0x0036, 0x0085);
134 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
136 freq_r3A_value(freq));
137 b43_radio_mask(dev, 0x003D, 0x00FF);
138 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
140 b43_radio_mask(dev, 0x0035, 0xFFEF);
141 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
143 b43_radio_set_tx_iq(dev);
144 //TODO: TSSI2dbm workaround
145 //FIXME b43_phy_xmitpower(dev);
148 static void b43_radio_init2060(struct b43_wldev *dev)
150 b43_radio_write16(dev, 0x0004, 0x00C0);
151 b43_radio_write16(dev, 0x0005, 0x0008);
152 b43_radio_write16(dev, 0x0009, 0x0040);
153 b43_radio_write16(dev, 0x0005, 0x00AA);
154 b43_radio_write16(dev, 0x0032, 0x008F);
155 b43_radio_write16(dev, 0x0006, 0x008F);
156 b43_radio_write16(dev, 0x0034, 0x008F);
157 b43_radio_write16(dev, 0x002C, 0x0007);
158 b43_radio_write16(dev, 0x0082, 0x0080);
159 b43_radio_write16(dev, 0x0080, 0x0000);
160 b43_radio_write16(dev, 0x003F, 0x00DA);
161 b43_radio_mask(dev, 0x0005, ~0x0008);
162 b43_radio_mask(dev, 0x0081, ~0x0010);
163 b43_radio_mask(dev, 0x0081, ~0x0020);
164 b43_radio_mask(dev, 0x0081, ~0x0020);
165 msleep(1); /* delay 400usec */
167 b43_radio_write16(dev, 0x0081,
168 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
169 msleep(1); /* delay 400usec */
171 b43_radio_write16(dev, 0x0005,
172 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
173 b43_radio_mask(dev, 0x0085, ~0x0010);
174 b43_radio_mask(dev, 0x0005, ~0x0008);
175 b43_radio_mask(dev, 0x0081, ~0x0040);
176 b43_radio_write16(dev, 0x0081,
177 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
178 b43_radio_write16(dev, 0x0005,
179 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
180 b43_phy_write(dev, 0x0063, 0xDDC6);
181 b43_phy_write(dev, 0x0069, 0x07BE);
182 b43_phy_write(dev, 0x006A, 0x0000);
184 aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
189 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
193 if (dev->phy.rev < 3) {
195 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
196 b43_ofdmtab_write16(dev,
197 B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
198 b43_ofdmtab_write16(dev,
199 B43_OFDMTAB_WRSSI, i, 0xFFF8);
202 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
203 b43_ofdmtab_write16(dev,
204 B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
205 b43_ofdmtab_write16(dev,
206 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
210 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
211 b43_ofdmtab_write16(dev,
212 B43_OFDMTAB_WRSSI, i, 0x0820);
214 for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
215 b43_ofdmtab_write16(dev,
216 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
220 static void b43_phy_ww(struct b43_wldev *dev)
222 u16 b, curr_s, best_s = 0xFFFF;
225 b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
226 b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
227 b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
228 b43_radio_set(dev, 0x0009, 0x0080);
229 b43_radio_write16(dev, 0x0012,
230 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
231 b43_wa_initgains(dev);
232 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
233 b = b43_phy_read(dev, B43_PHY_PWRDOWN);
234 b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
235 b43_radio_set(dev, 0x0004, 0x0004);
236 for (i = 0x10; i <= 0x20; i++) {
237 b43_radio_write16(dev, 0x0013, i);
238 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
242 } else if (curr_s >= 0x0080)
243 curr_s = 0x0100 - curr_s;
247 b43_phy_write(dev, B43_PHY_PWRDOWN, b);
248 b43_radio_mask(dev, 0x0004, 0xFFFB);
249 b43_radio_write16(dev, 0x0013, best_s);
250 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
251 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
252 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
253 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
254 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
255 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
256 b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
257 b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
258 b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
259 b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
260 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
261 for (i = 0; i < 6; i++)
262 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
263 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
264 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
265 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
266 b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
267 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
270 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
275 void b43_phy_inita(struct b43_wldev *dev)
277 struct ssb_bus *bus = dev->dev->bus;
278 struct b43_phy *phy = &dev->phy;
280 /* This lowlevel A-PHY init is also called from G-PHY init.
281 * So we must not access phy->a, if called from G-PHY code.
283 B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
284 (phy->type != B43_PHYTYPE_G));
289 if (phy->type == B43_PHYTYPE_A)
290 b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
291 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
292 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
294 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
299 if (phy->type == B43_PHYTYPE_A) {
300 if (phy->gmode && (phy->rev < 3))
301 b43_phy_set(dev, 0x0034, 0x0001);
302 b43_phy_rssiagc(dev, 0);
304 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
306 b43_radio_init2060(dev);
308 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
309 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
310 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
317 hardware_pctl_init_aphy(dev);
319 //TODO: radar detection
322 if ((phy->type == B43_PHYTYPE_G) &&
323 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
324 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
328 /* Initialise the TSSI->dBm lookup table */
329 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
331 struct b43_phy *phy = &dev->phy;
332 struct b43_phy_a *aphy = phy->a;
333 s16 pab0, pab1, pab2;
335 pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
336 pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
337 pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
339 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
340 pab0 != -1 && pab1 != -1 && pab2 != -1) {
341 /* The pabX values are set in SPROM. Use them. */
342 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
343 (s8) dev->dev->bus->sprom.itssi_a != -1)
344 aphy->tgt_idle_tssi =
345 (s8) (dev->dev->bus->sprom.itssi_a);
347 aphy->tgt_idle_tssi = 62;
348 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
353 /* pabX values not set in SPROM,
354 * but APHY needs a generated table. */
355 aphy->tssi2dbm = NULL;
356 b43err(dev->wl, "Could not generate tssi2dBm "
357 "table (wrong SPROM info)!\n");
364 static int b43_aphy_op_allocate(struct b43_wldev *dev)
366 struct b43_phy_a *aphy;
369 aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
374 err = b43_aphy_init_tssi2dbm_table(dev);
387 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
389 struct b43_phy *phy = &dev->phy;
390 struct b43_phy_a *aphy = phy->a;
391 const void *tssi2dbm;
394 /* tssi2dbm table is constant, so it is initialized at alloc time.
395 * Save a copy of the pointer. */
396 tssi2dbm = aphy->tssi2dbm;
397 tgt_idle_tssi = aphy->tgt_idle_tssi;
399 /* Zero out the whole PHY structure. */
400 memset(aphy, 0, sizeof(*aphy));
402 aphy->tssi2dbm = tssi2dbm;
403 aphy->tgt_idle_tssi = tgt_idle_tssi;
405 //TODO init struct b43_phy_a
409 static void b43_aphy_op_free(struct b43_wldev *dev)
411 struct b43_phy *phy = &dev->phy;
412 struct b43_phy_a *aphy = phy->a;
414 kfree(aphy->tssi2dbm);
415 aphy->tssi2dbm = NULL;
421 static int b43_aphy_op_init(struct b43_wldev *dev)
428 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
430 /* OFDM registers are base-registers for the A-PHY. */
431 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
432 offset &= ~B43_PHYROUTE;
433 offset |= B43_PHYROUTE_BASE;
437 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
438 /* Ext-G registers are only available on G-PHYs */
439 b43err(dev->wl, "Invalid EXT-G PHY access at "
440 "0x%04X on A-PHY\n", offset);
443 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
444 /* N-BMODE registers are only available on N-PHYs */
445 b43err(dev->wl, "Invalid N-BMODE PHY access at "
446 "0x%04X on A-PHY\n", offset);
449 #endif /* B43_DEBUG */
454 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
456 reg = adjust_phyreg(dev, reg);
457 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
458 return b43_read16(dev, B43_MMIO_PHY_DATA);
461 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
463 reg = adjust_phyreg(dev, reg);
464 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
465 b43_write16(dev, B43_MMIO_PHY_DATA, value);
468 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
470 /* Register 1 is a 32-bit register. */
471 B43_WARN_ON(reg == 1);
472 /* A-PHY needs 0x40 for read access */
475 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
476 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
479 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
481 /* Register 1 is a 32-bit register. */
482 B43_WARN_ON(reg == 1);
484 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
485 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
488 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
490 return (dev->phy.rev >= 5);
493 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
494 enum rfkill_state state)
496 struct b43_phy *phy = &dev->phy;
498 if (state == RFKILL_STATE_UNBLOCKED) {
501 b43_radio_write16(dev, 0x0004, 0x00C0);
502 b43_radio_write16(dev, 0x0005, 0x0008);
503 b43_phy_mask(dev, 0x0010, 0xFFF7);
504 b43_phy_mask(dev, 0x0011, 0xFFF7);
505 b43_radio_init2060(dev);
507 b43_radio_write16(dev, 0x0004, 0x00FF);
508 b43_radio_write16(dev, 0x0005, 0x00FB);
509 b43_phy_set(dev, 0x0010, 0x0008);
510 b43_phy_set(dev, 0x0011, 0x0008);
514 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
515 unsigned int new_channel)
517 if (new_channel > 200)
519 aphy_channel_switch(dev, new_channel);
524 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
526 return 36; /* Default to channel 36 */
529 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
531 struct b43_phy *phy = &dev->phy;
536 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
539 hf = b43_hf_read(dev);
540 hf &= ~B43_HF_ANTDIVHELP;
541 b43_hf_write(dev, hf);
543 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
544 tmp &= ~B43_PHY_BBANDCFG_RXANT;
545 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
546 << B43_PHY_BBANDCFG_RXANT_SHIFT;
547 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
550 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
551 if (antenna == B43_ANTENNA_AUTO0)
552 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
554 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
555 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
558 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
559 tmp = (tmp & 0xFF00) | 0x24;
560 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
562 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
564 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
565 if (phy->analog == 3) {
566 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
568 b43_phy_write(dev, B43_PHY_ADIVRELATED,
571 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
575 B43_PHY_ADIVRELATED);
576 tmp = (tmp & 0xFF00) | 8;
577 b43_phy_write(dev, B43_PHY_ADIVRELATED,
582 hf |= B43_HF_ANTDIVHELP;
583 b43_hf_write(dev, hf);
586 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
590 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
593 return B43_TXPWR_RES_DONE;
596 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
600 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
604 const struct b43_phy_operations b43_phyops_a = {
605 .allocate = b43_aphy_op_allocate,
606 .free = b43_aphy_op_free,
607 .prepare_structs = b43_aphy_op_prepare_structs,
608 .init = b43_aphy_op_init,
609 .phy_read = b43_aphy_op_read,
610 .phy_write = b43_aphy_op_write,
611 .radio_read = b43_aphy_op_radio_read,
612 .radio_write = b43_aphy_op_radio_write,
613 .supports_hwpctl = b43_aphy_op_supports_hwpctl,
614 .software_rfkill = b43_aphy_op_software_rfkill,
615 .switch_analog = b43_phyop_switch_analog_generic,
616 .switch_channel = b43_aphy_op_switch_channel,
617 .get_default_chan = b43_aphy_op_get_default_chan,
618 .set_rx_antenna = b43_aphy_op_set_rx_antenna,
619 .recalc_txpower = b43_aphy_op_recalc_txpower,
620 .adjust_txpower = b43_aphy_op_adjust_txpower,
621 .pwork_15sec = b43_aphy_op_pwork_15sec,
622 .pwork_60sec = b43_aphy_op_pwork_60sec,