3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
47 #include "phy_common.h"
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
286 static int b43_ratelimit(struct b43_wl *wl)
288 if (!wl || !wl->current_dev)
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
301 if (!b43_ratelimit(wl))
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
314 if (!b43_ratelimit(wl))
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
327 if (!b43_ratelimit(wl))
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
353 B43_WARN_ON(offset % 4 != 0);
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
400 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
402 struct b43_wl *wl = dev->wl;
406 spin_lock_irqsave(&wl->shm_lock, flags);
407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
413 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
434 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
436 struct b43_wl *wl = dev->wl;
440 spin_lock_irqsave(&wl->shm_lock, flags);
441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
447 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
462 b43_shm_control_word(dev, routing, offset);
463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
466 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
468 struct b43_wl *wl = dev->wl;
471 spin_lock_irqsave(&wl->shm_lock, flags);
472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
476 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
488 b43_shm_control_word(dev, routing, offset);
489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
492 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
494 struct b43_wl *wl = dev->wl;
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
499 spin_unlock_irqrestore(&wl->shm_lock, flags);
503 u64 b43_hf_read(struct b43_wldev * dev)
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
516 /* Write HostFlags */
517 void b43_hf_write(struct b43_wldev *dev, u64 value)
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
529 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
552 u16 test1, test2, test3;
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
577 static void b43_time_lock(struct b43_wldev *dev)
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
599 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
632 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
640 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
662 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
666 u8 mac_bssid[ETH_ALEN * 2];
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
688 static void b43_upload_card_macaddress(struct b43_wldev *dev)
690 b43_write_mac_bssid_templates(dev);
691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
694 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
703 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
705 b43_set_slot_time(dev, 9);
709 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
711 b43_set_slot_time(dev, 20);
715 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
716 * Returns the _previously_ enabled IRQ mask.
718 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
722 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
723 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
728 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
729 * Returns the _previously_ enabled IRQ mask.
731 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
735 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
736 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
741 /* Synchronize IRQ top- and bottom-half.
742 * IRQs must be masked before calling this.
743 * This must not be called with the irq_lock held.
745 static void b43_synchronize_irq(struct b43_wldev *dev)
747 synchronize_irq(dev->dev->irq);
748 tasklet_kill(&dev->isr_tasklet);
751 /* DummyTransmission function, as documented on
752 * http://bcm-specs.sipsolutions.net/DummyTransmission
754 void b43_dummy_transmission(struct b43_wldev *dev)
756 struct b43_wl *wl = dev->wl;
757 struct b43_phy *phy = &dev->phy;
758 unsigned int i, max_loop;
771 buffer[0] = 0x000201CC;
776 buffer[0] = 0x000B846E;
783 spin_lock_irq(&wl->irq_lock);
784 write_lock(&wl->tx_lock);
786 for (i = 0; i < 5; i++)
787 b43_ram_write(dev, i * 4, buffer[i]);
790 b43_read32(dev, B43_MMIO_MACCTL);
792 b43_write16(dev, 0x0568, 0x0000);
793 b43_write16(dev, 0x07C0, 0x0000);
794 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
795 b43_write16(dev, 0x050C, value);
796 b43_write16(dev, 0x0508, 0x0000);
797 b43_write16(dev, 0x050A, 0x0000);
798 b43_write16(dev, 0x054C, 0x0000);
799 b43_write16(dev, 0x056A, 0x0014);
800 b43_write16(dev, 0x0568, 0x0826);
801 b43_write16(dev, 0x0500, 0x0000);
802 b43_write16(dev, 0x0502, 0x0030);
804 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
805 b43_radio_write16(dev, 0x0051, 0x0017);
806 for (i = 0x00; i < max_loop; i++) {
807 value = b43_read16(dev, 0x050E);
812 for (i = 0x00; i < 0x0A; i++) {
813 value = b43_read16(dev, 0x050E);
818 for (i = 0x00; i < 0x19; i++) {
819 value = b43_read16(dev, 0x0690);
820 if (!(value & 0x0100))
824 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
825 b43_radio_write16(dev, 0x0051, 0x0037);
827 write_unlock(&wl->tx_lock);
828 spin_unlock_irq(&wl->irq_lock);
831 static void key_write(struct b43_wldev *dev,
832 u8 index, u8 algorithm, const u8 * key)
839 /* Key index/algo block */
840 kidx = b43_kidx_to_fw(dev, index);
841 value = ((kidx << 4) | algorithm);
842 b43_shm_write16(dev, B43_SHM_SHARED,
843 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
845 /* Write the key to the Key Table Pointer offset */
846 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
847 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
849 value |= (u16) (key[i + 1]) << 8;
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
854 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
856 u32 addrtmp[2] = { 0, 0, };
857 u8 per_sta_keys_start = 8;
859 if (b43_new_kidx_api(dev))
860 per_sta_keys_start = 4;
862 B43_WARN_ON(index < per_sta_keys_start);
863 /* We have two default TX keys and possibly two default RX keys.
864 * Physical mac 0 is mapped to physical key 4 or 8, depending
865 * on the firmware version.
866 * So we must adjust the index here.
868 index -= per_sta_keys_start;
871 addrtmp[0] = addr[0];
872 addrtmp[0] |= ((u32) (addr[1]) << 8);
873 addrtmp[0] |= ((u32) (addr[2]) << 16);
874 addrtmp[0] |= ((u32) (addr[3]) << 24);
875 addrtmp[1] = addr[4];
876 addrtmp[1] |= ((u32) (addr[5]) << 8);
879 if (dev->dev->id.revision >= 5) {
880 /* Receive match transmitter address mechanism */
881 b43_shm_write32(dev, B43_SHM_RCMTA,
882 (index * 2) + 0, addrtmp[0]);
883 b43_shm_write16(dev, B43_SHM_RCMTA,
884 (index * 2) + 1, addrtmp[1]);
886 /* RXE (Receive Engine) and
887 * PSM (Programmable State Machine) mechanism
890 /* TODO write to RCM 16, 19, 22 and 25 */
892 b43_shm_write32(dev, B43_SHM_SHARED,
893 B43_SHM_SH_PSM + (index * 6) + 0,
895 b43_shm_write16(dev, B43_SHM_SHARED,
896 B43_SHM_SH_PSM + (index * 6) + 4,
902 static void do_key_write(struct b43_wldev *dev,
903 u8 index, u8 algorithm,
904 const u8 * key, size_t key_len, const u8 * mac_addr)
906 u8 buf[B43_SEC_KEYSIZE] = { 0, };
907 u8 per_sta_keys_start = 8;
909 if (b43_new_kidx_api(dev))
910 per_sta_keys_start = 4;
912 B43_WARN_ON(index >= dev->max_nr_keys);
913 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
915 if (index >= per_sta_keys_start)
916 keymac_write(dev, index, NULL); /* First zero out mac. */
918 memcpy(buf, key, key_len);
919 key_write(dev, index, algorithm, buf);
920 if (index >= per_sta_keys_start)
921 keymac_write(dev, index, mac_addr);
923 dev->key[index].algorithm = algorithm;
926 static int b43_key_write(struct b43_wldev *dev,
927 int index, u8 algorithm,
928 const u8 * key, size_t key_len,
930 struct ieee80211_key_conf *keyconf)
935 if (key_len > B43_SEC_KEYSIZE)
937 for (i = 0; i < dev->max_nr_keys; i++) {
938 /* Check that we don't already have this key. */
939 B43_WARN_ON(dev->key[i].keyconf == keyconf);
942 /* Either pairwise key or address is 00:00:00:00:00:00
943 * for transmit-only keys. Search the index. */
944 if (b43_new_kidx_api(dev))
948 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
949 if (!dev->key[i].keyconf) {
956 b43err(dev->wl, "Out of hardware key memory\n");
960 B43_WARN_ON(index > 3);
962 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
963 if ((index <= 3) && !b43_new_kidx_api(dev)) {
965 B43_WARN_ON(mac_addr);
966 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
968 keyconf->hw_key_idx = index;
969 dev->key[index].keyconf = keyconf;
974 static int b43_key_clear(struct b43_wldev *dev, int index)
976 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
978 do_key_write(dev, index, B43_SEC_ALGO_NONE,
979 NULL, B43_SEC_KEYSIZE, NULL);
980 if ((index <= 3) && !b43_new_kidx_api(dev)) {
981 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
982 NULL, B43_SEC_KEYSIZE, NULL);
984 dev->key[index].keyconf = NULL;
989 static void b43_clear_keys(struct b43_wldev *dev)
993 for (i = 0; i < dev->max_nr_keys; i++)
994 b43_key_clear(dev, i);
997 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1005 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1006 (ps_flags & B43_PS_DISABLED));
1007 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1009 if (ps_flags & B43_PS_ENABLED) {
1011 } else if (ps_flags & B43_PS_DISABLED) {
1014 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1015 // and thus is not an AP and we are associated, set bit 25
1017 if (ps_flags & B43_PS_AWAKE) {
1019 } else if (ps_flags & B43_PS_ASLEEP) {
1022 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1023 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1024 // successful, set bit26
1027 /* FIXME: For now we force awake-on and hwps-off */
1031 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1033 macctl |= B43_MACCTL_HWPS;
1035 macctl &= ~B43_MACCTL_HWPS;
1037 macctl |= B43_MACCTL_AWAKE;
1039 macctl &= ~B43_MACCTL_AWAKE;
1040 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1042 b43_read32(dev, B43_MMIO_MACCTL);
1043 if (awake && dev->dev->id.revision >= 5) {
1044 /* Wait for the microcode to wake up. */
1045 for (i = 0; i < 100; i++) {
1046 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1047 B43_SHM_SH_UCODESTAT);
1048 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1055 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1060 flags |= B43_TMSLOW_PHYCLKEN;
1061 flags |= B43_TMSLOW_PHYRESET;
1062 ssb_device_enable(dev->dev, flags);
1063 msleep(2); /* Wait for the PLL to turn on. */
1065 /* Now take the PHY out of Reset again */
1066 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1067 tmslow |= SSB_TMSLOW_FGC;
1068 tmslow &= ~B43_TMSLOW_PHYRESET;
1069 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1070 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1072 tmslow &= ~SSB_TMSLOW_FGC;
1073 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1074 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1077 /* Turn Analog ON, but only if we already know the PHY-type.
1078 * This protects against very early setup where we don't know the
1079 * PHY-type, yet. wireless_core_reset will be called once again later,
1080 * when we know the PHY-type. */
1082 dev->phy.ops->switch_analog(dev, 1);
1084 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1085 macctl &= ~B43_MACCTL_GMODE;
1086 if (flags & B43_TMSLOW_GMODE)
1087 macctl |= B43_MACCTL_GMODE;
1088 macctl |= B43_MACCTL_IHR_ENABLED;
1089 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1092 static void handle_irq_transmit_status(struct b43_wldev *dev)
1096 struct b43_txstatus stat;
1099 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1100 if (!(v0 & 0x00000001))
1102 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1104 stat.cookie = (v0 >> 16);
1105 stat.seq = (v1 & 0x0000FFFF);
1106 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1107 tmp = (v0 & 0x0000FFFF);
1108 stat.frame_count = ((tmp & 0xF000) >> 12);
1109 stat.rts_count = ((tmp & 0x0F00) >> 8);
1110 stat.supp_reason = ((tmp & 0x001C) >> 2);
1111 stat.pm_indicated = !!(tmp & 0x0080);
1112 stat.intermediate = !!(tmp & 0x0040);
1113 stat.for_ampdu = !!(tmp & 0x0020);
1114 stat.acked = !!(tmp & 0x0002);
1116 b43_handle_txstatus(dev, &stat);
1120 static void drain_txstatus_queue(struct b43_wldev *dev)
1124 if (dev->dev->id.revision < 5)
1126 /* Read all entries from the microcode TXstatus FIFO
1127 * and throw them away.
1130 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1131 if (!(dummy & 0x00000001))
1133 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1137 static u32 b43_jssi_read(struct b43_wldev *dev)
1141 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1143 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1148 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1150 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1151 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1154 static void b43_generate_noise_sample(struct b43_wldev *dev)
1156 b43_jssi_write(dev, 0x7F7F7F7F);
1157 b43_write32(dev, B43_MMIO_MACCMD,
1158 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1161 static void b43_calculate_link_quality(struct b43_wldev *dev)
1163 /* Top half of Link Quality calculation. */
1165 if (dev->phy.type != B43_PHYTYPE_G)
1167 if (dev->noisecalc.calculation_running)
1169 dev->noisecalc.calculation_running = 1;
1170 dev->noisecalc.nr_samples = 0;
1172 b43_generate_noise_sample(dev);
1175 static void handle_irq_noise(struct b43_wldev *dev)
1177 struct b43_phy_g *phy = dev->phy.g;
1183 /* Bottom half of Link Quality calculation. */
1185 if (dev->phy.type != B43_PHYTYPE_G)
1188 /* Possible race condition: It might be possible that the user
1189 * changed to a different channel in the meantime since we
1190 * started the calculation. We ignore that fact, since it's
1191 * not really that much of a problem. The background noise is
1192 * an estimation only anyway. Slightly wrong results will get damped
1193 * by the averaging of the 8 sample rounds. Additionally the
1194 * value is shortlived. So it will be replaced by the next noise
1195 * calculation round soon. */
1197 B43_WARN_ON(!dev->noisecalc.calculation_running);
1198 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1199 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1200 noise[2] == 0x7F || noise[3] == 0x7F)
1203 /* Get the noise samples. */
1204 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1205 i = dev->noisecalc.nr_samples;
1206 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1207 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1208 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1209 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1210 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1211 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1212 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1213 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1214 dev->noisecalc.nr_samples++;
1215 if (dev->noisecalc.nr_samples == 8) {
1216 /* Calculate the Link Quality by the noise samples. */
1218 for (i = 0; i < 8; i++) {
1219 for (j = 0; j < 4; j++)
1220 average += dev->noisecalc.samples[i][j];
1226 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1227 tmp = (tmp / 128) & 0x1F;
1237 dev->stats.link_noise = average;
1238 dev->noisecalc.calculation_running = 0;
1242 b43_generate_noise_sample(dev);
1245 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1247 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1250 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1251 b43_power_saving_ctl_bits(dev, 0);
1253 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1257 static void handle_irq_atim_end(struct b43_wldev *dev)
1259 if (dev->dfq_valid) {
1260 b43_write32(dev, B43_MMIO_MACCMD,
1261 b43_read32(dev, B43_MMIO_MACCMD)
1262 | B43_MACCMD_DFQ_VALID);
1267 static void handle_irq_pmq(struct b43_wldev *dev)
1274 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1275 if (!(tmp & 0x00000008))
1278 /* 16bit write is odd, but correct. */
1279 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1282 static void b43_write_template_common(struct b43_wldev *dev,
1283 const u8 * data, u16 size,
1285 u16 shm_size_offset, u8 rate)
1288 struct b43_plcp_hdr4 plcp;
1291 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1292 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1293 ram_offset += sizeof(u32);
1294 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1295 * So leave the first two bytes of the next write blank.
1297 tmp = (u32) (data[0]) << 16;
1298 tmp |= (u32) (data[1]) << 24;
1299 b43_ram_write(dev, ram_offset, tmp);
1300 ram_offset += sizeof(u32);
1301 for (i = 2; i < size; i += sizeof(u32)) {
1302 tmp = (u32) (data[i + 0]);
1304 tmp |= (u32) (data[i + 1]) << 8;
1306 tmp |= (u32) (data[i + 2]) << 16;
1308 tmp |= (u32) (data[i + 3]) << 24;
1309 b43_ram_write(dev, ram_offset + i - 2, tmp);
1311 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1312 size + sizeof(struct b43_plcp_hdr6));
1315 /* Check if the use of the antenna that ieee80211 told us to
1316 * use is possible. This will fall back to DEFAULT.
1317 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1318 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1323 if (antenna_nr == 0) {
1324 /* Zero means "use default antenna". That's always OK. */
1328 /* Get the mask of available antennas. */
1330 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1332 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1334 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1335 /* This antenna is not available. Fall back to default. */
1342 /* Convert a b43 antenna number value to the PHY TX control value. */
1343 static u16 b43_antenna_to_phyctl(int antenna)
1347 return B43_TXH_PHY_ANT0;
1349 return B43_TXH_PHY_ANT1;
1351 return B43_TXH_PHY_ANT2;
1353 return B43_TXH_PHY_ANT3;
1354 case B43_ANTENNA_AUTO:
1355 return B43_TXH_PHY_ANT01AUTO;
1361 static void b43_write_beacon_template(struct b43_wldev *dev,
1363 u16 shm_size_offset)
1365 unsigned int i, len, variable_len;
1366 const struct ieee80211_mgmt *bcn;
1372 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1374 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1375 len = min((size_t) dev->wl->current_beacon->len,
1376 0x200 - sizeof(struct b43_plcp_hdr6));
1377 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1379 b43_write_template_common(dev, (const u8 *)bcn,
1380 len, ram_offset, shm_size_offset, rate);
1382 /* Write the PHY TX control parameters. */
1383 antenna = B43_ANTENNA_DEFAULT;
1384 antenna = b43_antenna_to_phyctl(antenna);
1385 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1386 /* We can't send beacons with short preamble. Would get PHY errors. */
1387 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1388 ctl &= ~B43_TXH_PHY_ANT;
1389 ctl &= ~B43_TXH_PHY_ENC;
1391 if (b43_is_cck_rate(rate))
1392 ctl |= B43_TXH_PHY_ENC_CCK;
1394 ctl |= B43_TXH_PHY_ENC_OFDM;
1395 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1397 /* Find the position of the TIM and the DTIM_period value
1398 * and write them to SHM. */
1399 ie = bcn->u.beacon.variable;
1400 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1401 for (i = 0; i < variable_len - 2; ) {
1402 uint8_t ie_id, ie_len;
1409 /* This is the TIM Information Element */
1411 /* Check whether the ie_len is in the beacon data range. */
1412 if (variable_len < ie_len + 2 + i)
1414 /* A valid TIM is at least 4 bytes long. */
1419 tim_position = sizeof(struct b43_plcp_hdr6);
1420 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1423 dtim_period = ie[i + 3];
1425 b43_shm_write16(dev, B43_SHM_SHARED,
1426 B43_SHM_SH_TIMBPOS, tim_position);
1427 b43_shm_write16(dev, B43_SHM_SHARED,
1428 B43_SHM_SH_DTIMPER, dtim_period);
1435 * If ucode wants to modify TIM do it behind the beacon, this
1436 * will happen, for example, when doing mesh networking.
1438 b43_shm_write16(dev, B43_SHM_SHARED,
1440 len + sizeof(struct b43_plcp_hdr6));
1441 b43_shm_write16(dev, B43_SHM_SHARED,
1442 B43_SHM_SH_DTIMPER, 0);
1444 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1447 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1448 u16 shm_offset, u16 size,
1449 struct ieee80211_rate *rate)
1451 struct b43_plcp_hdr4 plcp;
1456 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1457 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1460 /* Write PLCP in two parts and timing for packet transfer */
1461 tmp = le32_to_cpu(plcp.data);
1462 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1463 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1464 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1467 /* Instead of using custom probe response template, this function
1468 * just patches custom beacon template by:
1469 * 1) Changing packet type
1470 * 2) Patching duration field
1473 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1475 struct ieee80211_rate *rate)
1479 u16 src_size, elem_size, src_pos, dest_pos;
1481 struct ieee80211_hdr *hdr;
1484 src_size = dev->wl->current_beacon->len;
1485 src_data = (const u8 *)dev->wl->current_beacon->data;
1487 /* Get the start offset of the variable IEs in the packet. */
1488 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1489 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1491 if (B43_WARN_ON(src_size < ie_start))
1494 dest_data = kmalloc(src_size, GFP_ATOMIC);
1495 if (unlikely(!dest_data))
1498 /* Copy the static data and all Information Elements, except the TIM. */
1499 memcpy(dest_data, src_data, ie_start);
1501 dest_pos = ie_start;
1502 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1503 elem_size = src_data[src_pos + 1] + 2;
1504 if (src_data[src_pos] == 5) {
1505 /* This is the TIM. */
1508 memcpy(dest_data + dest_pos, src_data + src_pos,
1510 dest_pos += elem_size;
1512 *dest_size = dest_pos;
1513 hdr = (struct ieee80211_hdr *)dest_data;
1515 /* Set the frame control. */
1516 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1517 IEEE80211_STYPE_PROBE_RESP);
1518 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1519 dev->wl->vif, *dest_size,
1521 hdr->duration_id = dur;
1526 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1528 u16 shm_size_offset,
1529 struct ieee80211_rate *rate)
1531 const u8 *probe_resp_data;
1534 size = dev->wl->current_beacon->len;
1535 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1536 if (unlikely(!probe_resp_data))
1539 /* Looks like PLCP headers plus packet timings are stored for
1540 * all possible basic rates
1542 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1543 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1544 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1545 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1547 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1548 b43_write_template_common(dev, probe_resp_data,
1549 size, ram_offset, shm_size_offset,
1551 kfree(probe_resp_data);
1554 static void b43_upload_beacon0(struct b43_wldev *dev)
1556 struct b43_wl *wl = dev->wl;
1558 if (wl->beacon0_uploaded)
1560 b43_write_beacon_template(dev, 0x68, 0x18);
1561 /* FIXME: Probe resp upload doesn't really belong here,
1562 * but we don't use that feature anyway. */
1563 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1564 &__b43_ratetable[3]);
1565 wl->beacon0_uploaded = 1;
1568 static void b43_upload_beacon1(struct b43_wldev *dev)
1570 struct b43_wl *wl = dev->wl;
1572 if (wl->beacon1_uploaded)
1574 b43_write_beacon_template(dev, 0x468, 0x1A);
1575 wl->beacon1_uploaded = 1;
1578 static void handle_irq_beacon(struct b43_wldev *dev)
1580 struct b43_wl *wl = dev->wl;
1581 u32 cmd, beacon0_valid, beacon1_valid;
1583 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1584 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1587 /* This is the bottom half of the asynchronous beacon update. */
1589 /* Ignore interrupt in the future. */
1590 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1592 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1593 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1594 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1596 /* Schedule interrupt manually, if busy. */
1597 if (beacon0_valid && beacon1_valid) {
1598 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1599 dev->irq_savedstate |= B43_IRQ_BEACON;
1603 if (unlikely(wl->beacon_templates_virgin)) {
1604 /* We never uploaded a beacon before.
1605 * Upload both templates now, but only mark one valid. */
1606 wl->beacon_templates_virgin = 0;
1607 b43_upload_beacon0(dev);
1608 b43_upload_beacon1(dev);
1609 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1610 cmd |= B43_MACCMD_BEACON0_VALID;
1611 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1613 if (!beacon0_valid) {
1614 b43_upload_beacon0(dev);
1615 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1616 cmd |= B43_MACCMD_BEACON0_VALID;
1617 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1618 } else if (!beacon1_valid) {
1619 b43_upload_beacon1(dev);
1620 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1621 cmd |= B43_MACCMD_BEACON1_VALID;
1622 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1627 static void b43_beacon_update_trigger_work(struct work_struct *work)
1629 struct b43_wl *wl = container_of(work, struct b43_wl,
1630 beacon_update_trigger);
1631 struct b43_wldev *dev;
1633 mutex_lock(&wl->mutex);
1634 dev = wl->current_dev;
1635 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1636 spin_lock_irq(&wl->irq_lock);
1637 /* update beacon right away or defer to irq */
1638 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1639 handle_irq_beacon(dev);
1640 /* The handler might have updated the IRQ mask. */
1641 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1642 dev->irq_savedstate);
1644 spin_unlock_irq(&wl->irq_lock);
1646 mutex_unlock(&wl->mutex);
1649 /* Asynchronously update the packet templates in template RAM.
1650 * Locking: Requires wl->irq_lock to be locked. */
1651 static void b43_update_templates(struct b43_wl *wl)
1653 struct sk_buff *beacon;
1655 /* This is the top half of the ansynchronous beacon update.
1656 * The bottom half is the beacon IRQ.
1657 * Beacon update must be asynchronous to avoid sending an
1658 * invalid beacon. This can happen for example, if the firmware
1659 * transmits a beacon while we are updating it. */
1661 /* We could modify the existing beacon and set the aid bit in
1662 * the TIM field, but that would probably require resizing and
1663 * moving of data within the beacon template.
1664 * Simply request a new beacon and let mac80211 do the hard work. */
1665 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1666 if (unlikely(!beacon))
1669 if (wl->current_beacon)
1670 dev_kfree_skb_any(wl->current_beacon);
1671 wl->current_beacon = beacon;
1672 wl->beacon0_uploaded = 0;
1673 wl->beacon1_uploaded = 0;
1674 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1677 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1682 len = min((u16) ssid_len, (u16) 0x100);
1683 for (i = 0; i < len; i += sizeof(u32)) {
1684 tmp = (u32) (ssid[i + 0]);
1686 tmp |= (u32) (ssid[i + 1]) << 8;
1688 tmp |= (u32) (ssid[i + 2]) << 16;
1690 tmp |= (u32) (ssid[i + 3]) << 24;
1691 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1693 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1696 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1699 if (dev->dev->id.revision >= 3) {
1700 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1701 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1703 b43_write16(dev, 0x606, (beacon_int >> 6));
1704 b43_write16(dev, 0x610, beacon_int);
1706 b43_time_unlock(dev);
1707 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1710 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1714 /* Read the register that contains the reason code for the panic. */
1715 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1716 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1720 b43dbg(dev->wl, "The panic reason is unknown.\n");
1722 case B43_FWPANIC_DIE:
1723 /* Do not restart the controller or firmware.
1724 * The device is nonfunctional from now on.
1725 * Restarting would result in this panic to trigger again,
1726 * so we avoid that recursion. */
1728 case B43_FWPANIC_RESTART:
1729 b43_controller_restart(dev, "Microcode panic");
1734 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1736 unsigned int i, cnt;
1737 u16 reason, marker_id, marker_line;
1740 /* The proprietary firmware doesn't have this IRQ. */
1741 if (!dev->fw.opensource)
1744 /* Read the register that contains the reason code for this IRQ. */
1745 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1748 case B43_DEBUGIRQ_PANIC:
1749 b43_handle_firmware_panic(dev);
1751 case B43_DEBUGIRQ_DUMP_SHM:
1753 break; /* Only with driver debugging enabled. */
1754 buf = kmalloc(4096, GFP_ATOMIC);
1756 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1759 for (i = 0; i < 4096; i += 2) {
1760 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1761 buf[i / 2] = cpu_to_le16(tmp);
1763 b43info(dev->wl, "Shared memory dump:\n");
1764 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1765 16, 2, buf, 4096, 1);
1768 case B43_DEBUGIRQ_DUMP_REGS:
1770 break; /* Only with driver debugging enabled. */
1771 b43info(dev->wl, "Microcode register dump:\n");
1772 for (i = 0, cnt = 0; i < 64; i++) {
1773 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1776 printk("r%02u: 0x%04X ", i, tmp);
1785 case B43_DEBUGIRQ_MARKER:
1787 break; /* Only with driver debugging enabled. */
1788 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1790 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1791 B43_MARKER_LINE_REG);
1792 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1793 "at line number %u\n",
1794 marker_id, marker_line);
1797 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1801 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1802 b43_shm_write16(dev, B43_SHM_SCRATCH,
1803 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1806 /* Interrupt handler bottom-half */
1807 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1810 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1811 u32 merged_dma_reason = 0;
1813 unsigned long flags;
1815 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1817 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1819 reason = dev->irq_reason;
1820 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1821 dma_reason[i] = dev->dma_reason[i];
1822 merged_dma_reason |= dma_reason[i];
1825 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1826 b43err(dev->wl, "MAC transmission error\n");
1828 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1829 b43err(dev->wl, "PHY transmission error\n");
1831 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1832 atomic_set(&dev->phy.txerr_cnt,
1833 B43_PHY_TX_BADNESS_LIMIT);
1834 b43err(dev->wl, "Too many PHY TX errors, "
1835 "restarting the controller\n");
1836 b43_controller_restart(dev, "PHY TX errors");
1840 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1841 B43_DMAIRQ_NONFATALMASK))) {
1842 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1843 b43err(dev->wl, "Fatal DMA error: "
1844 "0x%08X, 0x%08X, 0x%08X, "
1845 "0x%08X, 0x%08X, 0x%08X\n",
1846 dma_reason[0], dma_reason[1],
1847 dma_reason[2], dma_reason[3],
1848 dma_reason[4], dma_reason[5]);
1849 b43_controller_restart(dev, "DMA error");
1851 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1854 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1855 b43err(dev->wl, "DMA error: "
1856 "0x%08X, 0x%08X, 0x%08X, "
1857 "0x%08X, 0x%08X, 0x%08X\n",
1858 dma_reason[0], dma_reason[1],
1859 dma_reason[2], dma_reason[3],
1860 dma_reason[4], dma_reason[5]);
1864 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1865 handle_irq_ucode_debug(dev);
1866 if (reason & B43_IRQ_TBTT_INDI)
1867 handle_irq_tbtt_indication(dev);
1868 if (reason & B43_IRQ_ATIM_END)
1869 handle_irq_atim_end(dev);
1870 if (reason & B43_IRQ_BEACON)
1871 handle_irq_beacon(dev);
1872 if (reason & B43_IRQ_PMQ)
1873 handle_irq_pmq(dev);
1874 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1876 if (reason & B43_IRQ_NOISESAMPLE_OK)
1877 handle_irq_noise(dev);
1879 /* Check the DMA reason registers for received data. */
1880 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1881 if (b43_using_pio_transfers(dev))
1882 b43_pio_rx(dev->pio.rx_queue);
1884 b43_dma_rx(dev->dma.rx_ring);
1886 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1887 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1888 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1889 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1890 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1892 if (reason & B43_IRQ_TX_OK)
1893 handle_irq_transmit_status(dev);
1895 b43_interrupt_enable(dev, dev->irq_savedstate);
1897 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1900 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1902 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1904 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1905 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1906 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1907 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1908 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1909 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1912 /* Interrupt handler top-half */
1913 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1915 irqreturn_t ret = IRQ_NONE;
1916 struct b43_wldev *dev = dev_id;
1922 spin_lock(&dev->wl->irq_lock);
1924 if (b43_status(dev) < B43_STAT_STARTED)
1926 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1927 if (reason == 0xffffffff) /* shared IRQ */
1930 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1934 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1936 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1938 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1940 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1942 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1944 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1947 b43_interrupt_ack(dev, reason);
1948 /* disable all IRQs. They are enabled again in the bottom half. */
1949 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1950 /* save the reason code and call our bottom half. */
1951 dev->irq_reason = reason;
1952 tasklet_schedule(&dev->isr_tasklet);
1955 spin_unlock(&dev->wl->irq_lock);
1960 static void do_release_fw(struct b43_firmware_file *fw)
1962 release_firmware(fw->data);
1964 fw->filename = NULL;
1967 static void b43_release_firmware(struct b43_wldev *dev)
1969 do_release_fw(&dev->fw.ucode);
1970 do_release_fw(&dev->fw.pcm);
1971 do_release_fw(&dev->fw.initvals);
1972 do_release_fw(&dev->fw.initvals_band);
1975 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1979 text = "You must go to "
1980 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1981 "and download the latest firmware (version 4).\n";
1988 static int do_request_fw(struct b43_wldev *dev,
1990 struct b43_firmware_file *fw,
1993 char path[sizeof(modparam_fwpostfix) + 32];
1994 const struct firmware *blob;
1995 struct b43_fw_header *hdr;
2000 /* Don't fetch anything. Free possibly cached firmware. */
2005 if (strcmp(fw->filename, name) == 0)
2006 return 0; /* Already have this fw. */
2007 /* Free the cached firmware first. */
2011 snprintf(path, ARRAY_SIZE(path),
2013 modparam_fwpostfix, name);
2014 err = request_firmware(&blob, path, dev->dev->dev);
2015 if (err == -ENOENT) {
2017 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2022 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2026 if (blob->size < sizeof(struct b43_fw_header))
2028 hdr = (struct b43_fw_header *)(blob->data);
2029 switch (hdr->type) {
2030 case B43_FW_TYPE_UCODE:
2031 case B43_FW_TYPE_PCM:
2032 size = be32_to_cpu(hdr->size);
2033 if (size != blob->size - sizeof(struct b43_fw_header))
2036 case B43_FW_TYPE_IV:
2045 fw->filename = name;
2050 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
2051 release_firmware(blob);
2056 static int b43_request_firmware(struct b43_wldev *dev)
2058 struct b43_firmware *fw = &dev->fw;
2059 const u8 rev = dev->dev->id.revision;
2060 const char *filename;
2065 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2066 if ((rev >= 5) && (rev <= 10))
2067 filename = "ucode5";
2068 else if ((rev >= 11) && (rev <= 12))
2069 filename = "ucode11";
2071 filename = "ucode13";
2074 err = do_request_fw(dev, filename, &fw->ucode, 0);
2079 if ((rev >= 5) && (rev <= 10))
2085 fw->pcm_request_failed = 0;
2086 err = do_request_fw(dev, filename, &fw->pcm, 1);
2087 if (err == -ENOENT) {
2088 /* We did not find a PCM file? Not fatal, but
2089 * core rev <= 10 must do without hwcrypto then. */
2090 fw->pcm_request_failed = 1;
2095 switch (dev->phy.type) {
2097 if ((rev >= 5) && (rev <= 10)) {
2098 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2099 filename = "a0g1initvals5";
2101 filename = "a0g0initvals5";
2103 goto err_no_initvals;
2106 if ((rev >= 5) && (rev <= 10))
2107 filename = "b0g0initvals5";
2109 filename = "b0g0initvals13";
2111 goto err_no_initvals;
2114 if ((rev >= 11) && (rev <= 12))
2115 filename = "n0initvals11";
2117 goto err_no_initvals;
2120 goto err_no_initvals;
2122 err = do_request_fw(dev, filename, &fw->initvals, 0);
2126 /* Get bandswitch initvals */
2127 switch (dev->phy.type) {
2129 if ((rev >= 5) && (rev <= 10)) {
2130 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2131 filename = "a0g1bsinitvals5";
2133 filename = "a0g0bsinitvals5";
2134 } else if (rev >= 11)
2137 goto err_no_initvals;
2140 if ((rev >= 5) && (rev <= 10))
2141 filename = "b0g0bsinitvals5";
2145 goto err_no_initvals;
2148 if ((rev >= 11) && (rev <= 12))
2149 filename = "n0bsinitvals11";
2151 goto err_no_initvals;
2154 goto err_no_initvals;
2156 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2163 b43_print_fw_helptext(dev->wl, 1);
2168 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2173 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2178 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2179 "core rev %u\n", dev->phy.type, rev);
2183 b43_release_firmware(dev);
2187 static int b43_upload_microcode(struct b43_wldev *dev)
2189 const size_t hdr_len = sizeof(struct b43_fw_header);
2191 unsigned int i, len;
2192 u16 fwrev, fwpatch, fwdate, fwtime;
2196 /* Jump the microcode PSM to offset 0 */
2197 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2198 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2199 macctl |= B43_MACCTL_PSM_JMP0;
2200 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2201 /* Zero out all microcode PSM registers and shared memory. */
2202 for (i = 0; i < 64; i++)
2203 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2204 for (i = 0; i < 4096; i += 2)
2205 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2207 /* Upload Microcode. */
2208 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2209 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2210 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2211 for (i = 0; i < len; i++) {
2212 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2216 if (dev->fw.pcm.data) {
2217 /* Upload PCM data. */
2218 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2219 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2220 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2221 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2222 /* No need for autoinc bit in SHM_HW */
2223 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2224 for (i = 0; i < len; i++) {
2225 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2230 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2232 /* Start the microcode PSM */
2233 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2234 macctl &= ~B43_MACCTL_PSM_JMP0;
2235 macctl |= B43_MACCTL_PSM_RUN;
2236 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2238 /* Wait for the microcode to load and respond */
2241 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2242 if (tmp == B43_IRQ_MAC_SUSPENDED)
2246 b43err(dev->wl, "Microcode not responding\n");
2247 b43_print_fw_helptext(dev->wl, 1);
2251 msleep_interruptible(50);
2252 if (signal_pending(current)) {
2257 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2259 /* Get and check the revisions. */
2260 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2261 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2262 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2263 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2265 if (fwrev <= 0x128) {
2266 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2267 "binary drivers older than version 4.x is unsupported. "
2268 "You must upgrade your firmware files.\n");
2269 b43_print_fw_helptext(dev->wl, 1);
2273 dev->fw.rev = fwrev;
2274 dev->fw.patch = fwpatch;
2275 dev->fw.opensource = (fwdate == 0xFFFF);
2277 if (dev->fw.opensource) {
2278 /* Patchlevel info is encoded in the "time" field. */
2279 dev->fw.patch = fwtime;
2280 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2281 dev->fw.rev, dev->fw.patch,
2282 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2284 b43info(dev->wl, "Loading firmware version %u.%u "
2285 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2287 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2288 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2289 if (dev->fw.pcm_request_failed) {
2290 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2291 "Hardware accelerated cryptography is disabled.\n");
2292 b43_print_fw_helptext(dev->wl, 0);
2296 if (b43_is_old_txhdr_format(dev)) {
2297 b43warn(dev->wl, "You are using an old firmware image. "
2298 "Support for old firmware will be removed in July 2008.\n");
2299 b43_print_fw_helptext(dev->wl, 0);
2305 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2306 macctl &= ~B43_MACCTL_PSM_RUN;
2307 macctl |= B43_MACCTL_PSM_JMP0;
2308 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2313 static int b43_write_initvals(struct b43_wldev *dev,
2314 const struct b43_iv *ivals,
2318 const struct b43_iv *iv;
2323 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2325 for (i = 0; i < count; i++) {
2326 if (array_size < sizeof(iv->offset_size))
2328 array_size -= sizeof(iv->offset_size);
2329 offset = be16_to_cpu(iv->offset_size);
2330 bit32 = !!(offset & B43_IV_32BIT);
2331 offset &= B43_IV_OFFSET_MASK;
2332 if (offset >= 0x1000)
2337 if (array_size < sizeof(iv->data.d32))
2339 array_size -= sizeof(iv->data.d32);
2341 value = get_unaligned_be32(&iv->data.d32);
2342 b43_write32(dev, offset, value);
2344 iv = (const struct b43_iv *)((const uint8_t *)iv +
2350 if (array_size < sizeof(iv->data.d16))
2352 array_size -= sizeof(iv->data.d16);
2354 value = be16_to_cpu(iv->data.d16);
2355 b43_write16(dev, offset, value);
2357 iv = (const struct b43_iv *)((const uint8_t *)iv +
2368 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2369 b43_print_fw_helptext(dev->wl, 1);
2374 static int b43_upload_initvals(struct b43_wldev *dev)
2376 const size_t hdr_len = sizeof(struct b43_fw_header);
2377 const struct b43_fw_header *hdr;
2378 struct b43_firmware *fw = &dev->fw;
2379 const struct b43_iv *ivals;
2383 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2384 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2385 count = be32_to_cpu(hdr->size);
2386 err = b43_write_initvals(dev, ivals, count,
2387 fw->initvals.data->size - hdr_len);
2390 if (fw->initvals_band.data) {
2391 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2392 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2393 count = be32_to_cpu(hdr->size);
2394 err = b43_write_initvals(dev, ivals, count,
2395 fw->initvals_band.data->size - hdr_len);
2404 /* Initialize the GPIOs
2405 * http://bcm-specs.sipsolutions.net/GPIO
2407 static int b43_gpio_init(struct b43_wldev *dev)
2409 struct ssb_bus *bus = dev->dev->bus;
2410 struct ssb_device *gpiodev, *pcidev = NULL;
2413 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2414 & ~B43_MACCTL_GPOUTSMSK);
2416 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2421 if (dev->dev->bus->chip_id == 0x4301) {
2425 if (0 /* FIXME: conditional unknown */ ) {
2426 b43_write16(dev, B43_MMIO_GPIO_MASK,
2427 b43_read16(dev, B43_MMIO_GPIO_MASK)
2432 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2433 b43_write16(dev, B43_MMIO_GPIO_MASK,
2434 b43_read16(dev, B43_MMIO_GPIO_MASK)
2439 if (dev->dev->id.revision >= 2)
2440 mask |= 0x0010; /* FIXME: This is redundant. */
2442 #ifdef CONFIG_SSB_DRIVER_PCICORE
2443 pcidev = bus->pcicore.dev;
2445 gpiodev = bus->chipco.dev ? : pcidev;
2448 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2449 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2455 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2456 static void b43_gpio_cleanup(struct b43_wldev *dev)
2458 struct ssb_bus *bus = dev->dev->bus;
2459 struct ssb_device *gpiodev, *pcidev = NULL;
2461 #ifdef CONFIG_SSB_DRIVER_PCICORE
2462 pcidev = bus->pcicore.dev;
2464 gpiodev = bus->chipco.dev ? : pcidev;
2467 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2470 /* http://bcm-specs.sipsolutions.net/EnableMac */
2471 void b43_mac_enable(struct b43_wldev *dev)
2473 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2476 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2477 B43_SHM_SH_UCODESTAT);
2478 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2479 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2480 b43err(dev->wl, "b43_mac_enable(): The firmware "
2481 "should be suspended, but current state is %u\n",
2486 dev->mac_suspended--;
2487 B43_WARN_ON(dev->mac_suspended < 0);
2488 if (dev->mac_suspended == 0) {
2489 b43_write32(dev, B43_MMIO_MACCTL,
2490 b43_read32(dev, B43_MMIO_MACCTL)
2491 | B43_MACCTL_ENABLED);
2492 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2493 B43_IRQ_MAC_SUSPENDED);
2495 b43_read32(dev, B43_MMIO_MACCTL);
2496 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2497 b43_power_saving_ctl_bits(dev, 0);
2501 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2502 void b43_mac_suspend(struct b43_wldev *dev)
2508 B43_WARN_ON(dev->mac_suspended < 0);
2510 if (dev->mac_suspended == 0) {
2511 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2512 b43_write32(dev, B43_MMIO_MACCTL,
2513 b43_read32(dev, B43_MMIO_MACCTL)
2514 & ~B43_MACCTL_ENABLED);
2515 /* force pci to flush the write */
2516 b43_read32(dev, B43_MMIO_MACCTL);
2517 for (i = 35; i; i--) {
2518 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2519 if (tmp & B43_IRQ_MAC_SUSPENDED)
2523 /* Hm, it seems this will take some time. Use msleep(). */
2524 for (i = 40; i; i--) {
2525 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2526 if (tmp & B43_IRQ_MAC_SUSPENDED)
2530 b43err(dev->wl, "MAC suspend failed\n");
2533 dev->mac_suspended++;
2536 static void b43_adjust_opmode(struct b43_wldev *dev)
2538 struct b43_wl *wl = dev->wl;
2542 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2543 /* Reset status to STA infrastructure mode. */
2544 ctl &= ~B43_MACCTL_AP;
2545 ctl &= ~B43_MACCTL_KEEP_CTL;
2546 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2547 ctl &= ~B43_MACCTL_KEEP_BAD;
2548 ctl &= ~B43_MACCTL_PROMISC;
2549 ctl &= ~B43_MACCTL_BEACPROMISC;
2550 ctl |= B43_MACCTL_INFRA;
2552 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2553 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2554 ctl |= B43_MACCTL_AP;
2555 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2556 ctl &= ~B43_MACCTL_INFRA;
2558 if (wl->filter_flags & FIF_CONTROL)
2559 ctl |= B43_MACCTL_KEEP_CTL;
2560 if (wl->filter_flags & FIF_FCSFAIL)
2561 ctl |= B43_MACCTL_KEEP_BAD;
2562 if (wl->filter_flags & FIF_PLCPFAIL)
2563 ctl |= B43_MACCTL_KEEP_BADPLCP;
2564 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2565 ctl |= B43_MACCTL_PROMISC;
2566 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2567 ctl |= B43_MACCTL_BEACPROMISC;
2569 /* Workaround: On old hardware the HW-MAC-address-filter
2570 * doesn't work properly, so always run promisc in filter
2571 * it in software. */
2572 if (dev->dev->id.revision <= 4)
2573 ctl |= B43_MACCTL_PROMISC;
2575 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2578 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2579 if (dev->dev->bus->chip_id == 0x4306 &&
2580 dev->dev->bus->chip_rev == 3)
2585 b43_write16(dev, 0x612, cfp_pretbtt);
2588 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2594 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2597 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2599 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2600 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2603 static void b43_rate_memory_init(struct b43_wldev *dev)
2605 switch (dev->phy.type) {
2609 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2610 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2611 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2612 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2613 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2614 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2615 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2616 if (dev->phy.type == B43_PHYTYPE_A)
2620 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2621 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2622 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2623 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2630 /* Set the default values for the PHY TX Control Words. */
2631 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2635 ctl |= B43_TXH_PHY_ENC_CCK;
2636 ctl |= B43_TXH_PHY_ANT01AUTO;
2637 ctl |= B43_TXH_PHY_TXPWR;
2639 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2640 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2641 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2644 /* Set the TX-Antenna for management frames sent by firmware. */
2645 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2650 ant = b43_antenna_to_phyctl(antenna);
2653 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2654 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2656 /* For Probe Resposes */
2657 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2658 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2659 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2662 /* This is the opposite of b43_chip_init() */
2663 static void b43_chip_exit(struct b43_wldev *dev)
2666 b43_gpio_cleanup(dev);
2667 /* firmware is released later */
2670 /* Initialize the chip
2671 * http://bcm-specs.sipsolutions.net/ChipInit
2673 static int b43_chip_init(struct b43_wldev *dev)
2675 struct b43_phy *phy = &dev->phy;
2677 u32 value32, macctl;
2680 /* Initialize the MAC control */
2681 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2683 macctl |= B43_MACCTL_GMODE;
2684 macctl |= B43_MACCTL_INFRA;
2685 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2687 err = b43_request_firmware(dev);
2690 err = b43_upload_microcode(dev);
2692 goto out; /* firmware is released later */
2694 err = b43_gpio_init(dev);
2696 goto out; /* firmware is released later */
2698 err = b43_upload_initvals(dev);
2700 goto err_gpio_clean;
2702 /* Turn the Analog on and initialize the PHY. */
2703 phy->ops->switch_analog(dev, 1);
2704 err = b43_phy_init(dev);
2706 goto err_gpio_clean;
2708 /* Disable Interference Mitigation. */
2709 if (phy->ops->interf_mitigation)
2710 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2712 /* Select the antennae */
2713 if (phy->ops->set_rx_antenna)
2714 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2715 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2717 if (phy->type == B43_PHYTYPE_B) {
2718 value16 = b43_read16(dev, 0x005E);
2720 b43_write16(dev, 0x005E, value16);
2722 b43_write32(dev, 0x0100, 0x01000000);
2723 if (dev->dev->id.revision < 5)
2724 b43_write32(dev, 0x010C, 0x01000000);
2726 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2727 & ~B43_MACCTL_INFRA);
2728 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2729 | B43_MACCTL_INFRA);
2731 /* Probe Response Timeout value */
2732 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2733 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2735 /* Initially set the wireless operation mode. */
2736 b43_adjust_opmode(dev);
2738 if (dev->dev->id.revision < 3) {
2739 b43_write16(dev, 0x060E, 0x0000);
2740 b43_write16(dev, 0x0610, 0x8000);
2741 b43_write16(dev, 0x0604, 0x0000);
2742 b43_write16(dev, 0x0606, 0x0200);
2744 b43_write32(dev, 0x0188, 0x80000000);
2745 b43_write32(dev, 0x018C, 0x02000000);
2747 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2748 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2749 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2750 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2751 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2752 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2753 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2755 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2756 value32 |= 0x00100000;
2757 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2759 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2760 dev->dev->bus->chipco.fast_pwrup_delay);
2763 b43dbg(dev->wl, "Chip initialized\n");
2768 b43_gpio_cleanup(dev);
2772 static void b43_periodic_every60sec(struct b43_wldev *dev)
2774 const struct b43_phy_operations *ops = dev->phy.ops;
2776 if (ops->pwork_60sec)
2777 ops->pwork_60sec(dev);
2779 /* Force check the TX power emission now. */
2780 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2783 static void b43_periodic_every30sec(struct b43_wldev *dev)
2785 /* Update device statistics. */
2786 b43_calculate_link_quality(dev);
2789 static void b43_periodic_every15sec(struct b43_wldev *dev)
2791 struct b43_phy *phy = &dev->phy;
2794 if (dev->fw.opensource) {
2795 /* Check if the firmware is still alive.
2796 * It will reset the watchdog counter to 0 in its idle loop. */
2797 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2798 if (unlikely(wdr)) {
2799 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2800 b43_controller_restart(dev, "Firmware watchdog");
2803 b43_shm_write16(dev, B43_SHM_SCRATCH,
2804 B43_WATCHDOG_REG, 1);
2808 if (phy->ops->pwork_15sec)
2809 phy->ops->pwork_15sec(dev);
2811 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2815 static void do_periodic_work(struct b43_wldev *dev)
2819 state = dev->periodic_state;
2821 b43_periodic_every60sec(dev);
2823 b43_periodic_every30sec(dev);
2824 b43_periodic_every15sec(dev);
2827 /* Periodic work locking policy:
2828 * The whole periodic work handler is protected by
2829 * wl->mutex. If another lock is needed somewhere in the
2830 * pwork callchain, it's aquired in-place, where it's needed.
2832 static void b43_periodic_work_handler(struct work_struct *work)
2834 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2835 periodic_work.work);
2836 struct b43_wl *wl = dev->wl;
2837 unsigned long delay;
2839 mutex_lock(&wl->mutex);
2841 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2843 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2846 do_periodic_work(dev);
2848 dev->periodic_state++;
2850 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2851 delay = msecs_to_jiffies(50);
2853 delay = round_jiffies_relative(HZ * 15);
2854 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2856 mutex_unlock(&wl->mutex);
2859 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2861 struct delayed_work *work = &dev->periodic_work;
2863 dev->periodic_state = 0;
2864 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2865 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2868 /* Check if communication with the device works correctly. */
2869 static int b43_validate_chipaccess(struct b43_wldev *dev)
2873 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2875 /* Check for read/write and endianness problems. */
2876 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2877 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2879 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2880 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2883 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2885 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2886 /* The 32bit register shadows the two 16bit registers
2887 * with update sideeffects. Validate this. */
2888 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2889 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2890 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2892 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2895 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2897 v = b43_read32(dev, B43_MMIO_MACCTL);
2898 v |= B43_MACCTL_GMODE;
2899 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2904 b43err(dev->wl, "Failed to validate the chipaccess\n");
2908 static void b43_security_init(struct b43_wldev *dev)
2910 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2911 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2912 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2913 /* KTP is a word address, but we address SHM bytewise.
2914 * So multiply by two.
2917 if (dev->dev->id.revision >= 5) {
2918 /* Number of RCMTA address slots */
2919 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2921 b43_clear_keys(dev);
2924 static int b43_rng_read(struct hwrng *rng, u32 * data)
2926 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2927 unsigned long flags;
2929 /* Don't take wl->mutex here, as it could deadlock with
2930 * hwrng internal locking. It's not needed to take
2931 * wl->mutex here, anyway. */
2933 spin_lock_irqsave(&wl->irq_lock, flags);
2934 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2935 spin_unlock_irqrestore(&wl->irq_lock, flags);
2937 return (sizeof(u16));
2940 static void b43_rng_exit(struct b43_wl *wl)
2942 if (wl->rng_initialized)
2943 hwrng_unregister(&wl->rng);
2946 static int b43_rng_init(struct b43_wl *wl)
2950 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2951 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2952 wl->rng.name = wl->rng_name;
2953 wl->rng.data_read = b43_rng_read;
2954 wl->rng.priv = (unsigned long)wl;
2955 wl->rng_initialized = 1;
2956 err = hwrng_register(&wl->rng);
2958 wl->rng_initialized = 0;
2959 b43err(wl, "Failed to register the random "
2960 "number generator (%d)\n", err);
2966 static int b43_op_tx(struct ieee80211_hw *hw,
2967 struct sk_buff *skb)
2969 struct b43_wl *wl = hw_to_b43_wl(hw);
2970 struct b43_wldev *dev = wl->current_dev;
2971 unsigned long flags;
2974 if (unlikely(skb->len < 2 + 2 + 6)) {
2975 /* Too short, this can't be a valid frame. */
2978 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2982 /* Transmissions on seperate queues can run concurrently. */
2983 read_lock_irqsave(&wl->tx_lock, flags);
2986 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2987 if (b43_using_pio_transfers(dev))
2988 err = b43_pio_tx(dev, skb);
2990 err = b43_dma_tx(dev, skb);
2993 read_unlock_irqrestore(&wl->tx_lock, flags);
2997 return NETDEV_TX_OK;
3000 /* We can not transmit this packet. Drop it. */
3001 dev_kfree_skb_any(skb);
3002 return NETDEV_TX_OK;
3005 /* Locking: wl->irq_lock */
3006 static void b43_qos_params_upload(struct b43_wldev *dev,
3007 const struct ieee80211_tx_queue_params *p,
3010 u16 params[B43_NR_QOSPARAMS];
3014 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3016 memset(¶ms, 0, sizeof(params));
3018 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3019 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3020 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3021 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3022 params[B43_QOSPARAM_AIFS] = p->aifs;
3023 params[B43_QOSPARAM_BSLOTS] = bslots;
3024 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3026 for (i = 0; i < ARRAY_SIZE(params); i++) {
3027 if (i == B43_QOSPARAM_STATUS) {
3028 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3029 shm_offset + (i * 2));
3030 /* Mark the parameters as updated. */
3032 b43_shm_write16(dev, B43_SHM_SHARED,
3033 shm_offset + (i * 2),
3036 b43_shm_write16(dev, B43_SHM_SHARED,
3037 shm_offset + (i * 2),
3043 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3044 static const u16 b43_qos_shm_offsets[] = {
3045 /* [mac80211-queue-nr] = SHM_OFFSET, */
3046 [0] = B43_QOS_VOICE,
3047 [1] = B43_QOS_VIDEO,
3048 [2] = B43_QOS_BESTEFFORT,
3049 [3] = B43_QOS_BACKGROUND,
3052 /* Update all QOS parameters in hardware. */
3053 static void b43_qos_upload_all(struct b43_wldev *dev)
3055 struct b43_wl *wl = dev->wl;
3056 struct b43_qos_params *params;
3059 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3060 ARRAY_SIZE(wl->qos_params));
3062 b43_mac_suspend(dev);
3063 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3064 params = &(wl->qos_params[i]);
3065 b43_qos_params_upload(dev, &(params->p),
3066 b43_qos_shm_offsets[i]);
3068 b43_mac_enable(dev);
3071 static void b43_qos_clear(struct b43_wl *wl)
3073 struct b43_qos_params *params;
3076 /* Initialize QoS parameters to sane defaults. */
3078 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3079 ARRAY_SIZE(wl->qos_params));
3081 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3082 params = &(wl->qos_params[i]);
3084 switch (b43_qos_shm_offsets[i]) {
3088 params->p.cw_min = 0x0001;
3089 params->p.cw_max = 0x0001;
3094 params->p.cw_min = 0x0001;
3095 params->p.cw_max = 0x0001;
3097 case B43_QOS_BESTEFFORT:
3100 params->p.cw_min = 0x0001;
3101 params->p.cw_max = 0x03FF;
3103 case B43_QOS_BACKGROUND:
3106 params->p.cw_min = 0x0001;
3107 params->p.cw_max = 0x03FF;
3115 /* Initialize the core's QOS capabilities */
3116 static void b43_qos_init(struct b43_wldev *dev)
3118 /* Upload the current QOS parameters. */
3119 b43_qos_upload_all(dev);
3121 /* Enable QOS support. */
3122 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3123 b43_write16(dev, B43_MMIO_IFSCTL,
3124 b43_read16(dev, B43_MMIO_IFSCTL)
3125 | B43_MMIO_IFSCTL_USE_EDCF);
3128 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3129 const struct ieee80211_tx_queue_params *params)
3131 struct b43_wl *wl = hw_to_b43_wl(hw);
3132 struct b43_wldev *dev;
3133 unsigned int queue = (unsigned int)_queue;
3136 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3137 /* Queue not available or don't support setting
3138 * params on this queue. Return success to not
3139 * confuse mac80211. */
3142 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3143 ARRAY_SIZE(wl->qos_params));
3145 mutex_lock(&wl->mutex);
3146 dev = wl->current_dev;
3147 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3150 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3151 b43_mac_suspend(dev);
3152 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3153 b43_qos_shm_offsets[queue]);
3154 b43_mac_enable(dev);
3158 mutex_unlock(&wl->mutex);
3163 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3164 struct ieee80211_tx_queue_stats *stats)
3166 struct b43_wl *wl = hw_to_b43_wl(hw);
3167 struct b43_wldev *dev = wl->current_dev;
3168 unsigned long flags;
3173 spin_lock_irqsave(&wl->irq_lock, flags);
3174 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3175 if (b43_using_pio_transfers(dev))
3176 b43_pio_get_tx_stats(dev, stats);
3178 b43_dma_get_tx_stats(dev, stats);
3181 spin_unlock_irqrestore(&wl->irq_lock, flags);
3186 static int b43_op_get_stats(struct ieee80211_hw *hw,
3187 struct ieee80211_low_level_stats *stats)
3189 struct b43_wl *wl = hw_to_b43_wl(hw);
3190 unsigned long flags;
3192 spin_lock_irqsave(&wl->irq_lock, flags);
3193 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3194 spin_unlock_irqrestore(&wl->irq_lock, flags);
3199 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3201 struct ssb_device *sdev = dev->dev;
3204 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3205 tmslow &= ~B43_TMSLOW_GMODE;
3206 tmslow |= B43_TMSLOW_PHYRESET;
3207 tmslow |= SSB_TMSLOW_FGC;
3208 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3211 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3212 tmslow &= ~SSB_TMSLOW_FGC;
3213 tmslow |= B43_TMSLOW_PHYRESET;
3214 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3218 static const char * band_to_string(enum ieee80211_band band)
3221 case IEEE80211_BAND_5GHZ:
3223 case IEEE80211_BAND_2GHZ:
3232 /* Expects wl->mutex locked */
3233 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3235 struct b43_wldev *up_dev = NULL;
3236 struct b43_wldev *down_dev;
3237 struct b43_wldev *d;
3242 /* Find a device and PHY which supports the band. */
3243 list_for_each_entry(d, &wl->devlist, list) {
3244 switch (chan->band) {
3245 case IEEE80211_BAND_5GHZ:
3246 if (d->phy.supports_5ghz) {
3251 case IEEE80211_BAND_2GHZ:
3252 if (d->phy.supports_2ghz) {
3265 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3266 band_to_string(chan->band));
3269 if ((up_dev == wl->current_dev) &&
3270 (!!wl->current_dev->phy.gmode == !!gmode)) {
3271 /* This device is already running. */
3274 b43dbg(wl, "Switching to %s-GHz band\n",
3275 band_to_string(chan->band));
3276 down_dev = wl->current_dev;
3278 prev_status = b43_status(down_dev);
3279 /* Shutdown the currently running core. */
3280 if (prev_status >= B43_STAT_STARTED)
3281 b43_wireless_core_stop(down_dev);
3282 if (prev_status >= B43_STAT_INITIALIZED)
3283 b43_wireless_core_exit(down_dev);
3285 if (down_dev != up_dev) {
3286 /* We switch to a different core, so we put PHY into
3287 * RESET on the old core. */
3288 b43_put_phy_into_reset(down_dev);
3291 /* Now start the new core. */
3292 up_dev->phy.gmode = gmode;
3293 if (prev_status >= B43_STAT_INITIALIZED) {
3294 err = b43_wireless_core_init(up_dev);
3296 b43err(wl, "Fatal: Could not initialize device for "
3297 "selected %s-GHz band\n",
3298 band_to_string(chan->band));
3302 if (prev_status >= B43_STAT_STARTED) {
3303 err = b43_wireless_core_start(up_dev);
3305 b43err(wl, "Fatal: Coult not start device for "
3306 "selected %s-GHz band\n",
3307 band_to_string(chan->band));
3308 b43_wireless_core_exit(up_dev);
3312 B43_WARN_ON(b43_status(up_dev) != prev_status);
3314 wl->current_dev = up_dev;
3318 /* Whoops, failed to init the new core. No core is operating now. */
3319 wl->current_dev = NULL;
3323 /* Write the short and long frame retry limit values. */
3324 static void b43_set_retry_limits(struct b43_wldev *dev,
3325 unsigned int short_retry,
3326 unsigned int long_retry)
3328 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3329 * the chip-internal counter. */
3330 short_retry = min(short_retry, (unsigned int)0xF);
3331 long_retry = min(long_retry, (unsigned int)0xF);
3333 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3335 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3339 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3341 struct b43_wl *wl = hw_to_b43_wl(hw);
3342 struct b43_wldev *dev;
3343 struct b43_phy *phy;
3344 struct ieee80211_conf *conf = &hw->conf;
3345 unsigned long flags;
3350 mutex_lock(&wl->mutex);
3352 /* Switch the band (if necessary). This might change the active core. */
3353 err = b43_switch_band(wl, conf->channel);
3355 goto out_unlock_mutex;
3356 dev = wl->current_dev;
3359 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3360 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3361 conf->long_frame_max_tx_count);
3362 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3364 goto out_unlock_mutex;
3366 /* Disable IRQs while reconfiguring the device.
3367 * This makes it possible to drop the spinlock throughout
3368 * the reconfiguration process. */
3369 spin_lock_irqsave(&wl->irq_lock, flags);
3370 if (b43_status(dev) < B43_STAT_STARTED) {
3371 spin_unlock_irqrestore(&wl->irq_lock, flags);
3372 goto out_unlock_mutex;
3374 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
3375 spin_unlock_irqrestore(&wl->irq_lock, flags);
3376 b43_synchronize_irq(dev);
3378 /* Switch to the requested channel.
3379 * The firmware takes care of races with the TX handler. */
3380 if (conf->channel->hw_value != phy->channel)
3381 b43_switch_channel(dev, conf->channel->hw_value);
3383 /* Enable/Disable ShortSlot timing. */
3384 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
3386 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3387 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
3388 b43_short_slot_timing_enable(dev);
3390 b43_short_slot_timing_disable(dev);
3393 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3395 /* Adjust the desired TX power level. */
3396 if (conf->power_level != 0) {
3397 spin_lock_irqsave(&wl->irq_lock, flags);
3398 if (conf->power_level != phy->desired_txpower) {
3399 phy->desired_txpower = conf->power_level;
3400 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3401 B43_TXPWR_IGNORE_TSSI);
3403 spin_unlock_irqrestore(&wl->irq_lock, flags);
3406 /* Antennas for RX and management frame TX. */
3407 antenna = B43_ANTENNA_DEFAULT;
3408 b43_mgmtframe_txantenna(dev, antenna);
3409 antenna = B43_ANTENNA_DEFAULT;
3410 if (phy->ops->set_rx_antenna)
3411 phy->ops->set_rx_antenna(dev, antenna);
3413 /* Update templates for AP/mesh mode. */
3414 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3415 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3416 b43_set_beacon_int(dev, conf->beacon_int);
3418 if (!!conf->radio_enabled != phy->radio_on) {
3419 if (conf->radio_enabled) {
3420 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3421 b43info(dev->wl, "Radio turned on by software\n");
3422 if (!dev->radio_hw_enable) {
3423 b43info(dev->wl, "The hardware RF-kill button "
3424 "still turns the radio physically off. "
3425 "Press the button to turn it on.\n");
3428 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3429 b43info(dev->wl, "Radio turned off by software\n");
3433 spin_lock_irqsave(&wl->irq_lock, flags);
3434 b43_interrupt_enable(dev, savedirqs);
3436 spin_unlock_irqrestore(&wl->irq_lock, flags);
3438 mutex_unlock(&wl->mutex);
3443 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3444 const u8 *local_addr, const u8 *addr,
3445 struct ieee80211_key_conf *key)
3447 struct b43_wl *wl = hw_to_b43_wl(hw);
3448 struct b43_wldev *dev;
3449 unsigned long flags;
3454 if (modparam_nohwcrypt)
3455 return -ENOSPC; /* User disabled HW-crypto */
3457 mutex_lock(&wl->mutex);
3458 spin_lock_irqsave(&wl->irq_lock, flags);
3460 dev = wl->current_dev;
3462 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3465 if (dev->fw.pcm_request_failed) {
3466 /* We don't have firmware for the crypto engine.
3467 * Must use software-crypto. */
3475 if (key->keylen == 5)
3476 algorithm = B43_SEC_ALGO_WEP40;
3478 algorithm = B43_SEC_ALGO_WEP104;
3481 algorithm = B43_SEC_ALGO_TKIP;
3484 algorithm = B43_SEC_ALGO_AES;
3490 index = (u8) (key->keyidx);
3496 if (algorithm == B43_SEC_ALGO_TKIP) {
3497 /* FIXME: No TKIP hardware encryption for now. */
3502 if (is_broadcast_ether_addr(addr)) {
3503 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3504 err = b43_key_write(dev, index, algorithm,
3505 key->key, key->keylen, NULL, key);
3508 * either pairwise key or address is 00:00:00:00:00:00
3509 * for transmit-only keys
3511 err = b43_key_write(dev, -1, algorithm,
3512 key->key, key->keylen, addr, key);
3517 if (algorithm == B43_SEC_ALGO_WEP40 ||
3518 algorithm == B43_SEC_ALGO_WEP104) {
3519 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3522 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3524 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3527 err = b43_key_clear(dev, key->hw_key_idx);
3536 spin_unlock_irqrestore(&wl->irq_lock, flags);
3537 mutex_unlock(&wl->mutex);
3539 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3541 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3547 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3548 unsigned int changed, unsigned int *fflags,
3549 int mc_count, struct dev_addr_list *mc_list)
3551 struct b43_wl *wl = hw_to_b43_wl(hw);
3552 struct b43_wldev *dev = wl->current_dev;
3553 unsigned long flags;
3560 spin_lock_irqsave(&wl->irq_lock, flags);
3561 *fflags &= FIF_PROMISC_IN_BSS |
3567 FIF_BCN_PRBRESP_PROMISC;
3569 changed &= FIF_PROMISC_IN_BSS |
3575 FIF_BCN_PRBRESP_PROMISC;
3577 wl->filter_flags = *fflags;
3579 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3580 b43_adjust_opmode(dev);
3581 spin_unlock_irqrestore(&wl->irq_lock, flags);
3584 static int b43_op_config_interface(struct ieee80211_hw *hw,
3585 struct ieee80211_vif *vif,
3586 struct ieee80211_if_conf *conf)
3588 struct b43_wl *wl = hw_to_b43_wl(hw);
3589 struct b43_wldev *dev = wl->current_dev;
3590 unsigned long flags;
3594 mutex_lock(&wl->mutex);
3595 spin_lock_irqsave(&wl->irq_lock, flags);
3596 B43_WARN_ON(wl->vif != vif);
3598 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3600 memset(wl->bssid, 0, ETH_ALEN);
3601 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3602 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3603 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
3604 B43_WARN_ON(vif->type != wl->if_type);
3605 if (conf->changed & IEEE80211_IFCC_SSID)
3606 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3607 if (conf->changed & IEEE80211_IFCC_BEACON)
3608 b43_update_templates(wl);
3609 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
3610 if (conf->changed & IEEE80211_IFCC_BEACON)
3611 b43_update_templates(wl);
3613 b43_write_mac_bssid_templates(dev);
3615 spin_unlock_irqrestore(&wl->irq_lock, flags);
3616 mutex_unlock(&wl->mutex);
3621 /* Locking: wl->mutex */
3622 static void b43_wireless_core_stop(struct b43_wldev *dev)
3624 struct b43_wl *wl = dev->wl;
3625 unsigned long flags;
3627 if (b43_status(dev) < B43_STAT_STARTED)
3630 /* Disable and sync interrupts. We must do this before than
3631 * setting the status to INITIALIZED, as the interrupt handler
3632 * won't care about IRQs then. */
3633 spin_lock_irqsave(&wl->irq_lock, flags);
3634 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3635 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3636 spin_unlock_irqrestore(&wl->irq_lock, flags);
3637 b43_synchronize_irq(dev);
3639 write_lock_irqsave(&wl->tx_lock, flags);
3640 b43_set_status(dev, B43_STAT_INITIALIZED);
3641 write_unlock_irqrestore(&wl->tx_lock, flags);
3644 mutex_unlock(&wl->mutex);
3645 /* Must unlock as it would otherwise deadlock. No races here.
3646 * Cancel the possibly running self-rearming periodic work. */
3647 cancel_delayed_work_sync(&dev->periodic_work);
3648 mutex_lock(&wl->mutex);
3650 b43_mac_suspend(dev);
3651 free_irq(dev->dev->irq, dev);
3652 b43dbg(wl, "Wireless interface stopped\n");
3655 /* Locking: wl->mutex */
3656 static int b43_wireless_core_start(struct b43_wldev *dev)
3660 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3662 drain_txstatus_queue(dev);
3663 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3664 IRQF_SHARED, KBUILD_MODNAME, dev);
3666 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3670 /* We are ready to run. */
3671 b43_set_status(dev, B43_STAT_STARTED);
3673 /* Start data flow (TX/RX). */
3674 b43_mac_enable(dev);
3675 b43_interrupt_enable(dev, dev->irq_savedstate);
3677 /* Start maintainance work */
3678 b43_periodic_tasks_setup(dev);
3680 b43dbg(dev->wl, "Wireless interface started\n");
3685 /* Get PHY and RADIO versioning numbers */
3686 static int b43_phy_versioning(struct b43_wldev *dev)
3688 struct b43_phy *phy = &dev->phy;
3696 int unsupported = 0;
3698 /* Get PHY versioning */
3699 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3700 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3701 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3702 phy_rev = (tmp & B43_PHYVER_VERSION);
3709 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3717 #ifdef CONFIG_B43_NPHY
3727 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3728 "(Analog %u, Type %u, Revision %u)\n",
3729 analog_type, phy_type, phy_rev);
3732 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3733 analog_type, phy_type, phy_rev);
3735 /* Get RADIO versioning */
3736 if (dev->dev->bus->chip_id == 0x4317) {
3737 if (dev->dev->bus->chip_rev == 0)
3739 else if (dev->dev->bus->chip_rev == 1)
3744 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3745 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3746 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3747 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3749 radio_manuf = (tmp & 0x00000FFF);
3750 radio_ver = (tmp & 0x0FFFF000) >> 12;
3751 radio_rev = (tmp & 0xF0000000) >> 28;
3752 if (radio_manuf != 0x17F /* Broadcom */)
3756 if (radio_ver != 0x2060)
3760 if (radio_manuf != 0x17F)
3764 if ((radio_ver & 0xFFF0) != 0x2050)
3768 if (radio_ver != 0x2050)
3772 if (radio_ver != 0x2055)
3779 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3780 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3781 radio_manuf, radio_ver, radio_rev);
3784 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3785 radio_manuf, radio_ver, radio_rev);
3787 phy->radio_manuf = radio_manuf;
3788 phy->radio_ver = radio_ver;
3789 phy->radio_rev = radio_rev;
3791 phy->analog = analog_type;
3792 phy->type = phy_type;
3798 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3799 struct b43_phy *phy)
3801 phy->hardware_power_control = !!modparam_hwpctl;
3802 phy->next_txpwr_check_time = jiffies;
3803 /* PHY TX errors counter. */
3804 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3807 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3811 /* Assume the radio is enabled. If it's not enabled, the state will
3812 * immediately get fixed on the first periodic work run. */
3813 dev->radio_hw_enable = 1;
3816 memset(&dev->stats, 0, sizeof(dev->stats));
3818 setup_struct_phy_for_init(dev, &dev->phy);
3820 /* IRQ related flags */
3821 dev->irq_reason = 0;
3822 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3823 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3825 dev->mac_suspended = 1;
3827 /* Noise calculation context */
3828 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3831 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3833 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3836 if (!modparam_btcoex)
3838 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3840 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3843 hf = b43_hf_read(dev);
3844 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3845 hf |= B43_HF_BTCOEXALT;
3847 hf |= B43_HF_BTCOEX;
3848 b43_hf_write(dev, hf);
3851 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3853 if (!modparam_btcoex)
3858 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3860 #ifdef CONFIG_SSB_DRIVER_PCICORE
3861 struct ssb_bus *bus = dev->dev->bus;
3864 if (bus->pcicore.dev &&
3865 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3866 bus->pcicore.dev->id.revision <= 5) {
3867 /* IMCFGLO timeouts workaround. */
3868 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3869 tmp &= ~SSB_IMCFGLO_REQTO;
3870 tmp &= ~SSB_IMCFGLO_SERTO;
3871 switch (bus->bustype) {
3872 case SSB_BUSTYPE_PCI:
3873 case SSB_BUSTYPE_PCMCIA:
3876 case SSB_BUSTYPE_SSB:
3880 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3882 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3885 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3889 /* The time value is in microseconds. */
3890 if (dev->phy.type == B43_PHYTYPE_A)
3894 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3896 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3897 pu_delay = max(pu_delay, (u16)2400);
3899 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3902 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3903 static void b43_set_pretbtt(struct b43_wldev *dev)
3907 /* The time value is in microseconds. */
3908 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
3911 if (dev->phy.type == B43_PHYTYPE_A)
3916 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3917 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3920 /* Shutdown a wireless core */
3921 /* Locking: wl->mutex */
3922 static void b43_wireless_core_exit(struct b43_wldev *dev)
3926 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3927 if (b43_status(dev) != B43_STAT_INITIALIZED)
3929 b43_set_status(dev, B43_STAT_UNINIT);
3931 /* Stop the microcode PSM. */
3932 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3933 macctl &= ~B43_MACCTL_PSM_RUN;
3934 macctl |= B43_MACCTL_PSM_JMP0;
3935 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3937 if (!dev->suspend_in_progress) {
3939 b43_rng_exit(dev->wl);
3944 dev->phy.ops->switch_analog(dev, 0);
3945 if (dev->wl->current_beacon) {
3946 dev_kfree_skb_any(dev->wl->current_beacon);
3947 dev->wl->current_beacon = NULL;
3950 ssb_device_disable(dev->dev, 0);
3951 ssb_bus_may_powerdown(dev->dev->bus);
3954 /* Initialize a wireless core */
3955 static int b43_wireless_core_init(struct b43_wldev *dev)
3957 struct b43_wl *wl = dev->wl;
3958 struct ssb_bus *bus = dev->dev->bus;
3959 struct ssb_sprom *sprom = &bus->sprom;
3960 struct b43_phy *phy = &dev->phy;
3965 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3967 err = ssb_bus_powerup(bus, 0);
3970 if (!ssb_device_is_enabled(dev->dev)) {
3971 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3972 b43_wireless_core_reset(dev, tmp);
3975 /* Reset all data structures. */
3976 setup_struct_wldev_for_init(dev);
3977 phy->ops->prepare_structs(dev);
3979 /* Enable IRQ routing to this device. */
3980 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3982 b43_imcfglo_timeouts_workaround(dev);
3983 b43_bluetooth_coext_disable(dev);
3984 if (phy->ops->prepare_hardware) {
3985 err = phy->ops->prepare_hardware(dev);
3989 err = b43_chip_init(dev);
3992 b43_shm_write16(dev, B43_SHM_SHARED,
3993 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3994 hf = b43_hf_read(dev);
3995 if (phy->type == B43_PHYTYPE_G) {
3999 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4000 hf |= B43_HF_OFDMPABOOST;
4001 } else if (phy->type == B43_PHYTYPE_B) {
4003 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4006 b43_hf_write(dev, hf);
4008 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4009 B43_DEFAULT_LONG_RETRY_LIMIT);
4010 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4011 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4013 /* Disable sending probe responses from firmware.
4014 * Setting the MaxTime to one usec will always trigger
4015 * a timeout, so we never send any probe resp.
4016 * A timeout of zero is infinite. */
4017 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4019 b43_rate_memory_init(dev);
4020 b43_set_phytxctl_defaults(dev);
4022 /* Minimum Contention Window */
4023 if (phy->type == B43_PHYTYPE_B) {
4024 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4026 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4028 /* Maximum Contention Window */
4029 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4031 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4032 dev->__using_pio_transfers = 1;
4033 err = b43_pio_init(dev);
4035 dev->__using_pio_transfers = 0;
4036 err = b43_dma_init(dev);
4041 b43_set_synth_pu_delay(dev, 1);
4042 b43_bluetooth_coext_enable(dev);
4044 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4045 b43_upload_card_macaddress(dev);
4046 b43_security_init(dev);
4047 if (!dev->suspend_in_progress)
4050 b43_set_status(dev, B43_STAT_INITIALIZED);
4052 if (!dev->suspend_in_progress)
4060 ssb_bus_may_powerdown(bus);
4061 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4065 static int b43_op_add_interface(struct ieee80211_hw *hw,
4066 struct ieee80211_if_init_conf *conf)
4068 struct b43_wl *wl = hw_to_b43_wl(hw);
4069 struct b43_wldev *dev;
4070 unsigned long flags;
4071 int err = -EOPNOTSUPP;
4073 /* TODO: allow WDS/AP devices to coexist */
4075 if (conf->type != NL80211_IFTYPE_AP &&
4076 conf->type != NL80211_IFTYPE_MESH_POINT &&
4077 conf->type != NL80211_IFTYPE_STATION &&
4078 conf->type != NL80211_IFTYPE_WDS &&
4079 conf->type != NL80211_IFTYPE_ADHOC)
4082 mutex_lock(&wl->mutex);
4084 goto out_mutex_unlock;
4086 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4088 dev = wl->current_dev;
4090 wl->vif = conf->vif;
4091 wl->if_type = conf->type;
4092 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4094 spin_lock_irqsave(&wl->irq_lock, flags);
4095 b43_adjust_opmode(dev);
4096 b43_set_pretbtt(dev);
4097 b43_set_synth_pu_delay(dev, 0);
4098 b43_upload_card_macaddress(dev);
4099 spin_unlock_irqrestore(&wl->irq_lock, flags);
4103 mutex_unlock(&wl->mutex);
4108 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4109 struct ieee80211_if_init_conf *conf)
4111 struct b43_wl *wl = hw_to_b43_wl(hw);
4112 struct b43_wldev *dev = wl->current_dev;
4113 unsigned long flags;
4115 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4117 mutex_lock(&wl->mutex);
4119 B43_WARN_ON(!wl->operating);
4120 B43_WARN_ON(wl->vif != conf->vif);
4125 spin_lock_irqsave(&wl->irq_lock, flags);
4126 b43_adjust_opmode(dev);
4127 memset(wl->mac_addr, 0, ETH_ALEN);
4128 b43_upload_card_macaddress(dev);
4129 spin_unlock_irqrestore(&wl->irq_lock, flags);
4131 mutex_unlock(&wl->mutex);
4134 static int b43_op_start(struct ieee80211_hw *hw)
4136 struct b43_wl *wl = hw_to_b43_wl(hw);
4137 struct b43_wldev *dev = wl->current_dev;
4140 bool do_rfkill_exit = 0;
4142 /* Kill all old instance specific information to make sure
4143 * the card won't use it in the short timeframe between start
4144 * and mac80211 reconfiguring it. */
4145 memset(wl->bssid, 0, ETH_ALEN);
4146 memset(wl->mac_addr, 0, ETH_ALEN);
4147 wl->filter_flags = 0;
4148 wl->radiotap_enabled = 0;
4150 wl->beacon0_uploaded = 0;
4151 wl->beacon1_uploaded = 0;
4152 wl->beacon_templates_virgin = 1;
4154 /* First register RFkill.
4155 * LEDs that are registered later depend on it. */
4156 b43_rfkill_init(dev);
4158 mutex_lock(&wl->mutex);
4160 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4161 err = b43_wireless_core_init(dev);
4164 goto out_mutex_unlock;
4169 if (b43_status(dev) < B43_STAT_STARTED) {
4170 err = b43_wireless_core_start(dev);
4173 b43_wireless_core_exit(dev);
4175 goto out_mutex_unlock;
4180 mutex_unlock(&wl->mutex);
4183 b43_rfkill_exit(dev);
4188 static void b43_op_stop(struct ieee80211_hw *hw)
4190 struct b43_wl *wl = hw_to_b43_wl(hw);
4191 struct b43_wldev *dev = wl->current_dev;
4193 b43_rfkill_exit(dev);
4194 cancel_work_sync(&(wl->beacon_update_trigger));
4196 mutex_lock(&wl->mutex);
4197 if (b43_status(dev) >= B43_STAT_STARTED)
4198 b43_wireless_core_stop(dev);
4199 b43_wireless_core_exit(dev);
4200 mutex_unlock(&wl->mutex);
4202 cancel_work_sync(&(wl->txpower_adjust_work));
4205 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4206 struct ieee80211_sta *sta, bool set)
4208 struct b43_wl *wl = hw_to_b43_wl(hw);
4209 unsigned long flags;
4211 spin_lock_irqsave(&wl->irq_lock, flags);
4212 b43_update_templates(wl);
4213 spin_unlock_irqrestore(&wl->irq_lock, flags);
4218 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4219 struct ieee80211_vif *vif,
4220 enum sta_notify_cmd notify_cmd,
4221 struct ieee80211_sta *sta)
4223 struct b43_wl *wl = hw_to_b43_wl(hw);
4225 B43_WARN_ON(!vif || wl->vif != vif);
4228 static const struct ieee80211_ops b43_hw_ops = {
4230 .conf_tx = b43_op_conf_tx,
4231 .add_interface = b43_op_add_interface,
4232 .remove_interface = b43_op_remove_interface,
4233 .config = b43_op_config,
4234 .config_interface = b43_op_config_interface,
4235 .configure_filter = b43_op_configure_filter,
4236 .set_key = b43_op_set_key,
4237 .get_stats = b43_op_get_stats,
4238 .get_tx_stats = b43_op_get_tx_stats,
4239 .start = b43_op_start,
4240 .stop = b43_op_stop,
4241 .set_tim = b43_op_beacon_set_tim,
4242 .sta_notify = b43_op_sta_notify,
4245 /* Hard-reset the chip. Do not call this directly.
4246 * Use b43_controller_restart()
4248 static void b43_chip_reset(struct work_struct *work)
4250 struct b43_wldev *dev =
4251 container_of(work, struct b43_wldev, restart_work);
4252 struct b43_wl *wl = dev->wl;
4256 mutex_lock(&wl->mutex);
4258 prev_status = b43_status(dev);
4259 /* Bring the device down... */
4260 if (prev_status >= B43_STAT_STARTED)
4261 b43_wireless_core_stop(dev);
4262 if (prev_status >= B43_STAT_INITIALIZED)
4263 b43_wireless_core_exit(dev);
4265 /* ...and up again. */
4266 if (prev_status >= B43_STAT_INITIALIZED) {
4267 err = b43_wireless_core_init(dev);
4271 if (prev_status >= B43_STAT_STARTED) {
4272 err = b43_wireless_core_start(dev);
4274 b43_wireless_core_exit(dev);
4280 wl->current_dev = NULL; /* Failed to init the dev. */
4281 mutex_unlock(&wl->mutex);
4283 b43err(wl, "Controller restart FAILED\n");
4285 b43info(wl, "Controller restarted\n");
4288 static int b43_setup_bands(struct b43_wldev *dev,
4289 bool have_2ghz_phy, bool have_5ghz_phy)
4291 struct ieee80211_hw *hw = dev->wl->hw;
4294 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4295 if (dev->phy.type == B43_PHYTYPE_N) {
4297 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4300 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4303 dev->phy.supports_2ghz = have_2ghz_phy;
4304 dev->phy.supports_5ghz = have_5ghz_phy;
4309 static void b43_wireless_core_detach(struct b43_wldev *dev)
4311 /* We release firmware that late to not be required to re-request
4312 * is all the time when we reinit the core. */
4313 b43_release_firmware(dev);
4317 static int b43_wireless_core_attach(struct b43_wldev *dev)
4319 struct b43_wl *wl = dev->wl;
4320 struct ssb_bus *bus = dev->dev->bus;
4321 struct pci_dev *pdev = bus->host_pci;
4323 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4326 /* Do NOT do any device initialization here.
4327 * Do it in wireless_core_init() instead.
4328 * This function is for gathering basic information about the HW, only.
4329 * Also some structs may be set up here. But most likely you want to have
4330 * that in core_init(), too.
4333 err = ssb_bus_powerup(bus, 0);
4335 b43err(wl, "Bus powerup failed\n");
4338 /* Get the PHY type. */
4339 if (dev->dev->id.revision >= 5) {
4342 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4343 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4344 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4348 dev->phy.gmode = have_2ghz_phy;
4349 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4350 b43_wireless_core_reset(dev, tmp);
4352 err = b43_phy_versioning(dev);
4355 /* Check if this device supports multiband. */
4357 (pdev->device != 0x4312 &&
4358 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4359 /* No multiband support. */
4362 switch (dev->phy.type) {
4374 if (dev->phy.type == B43_PHYTYPE_A) {
4376 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4380 if (1 /* disable A-PHY */) {
4381 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4382 if (dev->phy.type != B43_PHYTYPE_N) {
4388 err = b43_phy_allocate(dev);
4392 dev->phy.gmode = have_2ghz_phy;
4393 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4394 b43_wireless_core_reset(dev, tmp);
4396 err = b43_validate_chipaccess(dev);
4399 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4403 /* Now set some default "current_dev" */
4404 if (!wl->current_dev)
4405 wl->current_dev = dev;
4406 INIT_WORK(&dev->restart_work, b43_chip_reset);
4408 dev->phy.ops->switch_analog(dev, 0);
4409 ssb_device_disable(dev->dev, 0);
4410 ssb_bus_may_powerdown(bus);
4418 ssb_bus_may_powerdown(bus);
4422 static void b43_one_core_detach(struct ssb_device *dev)
4424 struct b43_wldev *wldev;
4427 /* Do not cancel ieee80211-workqueue based work here.
4428 * See comment in b43_remove(). */
4430 wldev = ssb_get_drvdata(dev);
4432 b43_debugfs_remove_device(wldev);
4433 b43_wireless_core_detach(wldev);
4434 list_del(&wldev->list);
4436 ssb_set_drvdata(dev, NULL);
4440 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4442 struct b43_wldev *wldev;
4443 struct pci_dev *pdev;
4446 if (!list_empty(&wl->devlist)) {
4447 /* We are not the first core on this chip. */
4448 pdev = dev->bus->host_pci;
4449 /* Only special chips support more than one wireless
4450 * core, although some of the other chips have more than
4451 * one wireless core as well. Check for this and
4455 ((pdev->device != 0x4321) &&
4456 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4457 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4462 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4468 b43_set_status(wldev, B43_STAT_UNINIT);
4469 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4470 tasklet_init(&wldev->isr_tasklet,
4471 (void (*)(unsigned long))b43_interrupt_tasklet,
4472 (unsigned long)wldev);
4473 INIT_LIST_HEAD(&wldev->list);
4475 err = b43_wireless_core_attach(wldev);
4477 goto err_kfree_wldev;
4479 list_add(&wldev->list, &wl->devlist);
4481 ssb_set_drvdata(dev, wldev);
4482 b43_debugfs_add_device(wldev);
4492 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4493 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4494 (pdev->device == _device) && \
4495 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4496 (pdev->subsystem_device == _subdevice) )
4498 static void b43_sprom_fixup(struct ssb_bus *bus)
4500 struct pci_dev *pdev;
4502 /* boardflags workarounds */
4503 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4504 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4505 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4506 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4507 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4508 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4509 if (bus->bustype == SSB_BUSTYPE_PCI) {
4510 pdev = bus->host_pci;
4511 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4512 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4513 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4514 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4515 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4516 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4517 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4518 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4522 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4524 struct ieee80211_hw *hw = wl->hw;
4526 ssb_set_devtypedata(dev, NULL);
4527 ieee80211_free_hw(hw);
4530 static int b43_wireless_init(struct ssb_device *dev)
4532 struct ssb_sprom *sprom = &dev->bus->sprom;
4533 struct ieee80211_hw *hw;
4537 b43_sprom_fixup(dev->bus);
4539 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4541 b43err(NULL, "Could not allocate ieee80211 device\n");
4546 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4547 IEEE80211_HW_SIGNAL_DBM |
4548 IEEE80211_HW_NOISE_DBM;
4550 hw->wiphy->interface_modes =
4551 BIT(NL80211_IFTYPE_AP) |
4552 BIT(NL80211_IFTYPE_MESH_POINT) |
4553 BIT(NL80211_IFTYPE_STATION) |
4554 BIT(NL80211_IFTYPE_WDS) |
4555 BIT(NL80211_IFTYPE_ADHOC);
4557 hw->queues = b43_modparam_qos ? 4 : 1;
4559 SET_IEEE80211_DEV(hw, dev->dev);
4560 if (is_valid_ether_addr(sprom->et1mac))
4561 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4563 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4565 /* Get and initialize struct b43_wl */
4566 wl = hw_to_b43_wl(hw);
4567 memset(wl, 0, sizeof(*wl));
4569 spin_lock_init(&wl->irq_lock);
4570 rwlock_init(&wl->tx_lock);
4571 spin_lock_init(&wl->leds_lock);
4572 spin_lock_init(&wl->shm_lock);
4573 mutex_init(&wl->mutex);
4574 INIT_LIST_HEAD(&wl->devlist);
4575 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4576 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4578 ssb_set_devtypedata(dev, wl);
4579 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4585 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4591 wl = ssb_get_devtypedata(dev);
4593 /* Probing the first core. Must setup common struct b43_wl */
4595 err = b43_wireless_init(dev);
4598 wl = ssb_get_devtypedata(dev);
4601 err = b43_one_core_attach(dev, wl);
4603 goto err_wireless_exit;
4606 err = ieee80211_register_hw(wl->hw);
4608 goto err_one_core_detach;
4614 err_one_core_detach:
4615 b43_one_core_detach(dev);
4618 b43_wireless_exit(dev, wl);
4622 static void b43_remove(struct ssb_device *dev)
4624 struct b43_wl *wl = ssb_get_devtypedata(dev);
4625 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4627 /* We must cancel any work here before unregistering from ieee80211,
4628 * as the ieee80211 unreg will destroy the workqueue. */
4629 cancel_work_sync(&wldev->restart_work);
4632 if (wl->current_dev == wldev)
4633 ieee80211_unregister_hw(wl->hw);
4635 b43_one_core_detach(dev);
4637 if (list_empty(&wl->devlist)) {
4638 /* Last core on the chip unregistered.
4639 * We can destroy common struct b43_wl.
4641 b43_wireless_exit(dev, wl);
4645 /* Perform a hardware reset. This can be called from any context. */
4646 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4648 /* Must avoid requeueing, if we are in shutdown. */
4649 if (b43_status(dev) < B43_STAT_INITIALIZED)
4651 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4652 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4657 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4659 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4660 struct b43_wl *wl = wldev->wl;
4662 b43dbg(wl, "Suspending...\n");
4664 mutex_lock(&wl->mutex);
4665 wldev->suspend_in_progress = true;
4666 wldev->suspend_init_status = b43_status(wldev);
4667 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4668 b43_wireless_core_stop(wldev);
4669 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4670 b43_wireless_core_exit(wldev);
4671 mutex_unlock(&wl->mutex);
4673 b43dbg(wl, "Device suspended.\n");
4678 static int b43_resume(struct ssb_device *dev)
4680 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4681 struct b43_wl *wl = wldev->wl;
4684 b43dbg(wl, "Resuming...\n");
4686 mutex_lock(&wl->mutex);
4687 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4688 err = b43_wireless_core_init(wldev);
4690 b43err(wl, "Resume failed at core init\n");
4694 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4695 err = b43_wireless_core_start(wldev);
4697 b43_leds_exit(wldev);
4698 b43_rng_exit(wldev->wl);
4699 b43_wireless_core_exit(wldev);
4700 b43err(wl, "Resume failed at core start\n");
4704 b43dbg(wl, "Device resumed.\n");
4706 wldev->suspend_in_progress = false;
4707 mutex_unlock(&wl->mutex);
4711 #else /* CONFIG_PM */
4712 # define b43_suspend NULL
4713 # define b43_resume NULL
4714 #endif /* CONFIG_PM */
4716 static struct ssb_driver b43_ssb_driver = {
4717 .name = KBUILD_MODNAME,
4718 .id_table = b43_ssb_tbl,
4720 .remove = b43_remove,
4721 .suspend = b43_suspend,
4722 .resume = b43_resume,
4725 static void b43_print_driverinfo(void)
4727 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4728 *feat_leds = "", *feat_rfkill = "";
4730 #ifdef CONFIG_B43_PCI_AUTOSELECT
4733 #ifdef CONFIG_B43_PCMCIA
4736 #ifdef CONFIG_B43_NPHY
4739 #ifdef CONFIG_B43_LEDS
4742 #ifdef CONFIG_B43_RFKILL
4745 printk(KERN_INFO "Broadcom 43xx driver loaded "
4746 "[ Features: %s%s%s%s%s, Firmware-ID: "
4747 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4748 feat_pci, feat_pcmcia, feat_nphy,
4749 feat_leds, feat_rfkill);
4752 static int __init b43_init(void)
4757 err = b43_pcmcia_init();
4760 err = ssb_driver_register(&b43_ssb_driver);
4762 goto err_pcmcia_exit;
4763 b43_print_driverinfo();
4774 static void __exit b43_exit(void)
4776 ssb_driver_unregister(&b43_ssb_driver);
4781 module_init(b43_init)
4782 module_exit(b43_exit)